CN112532250A

CN112532250A - Modular analog signal multiplexer for differential signals

Info

Publication number: CN112532250A
Application number: CN202010986477.7A
Authority: CN
Inventors: J·阿杜特; G·冯; B·汉密尔顿
Original assignee: Analog Devices International ULC
Current assignee: Analog Devices International ULC
Priority date: 2019-09-19
Filing date: 2020-09-18
Publication date: 2021-03-19

Abstract

The present disclosure relates to modular analog signal multiplexers for differential signals. The exemplary analog signal multiplexer includes two differential input signal ports for receiving a first differential input signal IN1 and a second differential input signal IN 2. The multiplexer also includes a differential output signal port having two output terminals OUT + and OUT-for outputting a signal based on one or more of the input signals IN1 and IN 2. In addition, the multiplexer includes a pair of load elements and an additional differential output signal port having two output terminals TERM + and TERM-. The load elements are not directly coupled to the output terminals OUT + and OUT-, but to the output terminals TERM + and TERM-of the additional output signal ports, thereby enabling a modular approach in which multiple instances of multiplexers can be combined on an "as needed" basis to enable multiplexing between the greater number of differential inputs that a single multiplexer would allow.

Description

Modular analog signal multiplexer for differential signals

Cross Reference to Related Applications

The present application is related to U.S. patent application No. 62/902,945 entitled "MODULAR ANALOG SIGNAL multiplexer FOR differential SIGNALs" (MODULAR ANALOG SIGNAL multiplexer FOR DIFFERENTIAL SIGNALS), filed on 19/9/2019, the disclosure of which is hereby incorporated by reference in its entirety.

Technical Field

The present disclosure relates generally to electronics, and more specifically to multiplexer circuits for differential analog signals.

Background

Light detection and ranging (LIDAR) refers to a measurement method that measures distance to a target object by illuminating the object with light, such as with a pulse of light, such as a pulse of laser light, and measuring the reflected light with an optical sensor, such as an Avalanche Photodiode (APD). The difference in pulse return time or wavelength can then be used to determine the distance to the object and/or to make a digital three-dimensional representation of the object. LIDAR systems are used in a variety of situations. For example, LIDAR systems may be used in airplanes, cars, binoculars, monoculars, or the like.

A conventional receiver chain of a LIDAR system may include a sequence of an optical sensor that receives/detects optical pulses and converts the optical pulses into a current, a transimpedance amplifier (TIA) that converts the current signal from the optical sensor into a voltage signal, and an analog-to-digital converter (ADC) that converts the voltage signal from the TIA into a digital signal for further processing.

High-definition LIDAR systems, such as those deployed on vehicles equipped with Advanced Driver Assistance Systems (ADAS), employ multiple lasers to emit light pulses and multiple optical sensors to receive light pulses reflected from objects. To reduce the board area, power consumption, and material expenditure of the LIDAR receiver of such a system, it is desirable to construct a multi-channel system in which, for example, the output signals from different TIAs may be multiplexed together to use a single ADC (rather than each TIA using a single ADC). Unfortunately, the traditional commercial off-the-shelf (COTS) TIA used in the most advanced LIDAR systems does not help LIDAR system engineers easily build multi-channel systems. One drawback of the conventional COTS TIA is that to assemble an economical system, additional analog switches and gain modules need to be placed in the signal path, which often compromises the bandwidth and dynamic range of the receiver. Another disadvantage is that conventional COTS TIAs are not modular because they do not allow any desired number of TIA outputs to be multiplexed into a single ADC.

Drawings

To provide a more complete understanding of the present disclosure and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, in which:

fig. 1 is a circuit diagram illustrating a LIDAR receiver.

Fig. 2 is a circuit diagram showing a differential amplifier as an example of an output stage.

Fig. 3 is a circuit diagram showing a non-modular analog signal multiplexer having two channels.

Fig. 4A-4B are circuit diagrams illustrating a modular analog signal multiplexer having two channels according to various embodiments of the present disclosure.

Fig. 5A-5C are circuit diagrams illustrating components using a single modular analog signal multiplexer having two channels according to various embodiments of the present disclosure.

Fig. 6A-6C are circuit diagrams illustrating the use of differential current mirrors instead of differential pairs according to various embodiments of the present disclosure.

Figures 7A-7E are circuit diagrams illustrating components using a combination of two modular analog signal multiplexers, according to various embodiments of the present disclosure.

Fig. 8 is a schematic diagram of an exemplary LIDAR system in which any of the modular analog signal multiplexers described herein may be implemented, according to some embodiments of the present disclosure.

Fig. 9 provides a block diagram illustrating an example data processing system that may be configured to implement or control at least some portions of any of the modular analog signal multiplexers described herein, according to some embodiments of the present disclosure.

Fig. 10 is an illustration of a LIDAR system integrated with an automobile, in accordance with some embodiments of the present disclosure.

Detailed Description

SUMMARY

The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all the desirable attributes disclosed herein. The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

Some aspects of the present disclosure relate to analog signal multiplexer circuits (or simply "analog signal multiplexers") that may be used to multiplex different analog signals. As used herein, the term "multiplexed" signal is used in its conventional sense as it refers to receiving a particular plurality of signals as input signals and providing a particular, lesser number of output signals at the outputs, where the output signals are indicative of one or more of the input signals in some manner. The circuit that carries out the multiplexing of the signals is called a "multiplexer circuit", or simply "multiplexer". When such circuits operate on analog signals, they may be referred to as "analog signal multiplexers".

The signals may be single ended or differential signals. The analog signal multiplexer described herein is an analog signal multiplexer for differential signals because the analog signal multiplexer described herein may be particularly advantageous for sharing a single ADC between multiple TIAs of a LIDAR receiver, and because some ADCs operate better when the input signals provided to them are differential signals. Thus, each input signal and each output signal of the analog signal multiplexer described herein is a differential signal. The signal port for the differential input signal has two input terminals: a non-inverting input terminal (denoted herein as "IN +") and an inverting input terminal (denoted herein as "IN +"). Similarly, a signal port for differential output signals has two output terminals: a non-inverting output terminal (denoted herein as "OUT +") and an inverting output terminal (denoted herein as "OUT-"). However, although differential signals are described herein with reference to input and output signals of a multiplexer, in some embodiments at least some of the input and/or output signals of the multiplexer itself may be single-ended, with a single-ended to differential converter stage coupled to any input of the multiplexer to convert a single-ended input signal to a differential input signal and/or with a differential to single-ended converter stage coupled to any output of the multiplexer to convert a differential output signal to a single-ended output signal. For example, although fig. 4A shows that each of the inputs IN1 and IN2 is a differential input, the analog signal multiplexer of this figure includes embodiments IN which: where differential inputs IN1 and IN2 are inputs to output stages 410-1 and 410-2, respectively, multiplexer 400A may have single-ended inputs for input signals IN1 and IN2 that are then converted to differential inputs provided to output stages 410-1 and 410-2.

IN some embodiments, the example analog signal multiplexer described herein may contain two differential input signal ports, where a first input signal port has two input terminals IN1+ and IN 1-for receiving a first differential input signal IN1 (e.g., signal IN1 may indicate an output from one TIA), and a second input signal port has two input terminals IN2+ and IN 2-for receiving a second differential input signal IN2 (e.g., signal IN2 may indicate an output from another TIA). Such a multiplexer may comprise one differential output signal port with two output terminals OUT + and OUT-for outputting a multiplexed signal based on one or more of the two input signals IN1 and IN 2. Additionally, such a multiplexer may include a pair of load elements, such as a pair of load resistors (denoted herein as resistors "RLA" and "RLB") and an additional differential output signal port having two output terminals denoted herein as "TERM +" and "TERM-". The load element is not directly coupled to the output terminals OUT + and OUT-, but to the output terminals TERM + and TERM-of the additional output signal port, which output terminals TERM + and TERM-may then be coupled to the output terminals OUT + and OUT-. In other embodiments, an exemplary analog signal multiplexer may include a switching device including one or more switches configured to couple (i.e., electrically connect) or decouple (i.e., electrically disconnect) a load element to output terminals OUT + and OUT-. This configuration enables a modular approach in which multiple instances of such analog signal multiplexers can be combined on an "as needed" basis to achieve multiplexing between the greater number of differential inputs that a single analog signal multiplexer would allow. Such an analog signal multiplexer may thus advantageously provide a modular, scalable output stage that can be easily configured to facilitate construction of a multi-channel LIDAR receiver, wherein multiple output stages may be combined with only a minimal number of additional components required for combination.

An "output stage" may refer to a circuit configured to condition a signal in some manner before providing the signal as an input signal to another electronic component. Any analog signal multiplexer described herein may be referred to as an "output stage" because they condition the signals in some way. However, some of the components of the analog signal multiplexer described herein (e.g., differential pairs or differential current mirrors) may also be referred to as "output stages".

In some embodiments, any of the modular analog signal multiplexers described herein may be used as or in one or more output stages of a plurality of TIAs (which may be used, for example, in LIDAR receivers of a LIDAR system) to enable conversion of differential outputs from the plurality of TIAs using a single ADC. For example, any of the modular analog signal multiplexers described herein may be used to implement the output stages of multiple TIAs by receiving the multiple differential input signals (i.e., by receiving differential inputs from the multiple TIAs) and providing a reduced number of differential output signals (e.g., providing a single differential output signal) to yet another electronic component, such as an ADC. In some embodiments, one or more such analog signal multiplexers may be used as output stages for a plurality of TIAs, where each of the plurality of TIAs may be associated with a designated optical sensor (e.g., for multiple instances of TIA834 coupled to optical sensor 832 shown in fig. 8). In some such embodiments, such an output stage may be implemented between the output of the TIA and a subsequent filter (such as filter 836 shown in fig. 8). In other words, the output stage may receive multiple inputs from different instances of TIA834 and provide the outputs as inputs to a single filter 836. In other such embodiments, such an output stage may be implemented between the output of the subsequent filter associated with each TIA (i.e., the output of multiple instances of the filter 836 for multiple instances of the optical sensor-TIA-filter link shown in fig. 8) and a single ADC driver, such as the ADC driver 838 shown in fig. 8. In other words, the output stage may receive multiple inputs from different instances of the filter 836 and provide the outputs as inputs to a single ADC driver 838. The ADC driver may perform functions such as buffering, amplitude scaling, single-ended to differential conversion, common-mode offset adjustment, and filtering.

In other embodiments, any of the modular analog signal multiplexers described herein may be used as an output stage for a plurality of ADC drivers, each of which is associated with a specified optical sensor and a specified TIA (e.g., as shown in fig. 8 for multiple instances of TIA834 coupled to optical sensor 832 and ADC driver 838 coupled to TIA 834). In some such embodiments, such an output stage may be implemented between the output of an ADC driver and a subsequent ADC (such as ADC 840 shown in fig. 8). In other words, the output stage may receive multiple inputs from different instances of the ADC driver 838 and provide the outputs as inputs to a single ADC 840.

Although some embodiments may relate to modular analog signal multiplexers that may be used as differential output stages for one or more TIAs, the description of these embodiments applies equally to embodiments in which these analog signal multiplexers themselves are used as independent TIAs, all of which are within the scope of this disclosure.

Other aspects of the present disclosure provide systems, such as LIDAR systems (and in particular LIDAR receivers), that may include one or more modular analog signal multiplexers as described herein, as well as methods of operating such systems and methods of determining a distance to at least one object using such systems. Although some embodiments of the present disclosure refer to LIDAR as an exemplary system in which a modular analog signal multiplexer as described herein may be implemented, in other embodiments, a modular analog signal multiplexer as described herein may be implemented in systems other than LIDAR in which multiplexing of differential analog signals may be desired, all of which are within the scope of the present disclosure.

The precise design of the modular analog signal multiplexer described herein can be implemented in many different ways, all of which are within the scope of the present disclosure. In one example of a design change according to various embodiments of the present disclosure, each of the transistors of the modular analog signal multiplexer according to any of the embodiments described herein may be individually selected to employ bipolar transistors (e.g., where the various transistors may be NPN or PNP transistors), Field Effect Transistors (FETs), such as Metal Oxide Semiconductor (MOS) technology transistors (e.g., where the various transistors may be N-type MOS (nmos) or P-type MOS (pmos) transistors), or a combination of one or more FETs and one or more bipolar transistors. In view of this, in the following description, the transistors are sometimes described with reference to their first, second, and third terminals. The term "first terminal" of a transistor is used to refer to an emitter terminal when the transistor is a bipolar transistor or a source terminal when the transistor is a FET, the term "second terminal" of the transistor is used to refer to a collector terminal when the transistor is a bipolar transistor or a drain terminal when the transistor is a FET, and the term "third terminal" of the transistor is used to refer to a base terminal when the transistor is a bipolar transistor or a gate terminal when the transistor is a FET. These terms remain the same regardless of whether the transistors of a given technology are N-type transistors (e.g., NPN transistors when the transistors are bipolar transistors or NMOS transistors when the transistors are FETs) or P-type transistors (e.g., PNP transistors when the transistors are bipolar transistors or PMOS transistors when the transistors are FETs). In another example, in various embodiments, which transistors are implemented as N-type transistors (such as NMOS transistors for transistors implemented as FETs, or NPN transistors for transistors implemented as bipolar transistors) and which transistors are implemented as P-type transistors (e.g., PMOS transistors for transistors implemented as FETs or PNP transistors for transistors implemented as bipolar transistors) may be selected separately for each of the transistors of any modular analog signal multiplexer as described herein. In still other examples, in various embodiments, which type of transistor architecture to employ may be selected. For example, any transistor of a modular analog signal multiplexer as described herein that is implemented as a FET may be a planar transistor or a non-planar transistor (some examples of the latter include a FinFET, a nanowire transistor, or a nanoribbon transistor).

As will be appreciated by one skilled in the art, aspects of the present disclosure, and in particular aspects of the modular analog signal multiplexer set forth herein, may be implemented in various ways (e.g., as a method, system, computer program product, or computer readable storage medium). Accordingly, various aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit," module "or" system. The functions described in this disclosure may be implemented as algorithms executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and portions of steps of each method described herein may be performed by different processing units. Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media, which is preferably non-transitory, having computer-readable program code embodied thereon (such as stored). In various embodiments, such computer programs may, for example, be downloaded (updated) to existing devices and systems (e.g., to existing receivers, LIDAR systems and/or their controllers, etc.) or stored at the time of manufacture of such devices and systems.

The following detailed description presents various descriptions of specific certain embodiments. However, the innovations described herein may be implemented in a number of different ways (e.g., as defined and encompassed by the selected examples). In the following description, reference is made to the accompanying drawings wherein like reference numbers may indicate identical or functionally similar elements. It will be understood that elements shown in the figures are not necessarily drawn to scale. Furthermore, some embodiments may incorporate any suitable combination of features from two or more of the figures. Further, it should be understood that certain embodiments may contain more elements than shown in the figures and/or a subset of the elements shown in the figures.

In general, although some of the figures provided herein illustrate various aspects of a modular analog signal multiplexer for differential signals, and systems in which such circuitry may be implemented, the details of such systems may differ in different embodiments. For example, the various components of the modular analog signal multiplexer presented herein may have other components contained therein or coupled thereto, such as logic, memory banks, passive elements (e.g., resistors, capacitors, inductors, etc.), or other elements (e.g., transistors, etc.), not specifically shown in the figures. In another example, the details shown in some of the figures, such as the particular arrangement and example implementation details of the various components of the modular analog signal multiplexer presented herein (e.g., load resistors RLA and RLB, differential pairs corresponding to different multiplexer inputs) and/or the particular means of coupling connections (e.g., coupling connections between differential terminals TERM + and TERM-and differential terminals OUT-and OUT +, coupling connections to ground and positive supply voltages, etc.) may be different in different embodiments, the figures of the present disclosure merely provide some examples of how these components may be used together to implement a modular analog signal multiplexer. In yet another example, although some embodiments shown in the figures of the present disclosure illustrate a particular number of components (e.g., a particular number of differential inputs of any modular analog signal multiplexer shown in the figures, a particular number of differential outputs of any modular analog signal multiplexer shown in the figures, or a particular number of load resistors in any modular analog signal multiplexer shown in the figures), it should be understood that these embodiments may be implemented in a modular analog signal multiplexer, or in any other device or system having any number of these components, in accordance with the description provided herein. Further, while certain elements (such as the various elements of the modular analog signal multiplexer described herein) may be depicted in the figures as being communicatively coupled using a single depicted line, in some embodiments any of these elements may be coupled by a plurality of conductive lines (such as may be present in a bus), or when differential signals are involved.

The description may use the phrases "in one embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Unless otherwise specified the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and do not imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. Further, for purposes of this disclosure, the phrase "a and/or B" or the symbol "a/B" represents (a), (B), or (a and B), while the phrase "A, B and/or C" represents (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C). The notation "A/B/C" as used herein means (A, B and/or C). The term "between" when referring to a measurement range encompasses the end of the measurement range.

Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term "connected" means a direct electrical connection between the things that are connected, without any intervening devices/components, while the term "coupled" means a direct electrical connection between the things that are connected, or an indirect electrical connection through one or more passive or active intervening devices/components. In another example, the term "circuit" represents one or more passive and/or active components arranged to cooperate with one another to provide a desired function. Sometimes, in this description, the term "circuitry" may be omitted (e.g., modular analog signal multiplexer circuitry may be referred to simply as "modular analog signal multiplexer" or the like). The terms "substantially," "approximately," "about," and the like, if used, may be used to generally refer to within +/-20% of a target value, such as within +/-10% of the target value, based on the context of the particular values described herein or known in the art.

Other features and advantages of the present disclosure will be apparent from the following description and selected examples.

Exemplary uses of analog Signal multiplexers and examples of conventional Signal multiplexers

To illustrate the modular analog signal multiplexer presented herein, it may be useful to first understand the settings in which analog signal multiplexing may be used and the phenomena that may occur when analog signal multiplexing is carried out. The following basic information may be considered as a basis on which the present disclosure may be appropriately interpreted. This information is provided for purposes of explanation only, and therefore should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

As described above, an analog signal multiplexer may be used in a LIDAR system. Fig. 1 is a schematic diagram of a LIDAR receiver 100. LIDAR receivers typically include an optical sensor (e.g., APD)102, a TIA 104, and an ADC 106. The optical sensor 102 may be configured to receive pulses of light reflected from an object and convert the pulses of light into pulses of current. As shown in fig. 1, in some embodiments, the optical sensor 102 may have its cathode connected to an input port of the TIA 104 (the input port of the TIA 104 is shown in fig. 1 with a white dot labeled "103"). Thus, the optical sensor 102 may be negatively biased and may sink current from the TIA 104. Although not specifically shown in this figure, in other embodiments, the optical sensor 102 may have its anode connected to the input port of the TIA 104; thus, the optical sensor 102 will then be forward biased and a current may be provided to the TIA 104. Although fig. 1 shows current source I2, in other embodiments, current source I2 may be replaced with voltage source V2.

The TIA 104 may be configured to amplify the current pulses from the optical sensor 102 and provide voltage pulses. In some embodiments, the TIA 104 may be a parallel feedback TIA, as shown in fig. 1. Such a TIA may include an amplification circuit 105 and a feedback Resistor (RT)107 electrically coupled between an input of the amplification circuit 105 and an output of the amplification circuit 105. The output of the amplification circuit 105 may be electrically connected to the input of the ADC driver 109. The amplification circuit 105 may include one or more amplifiers. The ADC driver 109 may be configured to drive the ADC 106. For example, the ADC driver 109 may perform single-ended to differential conversion prior to providing the drive signal to the ADC 106 (possibly via one or more intermediate components, such as filters). The ADC 106 may convert the received pulses into digital signals. The digital signal may be provided to a digital signal processor (not shown in fig. 1).

Fig. 2 shows a differential amplifier 200 as an example of an output stage. The differential amplifier 200 may be, for example, the output stage of the TIA 104 shown IN fig. 1, where the outputs shown as out and outbar IN fig. 1 are provided as inputs IN1+ and IN 1-to the differential amplifier 200, respectively. Thus, the differential amplifier 200 may comprise an input stage comprising a differential pair for receiving a differential input signal comprising IN1+ and IN 1-. The differential amplifier 200 may include a differential pair 210, the differential pair 210 including a pair of emitter-coupled bipolar transistors Q1A and Q1B, IN1+ being received by an input stage at the base of Q1A, and IN 1-being received by an input stage at the base of Q1B. The emitter coupled transistors Q1A and Q1B may be biased by a current source I1. The current source I1 may be turned off (or deactivated) to disable the differential pair of transistors Q1A and Q1B, or turned on (or activated) to enable the differential pair to produce a differential output current at the collectors of Q1A and Q1B. The collector of Q1A may be connected to terminal OUT-and coupled to positive power supply Vcc through resistor RLA. The collector of Q1B may be connected to terminal OUT + and coupled to positive power supply Vcc through resistor RLB. Resistors RLA and RLB may form a passive load 220. The differential output currents of the differential pair may produce a differential output signal when terminated to a passive load through terminals OUT + and OUT-.

Fig. 3 shows an analog signal multiplexer 300 (denoted as multiplexer "M") having two channels. Each channel may have a separate input signal path with the outputs of the channels combined in a common output signal path. For example, channel 1 may include terminals IN1+ and IN 1-coupled to a differential pair 310-1, which may include emitter-coupled transistors Q1A and Q1B biased by a current source I1. Similarly, channel 2 may include terminals IN2+ and IN2-2 coupled to a differential pair 310-2, which differential pair 310-2 may include emitter-coupled transistors Q2A and Q2B biased by a current source I2. Each of the differential pairs 310-1 and 310-2 may be a different instance of the differential pair 210 shown in fig. 2. Multiplexer 300 may also include a passive load 320, similar to load 220 described with reference to fig. 2. As shown in fig. 3, terminal OUT-may be connected to the collectors of Q1A and Q2A and resistor RLA, while terminal OUT + may be connected to the collectors of Q1B and Q2B and resistor RLB. By selectively enabling current sources I1 and I2, either channel 1 or channel 2 may be coupled to the output of multiplexer 300. To select channel 1, I1 may be activated when I2 is off. To select channel 2, I2 may be activated when I1 is off. Multiplexer 300 may also be configured to sum

channels

1 and 2 if I1 is activated at the same time as I2, or both channels may be isolated from the output by turning off I1 and I2 at the same time.

Although analog signal multiplexer 300 may provide a way to combine multiple channels into a common output, it is not modular. Multiple instances of analog signal multiplexer 300 cannot be combined at the output without reducing the amount of output impedance.

Modular analog signal multiplexer

Fig. 4A presents a scalable modular analog signal multiplexer 400A with two additional terminals TERM + and TERM-, according to some embodiments of the present disclosure. The analog signal multiplexer 400A may be, for example, the output stage of the TIA 104 shown IN fig. 1, where the outputs shown as out and outbar IN fig. 1 are provided as inputs IN1+ and IN 1-of the first input signal IN1, respectively, to the analog signal multiplexer 400A. With such use of the analog signal multiplexer 400A, there may be another TIA similar to TIA 104 (such other TIA not shown IN fig. 1) whose differential outputs may be provided to the analog signal multiplexer 400A as inputs IN2+ and IN 2-of the second input signal IN 2. Then, instead of providing the output of the TIA directly to the ADC 106 as shown in fig. 1, the input to the ADC 106 would be a differential output signal at the output terminals OUT + and OUT-, as shown in fig. 4A.

Thus, similar to the illustration of fig. 3, analog signal multiplexer 400A is shown as having two channels (although multiplexer 400A may have more than 2 channels in other embodiments without departing from the scope of the present disclosure). Each channel may have a separate input signal path with the outputs of the channels combined in a common output signal path. For example, channel 1 may include input terminals IN1+ and IN 1-coupled to differential pair 410-1, and differential pair 410-1 may include emitter-coupled transistors Q1A and Q1B biased by current source I1. Similarly, channel 2 may include input terminals IN2+ and IN 2-coupled to differential pair 410-2, and differential pair 410-2 may include emitter-coupled transistors Q2A and Q2B biased by current source I2. In some embodiments, each of the differential pairs 410-1 and 410-2 may be a different instance of the differential pair 210 shown in FIG. 2.

Similar to the arrangement of multiplexer 300, either channel 1 or channel 2 may be coupled to the output of multiplexer 400A by selectively enabling current sources I1 and I2. To select channel 1, I1 may be activated when I2 is off. To select channel 2, I2 may be activated when I1 is off. Also similar to multiplexer 300, if I1 and I2 are activated at the same time, multiplexer 400A may also be configured to sum

channels

1 and 2, or both channels may be isolated from the output by turning off I1 and I2 at the same time. The transconductance of each differential pair may be set by a gain setting resistor in the emitter of each transistor. Multiplexer 400A may also be configured as a programmable gain amplifier by shorting input terminal IN1+ to IN2+ and IN 1-to IN2-, where each differential pair may have a different current gain.

Continuing further similarly to the illustration of fig. 3, analog signal multiplexer 400A may include a passive load 420, similar to load 220 described with reference to fig. 2. Accordingly, the passive load 420 may include two load elements (e.g., two resistors), shown in fig. 4A as resistors RLA and RLB. In sharp contrast to the illustration of FIG. 3, however, in analog signal multiplexer 400A, the collectors of terminals OUT-and Q1A and Q2A are not directly coupled to resistor RLA, while the collectors of terminals OUT + and Q1B and Q2B are not directly coupled to resistor RLB. In contrast, multiplexer 400A includes an additional pair of differential terminals shown as terminals TERM-and TERM +, and load resistors RLA and RLB may be coupled to terminals TERM-and TERM +, respectively. Load resistors RLA and RLB may be referred to as "unorganized" because they are not directly coupled to differential pair 410-1 and 410-2 and output terminals OUT + and OUT-. As shown below, the inclusion of such unorganized load resistors RLA and RLB enables one or more analog signal multiplexers 400A to be populated with a minimal number of additional components (if any).

Fig. 4B presents a scalable modular analog signal multiplexer 400B with a switching device 430 according to some embodiments of the present disclosure. The multiplexer 400B is similar to the multiplexer 400A shown in fig. 4A, and thus, for the sake of brevity, the description provided with reference to the multiplexer 400A is not repeated for the multiplexer 400B and only the differences are described. As shown in FIG. 4B, multiplexer 400B does not include the two additional terminals TERM + and TERM-included in multiplexer 400A. In contrast, passive load 420 is coupled to output terminals OUT + and OUT-of multiplexer 400B via switching device 430. The switching device 430 may include two switches S1 and S2. In some embodiments, switch S1 may be coupled between load resistor RLA and terminal OUT-, while switch S2 may be coupled between load resistor RLB and terminal OUT +, as shown in FIG. 4B. In other embodiments (not specifically shown in this figure), switch S1 may be coupled between load resistor RLA and a power supply (e.g., Vcc shown in fig. 4B), while switch S2 may be coupled between load resistor RLB and a power supply (e.g., Vcc shown in fig. 4B). Such a switch between the power source and the load may be particularly advantageous for high speed applications and/or for reliability reasons, such as a lower voltage may be available on the switch that is switched on. Although not specifically shown in the subsequent figures showing the switch, such a variation may be applied thereto. The switch arrangement 430 may be configured to couple the load 420 to the output terminals OUT + and OUT of the multiplexer 400B- (such as when the switches S1, S2 are closed), resulting in the multiplexer 400B being configured to function substantially as the multiplexer 300 shown in fig. 3, or to decouple the load 420 from the output terminals OUT + and OUT-leaving the load resistors RLA and RLB unopposed (as they are in the multiplexer 400A shown in fig. 4A).

In general,

multiplexers

400A and 400B may be described as being configured to operate in one of two modes. In the first mode, load 420 is coupled to the output of multiplexer 400A/400B, and in the second mode, load 420 is decoupled from the output of multiplexer 400A/400B. Multiplexer 400A may be configured to operate in a first mode when the additional output terminals TERM + and TERM-are coupled to output terminals OUT + and OUT- (e.g., as shown in fig. 5A or 5B), respectively. When the additional output terminals TERM + and TERM are not coupled to the output terminals OUT + and OUT- (e.g., as shown in fig. 4A), multiplexer 400A may be configured to operate in the second mode. When switching device 430 is in a configuration in which current may flow between load 420 and output terminals OUT + and OUT- (e.g., when the switches shown in fig. 4B are closed), multiplexer 400B may be configured to operate in a first mode. When switching device 430 is in a configuration in which current cannot flow between load 420 and output terminals OUT + and OUT- (e.g., when the switch shown in fig. 4B is open), multiplexer 400B may be configured to operate in a second mode.

Fig. 5A is a circuit diagram illustrating an assembly 500A according to some embodiments of the present disclosure, the assembly 500A using a single modular analog signal multiplexer having two channels, such as the multiplexer 400A shown in fig. 4A. As shown in fig. 5A, the single instance of the proposed scalable analog signal multiplexer 400A may also contain two additional series resistors, shown in component 500A as resistors RSA and RSB. In addition to or instead of the additional series resistors RSA and RSB, the assembly 500A may further comprise two additional parallel resistors, shown as resistors RPA and RPB. In general, in current mode, the outputs are left at the terminals OUT + and OUT-and comprise series resistors RSA and RSB and/or parallel resistors RPA and RPB to allow the values of these resistors to be modified in order to obtain a voltage output that may be desired for a particular application in terms of impedance, gain, power, etc. In general, the series resistors may be implemented to increase the effective resistance of the load resistors RLA and RLB, while the parallel resistors may be implemented to decrease the effective resistance of the load resistors RLA and RLB. For example, if RSA-RSB-0 (or a relatively small resistance) and RPA-RPB-infinity (or a relatively large resistance whose electrical characteristics may approach infinity), then terminal OUT-of component 500A is shorted to terminal TERM-and terminal OUT + is shorted to terminal TERM + (i.e., multiplexer 400A of component 500A is configured to operate in the first mode), and scalable analog signal multiplexer 400A within component 500A is equivalent to the multiplexer shown in fig. 3. On the other hand, if RSA and RSB have relatively large resistances (e.g., relatively large resistances, whose electrical characteristics may approach infinity), then terminal OUT-of component 500A is not coupled to terminal TERM-, and terminal OUT + is not coupled to terminal TERM + (i.e., multiplexer 400A of component 500A is configured to operate in the second mode), and scalable analog signal multiplexer 400A within component 500A is equivalent to the multiplexer shown in FIG. 4A. In some embodiments, some or all of the resistors RSA, RSB, RPA, RPB may be variable resistors, where their resistance may be varied to place the multiplexer 400A in the first mode of operation or the second mode of operation.

In other embodiments of a component using a single modular analog signal multiplexer with two channels (not specifically shown in this figure), terminal OUT-of multiplexer 400A may be shorted to terminal TERM-and terminal OUT + of multiplexer 400A may be shorted to terminal TERM + without the use of resistors as shown in component 500A.

Fig. 5B is a circuit diagram illustrating an assembly 500B according to other embodiments of the present disclosure, assembly 500B using a single modular analog signal multiplexer having two channels, such as multiplexer 400A shown in fig. 4A. The assembly 500B is similar to the assembly 500A shown in fig. 5A, and therefore, for the sake of brevity, the description provided with reference to the assembly 500A is not repeated for the assembly 500B, only the differences are described. As shown in fig. 5B, assembly 500B still includes the two additional terminals TERM + and TERM "included in assembly 500A, however, in contrast to assembly 500A, assembly 500B also includes switching device 530, and switching device 530 may include a plurality of switches, such as switches S3-S6 shown in fig. 5B. The switching device 530 is configured to selectively couple various ones of the additional series resistors RSA and RSB and the additional parallel resistors RPA and RPB to the output terminals OUT + and OUT-. For example, if RSA-RSB-0 (or a relatively small resistance) and RPA-RPB-infinity (or a relatively large resistance, the electrical characteristics of which may approach infinity), and switches S3-S6 are closed, then terminal OUT-of component 500A is shorted to terminal TERM-and terminal OUT + is shorted to terminal TERM + (i.e., multiplexer 400A of component 500A is configured to operate in the first mode), and scalable analog signal multiplexer 400A within component 500A is equivalent to the multiplexer shown in fig. 3. On the other hand, if switches S3 and S4 are open, then terminal OUT-of component 500A is not coupled to terminal TERM-and terminal OUT + is not coupled to terminal TERM +, and multiplexer 400A of component 500B is configured to operate in the second mode. Other possibilities of varying the values of resistors RSA, RSB, RPA, RPB, and the closed or open positions of switches S3-S6 are possible to configure multiplexer 400A of assembly 500B to operate in either the first mode or the second mode, all within the scope of the present disclosure. Similar to component 500A, in some embodiments, some or all of resistors RSA, RSB, RPA, RPB may be variable resistors, where their resistance may be varied to place multiplexer 400A of component 500B in either the first mode of operation or the second mode of operation.

Fig. 5C is a circuit diagram illustrating an assembly 500C according to other embodiments of the present disclosure, the assembly 500C using a single modular analog signal multiplexer having two channels, such as the multiplexer 400B shown in fig. 4B. The assembly 500C is similar to the assembly 500B shown in fig. 5B, and therefore, for the sake of brevity, the description provided with reference to the assembly 500B is not repeated for the assembly 500C, only the differences are described. Similar to assembly 500B, assembly 500C includes a switching device 530. However, in contrast to component 500B, where the multiplexer is multiplexer 400A of fig. 4A, the multiplexer of component 500C is multiplexer 400B of fig. 4B. Thus, the assembly 500C may be viewed as a combination of the embodiment shown in fig. 4B and the embodiment shown in fig. 5B, and the combination of the explanations provided with reference to these figures applies to the assembly 500C shown in fig. 5C. Various possibilities of varying the values of resistors RSA, RSB, RPA, RPB, and the closed or open positions of switches S1-S2 of switching device 430 and switches S3-S6 of switching device 530 are possible to configure multiplexer 400B of assembly 500C to operate in either the first mode or the second mode, all within the scope of the present disclosure.

4A-4B and 5A-5C illustrate some exemplary embodiments of modular analog signal multiplexers 400A/400B, changes may be made to multiplexers 400A/400B without departing from the general concepts set forth herein, and all embodiments of such changes are intended to be encompassed within the broad scope of the present disclosure. Some of these variations will now be described.

The multiplexers 400A/400B shown in FIGS. 4A-4B and 5A-5C illustrate differential pairs 410-1 and 410-2, since a differential pair is one of the most common output stages. However, in other embodiments of multiplexers 400A/400B, each of differential pairs 410-1 and 410-2 may be replaced with a current mirror output stage. Such an embodiment may be more preferable when, for example, the output swing needs to be maximized at low supply voltages. Fig. 6A shows a differential amplifier 600A as an example of an output stage in which a differential current mirror 610 is used. The differential amplifier 600A is similar to the differential amplifier 200 shown in fig. 2, except that the differential pair 210 is replaced with a differential current mirror 610. As shown in FIG. 6A, differential current mirror 610 may include two current mirrors — a first current mirror formed by transistors Q10A and Q1A and driven by input current IIN1, a second current mirror formed by transistors Q10B and Q1B and driven by input current IIN1+, where currents IIN 1-and IIN1+ are differential input currents (i.e., one of currents IIN 1-and IIN1+ may be based on a difference of bias current IB and input current IIN1, and the other of currents IIN 1-and IIN1+ may be based on a sum of bias current IB and input current IIN 1). Currents IIN + and IIN-may be output currents from, for example, a differential pair, a current mirror, or any other component that may provide differential currents IIN + and IIN-. In some embodiments, for gain G, the ratio of the emitter area of transistor Q1A to the emitter area of Q10A is G:1, and the ratio of the emitter area of transistor Q1B to the emitter area of Q10B may be G:1 (in this disclosure, it is assumed that all components denoted as a and B are substantially the same, e.g., Q10A and Q10B).

In various variations of the embodiment of the multiplexer 400A/400B (e.g., in various embodiments as shown in FIGS. 4A-4B or FIGS. 5A-5C), each of the differential pairs 410-1 and 410-2 may be replaced with a respective differential current mirror 610 as described above. For example, FIG. 6B shows an analog signal multiplexer 600B, which is similar to multiplexer 400A shown in FIG. 4A, except that instead of implementing output stages 410-1 and 410-2 as differential pairs, multiplexer 600B employs differential current mirrors 610-1 and 610-2 (i.e., two different instances of differential current mirror 610 as described above), since it includes a load 420 coupled to additional terminals TERM-and TERM +, as described above. Thus, the multiplexer 600B may be considered as a combination of the embodiment shown in fig. 4A and the embodiment shown in fig. 6A, and the combination of the explanations provided with reference to these figures applies to the multiplexer 600B shown in fig. 6B. The description of how to operate multiplexer 400A in either the first mode or the second mode applies to multiplexer 600B and, therefore, is not repeated for the sake of brevity. In another example, FIG. 6C shows an analog signal multiplexer 600C, which is similar to multiplexer 400B shown in FIG. 4B in that it includes a load 420 coupled to switching device 430 as described above, except that instead of implementing output stages 410-1 and 410-2 as a differential pair, multiplexer 600C employs differential current mirrors 610-1 and 610-2 (i.e., two different instances of differential current mirror 610 as described above). Thus, the multiplexer 600C may be considered as a combination of the embodiment shown in fig. 4B and the embodiment shown in fig. 6A, and the combination of the explanations provided with reference to these figures applies to the multiplexer 600C shown in fig. 6C. The description of how to operate multiplexer 400B in either the first mode or the second mode applies to multiplexer 600C and, therefore, is not repeated for the sake of brevity.

Although not specifically shown in this figure, embodiments of the assemblies 500A-500C as shown in FIGS. 5A-5C (but wherein the differential pairs 410-1 and 410-2 are replaced by differential current mirrors 610-1 and 610-2) are possible and within the scope of the present disclosure.

Continuing with the variations of the various embodiments of multiplexers 400A/400B and 600B/600C and the embodiments of any of these multiplexers included in any of the components described with reference to FIGS. 5A-5C, in this disclosure, for simplicity, the differential pairs or differential current mirrors shown in the figures do not explicitly show the resistors at the emitters of the transistors employed in these circuit blocks. However, in a further variation, one or more resistors may be coupled to the emitter of any of these transistors. For example, in various embodiments of multiplexers 400A/400B and 600B/600C, and in embodiments of any of these multiplexers included in any of the components described with reference to FIGS. 5A-5C, the transconductance of each differential pair 410 or differential current mirror 610 may be set by a gain setting resistor in the emitter of each transistor of the differential pair 410 or differential current mirror 610.

Although the various embodiments of multiplexers 400A/400B and 600B/600C show examples with two input channels and one differential output OUT +, OUT-, in other embodiments, any of multiplexers 400A/400B and/or 600B/600C and embodiments of any of these multiplexers included in any of the components described with reference to FIGS. 5A-5C may include more than two input channels and a plurality of differential outputs OUT +, OUT-, so long as the number of outputs is less than the number of inputs. Furthermore, in other embodiments, any of multiplexers 400A/400B and 600B/600C (possibly in any of the components shown in FIGS. 5A-5C) as described above may contain only one input channel (i.e., only one differential pair 410 or differential current mirror 610).

Furthermore, the various embodiments of multiplexers 400A/400B and 600B/600C, as well as embodiments of any of these multiplexers included in any of the components described with reference to FIGS. 5A-5C, may have additional passive and/or active components to set or adjust a desired common mode output voltage, e.g., to match the input common mode of the ADC. Additional parallel resistors RPA and RPB may also be coupled to a supply voltage greater than Vcc to allow high voltage operation beyond the multiplexer's supply Vcc.

Continuing with variations on the various embodiments of multiplexers 400A/400B and 600B/600C and the embodiment of any of these multiplexers included in any of the components described with reference to FIGS. 5A-5C, moreover, although the illustrations of FIGS. 4A-4B, 5A-5C, and 6A-6C are provided for circuits employing bipolar transistors, these illustrations may be readily applied to circuits employing FETs or a combination of bipolar and FET technologies. Furthermore, although some of the illustrations may refer to N-type transistors (e.g., NPN transistors for those implemented using bipolar technology or NMOS transistors for those implemented as FETs), the illustrations may be readily applied to circuits employing P-type transistors (e.g., PNP transistors for those implemented using bipolar technology or PMOS transistors for those implemented as FETs) instead of N-type transistors, and vice versa. Accordingly, all such variations are within the scope of the present disclosure. In some embodiments, Vee shown in this figure may be replaced with any negative supply voltage for a complementary version of multiplexer M (e.g., when all N-type transistors are replaced with P-type transistors).

Arranging a plurality of modular analog signal multiplexers together

Further embodiments of the analog signal multiplexers shown in fig. 4A-4B, fig. 5A-5C, and fig. 6A-6C, as well as in these figures as described herein, all involve a single instance of a multiplexer. In further embodiments, any of the multiplexers described above may be combined with any other multiplexer, all of which are within the scope of the present disclosure. Some examples of such combinations are shown in fig. 7A-7E.

Fig. 7A is a circuit diagram illustrating an assembly 700A using a combination of two modular analog signal multiplexers, according to some embodiments of the present disclosure. In particular, assembly 700A shows two multiplexers 400A-1 and 400A-2, each of the two multiplexers 400A-1 and 400A-2 being a different instance of multiplexer 400A shown in FIG. 4A, where the different reference numbers used in FIG. 4A have not been used in FIG. 7A in order not to clutter the drawing. The description of how to operate any multiplexer 400A in either the first mode or the second mode applies to multiplexers 400A-1 and 400A-2 of component 700A and, therefore, is not repeated for the sake of brevity.

Component 700A illustrates an example of how identical scalable analog signal multiplexers 400A (e.g., each having two channels) (multiplexers 400A-1 and 400A-2 are denoted as M1 and M2, respectively) may be combined to construct a component 700A that provides a four-channel multiplexer. In general, any number N of multiplexers 400A (e.g., N may be an integer greater than or equal to 1) may be combined, with each multiplexer 400A containing any number K of channels (e.g., K may be an integer greater than or equal to 1) to provide a component that is an N x K channel multiplexer. In such an assembly, the load resistors of one of the N multiplexers 400A may be used as a common load, while the load resistors of the remaining (N-1) multiplexers 400A may remain electrically floating (i.e., not connected to the output terminals). In assembly 700A, load resistors RLA and RLB of multiplexer 400A-1 serve as a common load, while load resistors RLA and RLB of multiplexer 400A-2 are not connected to output terminals OUT-and OUT + and may remain floating. In assembly 700A, additional terminal TERM-of multiplexer 400A-1 can be coupled (e.g., shorted as shown in FIG. 7A) to the OUT-terminal of multiplexer 400A-1 and to the OUT-terminal of multiplexer 400A-2. In addition, the additional terminal TERM + terminal of multiplexer 400A-1 may be coupled (e.g., shorted as shown in FIG. 7A) to the OUT + terminal of multiplexer 400A-1 and the OUT + terminal of multiplexer 400A-2. Although not specifically shown in FIG. 7A, in other embodiments of assembly 700A, one or more resistors or other circuit elements may be used to couple the additional terminal TERM-of multiplexer 400A-1 to the OUT-terminal of multiplexer 400A-1 and the OUT-terminal of multiplexer 400A-2, and/or one or more resistors or other circuit elements may be used to couple the additional terminal TERM + of multiplexer 400A-1 to the OUT + terminal of multiplexer 400A-1 and the OUT + terminal of multiplexer 400A-2.

In component 700A, selective activation of current sources in each of the analog signal multiplexers may be used to couple or isolate any input channel from the output. To select channel 1 of M1, I1 of M1 may be activated while all other current sources of M1 and M2 are turned off. To select channel 2 of M1, I2 of M1 may be activated while all other current sources of M1 and M2 are turned off. To select channel 1 of M2, I1 of M2 may be activated while all other current sources of M1 and M2 are turned off. To select channel 2 of M2, I2 of M2 may be activated while all other current sources of M1 and M2 are turned off. The multiplexers of assembly 700A may also be configured to sum any combination of

channels

1 and 2 of any of multiplexers M1 and M2 by selectively activating multiple respective current sources at the same time, or to isolate all channels from the output by turning off I1 and I2 of multiplexers M1 and M2 at the same time, similar to the function described with reference to fig. 3.

Fig. 7B is a circuit diagram illustrating an assembly 700B using another combination of two modular analog signal multiplexers, according to some embodiments of the present disclosure. In particular, assembly 700B shows two multiplexers 400B-1 and 400B-2, each of the two multiplexers 400B-1 and 400B-2 being a different instance of multiplexer 400B shown in FIG. 4B, where the different reference numbers used in FIG. 4B have not been used in FIG. 7B in order not to clutter the drawing. The assembly 700B may be viewed as a combination of the embodiment shown in fig. 4B and the embodiment shown in fig. 7A, and the combination of the explanations provided with reference to these figures applies to the assembly 700B shown in fig. 7B. The description of how to operate any multiplexer 400B in either the first mode or the second mode applies to multiplexers 400B-1 and 400B-2 of component 700B and, therefore, is not repeated for the sake of brevity.

Fig. 7C is a circuit diagram illustrating an assembly 700C using yet another combination of two modular analog signal multiplexers, according to some embodiments of the present disclosure. In particular, assembly 700C shows two multiplexers 400A-1 and 400A-2, each of the two multiplexers 400A-1 and 400A-2 being a different instance of multiplexer 400A shown in FIG. 4A, but wherein multiplexer 400A-1 is contained within assembly 500A, as shown in FIG. 5A, wherein the different reference numbers used in FIG. 4A and FIG. 5A are not used in FIG. 7C in order not to obfuscate the drawing. The assembly 700C may be considered a combination of the embodiment shown in fig. 5A and the embodiment shown in fig. 7A, and the combination of the explanations provided with reference to these figures applies to the assembly 700C shown in fig. 7C. The description of how to operate any multiplexer 400A in either the first mode or the second mode applies to multiplexers 400A-1 and 400A-2 of component 700C and, therefore, is not repeated for the sake of brevity.

Fig. 7D is a circuit diagram illustrating an assembly 700D using yet another combination of two modular analog signal multiplexers, according to some embodiments of the present disclosure. In particular, assembly 700D shows two multiplexers 400A-1 and 400A-2, each of the two multiplexers 400A-1 and 400A-being a different instance of multiplexer 400A shown in FIG. 4A, but where multiplexer 400A-1 is contained within assembly 500B, as shown in FIG. 5B, where the different reference numbers used in FIGS. 4A and 5B are not used in FIG. 7D in order not to obfuscate the drawing. The assembly 700D may be viewed as a combination of the embodiment shown in fig. 5B and the embodiment shown in fig. 7A, and the combination of the explanations provided with reference to these figures applies to the assembly 700D shown in fig. 7D. The description of how to operate any multiplexer 400A in either the first mode or the second mode applies to multiplexers 400A-1 and 400A-2 of component 700D and, therefore, is not repeated for the sake of brevity.

Fig. 7E is a circuit diagram illustrating a component 700E using yet another combination of two modular analog signal multiplexers, according to some embodiments of the present disclosure. In particular, assembly 700E shows two multiplexers 400B-1 and 400B-2, each of the two multiplexers 400B-1 and 400B-2 being a different instance of multiplexer 400B shown in FIG. 4B, but with multiplexer 400B-1 being included in a first instance 500C-1 of assembly 500C, as shown in FIG. 5C, and multiplexer 400B-2 being included in a first instance 500C-2 of assembly 500C, wherein the different reference numbers used in FIGS. 4B and 5C are not used in FIG. 7E in order not to obfuscate the drawings. The assembly 700E may be viewed as a combination of the embodiment shown in fig. 5C and the embodiment shown in fig. 7A, and the combination of the explanations provided with reference to these figures applies to the assembly 700E shown in fig. 7E. The description of how to operate any multiplexer 400B in either the first mode or the second mode applies to multiplexers 400B-1 and 400-2 of component 700E and, therefore, is not repeated for the sake of brevity.

Still further combinations of the various embodiments of the analog signal multiplexer described herein are possible based on the foregoing description and are within the scope of the present disclosure.

In view of the above, an output stage is disclosed that is suitable for high bandwidth signaling across a standard Printed Circuit Board (PCB), facilitating a simple construction of a high speed LIDAR receiver. Multiple instances of the proposed output stage may be combined, for example, to construct an N:1 multiplexer without the presence of additional components in the signal path, while maintaining low noise and high bandwidth. The proposed modular analog signal multiplexer provides a simple way to extend the number of channels in the system. If the instances of the multiplexer are contained in separate Integrated Circuits (ICs), multiple instances may be combined on a circuit board to build a multiplexer with a higher number of channels. In other embodiments, multiple instances of the multiplexer may be contained in a single IC.

Exemplary System

The modular analog signal multiplexer described herein may be used in any type of system. Fig. 8 illustrates one example of such a system, which provides a block diagram of an exemplary laser ranging (e.g., LIDAR) system 800 according to some embodiments of the present disclosure, the system 800 may include one or more modular analog signal multiplexers for differential signals as described herein. As shown in fig. 8, system 800 may include a transmitter signal chain 810, a receiver signal chain 830, a processor 850, and a controller 860. In some cases, receiver signal chain 830 may be implemented separately from transmitter signal chain 810. As shown in fig. 8, the transmitter signal chain 810 may include a digital-to-analog converter (DAC)812, a Low Pass Filter (LPF)814, a Programmable Gain Amplifier (PGA)816, a laser driver 818, and a laser 820. Receiver chain 830 may contain optical sensors such as Photodiodes (PD)832, transimpedance amplifiers (TIAs) 834, LPFs 836, analog-to-digital converter (ADC) drivers 838, and ADCs 840. In some cases, the receiver chain may include a PGA coupled between TIA834 and LPF 836. Such a PGA may be implemented instead of or in addition to the ADC driver 838.

The processor 850 may be configured to generate a digital signal indicating that laser pulses are to be emitted by the laser 820. The digital signal from the processor 850 may then be converted to an analog signal by the DAC 812, further processed by the optional LPF 814, amplified by the PGA 816, and provided to the laser driver 818. In some embodiments, laser 820 may be a laser diode, such as an inductively resonant laser diode.

Light emitted by the laser 820 may reach an object or target and the reflected light may be received by an optical sensor 832 of the receiver signal chain 830. Thus, the reflected light may be detected at the optical sensor 832. For example, the optical sensor 832 may be an Avalanche Photodiode (APD). The optical sensor 832 may generate current pulses indicative of the received reflected light, and the current pulses may be converted to voltage pulses by the TIA834 and, optionally, further processed by the LPF 836. In some embodiments, LPF 836 may be a tunable filter. As shown, an LPF 836 may be coupled in the signal path between TIA834 and ADC driver 838. In some other implementations, the LPF 836 may be coupled in the signal path between the ADC driver 838 and the ADC 840. The ADC driver 838 may generate a drive signal based on the output of TIA834 to drive the ADC 840. The ADC 840 may convert the received drive signal to a digital signal for further processing by the processor 850. Although not specifically shown in fig. 8, ADC 840 may be shared between multiple receiver chains with PDs 832 and TIAs 834, where any of the embodiments of modular analog signal multiplexers described herein may be used to perform signal multiplexing to receive input signals indicative of the outputs of multiple TIAs and to provide an output signal that will later be the basis for the input signal to ADC 840.

In some embodiments, processor 850 may be a hardware processor. In some embodiments, processor 850 may be a baseband digital signal processor. In some embodiments, processor 850 may determine the distance between the object and laser ranging system 800. In some embodiments, processor 850 may output a signal indicative of the determined distance. In some embodiments, the processor 850 may identify an object from which the pulse of light reflected from the object is based at least in part on the width of the pulse generated by the TIA 834. In some embodiments, processor 850 may output data identifying the object. In some embodiments, one instance of processor 850 may be associated with receiver signal chain 830 and another instance of processor 850 may be associated with transmitter signal chain 810.

The controller 860 may be used to control various aspects of the system 800, and in particular, aspects of the present disclosure relate to implementing a modular analog signal multiplexer as described herein. For example, controller 860 may generate control signals that control the operation of various elements of an analog signal multiplexer, as well as components of such a multiplexer as described herein. In some embodiments, controller 860 may be implemented as a data processing system as shown in FIG. 9.

Fig. 9 provides a block diagram illustrating an example data processing system 900, which example data processing system 900 may be configured to implement or control at least a portion of any embodiment implementing a modular analog signal multiplexer as described herein, according to some embodiments of the present disclosure. For example, in some embodiments, controller 860 may be implemented as data processing system 900.

As shown in FIG. 9, the data processing system 900 may include at least one processor 902, such as a hardware processor 902, the at least one processor 902 coupled to memory elements 904 through a system bus 906. In this manner, the data processing system can store program code in the memory element 904. Further, the processor 902 may execute program code accessed from the memory element 904 via the system bus 906. In one aspect, a data processing system may be implemented as a computer adapted to store and/or execute program code. It should be understood, however, that data processing system 900 may be implemented in the form of any system including a processor and memory capable of performing the functions described in this disclosure.

In some embodiments, processor 902 may execute software or algorithms to perform the activities discussed in this specification, particularly the activities associated with the modular analog signal multiplexer described herein. Processor 902 may include any combination of hardware, software, or firmware that provides programmable logic, including a microprocessor, Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), Programmable Logic Array (PLA), application specific Integrated Circuit (IC) (ASIC), or virtual machine processor, as non-limiting examples. Processor 902 may be communicatively coupled to memory element 904, for example in a Direct Memory Access (DMA) configuration, such that processor 902 may read from or write to memory element 904.

In general, memory element 904 may comprise any suitable volatile or non-volatile memory technology, including Double Data Rate (DDR) Random Access Memory (RAM), Synchronous RAM (SRAM), Dynamic RAM (DRAM), flash memory, Read Only Memory (ROM), optical media, virtual memory, magnetic or tape memory, or any other suitable technology. Unless otherwise specified, any storage element discussed herein should be construed as being encompassed within the broad term "memory. Information measured, processed, tracked, or sent to or from any component of data processing system 900 may be provided in any database, register, control list, cache, or storage structure, all of which may be referenced at any suitable time frame. Any such storage options may be included in the broad term "memory" as used herein. Similarly, any potential processing elements, modules, and machines described herein should be construed as being encompassed within the broad term "processor. Each of the elements shown in this figure (e.g., any of the circuits/components of the modular analog signal multiplexer described herein) may also contain appropriate interfaces for receiving, transmitting, and/or otherwise communicating data or information in a network environment so that they may communicate with, for example, a data processing system 900 of another of these elements.

In certain example embodiments, the mechanisms associated with a modular analog signal multiplexer as outlined herein may be implemented by logic encoded in one or more tangible media, which may include non-transitory media, such as in an ASIC, embedded logic provided in DSP instructions, software (possibly including object code and source code) executed by a processor or other similar machine, and so forth. In some of these examples, a memory element (such as memory element 904 shown in fig. 9) may store data or information for the operations described herein. This includes memory elements capable of storing software, logic, code, or processor instructions that are executed to perform the activities described herein. A processor may execute any type of instructions associated with data or information to implement the operations detailed herein. In one example, a processor (such as processor 902 shown in FIG. 9) may transform an element or article (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein may be implemented with fixed logic or programmable logic (e.g., software/computer instructions executed by a processor) and the elements identified herein could be some type of a programmable processor, programmable digital logic (e.g., an FPGA, a DSP, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM)), or an ASIC that contains digital logic, software, code, electronic instructions, or any suitable combination thereof.

Memory element 904 may include one or more physical memory devices, such as local memory 908 and one or more mass storage devices 910. Local memory may refer to RAM or other volatile memory devices that are typically used during actual execution of the program code. The mass storage device may be implemented as a hard disk drive or other persistent data storage device. The processing system 900 may also include one or more cache memories (not shown) that provide temporary storage of at least some program code in order to reduce the number of times program code must be retrieved from the mass storage device 910 during execution.

As shown in fig. 9, the memory element 904 may store an application 918. In various embodiments, the application 918 may be stored in the local memory 908, the one or more mass storage devices 910, or separate from the local memory and mass storage devices. It is to be appreciated that data processing system 900 may further execute an operating system (not shown in FIG. 9) that may facilitate execution of applications 918. Applications 918 embodied in the form of executable program code may be executed by the data processing system 900, for example, by the processor 902. In response to executing the application, data processing system 900 may be configured to perform one or more operations or method steps described herein.

Input/output (I/O) devices, depicted as input device 912 and output device 914, may optionally be coupled to the data processing system. Examples of input devices may include, but are not limited to, a keyboard, a pointing device such as a mouse, and the like. Examples of output devices may include, but are not limited to, a monitor or display, speakers, and the like. In some embodiments, output device 914 may be any type of screen display, such as a plasma display, a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an Electroluminescent (EL) display, or any other indicator, such as a dial, a barometer, or an LED. In some embodiments, the system may include a driver (not shown) for the output device 914. The input and/or

output devices

912, 914 may be coupled to the data processing system either directly or through intervening I/O controllers.

In an embodiment, the input and output devices may be implemented as a combined input/output device (shown in fig. 9 with a dashed line around input device 912 and output device 914). Examples of such combined devices are touch sensitive displays, sometimes also referred to as "touch screen displays" or simply "touch screens". In such embodiments, input to the device may be provided by movement of a physical object (such as a user's stylus or finger) on or near the touch screen display.

Optionally, a network adapter 916 may also be coupled to the data processing system to enable it to be coupled to other systems, computer systems, remote network devices, and/or remote storage devices through intervening private or public networks. A network adapter may include a data receiver for receiving data transmitted by the system, device, and/or network to data processing system 900 and a data transmitter for transmitting data from data processing system 900 to the system, device, and/or network. Modems, cable modem and Ethernet cards are examples of different types of network adapters that may be used with data processing system 900.

Fig. 10 provides an illustration 1000 of a LIDAR system integrated with an automobile, in accordance with some embodiments of the present disclosure. This is an exemplary application in which any of the modular analog signal multiplexers described herein may be implemented. Fig. 10 shows two

LIDAR systems

1002 and 1004 integrated with an automobile 1006. The first LIDAR system 1002 may be located near a right front light of the automobile 1006 and the second LIDAR system 1004 may be located near a left front light of the automobile 1006. As described herein, the LIDAR systems 1002 and/or 1004 may implement any suitable principles of modular analog signal multiplexers. In some embodiments, any of the LIDAR systems 1002 and/or 1004 may include an ADC 840 shared with the PD 832 and the TIA834 between multiple receiver chains, where any of the modular analog signal multiplexers described herein may be used to perform signal multiplexing to receive input signals indicative of multiple TIA outputs and to provide an output signal that will later be the basis for the input signal to the ADC 840. In other embodiments, each of the LIDAR systems 1002 and/or 1004 may include a LIDAR receiver chain 830 as shown in fig. 8, where the ADC 840 of the LIDAR systems 1002 and/or 1004 may be shared between these systems using any of the modular analog signal multiplexers described herein. The LIDAR systems 1002 and/or 1004 may detect a distance between the car 1006 and the object 1008.

As shown, the emitter of the LIDAR system 1002 may emit a pulse of light 1010 at an angle 1012. At least some of the pulses of light 1010 may be generated by a laser diode (e.g., laser diode 820 shown in fig. 8). The transmitted light 1010 may pass through the air and reach the object 1008. The object 1008 may reflect the pulse of light 1014 back to the receiver of the LIDAR system 1002. Embodiments discussed herein may generate information identifying object 1008. The pulses of light 1010 may be transmitted in three dimensions to obtain three dimensional information of the surrounding environment.

One or more additional LIDAR systems may be integrated with the automobile 1006 to cover a greater range of detection areas and/or to obtain additional information about selected areas. In some embodiments, the data collected by each LIDAR system may be combined to analyze information from a wider area and/or to provide additional information about the selected area. In some embodiments, angle 1012 may be adjusted, and angle 1012 may be within any suitable range.

The illustrations of fig. 8 and 10 provide only some non-limiting examples in which the modular analog signal multiplexers described herein may be used as described herein. In other embodiments, any of the modular analog signal multiplexers described herein may be implemented in systems other than the LIDAR systems shown in fig. 8 and 10. The various teachings described herein relating to modular analog signal multiplexers are applicable to a wide variety of other systems. In some cases, various embodiments of a modular analog signal multiplexer as described herein may be used in automotive systems, safety critical industrial applications, medical systems, scientific instrumentation, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which may be highly accurate), and various digital processing based systems. In other instances, various embodiments of a modular analog signal multiplexer as described herein may be used in an industrial market that includes process control systems that facilitate increased productivity, energy efficiency, and reliability. In still other cases, various embodiments of modular analog signal multiplexers may be used for consumer applications.

Selection example

The following paragraphs provide examples of the various embodiments disclosed herein.

Example a1 provides an analog signal multiplexer that includes additional differential outputs with terminals TERM + and TERM-.

Example a2 provides an output stage that includes an analog signal multiplexer that includes additional differential outputs with terminals TERM + and TERM-.

Example A3 provides an output stage according to example a2, wherein the output stage includes coupling between components as shown in fig. 4A.

Example a4 provides an output stage according to example a2, wherein the output stage includes coupling between components as shown in fig. 5A.

Example a5 provides an output stage according to example a2, wherein the output stage includes coupling between components as shown in fig. 7A.

Example a6 provides an output stage according to example a2, wherein the output stage includes coupling between components as shown in any of fig. 4-6, but the differential pair is replaced with a differential current mirror.

Example a7 provides an electronic component including an analog signal multiplexer and/or an output stage according to any preceding example.

Example A8 provides the electronic component according to example a7, wherein the electronic component is a TIA or ADC driver.

Example a9 provides the electronic component according to example a7, wherein the electronic component is a LIDAR receiver.

Example B1 provides a signal multiplexer device, the signal multiplexer device including: a first signal multiplexer comprising a load and an output stage, wherein an input of the output stage of the first signal multiplexer is coupled to a first input of the signal multiplexer means, and wherein an output of the output stage of the first signal multiplexer is coupled to an output of the first signal multiplexer; and a second signal multiplexer comprising a load and an output stage, wherein an input of the output stage of the second signal multiplexer is coupled to the first input of the signal multiplexer means, and wherein an output of the output stage of the second signal multiplexer is coupled to an output of the second signal multiplexer. The output of the first signal multiplexer is coupled to the output of the second signal multiplexer, the load of the first signal multiplexer is coupled to the output of the first signal multiplexer (and thus also to the output of the second signal multiplexer), and the load of the second signal multiplexer is decoupled from the output of the first signal multiplexer and the output of the second signal multiplexer. In such an example, the output stage of the first signal multiplexer and the output stage of the second signal multiplexer are coupled to a load of the first signal multiplexer.

Example B2 provides the signal multiplexer device of example B1, wherein the load of the second signal multiplexer is electrically floating (i.e., not coupled to any potential).

Example B3 provides the signal multiplexer device of example B1 or B2, wherein the output stage of the first signal multiplexer is a first output stage, the output stage of the second signal multiplexer is a second output stage, the first signal multiplexer further including a third output stage, wherein an input of the third output stage is coupled to a third input of the signal multiplexer device, and wherein an output of the third output stage is coupled to an output of the first signal multiplexer, and the second signal multiplexer further including a fourth output stage, wherein an input of the fourth output stage is coupled to a fourth input of the signal multiplexer device, and wherein an output of the fourth output stage is coupled to an output of the second signal multiplexer. In such an example, all four output stages of the first and second signal multiplexers are coupled to the load of the first signal multiplexer.

Example B4 provides the signal multiplexer apparatus of example B3, wherein each of the first, second, third, and fourth output stages is configured to provide an output signal at an output of the output stage indicative of an input signal received at an input of the output stage when the bias signal is provided to the output stage.

Example B5 provides a signal multiplexer device according to any one of examples B1-B4, wherein at least one of the output stages includes a differential pair.

Example B6 provides a signal multiplexer device according to any one of examples B1-B4, wherein at least one of the output stages includes a differential current mirror.

Example B7 provides a signal multiplexer device, the signal multiplexer device including: a first signal multiplexer comprising a load and an output stage, wherein an input of the output stage of the first signal multiplexer is coupled to a first input of the signal multiplexer means, and wherein an output of the output stage of the first signal multiplexer is coupled to an output of the first signal multiplexer; a second signal multiplexer comprising a load and an output stage, wherein an input of the output stage of the second signal multiplexer is coupled to the first input of the signal multiplexer means, wherein an output of the output stage of the second signal multiplexer is coupled to an output of the second signal multiplexer, and wherein an output of the first signal multiplexer is coupled to an output of the second signal multiplexer; and a switching device comprising one or more switches configured to couple or decouple a load of the first signal multiplexer and an output of the first signal multiplexer. In such an example, when the switching device couples the load of the first signal multiplexer and the output of the first signal multiplexer, the output stage of the first signal multiplexer and the output stage of the second signal multiplexer are coupled to the load of the first signal multiplexer.

Example B8 provides the signal multiplexer device of example B7, wherein the switching device is a first switching device, and the signal multiplexer device further comprises a second switching device comprising one or more switches configured to couple or decouple a load of the second signal multiplexer and an output of the second signal multiplexer. In such an example, the output stage of the first signal multiplexer and the output stage of the second signal multiplexer are coupled to the load of the first signal multiplexer when the first switching device couples the load of the first signal multiplexer and the output of the first signal multiplexer or the second switching device couples the load of the second signal multiplexer and the output of the second signal multiplexer.

Example B9 provides the signal multiplexer device of example B8, wherein the first switch device and the second switch device are configured such that: the second switching device decouples the load of the second signal multiplexer and the output of the second signal multiplexer when the first switching device couples the load of the first signal multiplexer and the output of the first signal multiplexer, and the first switching device decouples the load of the first signal multiplexer and the output of the first signal multiplexer when the second switching device couples the load of the second signal multiplexer and the output of the second signal multiplexer.

Example B10 provides the signal multiplexer device of any one of examples B7-B9, wherein the load of the second signal multiplexer is electrically floating (i.e., not coupled to any potential) when the first switch device couples the load of the first signal multiplexer and the output of the first signal multiplexer.

Example B11 provides a signal multiplexer comprising a load and an output stage, having an input coupled to an input of the signal multiplexer, and having an output coupled to an output of the signal multiplexer, wherein at different times the signal multiplexer is configured to operate in a first mode in which the load is coupled to the output of the signal multiplexer, or in a second mode in which the load is not coupled to the output of the signal multiplexer.

Example B12 provides the signal multiplexer of example B11, wherein the output stage is a first output stage, the input of the signal multiplexer is a first input of the signal multiplexer, the signal multiplexer further comprising a second output stage having an input coupled to a second input of the signal multiplexer, and having an output coupled to the output of the signal multiplexer. In such an example, the first output stage and the second output stage have outputs coupled to the same output of the signal multiplexer, which may be coupled to a load (in the first mode) or not coupled to a load (in the second mode). Thus, in the first mode, the respective outputs of the first and second output stages are coupled to the load, while in the second mode, the respective outputs of the first and second output stages are decoupled from the load.

Example B13 provides the signal multiplexer of example B12, further comprising a first bias signal source configured to provide a bias signal to the first output stage; and a second bias signal source configured to provide a bias signal to the second output stage, wherein the signal multiplexer is configured to provide (output) at an output of the signal multiplexer a signal indicative of the input signal received at the first input of the signal multiplexer when the first bias signal source provides the bias signal to the first output stage, and the signal multiplexer is configured to provide (output) at an output of the signal multiplexer a signal indicative of the input signal received at the second input of the signal multiplexer when the second bias signal source provides the bias signal to the second output stage.

Example B14 provides the signal multiplexer of example B13, wherein the signal multiplexer is configured to provide (output) at the output of the signal multiplexer as a signal indicative of a combination of a signal of the input signal received at the first input of the signal multiplexer and a signal indicative of the input signal received at the second input of the signal multiplexer when the first bias signal source provides the bias signal to the first output stage and the second bias signal source provides the bias signal to the second output stage.

Example B15 provides the signal multiplexer of any one of examples B11-B14, further including a switching device including one or more switches configured to change a coupling between a load and an output of the signal multiplexer to place the signal multiplexer in the first mode of operation or the second mode of operation.

Example B16 provides the signal multiplexer of any one of examples B11-B15, wherein the output of the signal multiplexer is a first output, and the signal multiplexer further includes a second output separate from the first output, wherein a load is coupled to the second output; and a resistor arrangement comprising one or more resistive elements configured to change the coupling between the load and the output of the signal multiplexer to place the signal multiplexer in a first mode of operation or in a second mode of operation, wherein in the first mode the resistor arrangement couples the second output and the first output (thereby coupling the load and the first output of the signal multiplexer) and in the second mode the resistor arrangement decouples the second output and the first output (thereby decoupling the load and the first output of the signal multiplexer).

Example B17 provides the signal multiplexer of any one of examples B11-B16, wherein the input of the output stage is a differential input, each of the output stage and the output of the signal multiplexer is a differential output, and in the first mode, the load is coupled to the output of the signal multiplexer via a differential connection.

Example B18 provides a signal multiplexer according to example B17, wherein the inputs of the signal multiplexer are differential inputs.

Example B19 provides the signal multiplexer of example B17, wherein the input of the signal multiplexer is a single-ended input, and the signal multiplexer further comprises a single-ended to differential converter configured to convert a signal provided to the signal multiplexer through the single-ended input of the signal multiplexer into a differential signal to be provided to the input of the output stage.

Example B20 provides a signal multiplexer according to any one of examples B11-B19, wherein the output stage includes a differential pair or a differential current mirror.

Example B21 provides an electronic component comprising a signal multiplexer, an output stage, or a signal multiplexer device according to any of the preceding examples.

Example B22 provides the electronic component according to example B21, wherein the electronic component is a TIA or ADC driver.

Example B23 provides the electronic component according to example B21, wherein the electronic component is a LIDAR receiver.

Example B24 provides a method including steps carried out by a system or apparatus according to any of the preceding examples.

Example B25 provides a method comprising the step of causing a system to operate in accordance with any of the preceding examples.

Example B26 provides a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to carry out at least some portions of the method according to any one of examples B24-B25.

Example B27 provides a computer program product including instructions that, when executed by a processor, cause the processor to carry out at least some portions of the method according to any one of examples B24-B25.

Description of other embodiments, modifications and applications

The principles and advantages discussed herein may be used in any device in which multiplexing of analog signals is desired. For example, various aspects of the present disclosure may be implemented in various ranging systems. For example, various aspects of the present disclosure may be implemented in any suitable LIDAR system (such as automotive LIDAR, industrial LIDAR, spatial LIDAR, military LIDAR, and the like). LIDAR systems may include a receiver or a transmitter and a receiver. LIDAR systems may be integrated with vehicles such as automobiles, unmanned aircraft such as unmanned aerial vehicles, autonomous robots, or spacecraft. The LIDAR system may emit and/or receive laser light. LIDAR systems may be used for three-dimensional sensing applications. LIDAR systems may be used with augmented reality technologies. Further, various aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, electronic products, parts of electronic products (such as integrated circuits), vehicle electronics (such as automotive electronics), and the like. Further, the electronic device may contain unfinished products.

While certain embodiments have been described, these embodiments have been presented by way of example, and are not intended to limit the scope of the disclosure. For example, although some embodiments relate to an APD coupled to an input port of a TIA, the embodiments are equally applicable to any other device that may generate a current pulse to provide an input to a TIA (such as any other type of PD). In another example, while some embodiments may refer to a PD sinking current from a TIA, these embodiments may be modified to a PD providing current to a TIA in a manner apparent to one of ordinary skill in the art, and thus, all of these embodiments are within the scope of the present disclosure. Indeed, the novel methods, devices, and systems described herein relating to modular analog signal multiplexers may be embodied in various other forms. Furthermore, various omissions, substitutions and changes in the form of the methods, devices, and systems described herein may be made without departing from the spirit of the disclosure. For example, circuit blocks and/or circuit elements described herein may be deleted, moved, added, subdivided, combined, and/or modified. Each of these circuit blocks and/or circuit elements may be implemented in a variety of different ways. The accompanying claims and their equivalents are intended to cover any such forms or modifications as fall within the scope and spirit of the disclosure.

Any of the principles and advantages discussed herein may be applied to other systems, devices, integrated circuits, electronic devices, methods, and not just the embodiments described above. The elements and operations of the various embodiments described above can be combined to provide further embodiments. The principles and advantages of embodiments may be employed in conjunction with any other system, device, integrated circuit, device, or method that may benefit from any of the teachings herein.

It is to be understood that not necessarily all objectives or advantages may be achieved in accordance with any particular embodiment described herein. Thus, for example, those skilled in the art will recognize that certain embodiments may be configured to operate in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objectives or advantages as may be taught or suggested herein.

In an exemplary embodiment, any number of the circuits in the figures may be implemented on a board of an associated electronic device. The board may be a universal circuit board that may house various components of the internal electronic system of the electronic device and further provide connectors for other peripheral devices. More specifically, the board may provide electrical connections through which other components of the system may be in electrical communication. Any suitable processor (including digital signal processors, microprocessors, supporting chipsets, etc.), computer-readable non-transitory memory elements, etc., may be suitably coupled to the board based on particular configuration needs, processing requirements, computer design, etc. Other components, such as external memory banks, controllers for configuring any of the components, and peripherals, may be connected to the board as plug-in cards via cables, or integrated into the board itself. In various embodiments, the functions described herein may be implemented in emulated form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structure that supports those functions. The software or firmware providing the emulation may be provided on a non-transitory computer readable storage medium including instructions that allow the processor to perform those functions.

In another exemplary embodiment, the circuitry in the figures may be implemented as a stand-alone module (e.g., a device with associated components and circuitry configured to carry out a particular application or function), or as a plug-in module in dedicated hardware of an electronic device. Note that certain embodiments of the present disclosure may be readily incorporated, in part or in whole, in a system-on-a-chip (SOC) package. An SOC represents an IC that integrates components of a computer or other electronic system into a single chip. It may contain digital functions, analog functions, mixed signal functions and often radio frequency functions: all of these functions may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM) in which multiple independent ICs are located within a single electronic package and configured to interact closely with each other through the electronic package. In various other embodiments, the digital filter may be implemented in one or more silicon cores in an Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), and other semiconductor chips.

It must also be noted that all specifications, dimensions, and relationships outlined herein (e.g., number of processors, logical operations, etc.) are provided for purposes of example and teaching only. Such information may vary considerably without departing from the spirit of the disclosure or the scope of the appended claims. The description applies to one non-limiting example only and, therefore, they should be so interpreted. In the foregoing specification, exemplary embodiments have been described with reference to specific arrangements of components. Various modifications and changes may be made to these embodiments without departing from the scope of the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Note that in many of the examples provided herein, interaction may be described in terms of two, three, four, or more electronic components. However, this is done for purposes of clarity and example only. It will be appreciated that the system may be integrated in any suitable manner. Along similar design alternatives, any of the components, modules, and elements shown in the figures may be combined in various possible configurations, all of which are clearly within the broad scope of this specification. In some cases, it may be easier to describe one or more functions of a given flow set by only referencing a limited number of electrical elements. It will be appreciated that the circuitry of the figures and the teachings thereof are readily scalable and can accommodate a large number of components, as well as more complex/cumbersome arrangements and configurations. Thus, the examples provided should not limit the scope of the circuit or inhibit the broad teachings of the circuit as it may be applied to myriad other architectures.

It is noted that in this specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) are included in "one embodiment," "an exemplary embodiment," "an embodiment," "another embodiment," "some embodiments," "various embodiments," "other embodiments," "alternative embodiments," etc., and are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended selected examples. Note that all optional features of the devices described above may also be implemented for the methods or processes described herein, and the details in the examples may be used anywhere in one or more embodiments.

Claims

1. A signal multiplexer apparatus, comprising:

a first signal multiplexer including a load and an output stage, wherein an input of the output stage of the first signal multiplexer is coupled to a first input of the signal multiplexer device, and wherein an output of the output stage of the first signal multiplexer is coupled to an output of the first signal multiplexer; and

a second signal multiplexer including a load and an output stage, wherein an input of the output stage of the second signal multiplexer is coupled to a first input of the signal multiplexer device, and wherein an output of the output stage of the second signal multiplexer is coupled to an output of the second signal multiplexer,

wherein:

the output of the first signal multiplexer is coupled to the output of the second signal multiplexer,

the load of the first signal multiplexer is coupled to the output of the first signal multiplexer, and

the load of the second signal multiplexer is decoupled from the output of the first signal multiplexer and from the output of the second signal multiplexer.

2. The signal multiplexer device according to claim 1, wherein the load of the second signal multiplexer is electrically floating.

3. The signal multiplexer device of claim 1, wherein:

the output stage of the first signal multiplexer is a first output stage,

the output stage of the second signal multiplexer is a second output stage,

the first signal multiplexer also includes a third output stage, wherein an input of the third output stage is coupled to a third input of the signal multiplexer device, and wherein an output of the third output stage is coupled to the output of the first signal multiplexer, and

the second signal multiplexer also includes a fourth output stage, wherein an input of the fourth output stage is coupled to a fourth input of the signal multiplexer device, and wherein an output of the fourth output stage is coupled to the output of the second signal multiplexer.

4. The signal multiplexer device of claim 3, wherein each of the first, second, third and fourth output stages is configured to provide an output signal at the output of the output stage indicative of an input signal received at the input of the output stage when a bias signal is provided to the output stage.

5. The signal multiplexer device according to claim 1, wherein at least one of the output stages comprises a differential pair.

6. The signal multiplexer device according to claim 1, wherein at least one of the output stages comprises a differential current mirror.

7. A signal multiplexer apparatus, comprising:

a first signal multiplexer including a load and an output stage, wherein an input of the output stage of the first signal multiplexer is coupled to a first input of the signal multiplexer device, and wherein an output of the output stage of the first signal multiplexer is coupled to an output of the first signal multiplexer;

a second signal multiplexer including a load and an output stage, wherein an input of the output stage of the second signal multiplexer is coupled to a first input of the signal multiplexer device, wherein an output of the output stage of the second signal multiplexer is coupled to an output of the second signal multiplexer, and wherein the output of the first signal multiplexer is coupled to the output of the second signal multiplexer; and

a switching device configured to couple or decouple the load of the first signal multiplexer and the output of the first signal multiplexer.

8. The signal multiplexer device of claim 7, wherein:

the switching device is a first switching device, and

the signal multiplexer device also includes a second switching device configured to couple or decouple the load of the second signal multiplexer and the output of the second signal multiplexer.

9. The signal multiplexer device of claim 8, wherein the first and second switch devices are configured such that:

when the first switching device couples the load of the first signal multiplexer and the output of the first signal multiplexer, the second switching device decouples the load of the second signal multiplexer and the output of the second signal multiplexer, and

the first switching device decouples the load of the first signal multiplexer and the output of the first signal multiplexer when the second switching device couples the load of the second signal multiplexer and the output of the second signal multiplexer.

10. The signal multiplexer device of claim 7, wherein the load of the second signal multiplexer is electrically floating when the first switch device couples the load of the first signal multiplexer and the output of the first signal multiplexer.

11. A signal multiplexer, comprising:

an output stage having an input coupled to the input of the signal multiplexer and having an output coupled to the output of the signal multiplexer; and

the load is a load of the vehicle,

wherein:

the signal multiplexer is configured to operate in a first mode or a second mode,

in the first mode, the load is coupled to the output of the signal multiplexer, and

in the second mode, the load is not coupled to the output of the signal multiplexer.

12. The signal multiplexer of claim 11, wherein:

the output stage is a first output stage,

said input of said signal multiplexer is a first input of said signal multiplexer,

the signal multiplexer also includes a second output stage having an input coupled to a second input of the signal multiplexer and having an output coupled to the output of the signal multiplexer.

13. The signal multiplexer of claim 12, further comprising:

a first bias signal source configured to provide a bias signal to the first output stage; and

a second bias signal source configured to provide a bias signal to the second output stage,

wherein:

the signal multiplexer is configured to provide a signal indicative of an input signal received at the first input of the signal multiplexer at the output of the signal multiplexer when the first bias signal source provides the bias signal to the first output stage, and

the signal multiplexer is configured to provide a signal indicative of an input signal received at the second input of the signal multiplexer at the output of the signal multiplexer when the second bias signal source provides the bias signal to the second output stage.

14. The signal multiplexer of claim 13, wherein:

the signal multiplexer is configured to provide a signal at the output of the signal multiplexer when the first bias signal source provides the bias signal to the first output stage and the second bias signal source provides the bias signal to the second output stage, and the signal is a combination of the signal indicative of the input signal received at the first input of the signal multiplexer and the signal indicative of the input signal received at the second input of the signal multiplexer.

15. The signal multiplexer of claim 11, further comprising a switching device configured to change a coupling between the load and the output of the multiplexer to place the signal multiplexer in the first mode of operation or the second mode of operation.

16. The signal multiplexer of claim 11, wherein the output of the signal multiplexer is a first output, and the signal multiplexer further comprises:

a second output separate from the first output, wherein the load is coupled to the second output; and

a resistor arrangement configured to change a coupling between the load and the output of the signal multiplexer to place the signal multiplexer in the first mode of operation or the second mode of operation,

wherein:

in the first mode, the resistor means couples the second output and the first output, and

in the second mode, the resistor means decouples the second output and the first output.

17. The signal multiplexer of claim 11, wherein:

the inputs of the output stage are differential inputs,

each of the output stage and the output of the signal multiplexer is a differential output, an

In the first mode, the load is coupled to the output of the signal multiplexer via a differential connection.

18. The signal multiplexer of claim 17, wherein the input of the signal multiplexer is a differential input.

19. The signal multiplexer of claim 17, wherein the input of the signal multiplexer is a single-ended input, and the signal multiplexer further comprises a single-ended to differential converter configured to convert a signal provided to the signal multiplexer through the single-ended input of the signal multiplexer into a differential signal to be provided to the input of the output stage.

20. The signal multiplexer of claim 11, wherein the output stage comprises a differential pair or a differential current mirror.