TW202343984A - Wired transceiver with overvoltage protection - Google Patents

Abstract

A wired transceiver includes an output stage circuit and an input stage circuit. The output stage circuit operates in one of a first mode and a second mode, and transmits outputs signals to output pads and receives a first set of bias voltages to provide a first overvoltage protection in the first mode, and stops transmitting the output signals and receives a second set of bias voltages to provide the first overvoltage protection in the second mode. The input stage circuit receives input signals from the output pads when the output stage circuit operates in the second mode and attenuates the input signals to provide a second overvoltage protection.

Description

Wired transceiver with overvoltage protection

This case is about transmitters, especially wired transmitters with overvoltage protection, which can be implemented by transistors with relatively low withstand voltages.

Due to the advancement of manufacturing processes, the size of transistors is getting smaller and smaller, causing the withstand voltage of transistors to become lower and lower. However, in existing applications, signal transceivers in Ethernet applications still need to transmit signals with higher levels. If transistors with low withstand voltage are directly used to implement existing transceivers, these transistors will need to withstand excessive voltage and be damaged, resulting in reduced reliability of the transmitter.

In some embodiments, one of the purposes of this case is to provide a wired transceiver with overvoltage protection, which can be implemented by a transistor with a relatively low withstand voltage to improve the shortcomings of the previous technology.

In some implementations, the wired transceiver includes an output stage circuit and an input stage circuit. The output stage circuit operates in one of a first mode and a second mode according to a mode control signal, and transmits a plurality of output signals to a plurality of output pads and receives a first set of bias voltages in the first mode. To provide a first over-voltage protection, and in the second mode, stop transmitting the output signals and receive a second set of bias voltages to provide the first over-voltage protection. The input stage circuit receives a plurality of input signals from the output pads and attenuates the input signals to provide a second overvoltage protection when the output stage circuit operates in the second mode.

Regarding the characteristics, implementation and functions of this case, the preferred embodiments are described in detail below with reference to the drawings.

All words used in this article have their ordinary meanings. The definitions of the above words in commonly used dictionaries, and the use examples of any of the words discussed here in the content of this case are only examples and should not limit the scope and meaning of this case. Likewise, this case is not limited to the various embodiments shown in this specification.

As used in this article, "coupling" or "connection" can refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other. It can also refer to two or more components. Components interact or act with each other. As used herein, the term "circuit" may refer to a device consisting of at least one transistor and/or at least one active and passive component connected in a certain manner to process signals.

Figure 1 is a schematic diagram of a wired transceiver 100 according to some embodiments of the present application. In some embodiments, the wired transceiver 100 can be implemented by a low-voltage transistor, and an over-voltage protection mechanism is set for the transmitter 110 , the receiver 120 and the termination resistor circuit 130 respectively to output/receive signals with higher levels. (For example, data signals in Ethernet networks).

In some embodiments, the wired transceiver 100 includes a transmitter 110, a receiver 120, and a termination resistor (or termination resistor) circuit 130. Each of the transmitter 110, the receiver 120 and the termination resistor circuit 130 may operate in one of the first mode, the second mode and the third mode according to the mode control signal CTR. In the first mode (or transmitting mode), the transmitter 110 transmits the output signals VOP and VON to the output pads PP and PM respectively. In this mode, the receiver 120 does not work and the terminal resistor circuit 130 is not conductive to avoid affecting the transmitter. 110 operations. In the second mode (or reception mode), the termination resistor circuit 130 is turned on to provide a termination resistor to the output pads PP and PM for impedance matching. The receiver 120 can receive the input signals VIP and via the output pads PP and PM respectively. VIN, and the transmitter 110 is inactive so as not to affect the operation of the receiver 120. In the third mode (or standby mode), the termination resistor circuit 130 is turned on and the output pads PP and PM are coupled to ground to provide over-voltage protection, and neither the transmitter 110 nor the receiver 120 operates.

The transmitter 110 includes a main circuit 112 and an output stage circuit 114 . The main circuit 112 generates a data signal group SP and a data signal group SM, wherein each of the data signal group SP and the data signal group SM may include multiple data signals (for example, as shown in FIG. 2 , the data signal group SP includes a data signal SP1 and data signal SP2). In some embodiments, the main circuit 112 may include a signal processing circuit, an encoder circuit, etc., but this case is not limited thereto. The output stage circuit 114 operates in one of the first mode, the second mode and the third mode according to the mode control signal CTR.

In the first mode, the output stage circuit 114 can generate the output signal VOP according to the data signal group SP and transmit the output signal VOP to the output pad PP, and generate the output signal VON according to the data signal group SM and transmit the output signal VON to the output pad PM. The output stage circuit 114 further receives a first set of bias voltages VA in the first mode to provide overvoltage protection, and stops generating the output signal VOP and the output signal VON in the second mode or the third mode and receives a second set of bias voltages. voltage VB to remain off to continue to provide over-voltage protection.

The receiver 120 includes a main circuit 122 and an input stage circuit 124 . In the first mode or the third mode, the receiver 120 does not operate (ie does not receive signals from the output pads PP and PM). In the second mode, the input stage circuit 124 can receive the input signal VIP from the output pad PP and the input signal VIN from the output pad PM, and attenuate the input signal VIP and the input signal VIN to generate the input signal RP and the input signal RN, so as to Provide main circuit 122 overvoltage protection. For example, the input stage circuit 124 may divide and filter the input signal VIP and the input signal VIN to attenuate the input signal VIP and the input signal VIN. The main circuit 122 can process the input signal RP and the input signal RN to read the information carried on the input signal VIP and the input signal VIN. In some embodiments, the main circuit 112 may include a front-end circuit, a decoder circuit, etc., but this case is not limited thereto.

In the first mode, the termination resistor circuit 130 causes multiple internal switching signals according to multiple switching signals (for example, multiple switching signals 1[1]˜1[n] and 2[1]˜2[n] in FIG. 3A ). The switches form an open circuit to avoid affecting the operation of the transmitter 110. In the second mode, the terminal resistor circuit 130 forms multiple internal switches according to multiple switching signals to form a path to provide terminal resistors to the output pads PP and PM, thereby achieving impedance matching. In this way, the receiver 120 can receive a more complete input signal VIP and input signal VIN. In the third mode, the terminal resistor circuit 130 remains on and couples the output pads PP and PM to ground to ensure that the output pads PP and PM have a fixed potential, thereby achieving a certain voltage protection. In addition, the aforementioned multiple switching signals have different levels in different modes (for example, in FIG. 3A , the levels of the switching signals 1[1]˜1[n] in the first mode are different from those in the second mode or the third mode. The levels of the three modes, and the levels of the switching signals 2[1]˜2[n] in the first mode are different from their levels in the second mode or the third mode), and the termination resistor circuit 130 is in the first mode. Both the second mode and the second mode receive a reference voltage (for example, the reference voltage VREF in Figure 3A) to provide an over-voltage protection.

Through the over-voltage protection provided by each of the above circuits, a transistor with a lower withstand voltage can be used to implement the wired transceiver 100, and the wired transceiver 100 can still be used to send and receive data or signals with a higher level, so as to be suitable for A wider variety of applications (such as, but not limited to, Ethernet).

FIG. 2 is a schematic diagram of the output stage circuit 114 of FIG. 1 according to some embodiments of the present invention. For easy understanding, FIG. 2 only shows the circuit part of the output stage circuit 114 that generates the output signal VOP to the output pad PP according to the data signal group SP. It should be understood that the output stage circuit 114 also includes another circuit part that generates the output signal VON to the output pad PM according to the data signal group SM, and the circuit structure of the other circuit part is the same as that shown in FIG. 2 .

Referring to FIG. 2 , the output stage circuit 114 includes a conversion module 210 , a protection module 212 , a conversion module 220 and a protection module 222 . The conversion module 210, the protection module 212, the protection module 222 and the conversion module 220 are connected in series in sequence, and the protection module 212 and the protection module 222 are coupled to the output pad PP. The conversion module 210 converts the data signal SP1 in the data signal group SP into the current signal I1. The protection module 212 can select the corresponding bias voltage according to the mode control signal CTR. For example, in the first mode, the protection module 212 turns on an internal transistor according to the voltage VA1 in the first set of bias voltages VA to provide over-voltage protection, and transmits the current signal I1 to the output pad PP to generate FIG. 1 The output signal VOP. In the second mode or the third mode, the protection module 212 disables the aforementioned transistors in the protection module 212 according to the voltage VB1 in the second set of bias voltages VB to continue to provide overvoltage protection.

Similarly, the conversion module 220 converts the data signal SP2 in the data signal group SP into the current signal I2. The protection module 222 can select the corresponding bias voltage according to the mode control signal CTR. For example, in the first mode, the protection module 222 turns on an internal transistor according to the voltage VA2 in the first set of bias voltages VA to provide over-voltage protection, and draws the corresponding current signal I2 from the output pad PP to The output signal VOP shown in Figure 1 is generated. In the second mode or the third mode, the protection module 222 disables the aforementioned transistors in the protection module 222 according to the voltage VB2 in the second set of bias voltages VB to continue to provide overvoltage protection. The current signal I1 and the current signal I2 can be superimposed on the node of the output pad PP to generate the output signal VOP.

Specifically, in some embodiments, the conversion module 210 includes the transistor MP1, the protection module 212 includes the transistor MP2 and the switching circuit 214, the conversion module 220 includes the transistor MN1, and the protection module 222 includes the transistor MN2. and switching circuit 224. The first terminal (for example, the source) of the transistor MP1 receives the power supply voltage VDD, the second terminal (for example, the drain) of the transistor MP1 is coupled to the first terminal of the transistor MP2 to output the current signal I1, and the transistor MP1 The control terminal of MP1 (for example, the gate) receives the data signal SP1. The transistor MP1 can be selectively turned on according to the data signal SP1 to generate the current signal I1. The second terminal of the transistor MP2 is coupled to the output pad PP, and the control terminal of the transistor MP2 receives the voltage VA1 or the voltage VB1 via the switching circuit 214 . Transistor MP2 can be selectively turned on according to the received voltage to transmit current signal I1 to output pad PP. The switching circuit 214 can transmit the voltage VA1 or the voltage VB1 to the transistor MP2 according to the mode control signal CTR. For example, when the mode control signal CTR has a first logic value (eg, a logic value 1), it represents that the transmitter 110 intends to operate in the first mode. Under this condition, the switching circuit 214 can transmit the voltage VA1 to the transistor MP2, and then turn on the transistor MP2 to provide over-voltage protection for the transistor MP1. Alternatively, when the mode control signal CTR has a second logic value (for example, a logic value of 0), it represents that the transmitter 110 intends to operate in the second mode or the third mode. Under this condition, the switching circuit 214 can transmit the voltage VB1 to the transistor MP2, and then turn off the transistor MP2 to provide over-voltage protection for the transistor MP1.

The first terminal (for example, the source) of the transistor MN1 is coupled to the ground, the second terminal (for example, the drain) of the transistor MN1 is coupled to the second terminal of the transistor MN2 to draw the current signal I2, and the transistor MN1 The control terminal of MN1 (for example, a gate) receives the data signal SP2. The transistor MN1 can be selectively turned on according to the data signal SP2 to generate the current signal I2. The first terminal of the transistor MN2 is coupled to the output pad PP, and the control terminal of the transistor MN2 receives the voltage VA2 or the voltage VB2 via the switching circuit 224 . The transistor MN2 can be selectively turned on according to the received voltage to draw the current signal I2 from the output pad PP. The switching circuit 224 can transmit the voltage VA2 or the voltage VB2 to the transistor MN2 according to the mode control signal CTR. For example, when the mode control signal CTR has a first logic value (ie, operates in the first mode), the switching circuit 224 can transmit the voltage VA2 to the transistor MN2, and then turn on the transistor MN2 to provide over-voltage protection for the transistor MN1. Alternatively, when the mode control signal CTR has a second logic value (that is, operating in the second or third mode), the switching circuit 224 can transmit the voltage VB2 to the transistor MN2 and then turn off the transistor MN2 to provide an overvoltage to the transistor MN1 protect.

In one embodiment, the level of the power supply voltage VDD is about 3.3 volts, and the withstand voltage of each of the transistors MN1, MN2, MP1 and MP2 is about 1.8 volts. In the first mode, the voltage range of the output signal VOP on the output pad PP is about 0.4 to 2.9 volts. Under this condition, the level of each of voltage VA1 and voltage VA2 may be set to approximately 1.8 volts. In this way, it can be ensured that the voltage across the two ends of each of the plurality of transistors MN1, MN2, MP1 and MP2 does not exceed its withstand voltage value, thereby achieving overvoltage protection. Furthermore, when operating in the second mode, the output stage circuit 114 does not operate (ie stops generating the output signal VOP and the output signal VON) and the receiver 120 receives the input signal VIP and the input signal VIN. In the second mode, the voltage range of the input signal VIP on the output pad PP is approximately 0.25 to 2.75 volts. Under this condition, the level of voltage VB1 can be set to approximately 1.8 volts, and the level of voltage VB2 can be set to approximately 1.1 volts. In this way, the transistor MP2 and the transistor MN2 can remain turned off in the second mode, and ensure that the voltage across the two ends of each of the plurality of transistors MN1, MN2, MP1 and MP2 does not exceed its withstand voltage value, Thus over-voltage protection is achieved. The operation of the plurality of transistors MN1, MN2, MP1 and MP2 in the second mode is the same as the operation of the plurality of transistors MN1, MN2, MP1 and MP2 in the third mode, so the details are not repeated here.

It should be noted that the levels of voltage VB1 and voltage VB2 can be adjusted according to the voltage range of the input signal VIP to ensure that the transistor MP2 and the transistor MN2 will not be misled due to the different swings of the input signal VIP in the second mode. Pass. If the transistor MP2 and the transistor MN2 are mistakenly turned on in the second mode, the output stage circuit 114 may charge/discharge the output pad PP, causing distortion of the input signal VIP. Therefore, by setting the first set of bias voltage VA and the second set of bias voltage VB with different levels, the bias voltages required by the above-mentioned multiple transistors can be adjusted in different modes to achieve over-voltage protection and Ensure that the operation of the receiver 120 is not affected. The above-mentioned multiple voltage values and the withstand voltage value of the transistor are used as examples, and this case is not limited thereto.

FIG. 3A is a schematic diagram of the terminal resistor circuit 130 of FIG. 1 according to some embodiments of the present case. The terminal resistor circuit 130 includes a resistor array 310 , a switch array 320 , a resistor array 330 , a switch array 340 , a voltage driver 350 and a level converter 360 . The resistor array 310 is coupled between the output pad PP and the switch array 320 . The switch array 320 is coupled between the output pad PP and the reference node N1 via the resistor array 310 . The switch array 320 is selectively turned on according to a plurality of switching signals 1[1]˜1[n] and 2[1]˜2[n]. The resistor array 330 is coupled between the output pad PM and the switch array 340 . The switch array 340 is coupled between the output pad PM and the reference node N1 via the resistor array 330 . The switch array 340 is selectively turned on according to a plurality of switching signals 1[1]˜1[n] and 2[1]˜2[n].

As shown in FIG. 3A , the resistor array 310 includes a plurality of resistors, and the switch array 320 includes a plurality of switch circuits 321[1]˜321[n] (shown as a single switch), and these resistors are coupled to the Switching circuits 321[1]～321[n]. The switch circuits 321[1]˜321[n] are respectively controlled by the switching signals 1[1]˜1[n] and 2[1]˜2[n]. When at least one of the switch circuits is turned on, the corresponding resistors may be coupled in parallel to form a terminal resistor. The resistor array 330 includes a plurality of resistors, and the switch array 340 includes a plurality of switch circuits 341[1]˜341[n] (shown as a single switch). The arrangement between the resistors and the switch circuits 341[1]-341[n] is the same as the arrangement between the resistors and the switch circuits 321[1]-321[n] in the resistor array 310. method, so I won’t repeat it again. Through the above setting method, the resistance value of the terminal resistor can be adjusted by turning on different numbers of switch circuits.

The voltage driver 350 outputs the reference voltage VREF to the reference node N1 according to the mode control signal CTR, or couples the reference node N1 to ground to provide over-voltage protection. For example, in the first mode or the second mode, the voltage driver 350 may output the reference voltage VREF with a preset level to the reference node N1 to provide over-voltage protection for the switch array 320 and the switch array 340 . Alternatively, in the third mode, the voltage driver 350 may provide a path coupled to ground (shown as a dotted path) to couple the reference node N1 to ground. In this way, it can be ensured that the output pad PP and the output pad PM are not floating, thereby providing a certain degree of over-voltage protection. In some embodiments, the voltage driver 350 may receive another mode control signal (not shown) related to the mode control signal CTR to confirm the current operating mode, wherein the other mode control signal may be used to indicate whether to enter the second mode. (i.e. receive mode). The other mode control signal has a certain correlation with the mode control signal CTR. For example, the mode control signal CTR and the other mode control signal have opposite logical values. Alternatively, in other embodiments, the voltage driver 350 may receive the mode control signal CTR and the other mode control signal simultaneously. In some embodiments, the voltage driver 350 may include a voltage dividing circuit (not shown) and a voltage buffer (not shown). When the voltage driver 350 does not generate the reference voltage VREF, the internal diode in the voltage buffer may conduct to couple the reference node N1 to ground. The above is about the implementation of the voltage driver 350, and this case is not limited thereto.

The level converter 360 generates a plurality of switching signals 1[1]˜1[n] and 2[1]˜2[n] with corresponding levels according to the mode control signal CTR, so that the switch array 330 and the switch array 340 have Over voltage protection. The relevant operations here will be described later with reference to FIG. 3B.

FIG. 3B is a schematic circuit diagram of the switch array 320 and the switch array 340 in FIG. 3A according to some embodiments of the present case. The switch array 320 includes switch circuits 321[1]˜321[n]. Each of the switch circuits 321[1]˜321[n] is controlled by a corresponding one of the switching signals 1[1]˜1[n] and a corresponding one of the switching signals 2[1]˜2[n]. . For example, the switching circuit 321[1] is controlled by the switching signal 1[1] and the switching signal 2[1], and the switching circuit 321[2] is controlled by the switching signal 1[2] and the switching signal 2[2]. Similarly, switch array 340 includes switch circuits 341[1]˜341[n]. Each of the switch circuits 341[1]˜341[n] is controlled by a corresponding one of the switching signals 1[1]˜1[n] and a corresponding one of the switching signals 2[1]˜2[n]. . For example, the switching circuit 341[1] is controlled by the switching signal 1[1] and the switching signal 2[1], and the switching circuit 341[2] is controlled by the switching signal 1[2] and the switching signal 2[2].

Each of the switch circuits 321[1]˜321[n] has the same circuit structure. Taking the switch 321[1] as an example, the switch 321[1] includes a transistor MN3 and a transistor MP3. The first terminal of the transistor MN3 is coupled to a resistor of the resistor array 310 of FIG. 3A, the second terminal of the transistor MN3 is coupled to the first terminal of the transistor MP3, and the control terminal of the transistor MN3 receives the switching signal 1[ 1]. The transistor MN3 can be selectively turned on according to the switching signal 1[1]. The second terminal of the transistor MP3 is coupled to the reference node N1, and the control terminal of the transistor MP3 receives the switching signal 2[1]. Transistor MP3 can be selectively turned on according to switching signal 2[1]. The switch circuits 321[1]˜321[n] and the switch circuits 341[1]˜341[n] have symmetrical structures, so the details are not repeated here.

In the previously mentioned embodiment, the voltage range of each of the output signal VOP and the output signal VON is approximately 0.4-2.9 volts. In the first mode, the voltage driver 350 generates a reference voltage VREF with a level of approximately 1.5 volts to the reference node N1, and the level converter 360 outputs a plurality of switching signals 1[1]~ with a level of approximately 1.8 volts. 1[n] and 2[1]～2[n]. In this way, the switch circuits 321[1]˜321[n] and 341[1]˜341[n] can remain non-conductive to avoid affecting the operation of the transmitter 110. In addition, under this condition, the voltage across any two ends of the transistor MN3 and the transistor MP3 does not exceed its withstand voltage value (for example, 1.8 volts) to obtain the overvoltage protection effect. In other embodiments, according to the voltage range of each of the output signal VOP and the output signal VON, the voltage driver 350 may also couple the reference node N1 to ground in the first mode and continue to provide overvoltage protection.

In the second mode, the voltage driver 350 continuously generates the reference voltage VREF having a level of approximately 1.5 volts to the reference node N1. Assuming that the switch circuit 321[1] and the switch circuit 341[1] are selected to be turned on, the level converter 360 outputs a switching signal 1[1] with a level of approximately 3.3 volts and a switching signal with a level of approximately 0 volts. Signal 2[1]. In this way, the transistor MN3 and the transistor MP3 in the switch circuit 321[1] and the switch circuit 341[1] can be turned on, so that the corresponding resistors in the resistor array 310 and the resistor array 330 form part of the terminal resistor. In addition, by having multiple voltages with different levels, the voltage across any two ends of each of the transistor MN3 and the transistor MP3 does not exceed its withstand voltage value, thereby obtaining the overvoltage protection effect.

In the third mode, the voltage driver 350 couples the reference node N1 to ground, and the level converter 360 outputs a plurality of switching signals 1[1]˜1[n] with a level of about 3.3 volts and a level of Switching signals 2[1] ~ 2[n] at approximately 0 volts. As a result, the plurality of transistors MN3 and MP3 in each of the switch array 320 and the switch array 340 are turned on, so that the output pads PP and PM can be coupled to the ground via the reference node N1. In this way, the output pad PP and the output pad PM can be prevented from floating, thereby avoiding unnecessary voltage jumps, thereby achieving over-voltage protection.

As shown in FIG. 3B , in the switch circuit 321[1], the conductive modes of the transistor MN3 and the transistor MP3 are opposite to each other. For example, transistor MN3 is an N-type transistor, and transistor MP3 is a P-type transistor. In the examples of FIGS. 3A and 3B , the output pad PP is coupled to the reference node N1 via the resistor array 310 , the transistor MN3 and the transistor MP3 in order to ensure that the transistor MN3 and the transistor MP3 do not operate in the first mode. Will mislead to avoid affecting the output signal VOP and output signal VON. In different embodiments, according to the output signal VOP and the different voltage ranges of the output signal VOP, the connection sequence of the transistor MN3 and the transistor MP3 can also be exchanged (for example, the output pad PP is sequentially connected through the resistor array 330 and the transistor MP3 and transistor MN3 coupled to reference node N1).

FIG. 4 is a schematic circuit diagram of the input stage circuit 124 of FIG. 1 according to some embodiments of the present case. The input stage circuit 124 includes resistors R1˜R3 and a capacitor C. In some embodiments, the resistance of each of the resistors R1 , R2 , and R3 is much higher than the termination resistance provided by the termination resistance circuit 130 to avoid affecting the operation of the termination resistance circuit 130 .

The first terminal of the resistor R1 is coupled to the output pad PP to receive the input signal VIP, and the second terminal of the resistor R1 is coupled to the first terminal of the resistor R3 and the first terminal of the capacitor C. The first terminal of the resistor R2 is coupled to the output pad PM to receive the input signal VIN, and the second terminal of the resistor R2 is coupled to the second terminal of the resistor R3 and the second terminal of the capacitor C. The resistor R1, the resistor R2 and the resistor R3 form a voltage dividing circuit, which divides the voltage of the multiple input signals VIP and VIN. The voltage dividing circuit and the capacitor C form a filter to attenuate the noise on the divided multiple input signals VIP and VIN, and output the processed input signal RP and processed input signal RN to Figure 1 Main circuit 122. The resistor R3 can be a variable resistor, and its resistance can be adjusted according to the voltage range of the input signal VIP and the input signal VIN to ensure the signal attenuation effect. In this way, the main circuit 122 can be prevented from directly receiving the input signal VIP and the input signal VIN with excessively high levels, thereby achieving over-voltage protection.

To sum up, the wired transceiver in some embodiments of this case has multiple overvoltage protection mechanisms to respectively protect the transmitter, receiver and terminal resistor circuit in different operating modes. In this way, the wired transceiver can be implemented using transistors with low voltage withstand in newer processes. Furthermore, according to different operating modes, the wired transceiver will use corresponding circuit settings to ensure that the operation of other circuits is not affected.

Although the embodiments of this case are as described above, these embodiments are not intended to limit this case. Those with ordinary knowledge in the technical field can make changes to the technical features of this case based on the explicit or implicit contents of this case. All these changes All may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case must be determined by the scope of the patent application in this specification.

1[1]~1[n],2[1]~2[n]: switching signal 100:Wired transceiver 110:Transmitter 112: Main circuit 114:Output stage circuit 120:Receiver 122: Main circuit 124:Input stage circuit 130: Terminal resistor circuit 210,220:Conversion module 212,222: Protection module 214,224: switching circuit 310,330: Resistor array 320,340: switch array 321[1]~321[n],341[1]~341[n]: switching circuit 350: Voltage driver 360:Level Converter C: capacitor CTR: mode control signal I1, I2: current signal MN1~MN3,MP1~MP3: transistor N1: reference node PM,PP: output pad R1~R3: Resistor RN, RP: input signal SM, SP: data signal group SP1, SP2: data signal VA: first set of bias voltage VA1, VA2, VB1, VB2: voltage VB: The second set of bias voltage VDD: power supply voltage VIN, VIP: input signal VON, VOP: output signal VREF: reference voltage

[Figure 1] is a schematic diagram of a wired transceiver according to some embodiments of this case; [Figure 2] is a schematic diagram of the output stage circuit of Figure 1 according to some embodiments of this case; [Figure 3A] is a schematic diagram of the terminal resistor circuit of Figure 1 according to some embodiments of this case; [Figure 3B] is a schematic circuit diagram of multiple switch arrays in Figure 3A according to some embodiments of this case; and [Figure 4] is a circuit schematic diagram of the input stage circuit of Figure 1 according to some embodiments of this case.

100:Wired transceiver

110:Transmitter

112: Main circuit

114:Output stage circuit

120:Receiver

122: Main circuit

124:Input stage circuit

130: Terminal resistor circuit

CTR: mode control signal

PM,PP: output pad

RN, RP: input signal

SM, SP: data signal group

VA: first set of bias voltage

VB: The second set of bias voltage

VIN, VIP: input signal

VON, VOP: output signal

Claims (12)

A wired transceiver containing: An output stage circuit operates in one of a first mode and a second mode according to a mode control signal, and transmits a plurality of output signals to a plurality of output pads and receives a first set of biases in the first mode. bias voltage to provide a first over-voltage protection, and stop transmitting the output signals in the second mode and receive a second set of bias voltages to provide the first over-voltage protection; and An input stage circuit receives a plurality of input signals from the output pads when the output stage circuit operates in the second mode, and attenuates the input signals to provide a second overvoltage protection. The wired transceiver of claim 1, wherein the output stage circuit remains turned off in the second mode according to the second set of bias voltages. For example, the wired transceiver of claim 1, wherein the output stage circuit includes: a first conversion module, converting a first data signal into a first current signal; A first protection module, in the first mode, provides the first overvoltage protection according to a first voltage in the first set of bias voltages and transmits the first current signal to a first of the output pads. an output pad to generate a first output signal among the output signals and provide the first overvoltage protection according to a second voltage in the second set of bias voltages in the second mode; a second conversion module that converts a second data signal into a second current signal; and A second protection module, in the first mode, provides the first overvoltage protection according to a third voltage in the first set of bias voltages and draws the second current signal from the first output pad to generate The first output signal provides the first overvoltage protection according to a fourth voltage in the second set of bias voltages in the second mode. The wired transceiver of claim 1, wherein the output stage circuit further operates in a third mode according to the mode control signal without transmitting the output signals, and the first protection module includes: A transistor that is turned on in the first mode according to the first voltage in the first set of bias voltages to transmit the first current signal to the first output pad, and in the second mode and the third mode Turn off according to the second voltage in the second set of bias voltages; and A switching circuit transmits one of the first voltage in the first set of bias voltages and the second voltage in the second set of bias voltages to the transistor according to the mode control signal. For example, the wired transceiver of request item 1 further includes: A terminal resistor circuit is coupled between the output pads, and in the first mode forms an open circuit according to a plurality of first switching signals and a plurality of second switching signals and receives a reference voltage to provide a third overvoltage. protection, and in the second mode, selectively conduction according to the first switching signals and the second switching signals to provide a terminal resistor and receive the reference voltage to provide the third overvoltage protection, The level of the first switching signals in the first mode is different from the level of the first switching signals in the second mode, and the level of the second switching signals in the first mode is different from the level of the second switching signals in the first mode. The second switching signals are at the level of the second mode. For example, the wired transceiver of claim 5, wherein the output stage circuit further operates in a third mode according to the mode control signal and does not transmit the output signals, and the input stage circuit does not receive the input signals in the third mode. , and the terminal resistor circuit selectively conducts according to the first switching signals and the second switching signals in the third mode and couples the output pads to ground to provide the third overvoltage protection. For example, the wired transceiver of claim 5, wherein the terminal resistor circuit includes: a first resistor array; A first switch array is coupled between a first output pad among the output pads and a reference node via the first resistor array, and is selectively configured according to the first switching signals and the second switching signals. conduction; a second resistor array; a second switch array, coupled between a second output pad among the output pads and the reference node via the second resistor array, and selectively based on the first switching signals and the second switching signals conduction; and A voltage driver outputs the reference voltage to the reference node according to the mode control signal to provide the third overvoltage protection. The wired transceiver of claim 7, wherein the first switch array includes: a first transistor coupled to a resistor in the first resistor array and selectively turned on according to a first signal among the first switching signals; and A second transistor is coupled between the first transistor and the reference node, and is selectively turned on according to a second signal among the second switching signals. The wired transceiver of claim 8, wherein the first transistor and the second transistor have different conductivity types. For example, the wired transceiver of request item 5 further includes: A level converter generates the first switching signals and the second switching signals according to the mode control signal. For example, in the wired transceiver of claim 1, the input stage circuit divides and filters the input signals to attenuate the input signals. For example, the wired transceiver of claim 1, wherein the input stage circuit includes: a first resistor, receiving a first signal among the input signals via a first output pad among the output pads; a second resistor, receiving a second signal among the input signals via a second output pad among the output pads; a third resistor coupled between the first resistor and the second resistor; and A capacitor is coupled between the first resistor and the second resistor and generates a third input signal and a fourth input signal.

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