JP4977115B2 - Pipeline type A / D converter - Google Patents

Description

The present invention relates to a pipeline type A / D converter.

  FIG. 11 is a diagram for explaining the prior art of the pipeline type A / D converter. The prior art of such a pipeline type A / D converter is described in Patent Document 1, for example. This figure is a circuit diagram of a stage constituting the pipeline type A / D converter described in Patent Document 1, and includes an A / D conversion unit 40, two D / A conversion units D / A1, and D / D. A2 is provided. An analog input signal Vin is input to the A / D converters D / A1 and D / A2, and A / D conversion is performed. The converted digital signal is output to a control circuit that performs an operation using the digital signal and is D / A converted. The D / A converted analog signal is distributed to multi-value output values by two multi-value output circuits M1 and M2.

The illustrated stage includes two switchable sample and hold circuits S / H10 and S / H20 that sample and hold the analog input signal Vin. While one of the sample and hold circuits is in the hold operation, the other sample and hold circuit performs the sample operation.
The two sample and hold circuits are composed of a circuit in which analog switches SW1 and SW2 and capacitors C1 and C2 are connected in series, and a circuit in which analog switches SW3 and SW4 and capacitors C3 and C4 are connected in series, both connected in series. Has been. In each sample and hold circuit, the capacitances of the two capacitors are equal.

  When one of the capacitors included in one of the sample and hold circuits is connected to the input terminal of the operational amplifier 71, one of the capacitors included in the other of the sample and hold circuit is not connected to the input terminal of the operational amplifier 71. When the other of the capacitors included in one of the sample and hold circuits is connected to one output terminal of the multi-value output circuit, the other of the capacitors included in the other of the sample and hold circuit is the other of the multi-value output circuit. Not connected to.

With such a configuration, the conventional technology can alternately sample or hold the two sample and hold circuits S / H10 and S / H20.
JP 2000-13232 A

However, in the above-described pipeline type A / D converter, the charge stored in the parasitic capacitance of Vout of the operational amplifier 71, that is, information on the previous state may remain, and a desired settling accuracy cannot be obtained. Therefore, it has been difficult to achieve higher accuracy of the pipeline type A / D converter.
In order to achieve high accuracy of the pipeline type A / D converter, it is necessary to increase the settling accuracy while keeping the DC gain of the operational amplifier 71 high and to ensure the stability of the operational amplifier 71. In order to satisfy these requirements, it is necessary to increase the power consumption of the operational amplifier 71.
The present invention has been made in view of the above, and an object thereof is to provide a pipeline type A / D converter capable of high-precision operations without increasing the power consumption.

In order to solve the above problems, the pipeline type A / D converter according to claim 1 of the present invention is different from the analog first input signal (for example, VPin shown in FIG. 3) and the analog first input signal. The analog second input signal (for example, VNin shown in FIG. 3) forming a dynamic signal pair is converted into a digital signal (for example, dj shown in FIG. 3), and the digital signal, the analog first input signal, and the analog The analog first differential output signal (for example, VPout shown in FIG. 3) generated by the second input signal and the analog second differential output signal (for example, VNout shown in FIG. 3) are sent to other stages in the subsequent stage. A pipelined A / D converter having a plurality of output stages, wherein the stage samples the analog first input signal and the analog second input signal separately. Circuits (for example, sample caps CAPa 307a, 307b, 307c, 307d, SW304c, 304d, 304a, 304k, 304l, and 304i shown in FIG. 3) and sample timing changeover switches (for example, FIG. 3) that determine the sampling operation timing of the sampling circuit SW304c, 304d, 304k, 304l) and the value of the analog first input signal and the value of the analog second input signal sampled in the sampling circuit are adjusted in accordance with the value of the digital signal, respectively. Sampling value adjustment circuit (for example, the multi-value output circuits 306 and 309 shown in FIG. 3) and hold means (for example, holding the analog first input signal and the analog second input signal adjusted by the sampling value adjustment circuit) For example, the amplifier 305 shown in FIG. 3 and the analog first input signal and the analog second input signal are held, and then the analog first differential output signal (for example, VPout shown in FIG. 3), the analog first input signal. A transfer switch (for example, SW304b and 304j shown in FIG. 3) that outputs to the other stage as the second differential output signal (eg, VNout shown in FIG. 3), and the analog before the transfer by the transfer switch. Short-circuiting a terminal from which the first differential output signal is output (for example, the terminal 310 shown in FIG. 3) and a terminal from which the analog second differential output signal is output (for example, the terminal 311 shown in FIG. 3); wherein the equalizer switch for equalizing and said analog first differential output signal analog second differential output signal (e.g. SW304q shown in FIG. 3), wherein the hold The stage is an amplifier (eg, amplifier 305 shown in FIG. 3), and the equalizer switch outputs the amplifier during a period in which the analog first differential output signal and the analog second differential output signal are equalized. The terminals (for example, the terminals 310 and 311 shown in FIG. 3) are short-circuited, and the equalization by the equalizer switch is finished after the start of the hold by the amplifier and before the end of the started hold. Features.

In the pipeline type A / D converter according to claim 2 , in the above invention, equalization by the equalizer switch is started after a sampling period by the sampling circuit is finished and before a holding period by the amplifier is started. It is desirable that

According to the first aspect of the present invention, the terminal for outputting the analog first differential output signal and the analog second differential output prior to the transfer of the analog first differential output signal and the analog second differential output signal. A terminal to which a signal is output can be short-circuited. For this reason, the analog first differential output signal and the analog second differential output signal are both at an intermediate potential, and the charge stored in the parasitic capacitance of the terminal, that is, the information on the immediately preceding state can be canceled. Become. In addition, since the initial value of the voltage between the analog first differential output signal and the analog second differential output signal approaches 0 in the hold phase, settling is performed while keeping the DC gain of the output signal high without increasing power consumption. The accuracy can be increased. Furthermore, it becomes possible to ensure the stability of the value of the output signal.
In addition, since the equalizer switch short-circuits between the output terminals of the amplifier during the period in which the analog first differential output signal and the analog second differential output signal are equalized, the stability of the operational amplifier is ensured and high-precision operation is achieved. A possible pipelined A / D converter can be provided. Further, the operation of the equalizing switch can be terminated at an appropriate timing.

請 Motomeko 2 pipeline type A / D converter according to the Ru can initiate operation of the equalizing switch at an appropriate timing.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(Configuration of pipeline type A / D converter)
FIG. 1 is a block diagram of the pipeline type A / D converter of the present embodiment. The pipeline type A / D converter of this embodiment is a converter that converts an analog differential input signal Ain into an N-bit digital output signal Dout. Therefore, an input sample and hold circuit (denoted as S / H in the figure) 101 that samples and holds the analog differential input signal Ain, and k stages (in the figure, S in the figure) connected in cascade to determine each bit. S1, S2... Sk, a memory 103 for storing n-digit digital output signals dj (j is 1 to k) determined in each stage, and a digital output signal dj stored in the memory 103. And an arithmetic circuit 104 that calculates a digital output signal Dout from an A / D conversion value of the analog differential input signal Ain.

The sample hold circuit 101 is a circuit that samples the analog differential input signal Ain and sends the held value to the first stage S1 as the analog input signal Vin. The sample and hold circuit 101 is a non-feedback sample and hold circuit including an analog switch and a capacitor.
The stages S <b> 1 to Sk are connected in series, and send an n-digit digital output signal dj to the memory 103 based on each input analog input signal Vin. In each stage, the analog input signal Vin is input from the previous stage, and the analog output signal Vout generated by the digital output signal dj and the analog input signal Vin is output to the next stage. In the figure, an analog input signal Vin and an analog output signal Vout are shown with the stage S1 as a reference. The details of the analog input signal Vin and the analog output signal Vout will be described later.

The memory 103 receives and stores an n-digit digital output signal dj from each of the k stages S1 to Sk. Therefore, the memory 103 is a semiconductor memory or the like that can store at least k n-bit addresses.
The arithmetic circuit 104 calculates based on the digital output signal dj stored in the memory 103 and outputs an N-digit digital output signal Dout. The calculation for calculating the digital output signal Dout is performed as follows.

That is, the arithmetic circuit 104 adds the most significant digit of the digital output dk of the stage Sk and the least significant digit of the digital output d (k−1) of the stage S (k−1) in a binary system. Further, based on the result of addition (added value), the most significant digit of d (k−1) and the least significant digit of the digital output d (k−2) of stage S (k−2) are also binary-coded. Add by the method.
Such processing is repeated to add up the least significant digit of the digital output d1 of the stage S1 and the most significant digit of the digital output d2 of the stage S2. The final result of the addition is output as a digital output signal Dout.

FIG. 2 is a diagram for illustrating the calculation for calculating the digital output signal Dout described above. In the example of FIG. 2, there are four stages S1 to S4, and each of the stages S1 to S4 outputs three-digit digital outputs d1 to d4 to the memory 103 shown in FIG. More specifically, the values of the digital outputs d1 to d4 are determined as follows.
d1 = 001, d2 = 100, d3 = 101, d4 = 111
In the example of FIG. 2, as a result of adding the most significant digit and the least significant digit of the digital output output by the adjacent stages, a value of “010011011” is obtained as the digital output signal Dout.

(stage)
FIG. 3 is a diagram for describing the stages of the pipeline type A / D converter of the present embodiment, and shows a circuit configuration of one of the plurality of stages. Since each of the stages S1 to Sk shown in FIG. 1 has the same circuit configuration, the description of the stage according to FIG. 3 is replaced with the description of all the stages S1 to Sk.
Each stage receives analog differential input signals VPin and VNin from the preceding stage (for the stage S1, the sample-and-hold circuit (denoted as S / H in FIG. 1) 101), outputs the digital output signal dj, and the subsequent stage. When there is a stage, it is a circuit that outputs analog differential output signals VPout and VNout to the subsequent stage, where the analog differential input signals VPin and VNin are a pair of differential signals that constitute the analog input signal Vin, The analog differential output signals VPout and VNout are a pair of differential signals constituting the analog output signal Vout.

  Each stage is a sample cap (hereinafter referred to as CAP) 307a, 307b, 307c, 307d for sampling the input analog differential input signals VPin, VNin, and a switch for determining the sampling operation timing of the CAPs 307a, 307b, 307c, 307d. (Hereinafter referred to as SW) 304a, 304c, 304d, 304i, 304k, 304l, 304b, 304e, 304j, 304m. The SWs 304a, 304c, 304d, 304i, 304k, and 304l are opened and closed according to the clock φ1, and the SWs 304b, 304e, 304j, and 304m are opened and closed according to the clock φ2.

Each stage has a control circuit 302, and a sample trigger φ3 and clocks φ1 and φ2 are output by the control circuit 302.
Each stage also converts an analog differential input signal VPin, VNin into a digital output signal dj, and a signal sampled by the CAPs 307a, 307b, 307c, 307d into the value of the digital output signal dj. Multi-value output circuits 306 and 309 that adjust accordingly are provided. The adjustment by the multi-value output circuits 306 and 309 is performed by distributing the outputs of the CAPs 307a, 307b, 307c, and 307d to predetermined multi-value outputs.

  The stage also includes an amplifier 305 that amplifies the output of the sample and hold circuit 101 shown in FIG. 1 with a predetermined gain G corresponding to the number of bits of the digital output of the A / D converter 301. The amplifier 305 is a fully differential operational amplifier, and holds and amplifies the sampled signal. In the pipeline type A / D converter 301, the gain G of the amplifier 305 must be 2 (n-1) power when the number of digits of the input digital output signal dj of the A / D converter 301 is n. I must.

Further, the pipeline type A / D converter of the present embodiment includes a SW 304q that is turned on and off in accordance with the sample trigger φ3. SW304q is a switch that short-circuits the output terminal 310 of the amplifier 305 that outputs the analog differential output signal VPout and the output terminal 311 that outputs the analog differential output signal VNout, and equalizes the analog differential output signals VPout and VNout.
The SWs 304f, 304g, and 304h included in the multi-value output circuit 306 and the SWs 304n, 304o, and 304p included in the multi-value output circuit 309 are opened / closed according to the output result of the A / D converter 301. The above SWs 304a to 304p are all analog switches.

The CAP 307a, CAP 307b, CAP 307c, CAP 307d, SW 304a, 304c, 304d, 304e, 304i, 304k, 304l, 304m, and multi-value output circuits 306, 309 are configured to generate an analog signal from the digital output signal dj. It functions as a D / A sub-converter.
Further, portions denoted by reference numerals 303 and 308 in the figure are summing nodes (denoted as Node in the figure) and can store charges.

(A / D converter)
FIG. 4 is a block diagram for explaining the A / D converter 301 shown in FIG. Here, for simplicity, the analog differential input signal is
Analog input signal Vin = VPin-VNin
Will be described. The A / D converter 301 receives the sampling trigger φ1 and determines the value of the analog differential input signal VPin in synchronization with the falling of the sampling trigger φ1. The determination circuits 401 and 402 compare the determined value of the analog differential input signal VPin with preset reference voltages (1/4) Vr, (-1/4) Vr, and digitally output the result. Output as signal dj.

The digital output signal dj is input to the multi-value output circuits 306 and 309 to control the SWs 304f to 304h and 304n to 304p. The digital output signal dj is stored in the memory 103 shown in FIG. 1 and then input to the arithmetic circuit 104 shown in FIG. The arithmetic circuit 104 receives the digital output signals d1 to dk, calculates them, and outputs a digital output signal Dout [1: 0]. The determination circuits 401 and 402 are discrete system comparators, and at this time, a delay is generated with respect to the fall of the sample trigger φ1.
FIG. 4 shows the configuration of a comparator in a 1.5-bit A / D converter. In the case of the (m + 0.5) bit A / D converter, (2 (m + 1) th power −2) comparators are required, and the reference voltages are (± 1, ± 3, ± 5,..., ± (2 (M + 1) -3)) / (2 to the (m + 1) th power).

(Operation)
The operation of the stage having the above-described configuration will be described below.
As shown in FIG. 3, the analog differential input signal VPin is guided to the CAP 307a when the SW 304c is turned on, and is guided to the CAP 307b when the SW 304d is turned on. The analog differential input signal VNin is guided to the CAP 307c when the SW 304k is turned on, and is guided to the CAP 307d when the SW 304l is turned on. The CAP 307a, CAP 307b, CAP 307c, and CAP 307d perform sampling by charging the analog differential input signals VPin and VNin. Sampling is hereinafter also referred to as sampling operation.

The analog differential input signals VPin and VNin are also input to the A / D converter 301 and converted into a digital output signal dj. The digital output signal dj is output to the memory 103 shown in FIG. 1, and is branched and guided to the SWs 304f to 304h and SWs 304n to 304p via the multi-value output circuits 306 and 309.
Here, the A / D converter 301 performs calculation by a known method to determine the value of the digital output signal dj. In the multi-value output circuits 306 and 309, the SWs 304f to 304h and the SWs 304n to 304p are turned on or off according to the value of the digital output signal dj. By turning on / off the SWs 304f to 304h and SW304n to 304p, the multi-value output circuits 306 and 309 change the analog differential output signals VPout and VNout to values within the range between the preset upper limit value and lower limit value. Adjust as follows.

  In the example shown in FIG. 3, the multi-value output circuit 306 is connected to a terminal that outputs a voltage value + VrV when the SW 304f is turned on, and is connected to a terminal that outputs a voltage value 0V when the SW 304g is turned on. When the SW 304h is turned on, it is connected to a terminal that outputs a voltage value -VrV. The multi-value output circuit 309 is connected to a terminal that outputs a voltage value + VrV when the SW 304p is turned on, is connected to a terminal that outputs a voltage value 0V when the SW 304o is turned on, and a voltage value when the SW 304n is turned on. Connect to the terminal that outputs -VrV.

(Sampling trigger and clock)
Here, the sample trigger φ3 and the clocks φ1 and φ2 shown in FIG. 3 will be described.
5A to 5C are timing charts for explaining the output timing of the sample trigger φ3 and the clocks φ1 and φ2, and the vertical axis indicates the signal values High (H) and Low (L). Time is shown on the axis. FIG. 5A is a timing chart of the clock φ1. FIG. 5B is a timing chart of the clock φ2, and FIG. 5C is a timing chart of the sample trigger φ3.
In the pipeline type A / D converter, a period in which the clock φ1 is H is a sample phase. Further, a period during which the clock φ2 is H is a hold phase.

  In the figure, t1, t2, t3, and t4 all indicate the operation timing of the pipeline type A / D converter, and t1 is an arbitrary timing included in the sampling phase. Also, t2 is a timing that is neither a sample phase nor a hold phase. Such a timing range is called a non-overlap phase. Further, t3 is included in the phase in which both the clock φ2 and the sample trigger φ3 are H, that is, in the interval of several ns after the start of the hold phase. Further, t4 is included in the phase in which the clock φ2 is H and the sample trigger φ3 is L in the hold phase.

  In the present embodiment, the fall of the sample trigger φ3 is set to be about 0.3 ns earlier than the rise of the clock φ2. Note that the clocks φ1 and φ2 are non-overlapping clocks that do not simultaneously become H, as in the prior art. In the present embodiment, the time difference between the fall of the sample trigger φ3 and the rise of the clock φ2 is set to about 0.3 ns. However, the present embodiment is not limited to such a configuration, and it goes without saying that the time difference can be set larger or smaller.

As shown in FIG. 3, the SW 304q is turned on and off by the sample trigger φ3. Assuming that SW 304q is turned on at H of sample trigger φ3 shown in FIG. 5 and turned off at L, equalization by SW 304q is performed after the end of the sampling period (after the fall of clock φ1) and before the start of the hold period. It is started (before the rise of clock φ2). Also, after the start of the hold (after the rise of the clock φ2) and before the end of the held hold (before the fall of the clock φ2).
In the stage shown in FIG. 3, the hold phase after the rise of φ2 (FIG. 5B) that occurs immediately before time t3 is the sample phase of the next stage. The next stage operates in the same manner as in this embodiment by replacing φ1 of the stage described in FIG. 3 with φ2 and φ2 with φ1.

Next, the operation of the stage of this embodiment at the timings t1 to t4 shown in FIG. 5 will be described in order.
FIG. 6 is a diagram showing the timing of t1 shown in FIG. 5, that is, the state of the stage in the sample phase. In the sample phase, the SW 304c is turned on and the analog differential input signal VPin is guided to the CAP 307a, and the SW 304d is turned on and the analog differential input signal VPin is guided to the CAP 307b. Also, SW304k is turned on and the analog differential input signal VNin is guided to CAP307c, and SW304l is turned on and the analog differential input signal VNin is guided to CAP307d. Further, since the SWs 304a and 304i are turned on, the CAPs 307a, 307b, 307c, and 307d are charged and the sample operation is performed.

In FIG. 6, SW304f is turned on and SW304g and SW304h are turned off in the operation StateN-1 of the multi-value output circuit 306. At this time, the A / D converter 301 is controlling the sample operation, and the SW 304f is turned on and connected to + Vr.
Similarly, turning on SW304n and turning off SW304o and SW304p are performed in the operation StateN-1 of the multi-value output circuit 309. At this time, the A / D converter 301 is controlling the sample operation, and the SW 304n is turned on and connected to -Vr.

  FIG. 7 is a diagram illustrating the timing of t2 in FIG. 5, that is, the state of the stage in the non-overlap phase. In the non-overlap phase, SWs 304a, 304c, 304d, 304i, 304k, 304l are turned off and SW304q is turned on. For this reason, the charges of the analog differential input signal VPin sampled by the sample caps CAP 307 a and 307 b are stored and determined in the summing node 303. The charges of the analog differential input signal VNin sampled in the sample caps CAP 307 c and 307 d are stored and determined in the summing node 308. At this time, since the terminal 310 that outputs the analog differential output signal VPout and the terminal 311 that outputs VNout are short-circuited by the SW 304q, the voltage between VPout and VNout approaches approximately 0, and VPout and VNout are equalized. . That is, the SW 304q short-circuits the terminal 310 and the terminal 311 during the period when VPout and VNout are equalized.

  In FIG. 7, the calculation result of the A / D converter 301 is reflected in the multi-value output circuit 306, and the operation of the multi-value output circuit 306 indicates that from the operation State N−1, SW 304 h is turned on and SW 304 f and SW 304 g are turned off. This is done in StateN. Similarly, the operation result of the A / D converter 301 is reflected in the multi-value output circuit 309, and from the operation State N-1, the SW 304p is turned on and the SW 304n and the SW 304o are turned off from the operation State N of the multi-value output circuit 309. Done in

  FIG. 8 is a diagram showing the state of the stage at the timing t3 in FIG. 5, that is, 0.3 ns after the start of the hold phase. In the hold phase, the SWs 304e and 304b and the SWs 304m and 304j are turned on according to the trigger φ2. At this time, in the hold phase, calculations are performed on the charges stored in the summing node 303 and the summing node 308 in the CAPs 307a and 307b and the CAPs 307c and 307d. At this time, the charges charged in the CAPs 307a and 307b and the CAPs 307c and 307d are transferred to the subsequent stage reflecting the influence of the SWs 304e and 304b and the SWs 304m and 304j being turned on.

As a result of the transfer, the analog differential output signals VPout and VNout are output to the subsequent stage as target values.
At this time, in this embodiment, since the SW 304q is turned on first, the output signal terminals VPout and VNout are short-circuited. For this reason, the initial values of the output signals VPout and VNout are 0, and the settling time until the step input signal converges can be shortened.

More specifically, when the input ranges of VPin and VNin are 0.5V to 1.5V, VPin = 0.5V and VNin = 1.5V are input in the sample phase immediately before the non-overlap phase. In the subsequent hold phase, VPin = 1.5V and VNin = 0.5V are input. Under such conditions, it is generally known that the settling time becomes long.
Even in such a case, if VPout and VNout are short-circuited in the non-overlap phase, the slew rate of the step response for several ns after the start of the hold phase can be greatly improved. For this reason, according to the present embodiment, the settling accuracy can be improved even when the settling conditions are severe.

  FIG. 9 is a diagram illustrating the state of the stage when φ2 is H and φ3 is L in the timing of t4 in FIG. 5, that is, the hold phase. In the hold phase, the CAPs 307a and 307b perform calculations on the charges stored in the summing node 303. SW304e and SW304b are turned on according to the trigger φ2. The charges charged in the CAPs 307a and 307b reflect the influence of turning on the SWs 304e and 304b, and are transferred to the subsequent stage. As a result of the transfer, the analog differential output signal VPout is output to the subsequent stage as a target value.

  Similarly, calculation is performed on the charges stored in the summing node 308 by the sample caps CAP 307 c and 307 d. The SWs 304m and 304j are turned on according to the trigger φ2. The charges charged in the sample caps and CAPs 307c and 307d are transferred to the subsequent stage, reflecting the effect of turning on the SWs 304m and 304j. As a result of the transfer, the analog differential output signal VNout is output to the subsequent stage as a target value.

(Effect of embodiment)
Next, the effect of this embodiment will be described.
FIG. 10 is a diagram for explaining a change in the analog differential output signal VPout−VNout (difference between the analog differential output signals VPout and VNout output at the same time) as a step response according to the present embodiment. The axis indicates the analog differential output signal VPout−VNout, and the horizontal axis indicates time. The analog differential output signal VPout-VNout shown on the vertical axis is a plot of the output waveform when a unit step is input to the stage shown in FIG. It is assumed that the final target value appearing in the analog differential output signal VPout−VNout is normalized to 1, and a step input with a target value of 1.0 is input to the analog differential input signal VPin−VNin. In this normalization, when VPout = VNout, a step input whose target value is 0.5 is input.

FIG. 10A shows a step response appearing in the analog differential output signal VPout−VNout in the present embodiment. The time t3 in the figure represents the start time of the hold phase as described above, and the time t6 represents the time when the SW 304q in FIG. 3 is turned off.
FIG. 10B shows a step response of a configuration for comparison with the present embodiment. The configuration for comparison with the present embodiment refers to a configuration in which the switch SW304q is removed from the stage shown in FIG.

  According to FIG. 10B, as a result of the calculation by the A / D converter 301 shown in FIG. 3, the step response due to switching of the switches in the multi-value output circuit after entering the hold phase is the analog differential output signal VPout, Appears in VNout. Therefore, the step response of the transfer function from the node MX or the node MY shown in FIG. 3 to the analog differential output signals VPout and VNout, and the analog differential input signals VPin and VNin to the analog differential output signals VPout and VNout. The step response of the transfer function is superimposed after the hold operation. Therefore, the step response after the hold operation is increased, and the time until the step response converges, that is, settling is delayed.

  On the other hand, in the present embodiment, as shown in (a), since SW 304q shown in FIG. 3 is on from time t5 to time t6, the analog differential input signal VPin−VNin is not related to the target value. It converges to the target value of VPout = VNout, that is, 0.5. Therefore, it does not depend only on the slew rate determined by the amplifier 305 shown in FIG. 3, but converges to the target value 0.5 by the sum of the slew rate determined by the amplifier 305 and the slew rate depending on the ON resistance of the SW 304q. Therefore, this embodiment can significantly improve the slew rate without increasing the power consumption of the preamplifier 305.

  Since the SW 304q shown in FIG. 3 is turned off after time t6, the step response obtained when the step input of the initial value 0.5 and the target value 1.0 is input to the transfer function as in the prior art. Appearing in the analog differential output signal VPout−VNout. Since the initial value has already converged to 0.5 at time t6, the overshoot of the step response appearing in the analog differential output signal VPout−VNout is suppressed, and the settling accuracy is improved.

  According to the present embodiment described above, the SW 304q is turned on by the control signal φ3 that is in the non-overlap phase and becomes H for several ns after the start of the hold phase. For this reason, the analog differential output signal VPout and the analog differential output signal VNout are short-circuited within a few ns after the start of the hold phase. During several ns, the slew rate of the step response is greatly improved. Therefore, it is possible to provide a pipelined A / D converter that operates with high accuracy without increasing power consumption.

It is a block diagram of the pipeline type A / D converter of one embodiment of the present invention. FIG. 2 is a diagram for illustrating an operation for calculating a digital output signal Dout illustrated in FIG. 1. It is a figure for demonstrating the stage of the pipeline type A / D converter of one Embodiment of invention. It is a block diagram for demonstrating the A / D converter shown in FIG. It is a timing chart for demonstrating the output of sample trigger (phi) 3 and clock (phi) 1, (phi) 2 of one Embodiment of invention. It is a figure showing the state of the stage in the sample phase of one Embodiment of this invention. It is a figure showing the state of the stage in the non-overlap phase of one Embodiment of this invention. It is a figure showing the state of the stage immediately after the start of the hold phase of one Embodiment of this invention. It is a figure showing the state of the stage in the hold phase of one Embodiment of this invention. It is a figure for demonstrating the change of the analog differential output signal VPout-VNout which is a step response. It is a figure for demonstrating the invention equivalent to the prior art of the pipeline type A / D converter of one Embodiment of this invention.

Explanation of symbols

101 Sample hold circuit 103 Memory 104 Arithmetic circuit 301 A / D converter 302 Control circuit 303, 308 Summing nodes 304a, 304b, 304c, 304d, 304e, 304f, 304g, 304h, 304i, 304j, 304k, 304l, 304m, 304n , 304o, 304p switch 305 amplifier 306, 309 multi-value output circuit 307a, 307, b 307c, 307d sample cap 310, 311 terminal 401, 402 determination circuit

Claims (2)

The analog first input signal and the analog second input signal that forms a differential signal pair with the analog first input signal are converted into a digital signal, and the digital signal, the analog first input signal, and the analog second input are converted. A pipeline type A / D converter comprising a plurality of stages for outputting an analog first differential output signal and an analog second differential output signal generated by a signal to another stage after the signal,
The stage is
A sampling circuit for separately sampling the analog first input signal and the analog second input signal;
A sample timing changeover switch for determining a sampling operation timing of the sampling circuit;
A sampling value adjusting circuit for adjusting the value of the analog first input signal and the value of the analog second input signal sampled in the sampling circuit, respectively, according to the value of the digital signal;
Holding means for holding the analog first input signal and the analog second input signal adjusted by the sampling value adjustment circuit;
A transfer switch for outputting the analog first input signal and the analog second input signal held by the hold means to the other stage as the analog first differential output signal and the analog second differential output signal. When,
Prior to transfer by the transfer switch, a terminal from which the analog first differential output signal is output and a terminal from which the analog second differential output signal is output are short-circuited, and the analog first differential output signal is An equalizer switch for equalizing the analog second differential output signal;
Equipped with a,
The holding means is an amplifier;
The equalizer switch short-circuits between the output terminals of the amplifier during a period in which the analog first differential output signal and the analog second differential output signal are equalized.
The pipeline type A / D converter is characterized in that the equalization by the equalizer switch is ended after the start of the hold by the amplifier and before the end of the started hold . The equalization by the equalizer switch, after the end of the sampling period by the sampling circuit, a pipeline type A / D converter according to claim 1, characterized in that it is initiated before the period of holding by the amplifier is started.

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