JP5097064B2 - Pipeline type A / D converter and control method for pipeline type A / D converter - Google Patents

Description

  The present invention relates to a pipeline type A / D converter and a method for controlling a pipeline type A / D converter.

FIG. 14 is a diagram for explaining the prior art of the pipeline type A / D converter. The prior art of such a pipeline type A / D converter is described in Patent Document 1, for example. This figure is a circuit diagram of a stage constituting the pipeline type A / D converter described in Patent Document 1, and includes an A / D conversion unit 40, two D / A conversion units D / A1, and D / D. A2 is provided. An analog input signal Vin is input to the A / D converter 40 and A / D converted. The converted digital signal is output to a control circuit that performs an operation using the digital signal and is D / A converted. The D / A converted analog signal is distributed to multi-value output values by two multi-value output circuits M1 and M2.

The illustrated stage includes two switchable sample and hold circuits S / H10 and S / H20 that sample and hold the analog input signal Vin. While one of the sample and hold circuits is in the hold operation, the other sample and hold circuit performs the sample operation.
The two sample and hold circuits are composed of a circuit in which analog switches SW1 and SW2 and capacitors C1 and C2 are connected in series, and a circuit in which analog switches SW3 and SW4 and capacitors C3 and C4 are connected in series, both connected in parallel. Has been. In each sample and hold circuit, the capacitances of the two capacitors are equal.

  When one of the capacitors included in one of the sample and hold circuits is connected to the input terminal of the operational amplifier 71, one of the capacitors included in the other of the sample and hold circuit is not connected to the input terminal of the operational amplifier 71. When the other of the capacitors included in one of the sample and hold circuits is connected to one output terminal of the multi-value output circuit, the other of the capacitors included in the other of the sample and hold circuit is the other of the multi-value output circuit. Not connected to.

With such a configuration, the conventional technology can alternately sample or hold the two sample and hold circuits S / H10 and S / H20.
JP 2000-13232 A

  However, in the pipeline type A / D converter described above, it takes time until the calculation results of the D / A converters D / A1 and D / A2 are reflected on the node MX shown in the drawing. For this reason, the step input to the node MX occurs during the hold operation by the sample hold circuits S / H10 and S / H20. For this reason, in the prior art, useless time occurs in the output (step response) in response to the step input. In addition, a step response of a transfer function having a high-pass filter (HPF) characteristic is superimposed on the analog output signal Vout.

Increasing the output current can be considered to settle the step response to a negligible level. However, according to this method, it is necessary to increase the output current, which increases the consumption current of the pipeline type A / D converter.
The present invention has been made in view of the above points, and an object of the present invention is to provide a pipeline type A / D converter that can operate at high speed but does not increase power consumption.

In order to solve the above problems, a pipelined A / D converter according to claim 1 of the present invention inputs an analog input signal, converts it into a digital signal, and outputs the digital signal. a pipelined a / D converter having a plurality of stages for outputting the generated analog output signal to the other stages of the subsequent stage by the signal, the stage, the sample cap for sampling the analog input signal, provided between the other terminal and a reference potential between and the sample cap with one terminal of the sample cap and the input terminal of said analog input signal, the sample timing switch which determines the sampling operation timing of the sample cap and switches, wherein a sampled at the sample cap A multi-value output circuit that adjusts the value of the analog input signal to the analog input signal of the subsequent stage according to the value of the digital signal, and is provided between the sample cap and the output terminal of the analog output signal. , and a transfer switch for outputting a signal after adjustment by said multi-value output circuit in the other stages of the subsequent stage, the multi-value output circuit includes a plurality of adjustment switches, according to the value of the digital signal A circuit that adjusts the value of the analog input signal by switching the adjustment switch, and the adjustment is performed according to the digital signal determined by a trigger generated before a sampling operation start timing by switching of the sample timing selector switch. by switching the switch, faster than the transfer initiation by switching of the transfer switch Timing In grayed, characterized in that to complete the adjustment of the value of the analog input signal corresponding to the value of the digital signal.

Further, a pipeline type A / D converter according to claim 2 is the invention according to claim 1, wherein the stage further comprises a Saminguno de for storing the analog input signals sampled by the sample cap The multi-value output circuit reflects a change in voltage value caused by switching of the adjustment switch in the voltage applied to the summing node at a timing earlier than the start of transfer by switching of the transfer switch.

According to a third aspect of the present invention, there is provided a method for controlling a pipelined A / D converter, wherein an analog input signal is input, converted into a digital signal and output, and the digital signal and the analog input signal are generated. a plurality of stages for outputting an analog output signal to the other stages of the subsequent stage, the stage, the sample cap for sampling the analog input signal, with one terminal of input terminals of the analog input signal and the sample cap provided between and between the other terminal and a reference potential of the sample cap, said sump and sample timing changeover switch for determining the sampling operation timing of Le cap, the sample values of the analog input signal sampled in the cap a second-stage in accordance with the value of the digital signal And the multi-level output circuit for adjusting the analog input signal of the stage, the sample cap and said provided between the output terminal of the analog output signal, other stages of the subsequent signals adjusted by said multi-value output circuit a transfer switch for outputting, a pipeline type a / D converter control method comprising the in the, at a timing earlier than the start transfer by switching of the transfer switches, the multi-value output circuit to the value of the digital signal depending said saw including a complete adjustment step adjusts the value of the analog input signal, said adjusting step adjusts the value of the analog input signal by switching the adjustment switch in accordance with the value of the digital signal, the Confirmed by a trigger generated before the sampling operation start timing by switching the sample timing selector switch And switches the adjustment switch in accordance with said digital signal.

According to the first aspect of the present invention, the multi-value output circuit completes the adjustment of the value of the analog input signal according to the value of the digital signal at a timing earlier than the start of transfer by switching the transfer switch. The analog output signal that becomes the value does not change after the start of the hold operation. For this reason, the settling time of the analog output signal can be eliminated or shortened. Further, since it is not necessary to increase the output current in order to suppress settling, the power consumption of the pipeline type A / D converter is not increased. Therefore, it is possible to provide a pipeline type A / D converter that can operate at high speed and does not increase power consumption.

That is, the pipeline type A / D converter according to the present invention can switch the adjustment switch according to the trigger generated before the timing of starting the sampling operation. For this reason, in the analog output signal, the step response generated by the switching of the adjustment switch occurs before the step response due to the switching of the transfer switch. Therefore, the step response corresponding to the adjustment switch may be generated before the hold operation. it can. Since only the step response to the transfer switch switching occurs during the hold operation, the target value does not change after the hold operation, and the settling performance can be improved. In addition, such an operation can be performed by switching the adjustment switch according to a trigger generated before the multi-value output circuit starts sampling, so that the output current does not increase and the power consumption for high-speed operation. Can also be avoided.

Further, the pipeline type A / D converter according to claim 2 reflects the step response generated by the switching of the adjustment switch in the voltage applied to the summing node before the start of the hold operation. It can be generated before the hold operation. Since only the step response to the switching of the transfer switch occurs during the hold operation, the target value does not change after the hold operation, and the settling performance can be improved. Further, it is possible to avoid increasing the power consumption for high-speed operation without increasing the output current.

Further, the pipeline type A / D converter control method according to the third aspect can eliminate or shorten the settling time of the analog output signal. Further, since it is not necessary to increase the output current in order to suppress settling, the power consumption of the pipeline type A / D converter is not increased. Therefore, it is possible to provide a method for controlling a pipelined A / D converter that can operate at high speed and does not increase power consumption.

That is, since the pipeline type A / D converter control method according to the present invention generates only a step response to the transfer switch switching during the hold operation, the target value does not change after the hold operation, and the settling performance can be improved. it can. In addition, such an operation can be performed by switching the adjustment switch according to a trigger generated before the multi-value output circuit starts sampling, so that the output current does not increase and the power consumption for high-speed operation. Can also be avoided.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(Configuration of pipeline type A / D converter)
FIG. 1 is a block diagram of the pipeline type A / D converter of the present embodiment. The pipeline type A / D converter of this embodiment is a converter that converts an analog input signal Ain into an N-bit digital output signal Dout. Therefore, an input sample hold circuit (denoted as S / H in the figure) 101 that samples and holds the analog input signal Ain, and k stages connected in cascade for determining each bit (denoted as S in the figure). ) S1, S2... Sk, a memory 103 for storing n-digit digital output signals dj (j is 1 to k) determined in each stage, and an analog input based on the digital output signals dj stored in the memory 103 And an arithmetic circuit 104 for calculating a digital output signal Dout from an A / D conversion value of the signal Ain.

The sample hold circuit 101 is a circuit that samples the analog input signal Ain and sends the held value to the first stage S1 as the analog input signal Vin. The sample and hold circuit 101 is a non-feedback sample and hold circuit including an analog switch and a capacitor.
The stages S <b> 1 to Sk are connected in series, and send an n-digit digital output signal dj to the memory 103 based on each input analog input signal Vin. In each stage, the input analog input signal Vin is converted based on the D / A conversion result of the digital output signal dj, and is output to the next stage as the analog output signal Vout.

The memory 103 receives and stores an n-digit digital output signal dj from each of the k stages S1 to Sk. Therefore, the memory 103 is a semiconductor memory or the like that can store at least k n-bit addresses.
The arithmetic circuit 104 calculates based on the digital output signal dj stored in the memory 103 and outputs an N-digit digital output signal Dout. The calculation for calculating the digital output signal Dout is performed as follows.

That is, the arithmetic circuit 104 adds the most significant digit of the digital output dk of the stage Sk and the least significant digit of the digital output d (k−1) of the stage S (k−1) in a binary system. Further, based on the result of addition (added value), the most significant digit of d (k−1) and the least significant digit of the digital output d (k−2) of stage S (k−2) are also binary-coded. Add by the method.
Such processing is repeated to add up the least significant digit of the digital output d1 of the stage S1 and the most significant digit of the digital output d2 of the stage S2. The final result of the addition is output as a digital output signal Dout.

FIG. 2 is a diagram for illustrating the calculation for calculating the digital output signal Dout described above. In the example of FIG. 2, there are four stages S1 to S4, and each of the stages S1 to S4 outputs three-digit digital outputs d1 to d4 to the memory 103 shown in FIG. More specifically, the values of the digital outputs d1 to d4 are determined as follows.
d1 = 001, d2 = 100, d3 = 101, d4 = 111
In the example of FIG. 2, as a result of adding the most significant digit and the least significant digit of the digital output output by the adjacent stages, a value of “010011011” is obtained as the digital output signal Dout.

(stage)
FIG. 3 is a diagram for describing the stages of the pipeline type A / D converter of the present embodiment, and shows a circuit configuration of one of the plurality of stages. Since each of the stages S1 to Sk shown in FIG. 1 has the same circuit configuration, the description of the stage according to FIG. 3 is replaced with the description of all the stages S1 to Sk.
Each stage receives an analog input signal Vin from the preceding stage (sample hold circuit S / H101 for stage S1) and outputs a digital output signal dj. If there is a subsequent stage, each stage is set to the subsequent stage. This circuit outputs an analog output signal Vout.

For this purpose, each stage includes sample caps (shown as CAP in the figure) 307a and 307b that sample the input analog input signal Vin, and an A / D converter that converts the analog input signal Vin into a digital output signal dj. 301 and a multi-value output circuit 306 that distributes the output of the sample cap 307a to a predetermined multi-value output.
Further, the pipeline type A / D converter of the present embodiment amplifies the output of the sample hold circuit S / H101 shown in FIG. 1 with a predetermined gain G corresponding to the number of bits of the digital output of the A / D converter 301. An amplifier 305 is provided. In the pipeline type A / D converter, the gain G of the amplifier 305 must be 2 (n-1) when the number of digits of the input digital output signal dj of the A / D converter 301 is n. Don't be.

Further, the pipeline type A / D converter of this embodiment includes a switch 304a that opens and closes according to the sample trigger φ1F, a switch 304b that opens and closes according to the clock φ2, a switch 304c and a switch 304d that opens and closes according to the clock φ1, and a sample trigger φ 2F. The switch 304e opens and closes according to the above.
The switches 304f, 304g, and 304h included in the multi-value output circuit 306 are opened / closed according to the output result of the A / D converter 301. The above switches 304a to 304h are all analog switches.

In the present embodiment, the pipeline type A / D converter has a control circuit 302, the sample trigger φ1F, φ 2 F, clocks .phi.1, shall φ2 is output by the control circuit 302.
A portion indicated by reference numeral 303 in the figure is a summing node (denoted as Node in the figure), and can store charges.
The sample caps 307a and 307b, the switches 304a, 304c, 304d, and 304e and the multi-value output circuit 306 are configured to convert the digital output signal dj into an analog signal and function as a D / A sub-converter.

(A / D converter)
FIG. 4 is a block diagram for explaining the A / D converter 301 shown in FIG. A / D converter 301 receives the sample trigger Fai1F, to determine the value of the analog input signal Vin in synchronization with the falling of the sample trigger Fai1F. The determination circuits 401 and 402 compare the determined value of the analog input signal Vin with preset reference voltages (1/3) Vr, (−1/3) Vr, and the result is a digital output signal dj. Output as.

The digital output signal dj is input to the multi-value output circuit 306 to control the switches 304f to 304h. Further, after being stored in the memory 103 shown in FIG. 1, it is inputted to the arithmetic circuit 104 shown in FIG. The arithmetic circuit 104 receives the digital output signals d1 to dk, calculates them, and outputs a digital output signal Dout [1: 0]. The determination circuits 401 and 402 are discrete system comparators, and at this time, a delay is generated with respect to the fall of the sample trigger φ1F.
FIG. 4 shows the configuration of a comparator in a 1.5-bit A / D converter. In the case of an (m + 0.5) bit A / D converter, (2 (m + 1) th power-1) comparators are required, and the reference voltages are (1, 3, 5,..., (2 (m + 1)). (Multiplier-3)) / (2 to the (m + 1) th power-1).

(Operation)
The operation of the stage having the above-described configuration will be described below.
The analog input signal Vin is guided to the sample cap 307a when the switch 304c is turned on, and is guided to the sample cap 307b when the switch 304d is turned on. The sample caps 307a and 307b perform sampling by charging the charge of the analog input signal Vin (also referred to as sample operation).
The analog input signal Vin is also input to the A / D converter 301 and converted into a digital output signal dj. The digital output signal dj is output to the memory 103 shown in FIG. 1, is branched, and is guided to the switches 304 f to 304 h via the multi-value output circuit 306.

Here, the A / D converter 301 performs calculation by a known method to determine the value of the digital output signal dj. In the multi-value output circuit 306, the switches 304f to 304h are turned on or off according to the value of the digital output signal dj. On the switch 304F～304h, the off multilevel output circuit 306 adjusts the analog input signal V in, so that a value in the range between the upper limit value and the lower limit value set in advance.
In the example shown in FIG. 3, the switch 304f is turned on and connected to a terminal that outputs a voltage value + VrV. Further, when the switch 304g is turned on, it is connected to a terminal that outputs a voltage value 0V, and when the switch 304h is turned on, it is connected to a terminal that outputs a voltage value -VrV.

(Sample trigger and clock)
Here, the sample triggers φ1F and φ2F and the clocks φ1 and φ2 shown in FIG. 3 will be described.
FIGS. 5A to 5D are timing charts for explaining the output timing of the sample triggers φ1F and φ2F and the clocks φ1 and φ2, and the vertical axis indicates the signal values High (H) and Low (L). The horizontal axis indicates time. FIG. 5A is a timing chart of the sample trigger φ1F. FIG. 5B is a timing chart of the clock φ1. FIG. 5C is a timing chart of the clock φ2, and FIG. 5D is a timing chart of the sample trigger φ2F. FIG. 5E is a timing chart showing the operation state of the multi-value output circuit 306.

In the pipeline type A / D converter, a period in which both the clock φ1 and the sample trigger φ1F are H is a sample phase. In addition, a period in which both the clock φ2 and the sample trigger φ2F are H is a hold phase.
In the figure, t ₁ , t ₂ , t ₃ , t ₄ , and t ₅ all indicate the operation timing of the pipeline type A / D converter, and t ₁ is an arbitrary one included in the sampling phase. It is timing. T ₂ represents a sampling time for sampling. t ₃ indicates an arbitrary timing from the end of the sampling phase to the start of the hold phase, and t ₄ indicates a timing at which the calculation result of the A / D converter 301 is reflected on the summing node (Node 303). t ₅ shows the start timing of the hold phase.

The timing at which the calculation result is reflected on the summing node (Node 303) means that the switches 304f to 304h included in the multi-value output circuit 306 are opened and closed, the operation state is switched from N-1 to N, and the switch 304e. Is the timing ( φ 2F) when the is turned on. Further, the completion of the opening / closing of the switch in the present embodiment means that the switches 304f to 304h complete a predetermined opening / closing operation to be executed from the start of the sample operation to the start of the hold operation. Furthermore, in this embodiment, it is assumed that “adjustment of the value of the analog input signal is completed” when the opening / closing of the switch is completed.

  In the present embodiment, the switches 304f, 304g, and 304h of the multi-value output circuit 306 are switched at a timing when the calculation result is reflected. At this time, in this embodiment, as will be described later, the switch 304f is turned off, and the switch 304h is turned on instead. As a result, the calculation result of the A / D converter 301 is reflected on the node MX shown in FIG. 3, and the voltage applied to the node MX changes from + Vr to −Vr.

In the present embodiment, the rise of the sample trigger φ1F is set about 1 ns earlier than the rise of the clock φ1, and the fall of the sample trigger φ1F is set about 1 ns earlier than the fall of the clock φ1. Similarly, the rise of the sample trigger φ2F is 1ns about earlier than the rising edge of the clock φ2, the fall of the sample trigger φ2F is 1ns about earlier setting than the falling edge of the clock φ2. Note that the clocks φ1 and φ2 are non-overlapping clocks that do not simultaneously become H, as in the prior art.

Here, for comparison with the present embodiment, a timing chart of the conventional clocks φ1 and φ2 will be described with reference to FIG. 6A and 6B, the vertical axis represents signal values High (H) and Low (L), and the horizontal axis represents time. FIG. 6A is a timing chart of the clock φ1, and FIG. 6B is a timing chart of the clock φ2. FIG. 6C is a timing chart of the operation state of the multilevel output circuit 306. Note that t ₁ , t ₃ , and t ₅ shown in the figure indicate the same timings as t ₁ , t ₃ , and t ₅ shown in FIG. Note that t ₆ indicates the timing at which the operation state of the multi-value output circuit 306 is switched.

When the timing chart shown in FIG. 6 is compared with the timing chart of FIG. 5, the present embodiment shows that the operation state of the multi-value output circuit 306 is switched at the timing t ₆ after the start of the hold phase in the prior art. The operation state of the multi-value output circuit 306 is switched before the start of the hold phase (timing of t5).

Such differences, whereas in the present embodiment the sampling timing of the A / D converter 301 shown in FIG. 3 is controlled by the sample trigger Fai1F, clock φ1 is A / D converter 301 in the prior art This occurs to control the sampling timing. That is, in this embodiment, switching of the switch in the multi-level output circuit 306 is started earlier than in the prior art, and switching of the switch of the multi-level output circuit 306 is completed at the start of the hold phase.
In the present embodiment, the time difference between the rise and fall of the sample trigger φ1F and sample trigger φ2F and the clock φ1 and clock φ2 is about 1 ns. However, the present embodiment is not limited to such a configuration, and it goes without saying that the time difference can be set larger or smaller.

Then, sequentially illustrating the operation of the stage of the present embodiment at the timing of t ₁ ~t ₅ shown in FIG.
Figure 7 is a diagram showing the timing of t ₁ shown in FIG. 5, i.e., the state of the stage in the sample phase. In the sample phase, the switch 304c is turned on to guide the analog input signal Vin to the sample cap 307a. Further, the switch 304d is turned on, and the analog input signal Vin is guided to the sample cap 307b. Further, since the switch 304a is turned on, the sample caps 307a and 307b are charged and the sample operation is performed.

In FIG. 7, the switch 304 f is turned on and the switches 304 g and 304 h are turned off in the operation StateN−1 of the multilevel output circuit 306. At this time, the A / D converter 301 is controlling the sample operation, and the switch 304f is turned on and connected to + Vr.
FIG. 8 is a diagram showing the stage state at the timing t ₂ in FIG. 5, that is, the sampling timing. At the sampling timing, the switch 304a is turned off. Therefore, the charge of the analog input signal Vin sampled in the sample caps 307 a and 307 b is stored and determined in the summing node 303.
FIG. 9 is a diagram showing the timing of t ₃ in FIG. 5, that is, the state of the stage after the end of the sample phase. After the sample phase is completed, the switches 304c and 304d are turned off, and the sample caps 307a and 307b are disconnected from the analog input signal Vin.

FIG. 10 is a diagram showing the state of the stage at the timing of t _{4 in} FIG. 5, that is, the timing at which the calculation result of the A / D converter 301 is reflected on the summing node (Node 303). In the present embodiment, at the timing when the calculation result is reflected on the summing node (Node 303), after the switch 304f and the switch 304h are opened and closed through the multi-value output circuit 306 and the switch 304h is connected to -Vr, The switch 304e is turned on. When the switch 304h is turned on, the operation StateN-1 of the multi-value output circuit 306 is switched to the next operation StateN, and when the switch 304e is turned on, the operation result is reflected on the summing node (Node 303).

Referring now to FIG. 6, as in the prior art, when controlling the sampling of the A / D converter 301 by the clock .phi.1, switches 304f, complete timing t ₆ to open and close the switch 304h is, the rising of φ2 Timing t ₅ , that is, after the start of the hold operation. Therefore, in the prior art, the state of the circuit shown in FIG. 10 does not exist during operation. In such a conventional technique, the step input due to switching of the switch 304h of the multi-value output circuit 306 is superimposed on the step response due to switching of the switch 304b after the hold operation during the hold operation, and the target value fluctuates.

On the other hand, in the present embodiment, by introducing the rise, slightly timing falling early sample trigger Fai1F than .phi.1, it controls the sampling operation of the A / D converter 301 by the sample trigger Fai1F. Therefore, since the hold operation is started after the opening / closing of the switches 304f, 304g, and 304h of the multi-value output circuit 306 is completed, the step input by the switch 304h is not generated during the hold operation, and the input step response In addition, no time is wasted and the step response of the transfer function having the HPF characteristic is not superimposed on the target value.

Figure 11 is a diagram showing the timing of FIG. 5 in t _5, namely the state of the stage at the timing of the hold phase. In the hold phase, calculation is performed on the charges stored in the summing node 303 by the sample caps 307a and 307b. The switches 304e and 304b are turned on according to the sample trigger φ2F and the clock φ2. The charges charged in the sample caps 307a and 307b are transferred to the subsequent stage, reflecting the influence of turning on the switches 304e and 304b. As a result of the transfer, the analog output signal Vout is output to the subsequent stage as a target value.

(Effect of embodiment)
Next, the effect of this embodiment will be described. FIGS. 12A to 12F are diagrams for explaining the effects of the present embodiment. Figure 12 (d) ~ (f) shows about the present type state, FIG. 12 (a) ~ (c) shows the conventional example noted for comparison with the present embodiment. 12A to 12F, the vertical axis represents the analog output signal Vout that is the target value, and the horizontal axis represents time. T ₄ and t ₅ shown in FIG. 12 indicate the same timing as t ₄ and t ₅ shown in FIG.

Also, _{t 6} in FIG. 12 refers to the same timing as _{t 6} in FIG. t _6, the opening and closing of the switch 304f~304h is completed when controlling the multi-value output circuit 306 in the prior art as with the reference clock .phi.1, operation State refers to the switched timing from N-1 to N. In the example shown in FIG. 12, the final target value appearing in the analog output signal Vout is normalized to 1. Then, a step input at which the target value is 1.3 is input to the analog input signal Vin, and a step input at which the target value is −0.3 is input to the node MX shown in FIG.

  FIGS. 12A and 12D show target values when the analog input signal Vin is step-inputted in the transfer function from the analog input signal Vin to the analog output signal Vout. FIGS. 12B and 12E show target values when a step input is made to the node MX in the transfer function from the node MX to the analog output signal Vout shown in FIG. FIG. 12C shows a target value appearing in the analog output signal Vout obtained by adding the output signals Vout shown in FIGS. 12A and 12B. FIG. 12F shows a target value appearing in the analog output signal Vout obtained by adding the output signals Vout shown in FIGS. 12D and 12E.

As shown in FIGS. 12A and 12D, a step response appears in the analog output signal Vout simultaneously with the start of the hold phase. However, in the prior art, as shown in FIG. 12B, after the start of the hold phase, a step response responding to the step input to the node MX appears, and at step ₅ when the hold phase starts, two step responses are obtained. It is superimposed on the target value. For this reason, as shown in FIG. 12C, the analog output signal Vout which is the target value varies after the start of the hold operation.

On the other hand, in the present embodiment, as shown in FIG. 12 (e), the step response which responds to a step input to the node MX appears to t ₅ previously. Therefore, as shown in FIG. 12 (f), the step input to the node MX does not affect the analog output signal Vout at the start of the hold phase. Therefore, in this embodiment, by shifting the timing at which the step response appears between the switch 304b and the multi-value circuit 306, it is possible to prevent the step response from being superimposed after the start of the hold operation and to prevent the target value from fluctuating.

  FIG. 13 is a diagram for explaining a change in the analog output Vout, which is a target value, in this embodiment, where the vertical axis indicates the analog output Vout and the horizontal axis indicates time. The analog output Vout shown on the vertical axis is a plot of the output waveform when a unit step is input to the stage shown in FIG. The plot shown as “prior art” shows the output waveform of the example shown in FIG. 12C, and the plot shown as “present invention” shows the output waveform of the example shown in FIG. It is a result.

In FIG. 13, the final target value appearing in the analog output signal Vout is normalized to 1, and a step input with the target value 1.3 is input to the analog input signal Vin and the target value is −0.3 is input to the node MX. Shall.
According to FIG. 13, in the conventional technique, as a result of calculation by the A / D converter 301, a step response due to switching of the switches in the multi-value output circuit 306 appears in the analog output signal Vout after entering the hold phase. Therefore, the step response of the transfer function from the node MX shown in FIG. 3 to the analog output signal Vout and the step response of the transfer function from the analog input signal Vin to the analog output signal Vout are superimposed after the hold operation. Therefore, the step response after the hold operation is increased, and the time until the step response converges, that is, settling is delayed.

  On the other hand, in this embodiment, the step response of the transfer function of the node MX → Vout in FIG. 13 appears before the hold operation in the output signal Vout that is the analog target value. For this reason, the settling performance is greatly improved without being superimposed on the analog input signal Vin after the start of the hold operation. For this reason, when the settling error of the same level as the prior art is allowed, the power consumption can be greatly reduced.

Incidentally, t ₅ after the hold phase, shown in Figure 5, the sample phase in the subsequent stage shown in FIG. Subsequent stage, .phi.1 the .phi.2 stage described in FIG. 3, φ2F the Fai1F, the .phi.2 .phi.1, operates similarly to the embodiment by replacing phi 2F to phi 1F.
As another method, in the present embodiment, in a pipeline type A / D converter in which a plurality of stages for performing A / D conversion and D / A conversion are connected in cascade, the result of conversion by the D / A sub-converter is obtained. A structure with a short period reflected in the summing node 303 may be used.

It is a block diagram of the pipeline type A / D converter of one embodiment of the present invention. FIG. 2 is a diagram for illustrating an operation for calculating a digital output signal Dout illustrated in FIG. 1. It is a figure for demonstrating the stage of the pipeline type A / D converter of one Embodiment of invention. It is a block diagram for demonstrating the A / D converter shown in FIG. It is a timing chart for demonstrating the output of sample trigger (phi) 1F, (phi) 2F and clock (phi) 1, (phi) 2 of one Embodiment of this invention. It is a figure for demonstrating the timing chart of clock (phi) 1 and (phi) 2 output of a prior art. It is a figure showing the state of the stage in the sample phase of one Embodiment of this invention. It is a figure showing the state of the stage in the sampling timing of one Embodiment of this invention. It is a figure showing the state of the stage after completion | finish of the sample phase of one Embodiment of this invention. It is a figure showing the state of the stage in the timing when the calculation result of the A / D converter of one Embodiment of this invention is reflected in a summing node (Node303). It is a figure showing the state of the stage in the timing of the hold phase of one Embodiment of this invention. It is a figure for demonstrating the effect of one Embodiment of this invention. It is a figure for demonstrating the change of the analog output Vout which is target value. It is a figure for demonstrating the invention equivalent to the prior art of the pipeline type A / D converter of one Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Sample hold circuit 103 Memory 104 Arithmetic circuit 301 A / D converter 302 Control circuit 303 Summing node 304a, 304b, 304c, 304d, 304e, 304f, 304g, 304h Switch 305 Amplifier 306 Multi-value output circuit 307a, 307b Sample cap 401 402 determination circuit

Claims (3)

Pipeline type having a plurality of stages for inputting an analog input signal, converting it to a digital signal and outputting it, and outputting an analog output signal generated by the digital signal and the analog input signal to another stage after An A / D converter,
The stage is
A sample cap for sampling the analog input signal,
Provided between the other terminal and a reference potential between and the sample cap with one terminal of the sample cap and the input terminal of said analog input signal, the sample timing switch which determines the sampling operation timing of the sample cap A switch,
And the multi-level output circuit for adjusting the value of the sampled said analog input signal, to the analog input signal of the subsequent stage in accordance with the value of the digital signal in the sample cap,
A transfer switch that is provided between the sample cap and an output terminal of the analog output signal, and outputs a signal after adjustment by the multi-value output circuit to the other stage of the subsequent stage;
With
The multi-value output circuit is
A circuit that includes a plurality of adjustment switches and adjusts the value of the analog input signal by switching the adjustment switch according to the value of the digital signal;
By switching the adjustment switch according to the digital signal determined by the trigger generated before the sampling operation start timing by switching the sample timing switch, at a timing earlier than the transfer start by switching the transfer switch, A pipeline type A / D converter characterized in that the adjustment of the value of the analog input signal according to the value of the digital signal is completed. The stage is
Further comprising a summing node for storing the analog input signals sampled by the sample cap,
The multi-value output circuit is
2. The pipeline type A according to claim 1, wherein a change in a voltage value caused by switching of the adjustment switch is reflected in a voltage applied to the summing node at a timing earlier than a transfer start by switching of the transfer switch. / D converter. A plurality of stages for inputting an analog input signal, converting it to a digital signal and outputting it, and for outputting an analog output signal generated by the digital signal and the analog input signal to other stages subsequent thereto,
The stage is
Wherein the sample cap for sampling an analog input signal, provided between the other terminal and a reference potential between and the sample cap with one terminal of the sample cap and the input terminal of said analog input signal, said sump and sample timing changeover switch for determining the sampling operation timing of Le cap, adjusting the value of the analog input signal sampled in the sample cap, to the analog input signal of the subsequent stage in accordance with the value of the digital signal A multi-value output circuit, and a transfer switch that is provided between the sample cap and the analog output signal output terminal and outputs the signal adjusted by the multi-value output circuit to the other stage after the multi-value output circuit. A pipelined A / D converter control method comprising:
Wherein at a timing earlier than the start transfer by switching of the transfer switches, viewed contains a complete adjustment step adjusts the value of the analog input signal corresponding to the value of the multi-value output circuit said digital signal,
The adjustment step includes
The value of the analog input signal is adjusted by switching the adjustment switch according to the value of the digital signal, and the digital signal is determined by a trigger generated before the timing of starting the sampling operation by switching the sample timing switch. A control method for a pipeline type A / D converter, wherein the adjustment switch is switched according to the above .

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