JP5336348B2 - A / D converter - Google Patents

Description

  The present invention relates to an A / D converter applied to an input circuit of a digital device, and more particularly to a pipeline type A / D converter (A / D converter) operating at high speed.

Pipelined A / D converters that convert analog signals into digital signals by connecting multiple stages in multiple stages in a cascade are known to perform multiple signal processing in one clock in various image sensors and image processing circuits. It has been.
Each stage includes a switched capacitor circuit, an A / D converter, and the like, and outputs a digital signal having a predetermined bit corresponding to an analog input signal.
The pipeline type A / D converter generates a digital signal corresponding to an analog signal by synthesizing digital signals output from the respective stages.

First, the configuration of a pipeline type A / D converter will be described with reference to FIG. FIG. 9 is a block diagram showing a configuration of a conventional pipeline type A / D converter.
A pipeline type A / D converter 500 shown in FIG. 1 includes a plurality of stages S1 to Sk connected in cascade to each other, a memory 501 and an arithmetic circuit 502.

Each of the stages S1 to Sk includes an A / D converter 503, a D / A converter 504, and a switched capacitor circuit 505.
The A / D converter 503 receives the analog input signal Vin by the sample operation and the hold operation, converts the analog input signal Vin into digital signals d1 to dk, and outputs them.
The D / A converter 504 receives the digital signals d1 to dk output from the A / D converter 503, converts them into analog signals Van, and outputs them.

The switched capacitor circuit 505 generates an analog output signal Vout from an analog input signal Vin input from an input terminal Va described later by a sample operation and a hold operation and an analog signal Van output from the D / A converter 504. The analog output signal Vout is output to the next stage S (n + 1).
In the subsequent stages S (n + 1) to Sk, the analog output signal Vout output from the previous stage Sn is input as the analog input signal Vin, and the input analog input signal Vin is processed in the same manner. Is output as an analog output signal Vout.

In other words, the stages S1 to Sk receive the analog input signal Vin, convert it to the digital signals d1 to dk, and output them. The stages S1 to Sk generate the analog signals Van and analog input signals Vin converted from the digital signals d1 to dk. The analog output signal Vout is output to the stage S (n + 1) connected to the subsequent stage.
The memory 501 sequentially stores digital signals d1 to dk output from the stages S1 to Sk.

The arithmetic circuit 502 combines the bit values of the digital signals d1 to dk stored in the memory 501 and outputs a digital output signal Dout having a predetermined bit string corresponding to the analog input signal Vin.
N bit A / D converter: in order to realize the (N is a natural number), S1 is (M + 0.5) bit: an A / D converter 5 03 (M N a natural number equal to or less than), (M + 0.5) bits (M : A natural number equal to or less than N) D / A converter 504, the minimum settling accuracy required for the transfer from the stage S1 to S2 is generally expressed by (NM) bits. .

Next, a circuit configuration of a typical switched capacitor circuit 600 using an operational amplifier will be described with reference to FIG. FIG. 2 is a circuit configuration diagram showing a configuration of a conventional representative switched capacitor circuit 600 using an operational amplifier.
A switched capacitor circuit 600 shown in the figure includes an input terminal Va, an output terminal Vb, an operational amplifier AMP1, switches SW1 to SW5, and capacitors C1 and C2.

The input terminal Va is a terminal for inputting an analog input signal Vin.
The output terminal Vb is a terminal that amplifies the analog input signal Vin input from the input terminal Va and outputs it as an analog output signal Vout.
The switches SW1 to SW5 are sampling switches for sampling (sampling and holding) the analog input signal Vin, for example, by switching the circuit connection state by a control signal output from a control unit (not shown).

Capacitors C1 and C2 are connected to switches SW1 to SW5, respectively, and store and hold charges corresponding to the analog input signal Vin by switching the connection states of the switches SW1 to SW5, and the analog input input from the input terminal Va A sampling capacitor for sampling and holding a signal.
The operational amplifier AMP1 amplifies the analog input signal Vin sampled and held by the capacitors C1 and C2 based on the amplification degree based on the gain A and the feedback amount based on the loop feedback coefficient β.

When the switch SW3 is in the connected state, the capacitors C1 and C2 are connected to the non-inverting input (+) terminal and the inverting input (−) terminal of the operational amplifier AMP1.
When the switch SW3 is disconnected, the capacitors C1 and C2 are connected to the inverting input terminal of the operational amplifier AMP1, and the ground is connected to the non-inverting input terminal.
In the switched capacitor circuit 600 configured as described above, first, in the sample operation period (sample phase), the switches SW1 to SW3 are connected and the switches SW4 and SW5 are disconnected. Then, charges corresponding to the analog input signal Vin are stored in the two capacitors C1 and C2, respectively, and the analog input signal Vin is sampled.

Next, in the hold operation period (transfer phase), the switches SW1 to SW3 are disconnected and the switches SW4 and SW5 are connected. Since the electric charge stored in each of the capacitors C1 and C2 is held, an analog output signal Vout obtained by amplifying the analog input signal Vin by the operational amplifier AMP1 is output.
Signal processing is performed by alternately repeating the sample operation and the hold operation.

By the way, in order to reduce the power consumption of the pipeline type A / D converter, the ( M + 0.5) -bit A / D converter 503 ( M : a natural number equal to or less than N) and ( M + 0.5) Although it is conceivable to increase M (M: a natural number less than N ) with the D / A converter 504 of bits (M: a natural number less than N) to ease the settling request for transfer to the subsequent stage, M (M: (Natural number less than or equal to N) increases, the number of comparators constituting the A / D converter 503 increases exponentially, and the area, input capacity, and power consumption of the A / D converter 503 increase. .

Further, it is generally known that the offset margin of the comparator constituting the A / D converter 503 is reduced by increasing M (M: a natural number equal to or less than N) .
In order to reduce the power consumption of the pipeline type A / D converter, for example, there is a method of using an A / D converter (circuit configuration) shown in the following Patent Document 1 for the stage S1 in FIG.

Here, the A / D converter (circuit configuration) of Patent Document 1 will be described with reference to FIG.
As shown, the A / D converter includes an external input terminal 1, reference voltage selection units 2 to 4, a capacitor group 7, a first switch group 8, a second switch group 9, and an operational amplification unit. 5, a sub A / D converter 6 having a redundant bit, and a digital encoding circuit 15.
The analog signal is sampled in the capacitor group 7 and held as a charge. Then, MDAC calculation and A / D conversion are repeated using each component. As a result, A / D conversion is performed without losing the charge held in the capacitor group 7.
Non-Patent Document 1 below discloses a technique that enables high-accuracy transfer using a CLS (Correlated Level Shift) technique.

JP 2008-182530 A

B. Rpbert Gregoire, Un-Ku Moon "An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain" IEEE ISSCC 2008 Conference February 6, 2008 p540

  However, although it is possible to reduce power consumption and area by performing a cyclic operation with gain as in the method described in Patent Document 1, it is possible to reduce the power consumption and area, but use the same operational amplifier for the subsequent transfer and the cyclic operation. Therefore, the operational amplifier needs to secure a necessary gain at the time of transfer in a wide operating range, the structure of the operational amplifier becomes complicated, the power consumption / area becomes large, and the power consumption / area reduction effect is insignificant. Is.

  Therefore, the present invention has been devised in view of the above-described problems, and the object of the present invention is to divide the operational phase and level shift phase operational amplifiers by using CLS (Correlated Level Shift) technology. It is to provide a novel pipeline type A / D converter (converter) capable of greatly improving performance by specializing in the role of an operational amplifier.

  Further, another object of the present invention is to divide the operational phase and level shift phase operational amplifiers using the CLS technology, and further repeat the MDAC operation and A / D conversion using the operational phase operational amplifiers. To provide a new pipeline type A / D converter (converter) that can ease the settling accuracy requirement for transfer to the subsequent stage with a slight increase in time and can greatly reduce power consumption and area. .

In order to solve the above problems, the first invention
A plurality of stages are provided, and the stage inputs an analog input signal, converts it into a digital signal and outputs it, and outputs an analog output signal generated by the digital signal and the analog input signal to another stage in the subsequent stage. An A / D converter that outputs to
The stage is
A sampling circuit including a sampling capacitor for sampling the analog input signal; a first operational amplifier for amplifying and outputting the sampled analog input signal; and a timing switch for determining an operation timing of the sampling circuit; An A / D conversion circuit that converts the sampled analog input signal value into the digital signal and outputs the digital signal, and a sampling value adjustment circuit that adjusts the sampled analog input signal value according to the digital signal value A CLS circuit including a level shift capacitor for sampling and level shifting the analog input signal amplified by the first operational amplifier, and a second operational amplifier for amplifying and outputting the level shifted analog input signal And the level shift key Comprising a first and second changeover switch level shift for switching the connection state of the operational amplifier and Pashita, and a transfer switch for outputting a signal after the level shifting by the CLS circuit to another stage of the subsequent stage,
The first operational amplifier and the second operational amplifier are A / D converters having different output ranges and gains.

The second invention is
The second operational amplifier is an A / D converter characterized by having a narrower output range and a higher gain than the first operational amplifier.
The third invention is
The stage further includes a summing node to which the sampling capacitor is connected and stores the analog input signal sampled by the sampling circuit, and the A / D conversion circuit converts a voltage applied to the summing node to an A / D It is an A / D converter characterized by converting.

The fourth invention is:
A memory for storing the digital signals output from the plurality of stages; and an arithmetic circuit for combining and calculating the digital signals stored in the memory to output a digital output signal of a bit string. It is an A / D converter.
That is, according to the present invention, a switch for connecting an output of an estimate phase to a sub A / D converter having a redundant bit a plurality of times is provided in the conventional CLS, each having an estimate phase operational amplifier and a level shift phase operational amplifier. It is equipped.

According to the present invention having the above-described configuration, computation is performed using the first operational amplifier (op-amp) having a wide output range and low gain in the cyclic phase and the estimate phase, and a narrow output range in the level shift phase. In addition, a second operational amplifier (op-amp) having a high gain can be used.
This provides a pipelined A / D converter that does not reduce the offset margin of the sub A / D converter without increasing the area, eases the settling request to the subsequent stage, and can significantly reduce power consumption. it can.

1 is a block diagram showing an embodiment of an A / D converter 100 according to the present invention. It is the figure which illustrated the calculation which calculates digital output signal Dout. It is a block diagram which shows the structure of the stage S, and its sample phase. 3 is a block diagram showing a configuration of an A / D conversion circuit 302. FIG. FIG. 6 is a timing chart showing the relationship between the output timing of clocks φ1 to φ6 and each phase. It is a block diagram which shows the cyclic phase of the stage S. FIG. It is a block diagram which shows the estimate phase of the stage S. It is a block diagram which shows the level shift phase of the stage S. It is a block diagram which shows the structure of the conventional pipeline type A / D converter. It is a circuit block diagram of the typical switched capacitor circuit using the conventional operational amplifier. It is a circuit diagram which shows the structural example for reducing the power consumption of the conventional pipeline type A / D converter.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(Configuration of pipeline type A / D converter (A / D converter) 100)
FIG. 1 is a block diagram of a pipeline type A / D converter 100 of the present embodiment.
The pipeline type A / D converter 100 of this embodiment is a converter that converts an analog input signal Vin into an N-bit digital output signal Dout.

  For this reason, k stages (denoted as S in the figure) S1, S2... Sk connected in cascade to determine each bit, and the two-digit digital output signal dij (determined in each stage S1 to Sk) i is 1 to k, j is 1 to n), and the digital output signal Dout is calculated from the A / D conversion value of the analog input signal Vin based on the digital output signal dij stored in the memory 102 And an arithmetic circuit 101.

  The stages S1 to Sk are connected in multiple stages in series, and send a two-digit digital output signal dij to the memory 102 based on the input analog input signal Vin. In each of the stages S1 to Sk, the input analog input signal Vin is converted based on the D / A conversion result of the digital output signal dij, and is output to the next stage as the analog output signal Vout.

The memory 102 receives and stores a two-digit digital output signal dij from each of the k stages S1 to Sk. Therefore, the memory 102 is a semiconductor memory that can store at least (k × n) 2-bit addresses.
The arithmetic circuit 101 performs an operation based on the digital output signal dij stored in the memory 102 and outputs an N-digit digital output signal Dout. The calculation for calculating the digital output signal Dout is performed as follows.

That is, the arithmetic operation circuit 101 adds the most significant digit of dkn and the least significant digit of dk (n−1) in the binary system in the digital output signal dkn of the stage Sk. Further, based on the addition result (added value), the most significant digit of dk (n−1) and the least significant digit of dk (n−2) are similarly added in binary. The process between the stages is also the same. Based on the addition result (added value), the most significant digit of dk1 and the least significant digit of d (k-1) n are also added in the binary system.
Such processing is repeated to add up the least significant digit of the digital output signal d11 of the first stage S1 and the most significant digit of the digital output signal d12 of the first stage S1. The final result of the addition is output as a digital output signal Dout.

FIG. 2 is a diagram for illustrating the calculation for calculating the digital output signal Dout described above. In the example of FIG. 2, there are four stages S1 to S4, and each of the stages S1 to S4 has two digits of digital output signals d11, d12, d21, d22, d31, d32, d41, and d42 in FIG. Assume that the data is output to the memory 102 shown. More specifically, the values of the digital output signals d11, d12, d21, d22, d31, d32, d41, and d42 are determined as follows.
d11 = 01, d12 = 10, d21 = 00, d22 = 01, d31 = 01, d32 = 10, d41 = 00, d42 = 10
In the example of FIG. 2, as a result of adding the most significant digit and the least significant digit of the digital output output by the adjacent digital outputs, a value of “100100010” is obtained as the digital output signal Dout.

(Stage S1)
FIG. 3 is a diagram for explaining the stage S1 of the pipeline type A / D converter of the present embodiment, and shows a circuit configuration of the stage S1. Since each of the stages S1 to Sk shown in FIG. 1 has the same circuit configuration, the description of the stage S1 shown in FIG. 3 is replaced with the description of all the stages S1 to Sk. Further, the same structure as that of the prior art may be used for the circuit configuration of an arbitrary stage Sk.
This stage S1 is a circuit that receives an analog input signal Vin, outputs digital output signals d11, d1, d2,..., D1n, and outputs an analog output signal Vout to a subsequent stage S2.

  For this purpose, the stage S1 includes sample caps (cap) 306a, 306b, 306c for sampling the input analog input signal Vin, and CLS (Correlated Level Shift as disclosed in Non-Patent Document 1). ) CLS cap 306d for enabling high-precision transfer by technology, A / D conversion circuit 302 for converting analog input signal Vin into digital output signals d11, d12,..., D1n, and output of sample cap 306b as predetermined A multi-value output circuit 307_1 for distributing to a multi-value output, a multi-value output circuit 307_2 for distributing the output of the sample cap 306c to a predetermined multi-value output, and a digital output of a value based on the analog input signal Vin Operational amplifier (operational amplifier) 3 for amplifying with a predetermined gain G corresponding to the number of 03a and 303b.

The operational amplifier 303a that is the first operational amplifier has a circuit configuration that operates during the Estimate phase in the CLS technology, and the operational amplifier 303b that is the second operational amplifier is the level shift phase ( The circuit configuration operates during (Levelshift phase).
In this pipeline type A / D converter 100, when the number of digital output signals dij of the A / D conversion circuit 302 to which the gain G of the operational amplifiers 303a and 303b is input is n, it is set to 2 to the (n-1) th power. There must be. The caps of the sample caps 306a and 306b are both C, and the cap of the sample cap 306c is 2C.

  Here, it is preferable to use an operational amplifier having a wide output range and a low gain as the operational amplifier 303a. On the other hand, an operational amplifier having a narrow output range and a high gain is preferably used for one operational amplifier 303b. Since these operational amplifiers 303a and 303b can be realized with a simple structure, their power consumption and area can be greatly reduced as compared with the case of using a single amplifier having a wide output range and a high gain.

  Further, the pipeline type A / D converter 100 of the present embodiment opens and closes according to the SW (switch) 305a, 305b, 305c, 305d, 305e, 305f, and the clock φ2 that opens and closes according to the clock φ1 output from the control circuit 301. SW305g, 305n, SW305p that opens and closes according to clock φ3, SW305r that opens and closes according to clock φ4, SW305q that opens and closes according to clock φ5, and SW305o that opens and closes according to clock φ6.

The SWs 305h, 305i, and 305j included in the multilevel output circuit 307_1 are opened / closed according to the output result of the A / D conversion circuit 302, and the SW305k, 305l, and 305m included in the multilevel output circuit 307_2 are opened / closed. This is performed according to the output result of the D conversion circuit 302. The above SWs 305a to 305r are all analog switches.
In this embodiment, it is assumed that the pipeline A / D converter 100 includes the control circuit 301 and the clocks φ1, φ2, φ3, φ4, φ5, and φ6 are output by the control circuit 301.
A portion indicated by reference numeral 304 in the drawing is a summing node, and can store charges.
The multi-value output circuit 307_1 is configured to convert the digital output signal d12 into an analog signal, and the multi-value output circuit 307_2 is configured to convert the digital output signal d11 into an analog signal, and each functions as a D / A sub-converter.

(Operation)
The operation of the stage S configured as described above will be described.
The analog input signal Vin is guided to the sample cap 306a when the SWs 305b and 305c are turned on, guided to the sample cap 306b when the SWs 305b and 305d are turned on, and is guided to the sample cap 306c when the SWs 305b and 305e are turned on.
The sample caps 306a, 306b, and 306c charge the analog input signal Vin and perform sampling (also referred to as sample operation). The sampled charge is stored in the summing node 304.
At the same time, the analog input signal Vin is input to the A / D conversion circuit 302 when the SWs 305b and 305f are turned on, and further calculated by the A / D conversion circuit 302 to determine the value of the digital output signal d11.

  In the multi-value output circuit 307_2, when the value of the digital output signal d11 is 00, the SW 305k is turned on, the SW 305l and SW 305m are turned off, and the voltage value (VC + Vr) (VC: analog common ground voltage) (Vr: Vin When the value of the digital output signal d11 is 01, SW305l is turned on, SW305k and SW305m are turned off, and the voltage value (VC ) When connected to a terminal that outputs V, and when the value of the digital output signal d11 is 10, the SW 305m is turned on, the SW 305k and SW 305l are turned off, and the voltage value (VC−Vr) V is output. Connected.

Here, it is assumed that an analog input signal Vin that outputs d11 = 00 is input. The digital output signal d11 is output to the memory 102 shown in FIG. 1, is branched, and is guided to the SWs 305k to 305m via the multi-value output circuit 307_2.
In the cyclic phase (φ2 in FIG. 5 is H), the multi-value output circuit 307_1 has the SW 305i turned on, and the sample cap 306b is connected to the VC. With respect to the electric charge stored in the summing node 304, the output voltage of the operational amplifier 303a becomes (2 · Vin + Vr) V by turning on the SW 305n in the cyclic phase.

When the SW 305g is turned on in the cyclic phase, the output voltage of the operational amplifier 303a is input to the A / D conversion circuit 302, and further, the A / D conversion circuit 302 performs an operation to determine the value of the digital output signal d12.
In the cyclic phase, since the output voltage of the operational amplifier 303a is (2 · Vin + Vr) V, the input voltage Vin is multiplied by a gain of 2. Therefore, the offset margin of the A / D conversion circuit 302 is not lost at all. .

  In the transfer phase (φ4 is H in FIG. 5), in the multi-value output circuit 307_1, when the value of the digital output signal d12 is 00, SW305h is turned on, SW305i and SW305j are turned off, and the voltage value (VC + Vr) When the value of the digital output signal d12 is 01, the SW 305i is turned on, the SW 305h and the SW 305j are turned off, and connected to a terminal that outputs the voltage value (VC) V. When the value of the digital output signal d12 is 10, the SW 305j is turned on, the SW 305h and the SW 305i are turned off, and connected to a terminal that outputs a voltage value (VC−Vr) V. Here, it is assumed that an analog input signal Vin that outputs d12 = 10 is input.

  In the estimate phase (Φ3 and Φ4 are both H in FIG. 5), when the SW 305r is turned on, the charges stored in the summing node 304 are calculated by the sample caps 306a, 306b, and 306c and transferred to Vout. . At the same time, a CLS cap 306d is connected to Vout, and the calculation result in the estimate phase is stored in the CLS cap 306d.

  In the level shift phase (Φ5 in FIG. 5 is L), SW305p and 305q are turned off with the accuracy of ga · gb, which is expressed by the product of the finite gain ga of the operational amplifier 303a and the finite gain gb of the operational amplifier 303b by the CLS technique. The charge stored in the summing node 304 is calculated by the sample caps 306a, 306b, and 306c and transferred to Vout. As a result of the transfer, the analog output signal Vout is output to the stage S2 as a target value. In addition, since 1.5-bit determination is performed in the cyclic phase, the settling accuracy requirement at the time of transfer is relaxed compared to a general pipeline A / D converter, and the power consumption of the operational amplifier 303b is greatly reduced. It becomes possible.

(A / D conversion circuit 302)
FIG. 4 is a block diagram for explaining an example of the A / D conversion circuit 302 shown in FIG.
It is assumed that the input voltage of the A / D conversion circuit 302 shown in FIG. The control circuit 403 represents a 2-input 4-output control circuit. The control circuit 403 selectively outputs d11 and d12 from the two input signals by a control signal not shown.
The A / D conversion circuit 302 compares the voltage of the summing node 309 with preset reference voltages VC + (1/4) Vr, VC + (− 1/4) Vr, and compares the result with the digital output signal d11. , D12.

  When the voltage of the summing node 309 is larger than VC + (1/4) Vr, digital output signals d11 and d12 = 10 are output, and the voltage of the summing node 309 is larger than VC + (− 1/4) Vr, and VC + (1 / 4) When the voltage is smaller than Vr, the digital output signals d11 and d12 = 01 are output. When the voltage of the summing node 309 is smaller than VC + (− 1/4) Vr, the digital output signals d11 and d12 = 00 are output.

The digital output signal d11 is input to the multilevel output circuit 307_2 to control the SWs 305k to 305m. The digital output signal d12 is input to the multi-value output circuit 307_1 to control the SWs 305h to 305j.
FIG. 4 shows the configuration of the comparator when the stage S outputs two digital output signals d11 and d12. When the stage S has a structure that outputs m (m: natural number) digital output signals d11, d12,..., D1m, the control circuit 403 must be a 2-input 4-m output circuit.

  FIG. 4 shows the configuration of the comparator when the stage S includes a 1.5-bit A / D conversion circuit 302. Stage 1 is M.M. When a 5-bit (M: natural number) A / D conversion circuit 302 is provided, (2 to the (M + 1) th power −2) comparators are required, and the reference voltage of each comparator is (± 1 / (2 (+ (M + 1))), (± 3 / (2 to the (M + 1) th power)) (± 5 / (2 to the (M + 1) th power)), ..., (± (2 to the (M + 1) th power-3) / (2 to the power of (M + 1))).

(clock)
The clocks φ1, φ2, φ3, φ4, φ5, and φ6 shown in FIG. 3 will be described.
FIGS. 5A to 5F are timing charts for explaining the output timings of the clocks φ1, φ2, φ3, φ4, φ5, and φ6. The vertical axis represents the signal values High (H), Low (L ) On the horizontal axis.
5A is a timing chart of the clock φ1, and FIG. 5B is a timing chart of the clock φ2. 5C is a timing chart of the clock φ3, FIG. 5D is a timing chart of the clock φ4, FIG. 5E is a timing chart of the clock φ5, and FIG. 5F is a clock φ6. It is a timing chart.

  In the pipeline type A / D converter, a period in which the clock φ1 is H is a sample phase. Further, a period in which the clock φ2 is H is a cyclic phase. Further, a period in which the clock φ4 is H is a transfer phase. The transfer phase is divided into two phases (estimate phase and level shift phase) by the CLS technique. The period in which the clocks Φ3 and Φ4 are both H is the estimate phase, and the clock Φ5 is The period during which L is the level shift phase.

  The timings t1, t2, t3, and t4 shown in the figure all indicate the operation timing of the pipeline type A / D converter, and t1 is an arbitrary timing included in the sample phase. T2 is an arbitrary timing included in the cyclic phase. T3 is an arbitrary timing included in the estimate phase. T4 is an arbitrary timing included in the level shift phase.

  In this embodiment, the clock φ1, the clock φ2, and the clock φ4 are non-overlapping clocks that do not simultaneously become H. In the present embodiment, the clock φ1 and the clock φ6 are non-overlapping clocks that do not simultaneously become H. If the inversion of Φ5 is defined as Φ5B (not shown), the clock φ1, the clock φ3, and the clock Φ5B are non-overlapping clocks that do not simultaneously become H.

(Function)
Next, the operation (action) of the stage S of the present embodiment at the timings t1 to t4 shown in FIG. 5 will be described step by step.
<Sample phase>
FIG. 3 is a diagram showing the timing of t1 shown in FIG. 5, that is, the state of the stage S in the sample phase.
In the sample phase, the SW 305b and 305c are turned on to be guided to the sample cap 306a, the SW 305b and 305d are turned on to be guided to the sample cap 306b, and the SW 305b and 305e are turned on to be guided to the sample cap 306c. Further, since the SW 305a is turned on, the sample caps 306a, 306b, and 306c are charged and the sample operation is performed. At the same time, the analog input signal Vin is input to the A / D conversion circuit 302 when the SWs 305b and 305f are turned on.

  The A / D conversion circuit 302 performs an operation to determine the value of the digital output signal d11. Here, it is assumed that an analog input signal Vin that outputs d11 = 00 is input. The digital output signal d11 is output to the memory 102 shown in FIG. 1, is branched, and is guided to the switches 305k to 305m via the multi-value output circuit 307_2.

<Cyclic phase>
Next, FIG. 6 is a diagram showing the timing of t2 in FIG. 5, that is, the state of the stage 1 in the cyclic phase.
In the cyclic phase, the SWs 305a, 305b, 305c, 305d, 305e, and 305f are turned off. Therefore, the charge of the analog input signal Vin sampled in the sample caps 306a, 306b, and 306c is stored and determined in the summing node 304. Also, the SWs 305g, 305i, 305n, 305o, and 305p are turned on. Here, in the multi-value output circuit 307_2, when the value of the digital output signal d11 is 00, the SW 305k is turned on, the SW 305l and SW 305m are turned off, and the voltage value (VC + Vr) (VC: analog common ground voltage) ( Vr: Maximum input range of Vin, Vr> 0) When connected to a terminal that outputs V and the value of the digital output signal d11 is 01, SW305l is turned on, SW305k and SW305m are turned off, and voltage When the value (VC) V is connected to the terminal and the value of the digital output signal d11 is 10, SW305m is turned on, SW305k and SW305l are turned off, and the voltage value (VC−Vr) V is set. Connected to output terminal.

In the cyclic phase, the output node of the operational amplifier 303a is input to the A / D conversion circuit 302 when the switches 305g, 305o, and 305p are turned on.
In the cyclic phase, the charge stored in the summing node 304 is calculated by the sample caps 306 a, 306 b, and 306 c and transferred again to the A / D conversion circuit 302. As a result of the transfer, an operation is performed by the A / D conversion circuit 302, and the value of the digital output signal d12 is determined. Here, it is assumed that an analog input signal Vin that outputs d12 = 10 is input. The digital output signal d12 is output to the memory 102 shown in FIG. 1, is branched, and is guided to the switches 305h to 305j via the multi-value output circuit 307_1.

<Estimate phase>
FIG. 7 is a diagram showing the timing of t3 in FIG. 5, that is, the state of the stage S in the estimate phase.
In the estimate phase, the connection destination of the multi-value output circuit 307_1 is changed based on the result of d12. Here, since d12 = 10, SW 305j is turned on and SW 305h and 305i are turned off.
In the estimate phase, the charges stored in the summing node 304 are calculated by the sample caps 306a, 306b, and 306c, and transferred to Vout and the level shift cap 306d. As a result of the transfer, the analog output signal is stored as a target value in Vout and the level shift cap 306d.

<Levelshift phase>
FIG. 8 is a diagram showing the timing of t4 in FIG. 5, that is, the state of the stage S in the level shift phase.
In the level shift phase, Vout and the voltage stored in the level shift cap 306d as target values in the estimate phase are set to the next stage as the final target value with the voltage of Vout more accurately by the finite gain of the operational amplifier 303b by the CLS technique. To S.

  As described above, in the AD converter 100 of the present invention, the gain accuracy required for the operational amplifier can be improved by separating the amplifier (op-amp) used for the estimate phase and the amplifier (op-amp) used for the level shift phase in the CLS operation. The output range can be separated. As a result, the power consumption and area can be greatly reduced as compared with the case where the same amplifier having both gain accuracy and output range is used.

In addition, by making the amplifier (op-amp) used in the cyclic phase the same as the amplifier (op-amp) used in the estimate phase, the cyclic phase A / D conversion accuracy has redundancy, so low gain An amplifier (op-amp) can perform cyclic phase A / D conversion, and the area can be reduced.
In addition, by using CLS technology for a general cyclic A / D converter, the transfer accuracy in the transfer phase is the gain of an amplifier (op-amp) used in the estimate phase, and the amplifier used in the level shift phase ( The gain error during transfer is guaranteed because it depends on the product of the gain of the operational amplifier).

In addition, since A / D conversion is performed in the cyclic phase, the settling request to the target value when transferring to the subsequent stage is alleviated, and the power consumption of the amplifier (op-amp) used in the level shift phase can be greatly reduced. it can.
In the present embodiment, the configuration of the stage 1 when the stage S outputs two digital output signals d11 and d12 has been described. However, the stage S has m (three or more, the same applies hereinafter) digital output signals. In the case of having a structure for outputting d11, d12,..., d1m, it is necessary to further divide the cyclic phase Φ2 into m and introduce Φ2_1, Φ2_2, Φ2_m.

In addition, m circuit configurations of the same type as the circuit configuration 308_1 including the SWs 305d and 305f, the sample cap 306b, and the multi-value output circuit 307_1 are connected in parallel between the node 309 and the summing node 304 shown in the drawing, and the circuit configuration The capacity of the sample cap included in 308_x (x: a natural number less than or equal to m) must be (2 to the (x-1) th power) · C.
The digital output signal d11 is connected to the multi-value output circuit 307_m, the digital output signal d12 is connected to the multi-value output circuit 307_ (m−1),..., And the digital output signal d1m is connected to the multi-value output circuit 307_1. There must be.

In this embodiment, the configuration in which the stage S outputs the 2-bit digital output signals d11 and d12 has been described. However, the structure in which the stage S outputs the (M + 1) -bit digital output signals d11 and d12 is described. If you have M.M. It is necessary to provide a 5-bit A / D conversion circuit 302.
In addition, 2 · M pieces of the same circuit configuration as the circuit configuration 308_1 including the SWs 305d and 305f, the sample cap 306b, and the multi-value output circuit 307_1 are connected in parallel between the node 309 and the summing node 304 shown in the drawing, The capacity of the sample cap included in the circuit configuration 308_y (y: a natural number of 2 · M or less) must be (2 to the power of (y−1)) · C.

The digital output signal d11 is connected to the multi-value output circuits 307_ (2 · M), 307_ (2 · M−1)... 307_ (2 · M− (M−1)), and the digital output signal d12 is Must be connected to the value output circuits 307_M, 307_ (M-1)... 307_1.
This is the description of the operation of the stage S along the time series. Note that t5 shown in FIG. 5 is the rise time of φ4, and the transfer phase after t5 becomes a sample phase in the subsequent stage S2 shown in FIG. The even-numbered stages S2, S4,... Have the same circuit configuration as in FIG. 3, and the timing chart of the clock for driving the analog switch has a rise time of φ1, t5, and φ2, φ3, φ4, φ5, and φ6. The relative relationships with respect to φ1 are all driven by the same clock as in FIG. 5 and operate in the same manner as in the present embodiment.

The odd-numbered stages S3, S5,... Have the same circuit configuration as that in FIG. 3, and all timing charts of clocks for driving the analog switches are driven by the same clocks as in FIG. Works as well.
The circuit configuration of the embodiment of the present invention can also be applied to a fully differential circuit configuration.

The stages constituting the invention described in the means for solving the problems correspond to the stages S1 to Sk of the present embodiment, and the sampling circuits including the sampling capacitors and the sampling capacitors also correspond to the Caps 306a to 306c. The sampling value adjustment circuit corresponds to the multi-value output circuits 307_1 and 307_2.
Similarly, the first and second operational amplifiers correspond to the operational amplifiers 303a and 303b of the present embodiment, and the timing changeover switch corresponds to the analog switches SW305a to 305r.

The A / D conversion circuit corresponds to the A / D conversion circuit 302 of the present embodiment, the sampling value adjustment circuit corresponds to the multi-value output circuits 307_1 and 307_2, the level shift capacitor corresponds to the CLS cap 306d, The CLS circuit corresponds to a circuit including the CLS cap 306d.
Further, the level shift selector switch corresponds to the analog switches SW305p and 305q of this embodiment, and the transfer switch corresponds to the analog switch SW305r.

100 ... A / D converter (pipeline type AD converter)
DESCRIPTION OF SYMBOLS 101 ... Operation circuit 102 ... Memory 301 ... Control circuit 302 ... A / D conversion circuit 303a, 303b ... Operational amplifier (1st and 2nd operational amplifier)
304 ... Summing nodes 305a to 305o ... Analog switches 305p, 305q ... Analog switches (timing selector switches)
305r ... Analog switch (transfer switch)
306a to 306c: Capacitor (sampling circuit)
306d ... CLS cap (capacity for level shift, CLS circuit)
307_1, 307_2 ... multi-value output circuit (sampling value adjustment circuit)
308_1, 308_2 ... Circuit configuration including multi-value output circuit S (S1 to Sk) ... Stage φ1 to φ6 ... Clock

Claims (4)

A plurality of stages are provided, and the stage inputs an analog input signal, converts it to a digital signal and outputs it, and outputs an analog output signal generated by the digital signal and the analog input signal to another stage in the subsequent stage. An A / D converter for outputting,
The stage is
A sampling circuit including a sampling capacitor for sampling the analog input signal;
A first operational amplifier for amplifying and outputting the sampled analog input signal;
A timing selector switch for determining the operation timing of the sampling circuit;
An A / D conversion circuit that converts the sampled analog input signal value into the digital signal and outputs the digital signal;
A sampling value adjusting circuit for adjusting the value of the sampled analog input signal according to the value of the digital signal;
A CLS circuit including a level shift capacitor for sampling and level shifting the analog input signal amplified by the first operational amplifier;
A second operational amplifier for amplifying and outputting the level-shifted analog input signal;
A level shift selector switch for switching a connection state between the level shift capacitor and the first and second operational amplifiers;
A transfer switch for outputting a signal after level shift by the CLS circuit to the other stage of the subsequent stage,
The A / D converter characterized in that the first operational amplifier and the second operational amplifier have different output ranges and gains.   The A / D converter according to claim 1, wherein the second operational amplifier has a narrower output range and a higher gain than the first operational amplifier. The stage further includes a summing node connected to the sampling capacitor and storing the analog input signal sampled by the sampling circuit;
The A / D converter according to claim 1, wherein the A / D converter circuit performs A / D conversion on a voltage applied to the summing node. A memory for storing the digital signals output from the plurality of stages;
4. An A / D conversion according to claim 1, further comprising: an arithmetic circuit that combines the digital signals stored in the memory to output a digital output signal of a bit string. 5. vessel.

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