JP2007295378A - Analog-digital conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A-D conversion circuit in a pipeline system capable of suppressing the deterioration of monotonicity caused by errors of an amplification gain at each conversion step. <P>SOLUTION: An input analog signal A1 from a previous step and a delayed analog signal A2 generated by delaying the input analog signal A1 at a sample holder 11 are converted into digital signals (DU, DL) at an A-D converter 12. The digital signals (DU, DL) are converted into analog signals (AU, AL) at a D-A converter 13. Further, a difference between the analog signals (AU, AL) and the delayed analog signal A2 is amplified at residual difference amplifiers 14, 15, and the amplification result (residual signal) is supplied to a conversion block at a next step. In the A-D converter 12, a high-order digital code DU is determined according to the input analog signal A1, and a low-order digital code DL is determined according to the high-order digital code DU and the delayed analog signal A2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an analog / digital conversion circuit that performs one conversion operation in a plurality of steps, and more particularly to a pipelined analog / digital conversion circuit.

  Pipeline analog / digital conversion (hereinafter referred to as A / D conversion) circuits with high resolution and high resolution are widely used in analog front-end units of various digital devices such as video devices and communication devices.

FIG. 5 is a diagram illustrating an example of a configuration of a general pipeline A / D conversion circuit.
As shown in FIG. 5, for example, the pipeline A / D conversion circuit includes a sample hold unit SH that samples an input analog signal Ain, and a plurality of stages that perform A / D conversion of the sampling result stepwise from the upper bit side. , And a digital correction circuit 103 that generates a digital signal Dout corresponding to the analog signal Ain by adding the A / D conversion results of the respective conversion blocks. Have.

The conversion block 100-n (n = 1, 2,...) Includes an AD / DA conversion unit 102-n and a residual amplification unit 101-n.
The AD / DA conversion unit 102-n performs A / D conversion on the analog signal input from the previous stage with a relatively low resolution, and again performs digital / analog conversion (hereinafter referred to as D / A conversion) of the conversion result. Return to analog signal.
The residual amplifier 101-n amplifies the difference between the analog signal reproduced by the AD / DA converter 102-n and the original analog signal. When the resolution of the AD / DA conversion unit 102-n is “a”, the residual amplification unit 101-n has a gain of “2 ^(a−1) ”, for example.

FIG. 6 is a diagram for explaining the operation timing of the pipeline A / D conversion circuit shown in FIG.
The pipeline A / D conversion circuit is basically configured as a switched capacitor circuit, and each component operates in synchronization with a clock signal. In the example of FIG. 6, each half cycle (high level or low level period) of the clock signal is sequentially represented as phases φ0, φ1, φ2,.
In each phase, the following operations are performed.

First, in phase φ0, the sample-and-hold unit SH in the input stage samples the analog signal Ain.
In the phase φ1, the sample hold unit SH amplifies the analog signal Ain sampled in the phase φ0 with a gain of, for example, 1 and outputs it. The residual amplifier 101-1 samples the output signal of the sample and hold unit SH. The AD / DA conversion unit 102-1 A / D converts the output signal of the sample hold unit SH.
In the phase φ2, the AD / DA conversion unit 102-1 performs D / A conversion on the output signal of the sample hold unit SH that has been A / D converted in the phase φ1, and reproduces an analog signal. The residual amplifying unit 101-1 calculates, for example, 2 ^(a−1) times the difference between the analog signal reproduced by the AD / DA converter 102-1 and the output signal of the sample hold unit SH sampled in phase φ ¹ ( a: the resolution of the AD / DA converter 102-1) is amplified and output. In the next conversion block 100-2, the residual amplification unit 101-2 samples the output signal of the residual amplification unit 101-1, and the AD / DA conversion unit 102-2 outputs the output of the residual amplification unit 101-1. A / D-convert the signal.
Thereafter, the same operation is repeated in the phases φ3, φ4,..., Whereby the analog signal Ain sampled in the phase φ1 is A / D converted stepwise from the higher bit side. The digital correction circuit 103 sequentially acquires and adds the A / D conversion results of the conversion blocks 100-1, 100-2, 100-3,... In the phases φ1, φ2, φ3,. A digital signal Dout is generated.

  The most critical operation timing in the pipeline A / D conversion circuit shown in FIG. 5 is the conversion operation of the AD / DA conversion unit 102-n. As shown in FIG. 6, only half the period of the clock signal is allocated until the AD / DA converter 102-n determines the digital signal of the conversion result and reproduces the analog signal corresponding to the digital data. Absent. In the pipeline A / D conversion circuit shown in FIG. 5, since the conversion time of the AD / DA conversion unit 102-n becomes a bottleneck and the frequency of the clock signal cannot be increased so much, the conversion rate is increased. There is a disadvantage that you can not.

  An analog double sample pipeline A / D conversion circuit capable of allocating one cycle time of a clock signal to an A / D conversion operation in each conversion block is known as a solution to the above problems. (For example, refer to Patent Document 1).

FIG. 7 is a diagram illustrating a configuration example of an analog double sampling pipeline A / D conversion circuit.
The A / D conversion circuit shown in FIG. 7 converts the conversion blocks 100-1, 100-2, 100-3,... In the A / D conversion circuit shown in FIG. Replaced by 3, ...
In addition to the same configuration as the conversion block 100-n, the conversion block 100A-n includes a sample hold unit 103-n for delaying the analog signal input to the residual amplification unit 101-n.

  FIG. 8 is a diagram for explaining the operation timing of the pipeline A / D conversion circuit shown in FIG.

First, in phase φ0, the sample-and-hold unit SH in the input stage samples the analog signal Ain.
In the phase φ1, the sample-and-hold unit SH in the input stage amplifies the analog signal Ain sampled in the phase φ0 with a gain of, for example, 1 and outputs it. The sample hold unit 103-1 samples the output signal of the sample hold unit SH in the input stage. The AD / DA conversion unit 102-1 starts A / D conversion of the output signal of the sample hold unit SH.
In phase φ2, AD / DA converter 102-1 determines the A / D conversion result started in phase φ1. The sample hold unit 103-1 amplifies the analog signal sampled in the phase φ 1 with a gain of, for example, 1 and outputs it. Residual amplifier 101-1 samples the output signal of sample and hold unit 103-1.
In the phase φ3, the AD / DA conversion unit 102-1 converts the digital signal of the A / D conversion result determined in the phase φ2 into an analog signal. The residual amplification unit 101-1 calculates the difference between the output signal of the sample hold unit 103-1 sampled in the phase φ 2 and the analog signal reproduced by the AD / DA conversion unit 102-1, for example, 2 ^(a-1). Amplified by a gain of twice (a: resolution of AD / DA converter 102-1) and output. In the next conversion block 100-2, the sample hold unit 103-2 samples the output signal of the residual amplifier 101-1, and the AD / DA converter 102-2 outputs the output signal of the residual amplifier 101-1. Starts A / D conversion.
Thereafter, the same operation is repeated in the phases φ4, φ5,..., Whereby the analog signal Ain sampled in the phase φ1 is A / D converted stepwise from the upper bit side.

According to the pipelined A / D conversion circuit of the analog double sampling system shown in FIG. 7, the A / D conversion operation of the AD / DA conversion unit 102-1 is performed by providing the sample hold unit 103-n. It is possible to secure a period of time, and it is possible to relax the severe restrictions on the operation timing as in the A / D conversion circuit shown in FIG. This makes it possible to increase the frequency of the clock signal and increase the conversion rate. Further, when compared at the same conversion rate, the operation speed required for each element circuit is alleviated, so that it is possible to reduce the overall current consumption and reduce the power consumption.
Japanese Patent Laid-Open No. 05-14199

  However, if a sample hold unit 103-n for delaying an analog signal is provided as shown in FIG. 7, there is a disadvantage that the monotonicity of A / D conversion is greatly deteriorated by a slight gain error of the sample hold unit 103-n. There is.

FIG. 9 is a diagram for explaining the relationship between the gain error of the sample hold unit 103-n and the deterioration of monotonicity.
9A and 9B show an analog signal (input analog signal) input to the conversion block, an analog signal (reproduced analog signal) reproduced by the AD / DA converter 102-n, and a sample. It is a figure which shows the relationship with the analog signal (delayed analog signal) delayed by the holding | maintenance part 103-n. The horizontal axis indicates the level of the input analog signal, and the vertical axis indicates the level of each analog signal.
9A and 9B are diagrams illustrating the relationship between the input analog signal and the output signal (residual signal) of the residual amplifier 101-n. The horizontal axis indicates the level of the input analog signal, and the vertical axis indicates the level of each analog signal.

  When the gain of the sample hold unit 103-n is “1”, the delayed analog signal has almost the same level as the input analog signal, as shown in the upper part of FIG. On the other hand, the relationship between the input analog signal and the reproduction analog signal corresponds to the input / output characteristics of the AD / DA converter 102-n. When the input analog signal increases monotonously, the reproduction analog signal follows this. It increases in a staircase pattern. Since the AD / DA converter 102-n generates a stepped reproduction analog signal by quantizing the input analog signal in a certain step, the result of subtracting the reproduction analog signal from the input analog signal is in a certain level range. include. Therefore, the residual signal, which is the result of subtracting the reproduced analog signal from the delayed analog signal and amplifying it, is also included in a certain level range as shown in the lower part of FIG. This level range corresponds to the full scale range of the input analog signal in the next conversion block.

  However, when the gain of the sample hold unit 103-n becomes smaller than “1”, a difference occurs between the levels of the delayed analog signal and the input analog signal, as shown in the upper part of FIG. 9B. For this reason, as shown in the lower part of FIG. 9B, the residual signal deviates from the full scale range of the next stage, and the monotonicity of the A / D conversion deteriorates.

  The present invention has been made in view of such circumstances, and an object of the present invention is to execute one conversion operation in a plurality of steps, relax the restriction on the timing of A / D conversion in each step, and amplify in each step. An object of the present invention is to provide an A / D conversion circuit capable of suppressing deterioration of monotonicity caused by a gain error.

  The digital / analog conversion circuit according to the present invention includes a plurality of cascade-connected conversion blocks that perform analog / digital conversion step by step from coarse digital values to fine digital values. The conversion block includes a first sample hold unit that delays an input analog signal, an analog / digital conversion unit that performs analog / digital conversion, and a digital signal that converts a digital signal output from the analog / digital conversion unit into an analog signal. / Analog conversion unit, and a second sample hold that amplifies the difference between the delayed analog signal output from the first sample hold unit and the analog signal output from the digital / analog conversion unit and supplies the amplified signal to the next conversion block Part. The analog / digital conversion unit determines a higher-order digital code in accordance with the input analog signal, and determines a lower-order digital code in accordance with the higher-order digital code and the delayed analog signal.

  According to the digital / analog conversion circuit of the present invention, analog signals input to a plurality of cascade-connected conversion blocks are converted into digital signals stepwise from coarse digital values to fine digital values. In each conversion block, the input analog signal from the previous stage is output as a delayed analog signal from the first sample hold unit, and the input analog signal and the delayed analog signal are converted into a digital signal in the analog / digital conversion unit, The signal is converted into an analog signal in the digital / analog conversion unit, the difference between the analog signal and the delayed analog signal is amplified in the second sample hold unit, and the amplification result is supplied to the next conversion block. In the analog / digital conversion unit, the upper digit digital code is determined according to the input analog signal, and the lower digit digital code is determined according to the higher digit digital code and the delayed analog signal. .

  Preferably, the digital / analog conversion unit generates an upper analog signal corresponding to the digital code of the upper digit and a lower analog signal corresponding to the digital code of the lower digit, and the second sample hold unit An upper sample hold unit that amplifies the difference between the delayed analog signal and the upper analog signal, and a lower sample hold unit that amplifies the difference between the signal amplified in the upper sample hold unit and the lower analog signal.

  According to the present invention, in each of the cascade-connected conversion blocks that perform A / D conversion in stages, a high-order digital code is determined according to the analog signal input from the previous stage, and the delay of the input analog signal is determined. Since the lower-order digital code is determined according to the signal, it is possible to relax the restriction on the A / D conversion timing in each conversion block, and to suppress the monotonic deterioration due to the amplification gain error in the conversion block.

FIG. 1 is a diagram illustrating an example of a configuration of an A / D conversion circuit according to an embodiment of the present invention.
The A / D conversion circuit shown in FIG. 1 includes a sample-and-hold unit SH1 in the input stage, conversion blocks 1-1, 1-2, 1-3,. And a digital correction circuit 2 that generates a digital signal Dout based on the D conversion result.

  The sample hold unit SH1 samples the input analog signal Ain in synchronization with a clock signal (not shown) and outputs the sampled signal to the conversion block 1-1.

  The conversion block 1-n (n represents an integer equal to or greater than 1) A / D-converts the analog signal input from the previous stage and outputs a digital signal as a result of the conversion to the digital correction circuit 2. The digital signal is further D / A converted, a residual signal corresponding to the difference between the analog signal of the conversion result and the analog signal from the previous stage is generated, and this is output to the next stage as an analog signal to be A / D converted To do. The A / D conversion operation, the D / A conversion operation, and the residual signal generation operation are performed in synchronization with the clock signal.

  The digital correction circuit 2 adds the digital signals of the respective conversion blocks, for example, based on the digital signals output from the conversion blocks 1-1, 1-2, 1-3,. A digital signal Dout as a result of the / D conversion is generated.

In the example of FIG. 1, the conversion block 1-n includes a sample hold unit 11, an A / D conversion unit 12, a D / A conversion unit 13, a residual amplification unit 14, and a residual amplification unit 15. .
The sample hold unit 11 is an embodiment of the first sample hold unit of the present invention.
The A / D converter 12 is an embodiment of the analog / digital converter of the present invention.
The D / A converter 13 is an embodiment of the digital / analog converter of the present invention.
The circuit including the residual amplifiers 14 and 15 is an embodiment of the second sample and hold unit of the present invention.
Residual amplifier 14 is an embodiment of the upper sample-and-hold unit of the present invention.
The residual amplifier 15 is an embodiment of the lower sample hold unit of the present invention.

  The sample hold unit 11 delays the analog signal A1 (input analog signal A1) input from the previous stage. That is, the input analog signal A1 is sampled in synchronization with a clock signal (not shown).

For example, as shown in FIG. 1, the sample and hold unit 11 includes a switch SW1 that is turned on / off in synchronization with a clock signal, a capacitor C1 to which an input analog signal A1 is applied via the switch SW1, and a voltage of the capacitor C1. A buffer amplifier U1 for outputting a signal.
In the sampling period, the switch SW1 is turned on, and the voltage of the input analog signal A1 is sampled by the capacitor C1. In the hold period, the switch SW1 is turned off, the sampled voltage of the input analog signal A1 is held in the capacitor C1, and a signal corresponding to the voltage value is output from the buffer amplifier U1.
The buffer amplifier U1 has a gain of, for example, 1 and outputs a signal having substantially the same voltage as the capacitor C1.

  The A / D converter 12 performs A / D conversion of the input analog signal A1 and the delayed analog signal A2. In the digital signal output as the conversion result, the upper digit digital code DU is determined according to the input analog signal A1, and the lower digit digital code DL is determined according to the digital code DU and the delayed analog signal A2. For example, as shown in FIG. 2 described later, the A / D conversion unit 12 performs A / D conversion by dividing into upper digits and lower digits.

  The D / A converter 13 converts the digital signal (DU, DL) output from the A / D converter 12 into an analog signal (AU, AL). That is, the upper digit digital code DU is converted into an upper analog signal AU, and the lower digit digital code DL is converted into a lower analog signal AL.

  The residual amplifiers 14 and 15 amplify the difference between the delayed analog signal A2 output from the sample hold unit 11 and the analog signal (AU, AL) output from the D / A converter 13, and use it as a residual signal. This is supplied to the next conversion block. In the example of FIG. 1, the residual amplifier 14 amplifies the difference between the delayed analog signal A2 and the higher-order analog signal AU. The residual amplifier 15 amplifies the difference between the signal amplified in the residual amplifier 14 and the lower analog signal AL.

The gains of the residual amplifiers 14 and 15 are set according to the number of bits of the digital codes DU and DL output from the A / D converter 12, for example. That is, when the number of bits of the upper digit digital code DU is “NU”, the gain of the residual amplifier 14 is set to “2 ^NU ”. When the number of bits of the lower-order digital code DL is “NL”, the gain of the residual amplifier 15 is set to “2 ^NL ”.

For example, as shown in FIG. 1, the residual amplifier 14 includes switches SW2, SW3, SW4, capacitors C2, C3, and an inverting amplifier U2.
The switch SW2 is connected between the output terminal of the sample hold unit 11 and one terminal of the capacitor C2. The switch SW3 is connected between the output terminal of the higher-order analog signal AU of the D / A converter 13 and one terminal of the capacitor C2. One terminal of the capacitor C2 is connected to the switches SW2 and SW3, and the other terminal is connected to the input of the inverting amplifier U2. The switch SW4 and the capacitor C3 are connected in parallel between the input and output of the inverting amplifier U2. The inverting amplifier U2 amplifies the difference between the input voltage and the reference voltage.
The residual amplification operation is performed by the following procedure, for example.
First, in the sample period, the switches SW2 and SW4 are set to ON. When the switch SW4 is turned on, the input and output of the inverting amplifier U2 have the same potential. When the gain of the inverting amplifier U2 is sufficiently large, negative feedback control is performed so that the input voltage of the inverting amplifier U2 is substantially equal to the reference voltage, so that the input and output of the inverting amplifier U2 are substantially equal to the reference voltage. On the other hand, when the switch SW2 is turned on, the delayed analog signal A2 is sampled in the capacitor C2.
Next, in the amplification period, the switches SW2 and SW4 are turned off and the switch SW3 is turned on. At this time, the higher-order analog signal AU is input to the capacitor C2, but negative feedback control is performed so that the input voltage of the inverting amplifier U2 continues to be equal to the reference voltage. Therefore, the capacitor C2 is charged or discharged with a charge corresponding to the voltage difference between the higher-order analog signal AU and the delayed analog signal A2, and the same amount of charge is stored in the capacitor C3. Therefore, if the capacitance of the capacitor C2 is set to k times the capacitance of the capacitor C3, a voltage k times as large as the difference voltage between the higher-order analog signal AU and the delayed analog signal A2 is generated in the capacitor C3.
The above is an example of the configuration of the residual amplifying unit 14, but the residual amplifying unit 15 can also perform residual amplification with the same switched-capacitor circuit configuration as described above.

  Next, configuration examples of the A / D conversion unit 12 and the D / A conversion unit 13 will be described with reference to FIG. In the example of FIG. 2, the A / D conversion unit 12 and the D / A conversion unit 13 perform conversion of 4 bits (upper digit 2 bits, lower digit 2 bits), respectively.

For example, as illustrated in FIG. 2, the A / D conversion unit 12 includes a reference voltage generation unit 121, an upper digit comparison unit 122, an upper digit generation unit 123, a selection unit 124, a lower digit comparison unit 125, A digit generation unit 126 and an upper digit correction unit 127 are provided.
The reference voltage generator 121 is an embodiment of the reference voltage generator of the present invention.
The upper digit comparison unit 122 is an embodiment of the upper digit comparison unit of the present invention.
The upper digit generation unit 123 is an embodiment of the upper digit generation unit of the present invention.
The lower digit comparison unit 125 is an embodiment of the lower digit comparison unit of the present invention.
The lower digit generation unit 126 is an embodiment of the lower digit generation unit of the present invention.
The upper digit correction unit 127 is an embodiment of the upper digit correction unit of the present invention.

The reference voltage generation unit 121 generates reference voltages VR0 to VR16 necessary for performing 4-bit A / D conversion.
For example, the reference voltage generation unit 121 includes resistors R1 to R16 connected in series between the reference voltage VRB and VRT (VRT> VRB). The resistors R1 to R16 have substantially equal resistance values, and reference voltages VR1 to VR15 that divide the voltage ranges “VRB” to “VRT” into 16 equal parts are generated at connection points of the resistors. That is, the reference voltage VRm is generated at the connection point between the resistor Rm (1 ≦ m ≦ 15) and the resistor R (m + 1). In the example of FIG. 2, the reference voltage VR0 is equal to the reference voltage VRB, and the reference voltage VR16 is equal to the reference voltage VRT.

  The upper digit comparison unit 122 receives reference voltages VR4, VR8, and VR12 for determining the upper digit digital code from the reference voltage generation unit 121, and compares each of the reference voltages with the input analog signal A1. In the example of FIG. 2, the upper digit comparison unit 122 includes three comparators CP11, CP12, and CP13 that compare the reference voltages VR4, VR8, and VR12 with the input analog signal A1.

  The upper digit generation unit 123 generates an upper digit digital code DU according to the 3-bit signal output as the comparison result of the upper digit comparison unit 122. That is, a 3-bit signal input from the upper digit comparison unit 122 is encoded into a 2-bit binary code, and this is output as a digital code DU.

The selection unit 124 selects three reference voltages for determining the lower digit digital code DL corresponding to the upper digit digital code DU from the reference voltages VR0 to VR16 generated by the reference voltage generation unit 121.
For example, when the digital code DU indicating that the input analog signal A1 is included in the voltage range “VR4” to “VR8” is generated, the selection unit 124 divides this voltage range into four equal reference voltages VR5 and VR6. , VR7.

The selection unit 124 adds a reference voltage for determining a digital code included in a range expanded from the range of the lower digit digital code DL corresponding to the upper digit digital code DU to the three reference voltages described above. Select further.
For example, as shown in FIG. 3 to be described later, when an upper digit digital code DU (= “01”) indicating that the input analog signal A1 is included in the voltage range “VR4” to “VR8” is generated, the selection unit 124 denotes two reference voltages “VR8” used to determine the lower-order digital code DL included in the range (A2) expanded by “+2” from the range (A1) corresponding to the digital code DU, Two references used to select “VR9” and to determine the lower digit digital code DL included in the range (A3) extended by “−2” from the range (A1) corresponding to the digital code DU The voltages “VR3” and “VR4” are selected.

  The lower digit comparison unit 125 compares each reference voltage selected by the selection unit 124 with the delayed analog signal A2. 2 includes seven comparators CP21, CP22,..., CP27 that compare the seven reference voltages selected by the selection unit 124 with the delayed analog signal A2.

  The lower digit generation unit 126 generates a lower digit digital code DL according to the 7-bit signal output as the comparison result of the lower digit comparison unit 125, and whether the digital code DL is included in the above-described extended range. A correction signal indicating whether or not is generated.

  The high-order digit correction unit 127 corrects the high-order digit digital code DU generated by the high-order digit generation unit 123 in accordance with the correction signal output from the low-order digit generation unit 126.

FIG. 3 is a diagram for explaining a method of correcting the upper digit digital code DU.
In the A / D converter 12 shown in FIG. 2, an upper digit comparison unit 122 for determining the upper digit digital code DU and a lower digit comparison unit 125 for determining the lower digit digital code DU are independent. Therefore, a large error is likely to occur near the boundary where the value of the digital code DU of the upper digit changes. For example, when the correct value is “1000” (the black area in FIG. 3), if the high-order digital code DU is determined to be “01” due to the influence of a minute error, no correction is made to this. Otherwise, “0100” is output as the conversion result (the hatched area in FIG. 3), and an error of 50% occurs.
In such a case, the comparison result of the lower digit comparison unit 125 is not included in the normal range A1 as shown in FIG. 3, but is included in the positive extended range A2. Therefore, the lower digit generation unit 126 outputs “00” as the lower digit digital code DL and outputs a correction signal indicating that the digital code DL belongs to the extended range A2 to the upper digit correction unit 127. Upon receiving this correction signal, the upper digit correcting unit 127 adds “01” to the upper digit digital code DU and corrects the value from “01” to “10”. That is, the upper digit digital code DU is corrected in accordance with the comparison result of the extended range in the lower digit comparison unit 125.
By performing the correction process as described above, it is possible to prevent a large error from occurring in the vicinity of the boundary where the value of the high-order digital code DU changes and maintain continuity.

The D / A conversion unit 13 includes, for example, a lower-level D / A conversion unit 131 and an upper-level D / A conversion unit 132 as shown in FIG.
The low-order D / A converter 131 D / A converts the digital code DL (low-order 2 bits: D0, D1) generated by the low-order digit generator 126, and outputs it as a low-order analog signal AL.
The upper D / A converter 132 D / A converts the digital code DU (upper 2 bits: D2, D3) corrected by the upper digit corrector 127, and outputs it as an upper analog signal AU.

  Here, the operation of the A / D conversion circuit according to this embodiment having the above-described configuration will be described with reference to FIG.

  FIG. 4 is a diagram for explaining a series of operations (phases φ0 to φ4) when the analog signal Ain sampled in the sample hold unit SH1 is A / D converted in the conversion block 1-1. Each phase corresponds to a half cycle (high level or low level period) of the clock signal, for example, as shown in FIG.

[Phase φ0]
The sample hold unit SH1 samples the analog signal Ain.

[Phase φ1]
The sample hold unit SH1 amplifies the analog signal Ain sampled in the phase φ0 with a gain of 1 and outputs the amplified signal. The sample hold unit 11 and the upper digit comparison unit 122 of the A / D conversion unit 12 sample the input analog signal A1.

[Phase φ2]
The sample hold unit 11 amplifies the voltage of the input analog signal A1 sampled in the phase φ1 with a gain of 1 and outputs this as a delayed analog signal A2. As a result, the delayed analog signal A2 becomes a signal delayed by a half cycle of the clock signal with respect to the input analog signal A1.
The A / D converter 12 performs A / D conversion of the input analog signal A1 sampled in the phase φ1. That is, the high-order digit comparison unit 122 compares the input analog signal A1 sampled in the phase φ1 with the reference signals (VR4, VR8, VR12), and the high-order digit generation unit 123 sets the high-order digit corresponding to the comparison result. A digital code DU is generated.
The lower digit comparison unit 125 and the residual amplification unit 14 of the A / D conversion unit 12 sample the delayed analog signal A2.

[Phase φ3]
The A / D converter 12 performs A / D conversion of the delayed analog signal A2 in the range (and its extended range) corresponding to the higher-order digital code DU acquired as the A / D conversion result of the input analog signal A1. Do. That is, the selection unit 124 selects a reference voltage used to determine a range corresponding to the upper digit digital code DU and an extension range digital code DL adjacent thereto, and inputs the reference voltage to the lower digit comparison unit 125. The lower digit comparison unit 125 compares each reference voltage selected by the selection unit 124 with the delayed analog signal A2. The lower digit generation unit 126 generates a lower digit digital code DL and an upper digit correction signal according to the comparison result. When the lower digit generation unit 126 generates the correction signal, the correction content of the upper digit correction unit 127 is determined, and the upper digit digital code DU is determined.
The D / A converter 13 converts the upper digit digital code DU into an upper analog signal AU.
The residual amplifier 14 amplifies and outputs the difference between the delayed analog signal A2 sampled in the phase φ2 and the higher-order analog signal AU output from the D / A converter 13.
The residual amplifier 15 samples the output signal of the residual amplifier 14.

[Phase φ4]
The D / A conversion unit 13 converts the lower-order digital code DL acquired as an A / D conversion result of the delayed analog signal A2 into a lower analog signal AL.
Residual amplifier 15 amplifies and outputs the difference between the output signal of residual amplifier 14 sampled in phase φ3 and lower analog signal AL output from D / A converter 13.

  The conversion block 1-1 performs A / D conversion on the sampling result of the sample hold unit SH1 by sequentially executing the operations of the phases φ1 to φ4 described above. Each subsequent conversion block (1-2, 1-3, 1-4,...) Also performs A / D conversion of the residual signal supplied from the previous conversion block by the same operation as described above. The digital correction circuit 2 generates the digital signal Dout by adding these digital values, for example, based on the conversion results of the conversion blocks 1-1, 1-2, 1-3,.

As described above, according to the A / D conversion circuit according to the present embodiment, in the cascade-connected conversion blocks 1-1, 1-2, 1-3,..., From coarse digital values to fine digital values. A / D conversion is performed step by step. In each conversion block 1-n, an analog signal A1 from the previous stage and a delayed analog signal A2 obtained by delaying the input analog signal A1 in the sample hold unit 11 (first sample hold unit) are converted into digital signals ( DU, DL), the digital signal (DU, DL) is converted into an analog signal (AU, AL) by the D / A converter 13, and the analog signal (AU, AL) and the delayed analog signal A2 are further converted. Is amplified in the residual amplifiers 14 and 15 (second sample hold unit), and the amplification result (residual signal) is supplied to the next conversion block. The A / D converter 12 determines the upper digit digital code DU according to the input analog signal A1, and the lower digit digital code DL according to the higher digit digital code DU and the delayed analog signal A2. It is determined.
In this way, the input analog signal A1 is delayed in the sample hold unit 11, and the delayed analog signal A2 is A / D converted in the A / D conversion unit 12, so that the A / D is equal to the delay time of the sample hold unit 11. Since the conversion time of the conversion unit 12 can be given a margin, restrictions on the conversion timing in the A / D conversion unit 12 can be relaxed. As a result, even a clock signal having a higher frequency can be operated, and the conversion rate can be improved. In addition, power consumption can be reduced because the current consumption of a circuit related to A / D conversion or D / A conversion can be reduced and the operation speed can be reduced as long as the timing constraint is satisfied.

  Further, since the lower digit digital code DL is determined according to the delayed analog signal A2, the lower digit component (lower analog signal AL) corresponding to the digital code DL in the output signal of the D / A converter 13 is also obtained. It is determined according to the delayed analog signal A2. The difference between the delayed analog signal A2 and the lower analog signal AL depends exclusively on the input / output characteristics of the A / D converter 12 and the D / A converter 13, and does not depend on the gain error of the sample hold unit 11. Therefore, even in the residual signal that is the result of amplifying the difference between the output signal of the D / A conversion unit 13 and the delayed analog signal A2, the gain of the sample hold unit 11 is used for the lower-order component corresponding to the digital code DL. It does not depend on errors. Thus, since the influence of the gain error of the sample hold unit 11 on the residual signal can be reduced, the monotonic deterioration due to the gain error of the sample hold unit 11 can be effectively suppressed.

Further, according to the present embodiment, the D / A converter 13 generates the upper analog signal AU corresponding to the upper digit digital code DU and the lower analog signal AL corresponding to the lower digit digital code DL. The Then, the difference between the delayed analog signal A2 and the higher-order analog signal AU is amplified in the residual amplifier 14, and the difference between the output signal of the residual amplifier 14 and the lower-order analog signal AL is amplified in the residual amplifier 15. Then, the amplification result is supplied as a residual signal to the next conversion block.
Thus, by performing the amplification operation of the residual signal in two stages, a high gain as a whole can be obtained without increasing the gain of each stage so much.

For example, the literature “Wenhua (Will) Yang et al.,“ A 3-V 340-mW 14-b 75-Msample / s CMOS ADC with 85-dB SFDR at Nyquist Input Solid ”,“ IEEE Journal of Solid-Solid ”. , (USA), December 2001, VOL.36, No. 12, p.1931- 1936, the pipeline A / D converter circuit increases the number of bits of the first stage conversion block, It is known that the linearity of typical A / D conversion can be improved.
When the number of bits is increased, the residual amplification gain must be increased accordingly. However, in a general switched capacitor type amplifier, the gain is set according to the size ratio of the capacitors, so that there is a limit to the gain that can be obtained with a single-stage amplifier. For example, if the number of bits of the first stage conversion block is 6 bits, 64 times of residual amplification must be performed. However, a general switched capacitor type amplifier has a problem that the circuit size becomes very large, and so on. This gain is very difficult to achieve. According to this embodiment, since the amplification operation is performed in two stages of the upper 3 bits and the lower 3 bits, the gain of each stage may be 8 times, and can be sufficiently realized by a general switched capacitor amplifier.
Therefore, according to the present embodiment, it is possible to increase the number of bits of the first stage conversion block, thereby improving the linearity of A / D conversion.

Further, according to the present embodiment, in the A / D conversion unit 12, each of the reference voltages (VR 4, VR 8, VR 12) for determining the upper digit digital code DU and the input analog signal AU are converted into the upper digit comparison unit 122. And the upper digit digital code DU corresponding to the comparison result is generated in the upper digit generator 123. When the upper digit digital code DU is generated, the selection unit 124 determines the lower digit digital code DL corresponding to the upper digit digital code DU from the plurality of reference voltages generated by the reference voltage generation unit 121. A plurality of reference voltages to be selected are selected. Then, each of the selected reference voltages and the delayed analog signal A2 are compared in the lower digit comparison unit 125, and the lower digit digital code DL corresponding to the comparison result is generated in the lower digit generation unit 126.
In this way, by performing A / D conversion in two stages of upper digits and lower digits, the number of comparators can be greatly reduced compared to the case where all digits are converted simultaneously, and the circuit size can be reduced. Can be reduced in size and power consumption.

In addition, according to the present embodiment, the selection unit 124 further selects a reference voltage for determining a digital code included in a range expanded from the range of the lower digit digital code DL corresponding to the upper digit digital code DU. The lower digit comparing unit 125 compares the delayed analog signal A2. Then, the lower digit generation unit 126 generates a correction signal indicating whether or not the lower digit digital code DL is included in the above-described extended range in accordance with the comparison result of the lower digit comparison unit 125. This correction signal Accordingly, the upper digit digital code DU generated by the upper digit generation unit 123 is corrected by the upper digit correction unit 127.
In this way, the A / D conversion is performed in two steps of the upper digit and the lower digit by correcting the A / D conversion result of the upper digit according to the A / D conversion result of the lower digit. However, it is possible to effectively prevent a discontinuous error from occurring in the digital value of the conversion result.
In addition, since the A / D conversion result (digital code DL) of the lower digit is determined according to the delayed analog signal A2, as described above, the monotonic deterioration due to the gain error of the sample hold unit 11 does not occur. Therefore, by correcting the A / D conversion result of the upper digit in accordance with the A / D conversion result (digital code DL) of the lower digit, the monotonic deterioration due to the gain error of the sample hold unit 11 is more effective. Can be suppressed.

  In addition, this invention is not limited only to embodiment mentioned above, Various modifications are included.

The numerical values given in the description such as the resolution (number of bits) and the number of stages of the conversion block in the embodiment described above are arbitrary, and the present invention is not limited to these numerical values.
Further, the circuit configuration of the sample hold unit and the residual amplification unit shown in FIG. 1 and the circuit configuration of the A / D conversion unit 12 shown in FIG. 2 are arbitrary and can be changed to other circuits having equivalent functions. .

It is a figure which shows an example of a structure of the A / D conversion circuit which concerns on embodiment of this invention. It is a figure which shows the structural example of an A / D conversion part and a D / A conversion part. It is a figure for demonstrating the correction method of the high-order digit digital code. It is a figure for demonstrating a series of operation | movement when the analog signal Ain sampled in the sample hold part is A / D converted in the conversion block of the first stage. It is a figure which shows an example of a structure of a general pipeline A / D conversion circuit. FIG. 6 is a diagram for explaining an operation timing of the pipeline A / D conversion circuit shown in FIG. 5. It is a figure which shows the structural example of the pipeline A / D conversion circuit of an analog double sampling system. It is a figure for demonstrating the operation timing of the pipeline A / D conversion circuit shown in FIG. It is a figure for demonstrating the relationship between the gain error of the sample hold part provided in the conversion block, and deterioration of monotonicity.

Explanation of symbols

1-1, 1-2, 1-3 ... conversion block, 2 ... digital correction circuit, SH1, 11 ... sample hold unit, 12 ... A / D conversion unit, 13 ... D / A conversion unit, 14, 15 ... remaining Difference amplifier 121, reference voltage generator 122, upper digit comparison unit 123, upper digit generation unit 124 ... selection unit 125 ... lower digit comparison unit 126 ... lower digit generation unit 127, upper digit correction unit

Claims (5)

An analog / digital conversion circuit comprising a plurality of cascaded conversion blocks that perform analog / digital conversion step by step from coarse digital values to fine digital values,
The transformation block is
A first sample and hold unit for delaying an input analog signal;
An analog / digital converter that performs analog / digital conversion;
A digital / analog converter that converts the digital signal output from the analog / digital converter to an analog signal;
A second sample hold unit that amplifies the difference between the delayed analog signal output from the first sample hold unit and the analog signal output from the digital / analog conversion unit and supplies the amplified signal to the next conversion block. And
The analog / digital conversion unit determines an upper digit digital code according to the input analog signal, and determines a lower digit digital code according to the upper digit digital code and the delayed analog signal.
Analog / digital conversion circuit. The digital / analog conversion unit generates an upper analog signal corresponding to the digital code of the upper digit and a lower analog signal corresponding to the digital code of the lower digit,
The second sample and hold unit includes:
An upper sample-and-hold unit that amplifies the difference between the delayed analog signal and the upper analog signal;
A lower sample hold unit that amplifies a difference between the signal amplified in the upper sample hold unit and the lower analog signal;
The analog / digital conversion circuit according to claim 1. The analog / digital converter is
A reference voltage generator for generating a plurality of reference voltages;
One or more reference voltages for determining the upper digit digital code are input from the reference voltage generation unit, and the upper digit comparison unit for comparing each of the reference voltages with the input analog signal;
An upper digit generation unit that generates a digital code of the upper digit in accordance with a comparison result of the upper digit comparison unit;
A selection unit that selects one or a plurality of reference voltages for determining a lower digit digital code corresponding to the generated higher digit digital code from a plurality of reference voltages generated in the reference voltage generation unit When,
A lower-order digit comparison unit that compares each of the reference voltages selected in the selection unit with the delayed analog signal;
A lower digit generation unit that generates a digital code of the lower digit in accordance with a comparison result of the lower digit comparison unit,
The analog / digital conversion circuit according to claim 1. The selection unit further selects a reference voltage for determining a digital code included in a range extended from a range of a lower digit digital code corresponding to the generated upper digit digital code,
The lower digit generation unit generates a correction signal indicating whether the digital code of the lower digit is included in the extended range according to a comparison result of the lower digit comparison unit;
The analog / digital conversion unit includes an upper digit correction unit that corrects the digital code of the upper digit generated by the upper digit generation unit according to the correction signal.
The analog / digital conversion circuit according to claim 3. The conversion block has four phases as operation steps for converting the input analog signal into a digital signal,
In the first phase,
The first sample hold unit and the analog / digital conversion unit sample the input analog signal,
In the second phase,
The first sample and hold unit outputs the sampling result of the first phase as a delayed analog signal,
The analog / digital conversion unit performs analog / digital conversion of the input analog signal sampled in the first phase, samples a delayed analog signal output from the first sample hold unit,
The upper sample hold unit samples the delayed analog signal output from the first sample hold unit,
In the third phase,
The analog / digital conversion unit performs analog / digital conversion of the delayed analog signal in a range corresponding to the high-order digital code acquired by the second phase analog / digital conversion,
The digital / analog conversion unit converts the analog / digital conversion result of the upper digit into an analog signal,
The upper sample hold unit amplifies and outputs the difference between the delayed analog signal sampled in the second phase and the upper digit analog signal converted by the digital / analog conversion unit,
The lower sample hold unit samples the output signal of the upper sample hold unit,
In the fourth phase,
The digital / analog conversion unit converts the analog / digital conversion result of the lower digit into an analog signal,
The lower sample hold unit amplifies and outputs the difference between the output signal of the upper sample hold unit sampled in the third phase and the analog signal of the lower digit converted by the digital / analog conversion unit,
The analog / digital conversion circuit according to claim 2.

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