JP3138262B2 - Analog-digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter (A / D converter), and more particularly, to an A / D converter having a multi-stage pipeline (step flash) configuration.
It relates to a D converter.

[0002]

2. Description of the Related Art In recent years, with the development of digital processing technology for video signals, the demand for A / D converters for video signal processing has increased. Since a high-speed conversion operation is required for an A / D converter for video signal processing, a two-step flash (two-step parallel) method has conventionally been widely used.

However, with the increase in the number of conversion bits, sufficient conversion accuracy cannot be obtained with the two-step flash method. LSB (Least Significant)
Bit) is represented using the input voltage range (FSR; Full Scale Range) of the analog input signal and the number of bits N as shown in Expression (1). 1LSB = FSR / 2N (1) For example, when the number of bits is 10 bits and the FSR is 2V,
From equation (1), LSB is 2 mV. Thus, LSB
Is smaller, the resolution of each comparator constituting the two-step flash A / D converter is limited, and it is difficult to obtain sufficient conversion accuracy. As a practical matter, obtaining 9 bits or more by the two-step flash method is not practical.

Accordingly, an A / D converter having a multi-stage pipeline configuration in which each stage includes an A / D converter, a digital-analog conversion circuit (D / A converter), and a difference amplifier has been developed. The operation is as follows. First, A / D conversion is performed on the analog input signal using the first-stage A / D converter.
Perform the conversion. Next, the A / D of the first stage A / D converter
The conversion result is applied to the first stage D / A converter to perform D / A conversion. Then, the D / A of the first stage D / A converter
The conversion result and the analog input signal are added to the first-stage difference amplifier, and the difference is amplified. The output of the first-stage difference amplifier is subjected to A / D conversion using the second-stage A / D converter. Next, the A / D conversion result of the second-stage A / D converter is added to the second-stage D / A converter to perform D / A conversion.

Subsequently, the D / A converter of the second stage D / A converter
The result of the A conversion and the output of the first-stage difference amplifier are added to the second-stage difference amplifier to amplify the difference. Thereafter, the same operation is sequentially performed in each stage. However, the last stage includes only an A / D converter, and A / D converts the output of the difference amplifier of the preceding stage. For example, if the number of bits (bit configuration) of the A / D converters in the first to third stages is a, b, and c in a three-stage pipeline configuration, the higher-order a bits From the second stage A / D converter to middle b
A digital output of lower c bits is obtained from the A / D converter of the third stage.

By the way, in the pipeline operation, when the A / D converter at the m-th stage is performing A / D conversion sampling, the D / A converter at the (m + 1) -th stage performs the D / A conversion. That is, in the pipeline operation, the operation of each adjacent stage is different, and the odd and even stages perform different operations. still,
In each stage, the number of bits (bit configuration) n of the A / D converter and the D / A converter is set to be the same. Further, the A / D converter in each stage is called a sub A / D converter to distinguish it from the entire A / D converter. The sub-A / D converter uses an all-parallel comparison (flash) system capable of high-speed conversion operation.

The difference amplifier amplifies the difference between the analog input signal or the output of the preceding stage difference amplifier and the D / A conversion result of the same stage D / A converter. The D / A conversion result is generated after the analog input signal or the output of the preceding difference amplifier is input to that stage. for that reason,
The difference amplifier samples and holds the analog input signal or the output of the preceding difference amplifier until the D / A conversion result is obtained. The sampling time of the difference amplifier is the same as the sampling time of the sub A / D converter in the same stage.

As described above, in the multi-stage pipeline configuration, in each stage, the difference between the analog input signal or the output of the difference amplifier of the preceding stage and the D / A conversion result of the digital output of the stage is determined by the difference of the stage. It is amplified by the difference amplifier. Therefore, even when the number of conversion bits increases and the LSB decreases, the resolution of each comparator constituting the A / D converter can be substantially improved, and sufficient conversion accuracy can be obtained.

[0009]

An A / D converter having a multi-stage pipeline configuration has the following problems. The characteristics of the difference amplifier greatly affect the A / D conversion. Therefore, there is a need for a differential amplifier having a constant gain, high stability, high accuracy and high-speed operation. In order to configure such a differential amplifier with CMOS logic, it is necessary to use a cascaded operational amplifier. However, in the cascade method, the power supply voltage must be increased, and it is difficult to reduce power consumption.

In order to realize a high-precision difference amplifier,
It is necessary to reduce the variation in the negative feedback capacitance by using an operational amplifier. When the A / D converter is formed on-chip, a two-layer polysilicon structure having a sufficiently thick interlayer insulating film is employed to reduce the variation of the negative feedback capacitance, and the negative feedback capacitance is provided between the polysilicon layers. Must be formed. This is because when a single-layer polysilicon structure is used, the negative feedback capacitance must be formed between the polysilicon layer and the metal layer, and the thickness of the interlayer insulating film between the polysilicon layer and the metal layer is small. This is because it is difficult to reduce the variation of the negative feedback capacity. The adoption of the two-layer polysilicon structure complicates the manufacturing process and increases the cost.

The sampling time of the difference amplifier is the same as the sampling time of the sub-A / D converter in the same stage. Therefore, a large slew rate is required for the difference amplifier. In the pipeline operation, since the odd-numbered stage and the even-numbered stage perform different operations, noise is easily generated in the reference voltage line, and the reference voltage is likely to be unstable. When the reference voltage becomes unstable, the A / D conversion accuracy decreases. That is, the reference voltage is supplied to the sub A / D converter and the D / A converter of each stage from the common reference voltage line. Therefore, noise generated in the reference voltage line due to the D / A conversion operation of the odd-numbered (or even-numbered) D / A converter adversely affects the A / D conversion operation of the even-numbered (or odd-numbered) sub-A / D converter. May be exerted. Further, noise generated in the reference voltage line by the A / D conversion operation of the odd-numbered (or even-numbered) sub A / D converter adversely affects the D / A conversion operation of the even-numbered (or odd-numbered) D / A converter. May be exerted.

This problem is particularly conspicuous when the flash method of the sub A / D converter is used. That is, a flash A / D converter having n bits has (2 n -1) comparators, but since many of these comparators operate simultaneously, noise is likely to occur in the reference voltage line. In addition, when the chopper method or the differential chopper method is used for the comparator, the charge / discharge current of the chopper capacitance included in the comparator flows through the reference voltage line, so that very large noise may be generated. In order to reduce this noise, the reference resistance connected in series between the reference voltage lines inside the flash A / D converter may be reduced. However, when the reference resistance is reduced, a through current flowing between the reference voltage lines increases, and power consumption increases.

An object of the present invention is to solve the above-mentioned problems in a multi-stage analog-to-digital conversion circuit.

[0014]

An analog-to-digital converter according to claim 1.
In the digital conversion circuit, each stage except the last stage is analog-to-digital.
Digital conversion circuit and digital-analog conversion circuit
And the last stage is at least analog-digital
A multi-stage pipeline configuration consisting of
The difference amplifier of the desired stage samples the output of the difference amplifier of the previous stage.
The ringing point is the same stage of analog-to-digital conversion
Data is transferred from the
And the output of this digital-analog conversion circuit has settled.
The gist is that it is set after the time point.

An analog-digital conversion circuit according to claim 2
Is a bit configuration of the first stage according to the first aspect of the present invention.
Is set at least 2 bits larger than that of the second and subsequent stages
That is the gist. The analog-digital of claim 3
The conversion circuit according to the first aspect of the present invention,
The bit configuration is set at least 2 bits larger than that of the second and subsequent stages
And the bit configuration from the second stage to the last stage is equally divided
The gist is that it was done.

An analog-digital conversion circuit according to claim 4.
Is the invention according to any one of claims 1 to 3.
The analog-to-digital conversion circuit of each stage
The reference voltage applied to the analog conversion circuit
Is supplied directly from the reference voltage line.
Make a summary.

An analog-digital conversion circuit according to claim 5
The invention according to claim 4, wherein the reference
The gist is that the voltage line has been decoupled.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the first embodiment.
1 shows a block circuit of an A / D converter 1 having a 0-bit 4-stage pipeline configuration. The A / D converter 1 includes a sample-and-hold circuit 2, first to fourth-stage circuits 3 to 6, a latch circuit 7, and an output circuit 8. 1st stage ~
The third-stage circuits 3 to 5 include a sub A / D converter 9 and a D /
An A converter 10 and a difference amplifier 11 are provided. The fourth stage (final stage) circuit 6 includes only the sub A / D converter 9.

The first stage (initial stage) circuit 3 has a 4-bit configuration,
The circuits 4 to 6 in the second to fourth stages each have a 2-bit configuration. In the circuits 3 to 5 of the first to third stages, the number of bits (bit configuration) n of the sub A / D converter 9 and the D / A converter 10 are set to be the same. Next, the operation of the A / D converter 1 will be described.

The sample hold circuit 2 samples the analog input signal Vin and holds it for a certain time. Analog input signal Vin output from sample and hold circuit 2
Is transferred to the first stage circuit 3. In the first-stage circuit 3, the sub-A / D converter 9 outputs the analog input signal Vin.
A / D conversion is performed. Upper 4 bits digital output (2) which is the A / D conversion result of sub A / D converter 9
⁹ , 2 ⁸ , 2 ⁷ , 2 ⁶ ) are transferred to the D / A converter 10 and to the output circuit 8 via the four latch circuits 7. The difference amplifier 11 amplifies the difference between the D / A conversion result of the D / A converter 10 and the analog input signal Vin. The output of the difference amplifier 11 is transferred to the circuit 4 of the second stage.

In the second stage circuit 4, the same operation as that of the first stage circuit 3 is performed on the output of the difference amplifier 11 of the first stage circuit 3. In the circuit 5 of the third stage, the output of the difference amplifier 11 of the circuit 4 of the second stage is
An operation similar to that of the first-stage circuit 3 is performed. Then, the digital output (2 ⁵ , 2
⁴ ) is obtained, and a digital output (2 ³ , 2 ² ) of middle and lower 2 bits is obtained from the third stage circuit 5.

In the circuit 6 of the fourth stage, the sub-A / D converter 9 performs A / D conversion on the output of the difference amplifier 11 of the circuit 5 of the third stage, and outputs the lower 2 bits of digital output (2 ¹ , 2 ⁰ ) are obtained. Digital outputs of the circuits 3 to 6 of the first to fourth stages reach the output circuit 8 at the same time via the respective latch circuits 7. That is, each latch circuit 7 is connected to each of the circuits 3 to
6 for synchronizing the digital outputs.

The output circuit 8 outputs 1 of the analog input signal Vin.
A 0-bit digital output Dout is output in parallel. Incidentally, the difference amplifier 11 is constituted by an operational amplifier, and the accuracy parameter thereof is defined by the gain error GE and the offset OF. Accordingly, as shown in the equation (2), the overrange amount X of the i-th circuits 3 to 6 is determined by the gain error GE and the offset OF and the gain (closed loop gain) Ai of the difference amplifier 11 of the circuits 2 to 6. And the LSBi of the circuits 2-6. Also, the linearity error Y
Is, as shown in equation (3), the gain error GE and the gain A
i and LSBi.

X = Ai × OF + LSBi × Ai × GE (2) Y = [LSB1 + LSB2 / A1 + LSB3 / (A2 × A1) + LSB4 / (A3 × A2)] × GE (3) Overrange Since the smaller the quantity X is, the smaller the gain Ai and the smaller the LSBi are, the better from equation (2). By the way, in order to improve the miscode resistance,
It is better to increase LSBi. Therefore, it is necessary to make the gain Ai as small as possible. Reducing the gain Ai of the circuits 3 to 6 at each stage is nothing less than increasing the number of bits of the circuits 3 to 6 at each stage after increasing the number of stages in the multistage pipeline configuration.

Accordingly, the overrange amount X can be smaller in the case of the four-stage configuration as in the present embodiment than in the case of the two-stage or three-stage configuration. by the way,
In the case of a configuration with five or more stages, the circuit scale of the entire A / D converter may be too large. Also, from the equation (3), when LSB1 of the first stage circuit 3 is reduced, LSB2 to LSB4 of the second to fourth stage circuits 4 to 6 are obtained.
It can be seen that the effect of reducing the linearity error Y is greater than when the value is reduced. Reducing the LSB1 of the first-stage circuit 3 is nothing less than increasing the number of bits (bit configuration) of the first-stage circuit 3. Therefore, the linearity error Y can be made smaller when the first stage circuit 3 is made up of 4 bits as in the present embodiment than when the circuit 3 is made up of 1 to 3 bits.

If the circuit 3 in the first stage has 5 bits or more, LSB1 becomes too small, and it becomes difficult to obtain sufficient conversion accuracy, and the significance of the multistage pipeline configuration is lost. As a practical matter, it is not practical to make the first-stage circuit 3 9 bits or more. In addition, the circuits 3 to
If the number of bits (bit configuration) of 6 is equal, each circuit 3
To 6 have the same configuration, so that it is easy to implement on-chip by CMOS logic.

To summarize the above results, 10 bits A /
To embody the D converter, as in this embodiment,
In a 4-stage pipeline, the first stage circuit 3 has a 4-bit configuration,
The circuits 4 to 6 in the second to fourth stages have a 2-bit configuration (hereinafter, referred to as a 2 bit configuration)
4-2-2-2 configuration). For example, when the 3-3-3-2 configuration is adopted with a four-stage pipeline, the linearity error Y increases while the overrange amount X decreases. Further, when the 4--3-3 configuration is adopted in the three-stage pipeline, the linearity error Y is reduced, but the overrange amount X is increased.
If the 4-stage pipeline has a 4-3-2-1 configuration, the internal circuit configurations of the respective stages are all different, resulting in poor design efficiency.

FIG. 2 shows an internal circuit of the sub A / D converter 9. The sub A / D converter 9 employs a flash method, and includes a reference resistor R, a comparator 21, and an encoder 22. All of the reference resistors R have the same resistance value and are connected in series between the high-potential-side reference voltage line Vrb1 and the low-potential-side reference voltage line Vrt1 (or the high-potential-side reference voltage line Vrb2 and the low-potential-side reference voltage line Vrt2). Have been. The sub-A / D converter 9 having the number of bits (bit configuration) n is (2n
-1) Comparators are provided.

Each comparator 21 receives a divided voltage of the reference voltage generated by the reference resistor R and an input signal (analog input signal Vin or the preceding circuits 3 to 5).
Of the difference amplifier 11). Encoder 2
2 generates a digital output as an A / D conversion result of the input signal based on the comparison result of each comparator 21.

The sub A / Ds of the circuits 4 to 6 in the second to fourth stages
Since the converter 9 has one or more redundant bits, the converter 9 additionally has a reference resistor R and a comparator 21 corresponding to the redundant bits. FIG.
The third-stage circuits 3 to 6 and the reference voltage lines Vrb1, Vrt1, V
The connection relationship between rb2 and Vrt2 is shown.

The first and third stage circuits 3 and 5 are connected to reference voltage lines Vrb1 and Vrt1, and are connected to the second and fourth stages.
The circuits 4 and 6 at the stage are connected to reference voltage lines Vrb2 and Vrt2. That is, the reference voltage lines are separated between the odd-numbered circuits 3 and 5 and the even-numbered circuits 4 and 6. A reference voltage is supplied from a reference voltage line connected to each of the circuits 3 to 6 to the sub A / D converter 9 and the D / A converter 10 of each of the circuits 3 to 6.

The circuits 3 to 6 of the first to fourth stages are formed on one semiconductor chip 31 and are on-chip. The two high-potential-side reference voltage lines Vrb1 and Vrb2 are connected in the vicinity of the power supply pad 32, and the connection point is a capacitor 33.
Decoupled. The two low-potential-side reference voltage lines Vrt1 and Vrt2 are connected near the power supply pad 34, and the connection point is decoupled by the capacitor 35.

In the pipeline operation, the odd-numbered stage circuits 3,
5, when the sub-A / D converter 9 performs A / D conversion, the D / A converters 10 of the even-numbered circuits 4 and 6 perform D / A conversion.
A conversion is performed. When the D / A converters 10 of the odd-numbered circuits 3 and 5 perform D / A conversion, the sub-A / D converters 9 of the even-numbered circuits 4 and 6 perform A / D conversion.

The sub A / D converter 9 includes a large number of comparators 21. Since the large number of comparators operate at the same time, noise is easily generated in the reference voltage line.
In particular, when the chopper method or the differential chopper method is used for the comparator 21, the charge / discharge current of the chopper capacitance included in the comparator 21 flows through the reference voltage line, so that very large noise may be generated.

However, in this embodiment, the reference voltage lines are separated by the odd-numbered circuits 3 and 5 and the even-numbered circuits 4 and 6. Therefore, noise generated in the reference voltage line by the A / D conversion operation of the odd-numbered (or even-numbered) sub A / D converter 9 causes the D / A conversion operation of the even-numbered (or odd-numbered) D / A converter 10. There is no danger of adverse effects. As a result, the reference voltage can be stabilized.

Further, since the reference voltage line is decoupled by the capacitors 33 and 35, the reference voltage is fixed by the capacitance of the capacitors 33 and 35. Therefore, even when the chopper method or the differential chopper method is used for the comparator 21, the comparator 21
The charge / discharge current of the chopper capacity of the
Absorbed by 3,35. Conversely, when the differential method is used for the comparator 21, the noise generated in the reference voltage line is small.
5 may be reduced, and if the noise is extremely small, the capacitors 33 and 35 may be omitted.

The difference amplifier 11 converts the analog input signal Vin or the output of the difference amplifier 11 of the circuits 3 and 4 of the preceding stage with the D / A conversion result of the D / A converter 10 of the circuits 3 to 5 of the same stage. Amplify the difference. The D / A conversion result is generated after the analog input signal Vin or the output of the difference amplifier 11 of the circuits 3 and 4 of the preceding stage is input to the circuits 3 to 5 of that stage. Therefore, the difference amplifier 11 outputs D /
Until the A conversion result is obtained, the analog input signal Vin
Alternatively, the output of the difference amplifier 11 of the circuits 3 and 4 at the preceding stage is sampled and held.

Conventionally, as shown in FIG.
1 and the circuit 3 to the same stage
The sampling time (B in the drawing) of the sub-A / D converter 9 of No. 5 is set to be the same. This is the same circuit 3
5, the sample voltage of the difference amplifier 11 and the sub-A
This is to make the sample voltage of the / D converter 9 equal. If a difference occurs between the two sample voltages, the A / D conversion accuracy decreases.

In the present embodiment, as shown in FIG. 5, the sampling time of the difference amplifier 11 (illustrated A) is set to be longer than the sampling time (illustrated B) of the sub A / D converter 9 of the circuits 3 to 5 in the same stage. I have set it later. As a result, in the circuits 3 to 5 at the same stage, a slight difference occurs between the sample voltage of the difference amplifier 11 and the sample voltage of the sub A / D converter 9. However, the second and third circuits 4, 5
Since the bit configuration is small at 2 bits, the difference in the sample voltage is very small with respect to LSBi. Therefore, the A / D conversion accuracy hardly decreases due to the difference in the sample voltage.

As described above, the sub-A / D converters 9 of the circuits 4 to 6 of the second to fourth stages have one or more redundant bits. Since the difference generated in the sample voltage is absorbed by the redundant bit, a decrease in A / D conversion accuracy can be prevented. It should be noted that the number of redundant bits required to absorb the difference between the sample voltages is only one bit.

As described above, according to the present embodiment, the following operations and effects can be obtained. (1) By adopting a multi-stage pipeline configuration, each stage circuit 3
5, the analog input signal Vin or the output of the difference amplifier 11 of the circuits 3 and 4 of the preceding stage and the circuits 3 to 5 of that stage.
Is amplified by the difference amplifier 11. Therefore, even if the number of conversion bits increases and the LSB decreases, the resolution of each comparator 21 constituting the sub-A / D converter 9 can be substantially improved, and sufficient conversion accuracy can be obtained.

(2) Even if the characteristics of the difference amplifier 11 are inferior, sufficient conversion accuracy can be obtained. Therefore, the above-mentioned problems can be avoided. That is,
There is no need to configure the difference amplifier 11 with a cascaded operational amplifier. Further, since it is not necessary to pay much attention to the variation of the negative feedback capacitance of the difference amplifier 11, the semiconductor chip 31 can adopt a single-layer polysilicon structure. As a result, both power consumption and cost of the A / D converter 1 can be reduced.

(3) Since the sampling time of the difference amplifier 11 is set after the sampling time of the sub A / D converter 9 of the circuits 3 to 5 in the same stage, the slew rate of the difference amplifier 11 needs to be increased. There is no. That is, the slew rate characteristic required for the difference amplifier 11 is reduced. Therefore, the above-mentioned problem can be avoided.

(4) Since the reference voltage is stabilized, the conversion accuracy of the A / D converter 1 is improved. Therefore, the above-mentioned problem can be avoided. That is, since it is not necessary to reduce the reference resistance R,
Through current flowing between the reference voltage lines can be reduced, and power consumption can be reduced. (5) The A / D converter 1 can be constituted by CMOS logic to be on-chip.

The above embodiment may be modified as follows, and the same operation and effect can be obtained in such a case. (1) Four reference voltage lines Vrb1, Vrt1, Vrb2, V
Decouple rt2 with separate capacitors. In this way, the reference voltage is further stabilized.

(2) Separate reference voltage lines are provided for each of the circuits 3 to 6 in the first to fourth stages. In this way, the reference voltage is further stabilized. (3) The sub A / D converter 9 is embodied by a method other than the flash method. Although the embodiments have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below along with their effects.

(A) The analog-digital conversion circuit according to any one of claims 1 to 7, wherein the bit configuration of each stage is 8 bits or less. By doing so, the A / D conversion accuracy is improved. (B) Each stage has an analog-digital conversion circuit and digital
It has a multi-stage pipeline configuration consisting of an analog conversion circuit and a difference amplifier, and has separate reference voltage lines for odd and even stages.Each reference voltage line is composed of a high-potential-side wiring and a low-potential-side wiring. An analog-to-digital conversion circuit in which voltage lines are separately decoupled.

By doing so, the reference voltage is further stabilized.

[0049]

As described above in detail, according to the present invention, the slew rate characteristic required for the difference amplifier in the multi-stage analog-to-digital converter can be reduced.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of one embodiment.

FIG. 2 is a circuit diagram of a comparator constituting one embodiment.

FIG. 3 is a circuit diagram showing a connection relation of reference voltage lines according to one embodiment.

FIG. 4 is a conventional timing chart.

FIG. 5 is a timing chart of one embodiment.

[Explanation of symbols]

 3 1st stage circuit 4 2nd stage circuit 5 3rd stage circuit 6 4th stage circuit 9 ... sub A / D converter 10 ... D / A converter 11 ... differential amplifier Vrb1, Vrb2 ... high Potential-side reference voltage lines Vrt1, Vrt2 ... low-potential-side reference voltage lines 33, 35 ... capacitors

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-9-69776 (JP, A) JP-A-2-257719 (JP, A) JP-A-5-14199 (JP, A) JP-A-7-69 202700 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (5)

(57) [Claims] 1. A multi-stage pipeline configuration in which each stage except the last stage includes an analog-to-digital conversion circuit, a digital-to-analog conversion circuit, and a difference amplifier, and the last stage includes at least an analog-to-digital conversion circuit .
Stage difference amplifier samples the output of the previous stage difference amplifier
Is the same stage analog-digital conversion circuit
Data is transferred to the digital-to-analog conversion circuit.
After the output of the digital-to-analog conversion circuit of
An analog-to-digital conversion circuit, which is set to be lower . 2. The contractor according to claim 1, wherein the bit configuration of the first stage is set to be larger than that of the second stage by 2 bits or more.
Digital converter - analogue according to Motomeko 1. 3. A bit configuration of the first stage is set to be larger than 2 bits than that of the second stage or later, according to claim 1 which is characterized in that the bit configuration of the last stage is equally evenly divided two stages
3. The analog-digital conversion circuit according to claim 1. Wherein said each stage of the analog - digital converter and a digital - the reference voltage applied to the analog conversion circuit, any one of claims 1 to 3 characterized in that it is supplied directly from the reference voltage line 2. The analog-digital conversion circuit according to claim 1. 5. The analog-to-digital converter according to claim 4 , wherein said reference voltage line is decoupled.
Digital conversion circuit.