JP3086636B2 - Analog-digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an analog-to-digital converter (A / D converter), and more particularly, to an A / D converter having a multi-stage pipeline (step flash) configuration.
It concerns a converter.

[0002]

2. Description of the Related Art In recent years, with the development of digital processing technology for video signals, the demand for A / D converters for video signal processing has increased. Since a high-speed conversion operation is required for an A / D converter for video signal processing, a two-step flash (two-step parallel) method has conventionally been widely used.

However, with the increase in the number of conversion bits, sufficient conversion accuracy cannot be obtained with the two-step flash method. LSB (Least Significant)
Bit) is represented using the input voltage range (FSR; Full Scale Range) of the analog input signal and the number of bits N as shown in Expression (1).

1 LSB = FSR / 2 ^N (1) For example, when the number of bits is 10 bits and the FSR is 2 V,
From equation (1), LSB is 2 mV. Thus, LSB
Is smaller, the resolution of each comparator constituting the two-step flash A / D converter is limited, and it is difficult to obtain sufficient conversion accuracy. As a practical matter, obtaining 9 bits or more by the two-step flash method is not practical.

Accordingly, an A / D converter having a multi-stage pipeline configuration in which each stage includes an A / D converter, a digital-analog conversion circuit (D / A converter), and a difference amplifier has been developed.

In the operation, first, A / D conversion is performed on an analog input signal using an A / D converter of the first stage. Next, the A / D conversion result of the first-stage A / D converter is added to the first-stage D / A converter to perform D / A conversion. Subsequently, the D / A conversion result of the first stage D / A converter and the analog input signal are added to the first stage difference amplifier,
Amplify the difference. The output of the first-stage difference amplifier is subjected to A / D conversion using the second-stage A / D converter. Next, the A / D conversion result of the second-stage A / D converter is added to the second-stage D / A converter to perform D / A conversion. Subsequently, the D / A conversion result of the second stage D / A converter and the output of the first stage difference amplifier are added to the second stage difference amplifier to amplify the difference. Thereafter, the same operation is sequentially performed in each stage. However, the last stage includes only an A / D converter, and A / D converts the output of the difference amplifier of the preceding stage.
For example, in a three-stage pipeline configuration, the A / D of the first to third stages
The number of bits (bit configuration) of the converter is a,
In the case of b and c, digital output of the upper a bits from the first-stage A / D converter, the middle b bits from the second-stage A / D converter, and the lower c bits from the third-stage A / D converter Is obtained.

In the pipeline operation, when the A / D converter in the m-th stage is performing A / D conversion sampling, the D / A converter in the (m + 1) -th stage performs D / A conversion. That is, in the pipeline operation, the operation of each adjacent stage is different, and the odd and even stages perform different operations.

In each stage, an A / D converter and D
The number of bits (bit configuration) n of the / A converter is set to be the same. In addition, the A / D converter of each stage has an A / D converter.
It is called a sub A / D converter to distinguish it from the whole D converter. The sub-A / D converter uses an all-parallel comparison (flash) system capable of high-speed conversion operation.

The difference amplifier amplifies the difference between the analog input signal or the output of the preceding stage difference amplifier and the D / A conversion result of the D / A converter in the same stage. The D / A conversion result is generated after the analog input signal or the output of the preceding difference amplifier is input to that stage. for that reason,
The difference amplifier samples and holds the analog input signal or the output of the preceding difference amplifier until the D / A conversion result is obtained. The sampling time of the difference amplifier is the same as the sampling time of the sub A / D converter in the same stage.

As described above, in the multistage pipeline configuration, in each stage, the difference between the analog input signal or the output of the difference amplifier of the preceding stage and the D / A conversion result of the digital output of the stage is determined by the difference of the stage. It is amplified by the difference amplifier. Therefore, even when the number of conversion bits increases and the LSB decreases, the resolution of each comparator constituting the A / D converter can be substantially improved, and sufficient conversion accuracy can be obtained.

[0011]

An A / D converter having a multi-stage pipeline configuration has the following problems. The characteristics of the difference amplifier greatly affect the A / D conversion. Therefore, there is a need for a differential amplifier having a constant gain, high stability, high accuracy and high-speed operation.

In order to constitute the above-described differential amplifier with CMOS logic, it is necessary to use a cascade type operational amplifier. However, in the cascade method, the power supply voltage must be increased, and it is difficult to reduce power consumption.

In order to implement a high-precision difference amplifier,
It is necessary to reduce the variation in the negative feedback capacitance by using an operational amplifier. When the A / D converter is formed on-chip, a two-layer polysilicon structure having a sufficiently thick interlayer insulating film is employed to reduce the variation of the negative feedback capacitance, and the negative feedback capacitance is provided between the polysilicon layers. Must be formed. This is because when a single-layer polysilicon structure is used, the negative feedback capacitance must be formed between the polysilicon layer and the metal layer, and the thickness of the interlayer insulating film between the polysilicon layer and the metal layer is small. This is because it is difficult to reduce the variation of the negative feedback capacity. The adoption of the two-layer polysilicon structure complicates the manufacturing process and increases the cost.

The sampling time of the difference amplifier is the same as the sampling time of the sub A / D converter in the same stage. Therefore, a large slew rate is required for the difference amplifier.

In the pipeline operation, since the odd-numbered stage and the even-numbered stage perform different operations, noise is easily generated in the reference voltage line, and the reference voltage is likely to be unstable. When the reference voltage becomes unstable, the A / D conversion accuracy decreases. That is, the reference voltage is supplied from the common reference voltage line to the sub A / D converter and the D / A converter in each stage. Therefore, noise generated in the reference voltage line by the D / A conversion operation of the odd-numbered (or even-numbered) D / A converter adversely affects the A / D conversion operation of the even-numbered (or odd-numbered) sub-A / D converter. May be exerted. In addition, noise generated in the reference voltage line by the A / D conversion operation of the odd-numbered (or even-numbered) sub A / D converter adversely affects the D / A conversion operation of the even-numbered (or odd-numbered) D / A converter. May be exerted.

This problem is particularly prominent when the flash method is used for the sub A / D converter. In other words, the flash A / D converter having n bits has (2 ⁿ -1) comparators, but since many of these comparators operate simultaneously, noise is likely to occur in the reference voltage line.

In addition, when the chopper method or the differential chopper method is used for the comparator, a very large noise may be generated because the charge / discharge current of the chopper capacitance included in the comparator flows through the reference voltage line. To reduce this noise, the reference resistance connected in series between the reference voltage lines inside the flash A / D converter may be reduced. However, when the reference resistance is reduced, a through current flowing between the reference voltage lines increases, and power consumption increases.

The present invention has been made in view of the above problems, and has as its object
Is a high-precision, low-power analog-to-digital conversion circuit.
To provide a road.

[0019]

An analog-to-digital converter according to claim 1.
In the digital conversion circuit, each stage except the last stage is analog-to-digital.
Digital conversion circuit and digital-analog conversion circuit
And the last stage is at least analog-digital
Takes a multi-stage pipeline configuration consisting of
The bit configuration of the stage is 2 bits or more larger than that of the second stage or later.
Supply a reference voltage to each stage.
Reference voltage lines are separated between odd and even stages.
The gist is that it was done.

An analog-to-digital conversion circuit according to claim 2
The invention according to claim 1, wherein the reference voltage line
Is decoupled.

An analog-digital conversion circuit according to claim 3
In the invention of claim 1 or 2,
The gist is that the bit structure of the stage is equally divided
And

An analog-to-digital conversion circuit according to claim 4.
In the invention of claim 3, the bit configuration of the first stage is
4 bits, the bit configuration from the second stage to the last stage is 2
The gist is that it is a bit.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block circuit of an A / D converter 1 having a 10-bit four-stage pipeline configuration according to the present embodiment.

The A / D converter 1 includes a sample hold circuit 2, first to fourth stage circuits 3 to 6, a latch circuit 7,
It comprises an output circuit 8.

The circuits 3 to 5 in the first to third stages include a sub A /
D converter 9, D / A converter 10, difference amplifier 1
1 is provided. The fourth stage (final stage) circuit 6 includes only the sub A / D converter 9. Circuit 3 of the first stage (first stage) is 4
The bit configuration and the circuits 4 to 6 in the second to fourth stages each have a 2-bit configuration. In the circuits 3 to 5 of the first to third stages, the number of bits (bit configuration) n of the sub A / D converter 9 and the D / A converter 10 are set to be the same.

Next, the operation of the A / D converter 1 will be described. The sample and hold circuit 2 receives the analog input signal Vin
Is sampled and held for a certain period of time. The analog input signal Vin output from the sample and hold circuit 2 is transferred to the first stage circuit 3.

In the circuit 3 of the first stage, the sub A / D converter 9 performs A / D conversion on the analog input signal Vin. The upper 4 bits of the digital output (2 ⁹ , 2 ⁸ , 2 ⁷ , 2 ⁶ ) as the A / D conversion result of the sub A / D converter 9 are
The data is transferred to the D / A converter 10 and to the output circuit 8 via the four latch circuits 7. The difference amplifier 11 amplifies the difference between the D / A conversion result of the D / A converter 10 and the analog input signal Vin. The output of the difference amplifier 11 is transferred to the circuit 4 of the second stage.

In the second stage circuit 4, the same operation as that of the first stage circuit 3 is performed on the output of the difference amplifier 11 of the first stage circuit 3. In the circuit 5 of the third stage, the output of the difference amplifier 11 of the circuit 4 of the second stage is
An operation similar to that of the first-stage circuit 3 is performed. Then, the digital output (2 ⁵ , 2
⁴ ) is obtained, and a digital output (2 ³ , 2 ² ) of middle and lower 2 bits is obtained from the third stage circuit 5.

In the circuit 6 of the fourth stage, the sub-A / D converter 9 performs A / D conversion on the output of the difference amplifier 11 of the circuit 5 of the third stage, and outputs the lower 2 bits of digital output (2 ¹ , 2 ⁰ ) are obtained.

The digital outputs of the circuits 3 to 6 at the first to fourth stages reach the output circuit 8 via the respective latch circuits 7 at the same time. That is, each latch circuit 7 is provided for synchronizing digital outputs of the circuits 3 to 6.

The output circuit 8 outputs 1 of the analog input signal Vin.
A 0-bit digital output Dout is output in parallel. Incidentally, the difference amplifier 11 is constituted by an operational amplifier, and the accuracy parameter thereof is defined by the gain error GE and the offset OF. Accordingly, as shown in the equation (2), the overrange amount X of the i-th circuits 3 to 6 is determined by the gain error GE and the offset OF and the gain (closed loop gain) Ai of the difference amplifier 11 of the circuits 2 to 6. And the LSBi of the circuits 2-6. Also, the linearity error Y
Is, as shown in equation (3), the gain error GE and the gain A
i and LSBi.

X = Ai × OF + LSBi × Ai × GE (2) Y = [LSB1 + LSB2 / A1 + LSB3 / (A2 × A1) + LSB4 / (A3 × A2)] × GE (3) Overrange Since the smaller the quantity X is, the smaller the gain Ai and the smaller the LSBi are, the better from equation (2). By the way, in order to improve the miscode resistance,
It is better to increase LSBi. Therefore, it is necessary to make the gain Ai as small as possible. Reducing the gain Ai of the circuits 3 to 6 at each stage is nothing less than increasing the number of bits of the circuits 3 to 6 at each stage after increasing the number of stages in the multistage pipeline configuration. Therefore, the overrange amount X can be smaller in the case of the four-stage configuration as in the present embodiment than in the case of the two-stage or three-stage configuration. By the way, when it is composed of five or more stages, A / D
The circuit scale of the entire converter may be too large.

From the equation (3), L of the circuit 3 of the first stage is obtained.
When SB1 is reduced, the circuits 4 to 6 in the second to fourth stages are used.
It can be seen that the effect of reducing the linearity error Y is greater than when LSB2 to LSB4 are reduced. Decreasing LSB1 of the first stage circuit 3 is equivalent to reducing the first stage circuit 3
Is to increase the number of bits (bit configuration). Therefore, the linearity error Y can be made smaller when the first stage circuit 3 is made up of 4 bits as in the present embodiment than when the circuit 3 is made up of 1 to 3 bits. by the way,
If the first-stage circuit 3 has 5 bits or more, LSB1 becomes too small, and it becomes difficult to obtain sufficient conversion accuracy, and the significance of the multi-stage pipeline configuration is lost. As a practical matter, it is not practical to make the first-stage circuit 3 9 bits or more.

If the number of bits (bit configuration) of the circuits 3 to 6 in each stage is made equal, the circuits 3 to 6 have the same configuration, so that it is easy to implement on-chip by CMOS logic. Summarizing the above results, in order to embody a 10-bit A / D converter, as in the present embodiment, the first-stage circuit 3 has a 4-bit configuration using a four-stage pipeline and the second to fourth stages. The circuits 4 to 6 have a 2-bit configuration (hereinafter referred to as 4-2
2-2 configuration).

For example, in a 4-stage pipeline,
When the two configurations are adopted, the linearity error Y increases while the overrange amount X decreases. Further, when the 4--3-3 configuration is adopted in the three-stage pipeline, the linearity error Y is reduced, but the overrange amount X is increased. If the 4-stage pipeline has a 4-3-2-1 configuration, the internal circuit configurations of the respective stages are all different, resulting in poor design efficiency.

FIG. 2 shows an internal circuit of the sub A / D converter 9. The sub A / D converter 9 employs a flash method, and includes a reference resistor R, a comparator 21, and an encoder 22. All of the reference resistors R have the same resistance value and are connected in series between the high-potential-side reference voltage line Vrb1 and the low-potential-side reference voltage line Vrt1 (or the high-potential-side reference voltage line Vrb2 and the low-potential-side reference voltage line Vrt2). Have been. The sub A / D converter 9 having the number of bits (bit configuration) n is (2 ⁿ
-1) Comparators are provided. Each comparator 21 receives the divided voltage of the reference voltage generated by the reference resistor R and an input signal (analog input signal V
in or the output of the difference amplifier 11 of the preceding circuits 3 to 5). The encoder 22 generates a digital output, which is an A / D conversion result of the input signal, based on a comparison result of each comparator 21.

The sub A / Ds of the circuits 4 to 6 in the second to fourth stages
Since the converter 9 has one or more redundant bits, the converter 9 additionally has a reference resistor R and a comparator 21 corresponding to the redundant bits.

FIG. 3 shows a connection relationship between the first to fourth stage circuits 3 to 6 and the reference voltage lines Vrb1, Vrt1, Vrb2, Vrt2. The first and third stage circuits 3 and 5 are connected to reference voltage lines Vrb1 and Vrt1, and the second and fourth stage circuits 4 and 6 are connected to reference voltage lines Vrb2 and Vrt2. That is, the reference voltage lines are separated between the odd-numbered circuits 3 and 5 and the even-numbered circuits 4 and 6. Sub A / D converter 9 and D / A of circuits 3 to 6 at each stage
The converter 10 is supplied with reference voltages from reference voltage lines connected to the circuits 3 to 6.

The circuits 3 to 6 of the first to fourth stages are formed on one semiconductor chip 31 and are on-chip. The two high-potential-side reference voltage lines Vrb1 and Vrb2 are connected in the vicinity of the power supply pad 32, and the connection point is a capacitor 33.
Decoupled. The two low-potential-side reference voltage lines Vrt1 and Vrt2 are connected near the power supply pad 34, and the connection point is decoupled by the capacitor 35.

In the pipeline operation, the odd-numbered stage circuits 3,
5, when the sub-A / D converter 9 performs A / D conversion, the D / A converters 10 of the even-numbered circuits 4 and 6 perform D / A conversion.
A conversion is performed. When the D / A converters 10 of the odd-numbered circuits 3 and 5 perform D / A conversion, the sub-A / D converters 9 of the even-numbered circuits 4 and 6 perform A / D conversion.

The sub A / D converter 9 includes a large number of comparators 21. Since the large number of comparators operate at the same time, noise is easily generated in the reference voltage line.
In particular, when the chopper method or the differential chopper method is used for the comparator 21, the charge / discharge current of the chopper capacitance included in the comparator 21 flows through the reference voltage line, so that very large noise may be generated.

However, in this embodiment, the reference voltage lines are separated by the odd-numbered circuits 3 and 5 and the even-numbered circuits 4 and 6. Therefore, noise generated in the reference voltage line by the A / D conversion operation of the odd-numbered (or even-numbered) sub A / D converter 9 causes the D / A conversion operation of the even-numbered (or odd-numbered) D / A converter 10. There is no danger of adverse effects. As a result, the reference voltage can be stabilized.

Further, since the reference voltage line is decoupled by the capacitors 33 and 35, the reference voltage is fixed by the capacitance of the capacitors 33 and 35. Therefore, even when the chopper method or the differential chopper method is used for the comparator 21, the comparator 21
The charge / discharge current of the chopper capacity of the
Absorbed by 3,35. Conversely, when the differential method is used for the comparator 21, the noise generated in the reference voltage line is small.
5 may be reduced, and if the noise is extremely small, the capacitors 33 and 35 may be omitted.

By the way, the difference amplifier 11 converts the analog input signal Vin or the output of the difference amplifier 11 of the circuits 3 and 4 of the preceding stage with the D / A conversion result of the D / A converter 10 of the circuits 3 to 5 of the same stage. Amplify the difference. The D / A conversion result is generated after the analog input signal Vin or the output of the difference amplifier 11 of the circuits 3 and 4 of the preceding stage is input to the circuits 3 to 5 of that stage. Therefore, the difference amplifier 11 outputs D /
Until the A conversion result is obtained, the analog input signal Vin
Alternatively, the output of the difference amplifier 11 of the circuits 3 and 4 at the preceding stage is sampled and held.

Conventionally, as shown in FIG.
1 and the circuit 3 to the same stage
The sampling time (B in the drawing) of the sub-A / D converter 9 of No. 5 is set to be the same. This is the same circuit 3
5, the sample voltage of the difference amplifier 11 and the sub-A
This is to make the sample voltage of the / D converter 9 equal. If a difference occurs between the two sample voltages, the A / D conversion accuracy decreases.

In the present embodiment, as shown in FIG. 5, the sampling time of the difference amplifier 11 (illustrated A) is set longer than the sampling time of the sub A / D converter 9 of the circuits 3 to 5 in the same stage (illustrated B). I have set it later.

As a result, in the circuits 3 to 5 in the same stage,
A slight difference occurs between the sample voltage of the difference amplifier 11 and the sample voltage of the sub A / D converter 9. However, since the bit configuration of the circuits 4 and 5 in the second and third stages is as small as 2 bits, the difference in the sample voltage is very small with respect to LSBi. Therefore, the A / D conversion accuracy hardly decreases due to the difference in the sample voltage.

As described above, the sub-A / D converters 9 of the circuits 4 to 6 in the second to fourth stages have one or more redundant bits. Since the difference generated in the sample voltage is absorbed by the redundant bit, a decrease in A / D conversion accuracy can be prevented. It should be noted that the number of redundant bits required to absorb the difference between the sample voltages is only one bit.

As described above, according to the present embodiment, the following operations and effects can be obtained. (1) By adopting a multi-stage pipeline configuration, each stage circuit 3
5, the analog input signal Vin or the output of the difference amplifier 11 of the circuits 3 and 4 of the preceding stage and the circuits 3 to 5 of that stage.
Is amplified by the difference amplifier 11. Therefore, even if the number of conversion bits increases and the LSB decreases, the resolution of each comparator 21 constituting the sub-A / D converter 9 can be substantially improved, and sufficient conversion accuracy can be obtained.

(2) Even if the characteristics of the difference amplifier 11 are inferior, sufficient conversion accuracy can be obtained. Therefore, the above-mentioned problems can be avoided. That is,
There is no need to configure the difference amplifier 11 with a cascaded operational amplifier. Further, since it is not necessary to pay much attention to the variation of the negative feedback capacitance of the difference amplifier 11, the semiconductor chip 31 can adopt a single-layer polysilicon structure. As a result, both power consumption and cost of the A / D converter 1 can be reduced.

(3) Since the sampling time of the difference amplifier 11 is set after the sampling time of the sub A / D converter 9 of the circuits 3 to 5 in the same stage, it is necessary to increase the slew rate of the difference amplifier 11. There is no. That is, the slew rate characteristic required for the difference amplifier 11 is reduced. Therefore, the above-mentioned problem can be avoided.

(4) Since the reference voltage is stabilized, the conversion accuracy of the A / D converter 1 is improved. Therefore, the above-mentioned problem can be avoided. That is, since it is not necessary to reduce the reference resistance R,
Through current flowing between the reference voltage lines can be reduced, and power consumption can be reduced.

(5) The A / D converter 1 can be formed on a chip by using CMOS logic. The above embodiment may be modified as follows, and the same operation and effect can be obtained in such a case.

(1) Four reference voltage lines Vrb1, Vrb
Decouple rt1, Vrb2, and Vrt2 with separate capacitors. In this way, the reference voltage is further stabilized.

(2) Separate reference voltage lines are provided for each of the circuits 3 to 6 in the first to fourth stages. In this way, the reference voltage is further stabilized. (3) The sub A / D converter 9 is embodied by a method other than the flash method.

Although the embodiments have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below together with their effects. (A) The analog according to any one of claims 1 to 3.
In a digital conversion circuit, an analog-digital conversion circuit in which the bit configuration of each stage is 8 bits or less.

In this way, the A / D conversion accuracy is improved. (B) Each stage has an analog-digital conversion circuit and digital
It has a multi-stage pipeline configuration consisting of an analog conversion circuit and a difference amplifier, and has separate reference voltage lines for odd and even stages.Each reference voltage line is composed of a high-potential-side wiring and a low-potential-side wiring. An analog-to-digital conversion circuit in which voltage lines are separately decoupled.

In this case, the reference voltage is further stabilized.

[0060]

According to the present invention as described in detail above, high
Providing accurate and low power consumption analog-to-digital conversion circuit
Can be offered.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of one embodiment.

FIG. 2 is a circuit diagram of a comparator constituting one embodiment.

FIG. 3 is a circuit diagram showing a connection relation of reference voltage lines according to one embodiment.

FIG. 4 is a conventional timing chart.

FIG. 5 is a timing chart of one embodiment.

[Explanation of symbols]

 3 1st stage circuit 4 2nd stage circuit 5 3rd stage circuit 6 4th stage circuit 9 ... sub A / D converter 10 ... D / A converter 11 ... differential amplifier Vrb1, Vrb2 ... high Potential-side reference voltage lines Vrt1, Vrt2 ... low-potential-side reference voltage lines 33, 35 ... capacitors

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (4)

(57) [Claims] 1. Each stage except the last stage is analog-digital
Conversion circuit, digital-analog conversion circuit, difference amplifier
And the last stage is at least analog-digital
Takes a multi-stage pipeline configuration consisting of conversion circuits,
The bit configuration is at least 2 bits larger than that of the second and subsequent stages
Set and supply a reference voltage to each stage
Reference voltage lines are separated at odd and even stages
An analog-digital conversion circuit characterized by the above-mentioned. 2. The method according to claim 1, wherein the reference voltage line is decoupled.
2. The analog according to claim 1, wherein
Digital conversion circuit. 3. The bit configuration of the two stages to the last stage is equal.
3. The method according to claim 1, wherein
Analog-digital conversion circuit. 4. The bit configuration of the first stage is 4 bits and 2 bits
The bit configuration from the stage to the last stage is 2 bits each.
4. The analog-to-digital converter according to claim 3, wherein
Replacement circuit.