WO2015002478A1

WO2015002478A1 - Multiplying digital analog converter and operating method for same

Info

Publication number: WO2015002478A1
Application number: PCT/KR2014/005948
Authority: WO
Inventors: 김철우; 이호규; .아으렁거젭; 박세진
Original assignee: 고려대학교 산학협력단
Priority date: 2013-07-03
Filing date: 2014-07-03
Publication date: 2015-01-08
Also published as: KR101476539B1

Abstract

The present invention relates to a multiplying digital analog converter included in a pipelined analog digital converter, and an operating method for same. The multiplying digital analog converter comprises: a first capacitor unit which samples an input voltage in a sampling phase and holds same, and amplifies the difference between the input voltage and a reference voltage in an amplification phase, and transmits same to an output terminal; and a second capacitor unit which samples the input voltage in the sampling phase, and holds same, and transmits, to the first capacitor unit, the voltage difference resulting from the reference voltage having been subtracted from the input voltage in the amplification phase. The first capacitor unit can comprise three Y-connected capacitors.

Description

Multiplying Digital Analog Converter and Its Operation Method

It relates to the structure and operation method of a multiplying digital analog converter included in a pipelined analog to digital converter.

Analog-to-Digital Converter (ADC) is a device that converts analog signals to digital signals.The analog-to-digital converter is a flash analog-to-digital converter (Flash ADC), a sequential comparison analog-to-digital converter ( It is divided into Successive-approximation ADC, Integrated Analog-to-Digital Converter (Integrating ADC), Pipelined Analog-to-Digital Converter (Pipelined ADC), and Sigma-Delta Analog-to-Digital Converter (Sigma-Delta ADC).

The analog-to-digital converter converts an analog signal into a digital code corresponding to the analog signal. The generated digital code is processed in the digital domain and is easy to store data.

In portable systems, high-speed, high resolution, low-power analog-to-digital converters are popular for digital multimedia. Recently, many researches on digital converters related to digital multimedia have been conducted.

It is an object of one embodiment of the present invention to provide a multiplying digital analog converter and a method of operation thereof.

According to one side, a first capacitor unit for sampling and holding the input voltage in the sampling phase, and amplifies the difference between the input voltage and the reference voltage in the amplifying phase and transfers it to an output terminal; And a second capacitor unit configured to sample and hold the input voltage in the sampling phase, and to transfer the voltage difference obtained by subtracting the reference voltage from the input voltage in the amplifying phase to the first capacitor unit. The capacitor section is provided with a multiplying digital-to-analog converter comprising three capacitors connected Y-shaped.

According to one embodiment of the present invention, a reduction in clock distribution circuit, a reduction in silicon area, and low power operation can be expected.

1 is a block diagram of a multiplying digital-to-analog converter according to one embodiment.

2 is a schematic conceptual diagram of a pipelined analog-to-digital converter according to an embodiment.

3 is a block diagram of a multiplying digital-to-analog converter according to an embodiment.

4 is a circuit diagram showing the structure of a conventional multiplying digital-to-analog converter.

FIG. 5 shows an operation diagram of the circuit during the sampling phase of the multiplying digital analog converter of FIG. 4.

FIG. 6 shows an operation diagram of the circuit during the amplifying phase of the multiplying digital analog converter of FIG. 4.

Figure 7 shows a detailed circuit diagram of a multiplying digital analog converter according to one embodiment.

8 is a diagram illustrating an operation of a circuit during a sampling phase of the multiplying digital-to-analog converter of FIG. 7 according to an embodiment.

9 illustrates an operation diagram of a circuit during an amplifying phase of the multiplying digital analog converter of FIG. 7 according to one embodiment.

10 illustrates a block diagram of a differential mode multiplying digital analog converter according to one embodiment.

11 is a circuit diagram illustrating a structure of a differential mode multiplying digital analog converter according to an embodiment.

12 illustrates an operation diagram of a circuit during the sampling phase of a differential mode multiplying digital analog converter according to one embodiment.

FIG. 13 illustrates an operation diagram of a circuit during an amplification phase of a differential mode multiplying digital analog converter according to one embodiment.

In an embodiment, the first sample and hold unit may transfer the input voltage to a first one of the three Y-connected capacitors in the sampling phase; A second sample and hold unit connecting the first capacitor to the output terminal in the amplifying phase; And a third sample and hold unit configured to transfer the input voltage to the second capacitance unit in the sampling phase.

According to another embodiment, at least one of the first sample and hold part, the second sample and hold part, and the third sample and hold part may include a bootstrap switch.

According to another embodiment, a second capacitor different from the first capacitor among the second capacitor portion and the three Y-type connected capacitors is connected to the negative input of the OP AMP, and the positive input of the OP AMP may be grounded. Can be.

In addition, the three capacitors connected to the Y-type capacitor and the capacitor included in the second capacitor part may have the same capacitance.

According to another embodiment, the reference voltage may be determined according to the digital value of the previous step measured the input voltage in the previous step of the multiplying digital-to-analog converter.

According to the other side, the first positive capacitor unit for sampling and holding a positive input voltage in the sampling phase, and amplifies the difference between the input voltage and the first reference voltage in the amplifying phase and transfers it to a first output terminal; A second positive capacitor unit configured to sample and hold the positive input voltage in the sampling phase, and to transfer the voltage difference obtained by subtracting the first reference voltage from the positive input voltage in the amplifying phase to the first capacitor unit; ; A first sub-capacitor for sampling and holding a negative input voltage in the sampling phase and amplifying a difference between the negative input voltage and a second reference voltage in the amplifying phase and transferring the negative input voltage to a second output terminal; And a second unit configured to sample and hold the negative input voltage in the sampling phase, and to transfer the voltage difference obtained by subtracting the second reference voltage from the negative input voltage in the amplifying phase to the first unit capacitor. A differential mode multiplying digital-to-analog converter is provided that includes a capacitor portion, wherein the first positive capacitor portion includes three capacitors connected to a first Y type, and the first portion capacitor portion includes three capacitors connected to a second Y type. do.

In an embodiment, the first positive sample and hold unit may transfer the positive input voltage to a first positive capacitor among the three Y-type connected capacitors in the sampling phase; A second positive sample and hold unit connecting the first positive capacitor to the first output terminal in the amplifying phase; A third positive sample and hold unit transferring the positive input voltage to the second positive capacitance unit in the sampling phase; A first part sample and hold part configured to transfer the negative input voltage to a first part capacitor among the two Y-type connected capacitors in the sampling phase; A second part sample and hold part connecting the first part capacitor to the second output terminal in the amplifying phase; And a third part sample and hold part configured to transfer the negative input voltage to the second part capacitance part in the sampling phase.

According to another embodiment, the first tablet sample and hold part, the second tablet sample and hold part, the third tablet sample and hold part, the first part sample and hold part, the second part sample and hold part And at least one of the third unit sample and hold unit may include a bootstrap switch.

According to another embodiment, a second positive capacitor different from the first positive capacitor among the second positive capacitor part and the three Y-type connected capacitors is connected to the positive input of the OP AMP, and the second part A second part capacitor different from the first part capacitor among the capacitor part and the three Y-type connected capacitors may be connected to the negative input of the OP AMP.

According to yet another embodiment, the first reference voltage is an analog voltage level that is determined according to a first digital value of a previous step of measuring the positive input voltage in a previous step of the differential mode multiplying digital-to-analog converter. The second reference voltage may be an analog voltage level that is determined according to the second digital value of the previous step measured the negative input voltage in the previous step of the differential mode multiplying digital-analog converter.

According to yet another aspect, the method includes: holding and sampling an input voltage of a sampling phase in a second capacitor unit; Transferring, by the second capacitor unit, a voltage difference obtained by subtracting a reference voltage from the input voltage of an amplifying phase; Sampling and holding the input voltage of the sampling phase in the first capacitor unit; And amplifying and transmitting the difference between the input voltage and the reference voltage of the amplifying phase in the first capacitor part to an output terminal, wherein the first capacitor part includes three Y-connected capacitors. An analog conversion method is provided.

According to one embodiment, the step of transferring the input voltage of the sampling phase to a first one of the three Y-connected capacitors in the first sample and hold unit; And connecting the first capacitor of the amplifying phase to the output terminal in a second sample and hold unit, and transferring the input voltage of the sampling phase to the second capacitance unit in a third sample and hold unit. can do.

According to another embodiment, a second capacitor different from the first capacitor among the second capacitor unit and the three Y-type connected capacitors may be connected to the negative input of the OP AMP, and the positive input of the OP AMP may be grounded. have.

According to another embodiment, the method may further include determining the reference voltage according to the digital value of the previous step measured by the input voltage before the multiplying digital-to-analog converter.

Hereinafter, some embodiments will be described in detail with reference to the accompanying drawings. However, it is not limited or limited by these embodiments. Like reference numerals in the drawings denote like elements.

The terminology used in the following description has been selected as widely used as possible in the present invention in consideration of the functions in the present invention, but may vary according to the intention or custom of the person skilled in the art, the emergence of new technologies and the like.

In addition, in certain cases, there are terms arbitrarily selected by the applicant for the sake of understanding and / or convenience of description, and in this case, detailed meanings thereof will be described in the corresponding description. Therefore, the terms used in the following description should be understood based on the meanings of the terms and the contents throughout the specification, rather than simply the names of the terms.

Terms such as "first" and "second" are intended to distinguish one component from another component, and the scope of the present invention should not be limited by these terms. For example, the first component may be named a second component, and similarly, the second component may also be named a first component.

When a component is referred to as being "connected" to another component, it should be understood that there may be other components in between, although it may be directly connected to the other component. On the other hand, when a component is said to be "directly connected" to another component, it should be understood that there is no other component in between.

The multiplying digital-analog converter includes a first capacitor unit 110, a second capacitor unit 120, a first sample and hold unit 130, a second sample and hold unit 140, and a third sample and hold unit ( 150).

The first capacitor unit 110 may sample and hold an input voltage in a sampling phase, and amplify a difference between the input voltage and a reference voltage in an amplifying phase and transfer the same to an output terminal. The first capacitor unit 110 may include three capacitors Y-connected.

The second capacitor unit may sample and hold the input voltage in the sampling phase and transfer the voltage difference obtained by subtracting the reference voltage from the input voltage in the amplifying phase to the first capacitor unit 110.

The first sample and hold unit 130 may transfer the input voltage to a first one of the three Y-connected capacitors in the sampling phase. The second sample and hold unit 140 may connect the first capacitor to the output terminal in the amplifying phase. The third sample and hold unit 150 may transfer the input voltage to the second capacitance unit in the sampling phase. In addition, at least one of the first sample and hold unit 130, the second sample and hold unit 140, and the third sample and hold unit 150 may include a bootstrap switch.

A second capacitor different from the first capacitor among the second capacitor unit 120 and the three Y-connected capacitors may be connected to the negative input of the OP AMP, and the positive input of the OP AMP may be grounded.

In addition, the three capacitors connected to the Y-type capacitor and the capacitor included in the second capacitor unit 120 may have the same capacitance.

The reference voltage may be determined according to the digital value of the previous step measured the input voltage in the previous step of the multiplying digital-to-analog converter.

Pipeline analog-to-digital converters include multiple multiplying digital-to-analog converters that convert digital signals to analog signals, and multiple sub-flash analog-to-digital converters that convert analog signals to digital signals. Converter, a pipelined analog-to-digital converter for converting an input analog signal into a digital signal, and a digital correction logic for correcting an error of a digital signal output from a plurality of sub-flash analog-to-digital converters of the pipelined analog-to-digital converter. Logic).

The pipelined analog-to-digital converter may have a pipeline structure in which a multiplying digital analog converter and a sub-flash analog-to-digital converter form a single stage and connect a plurality of stages.

The multiplying digital to analog converter 300 is a digital to analog converter 302, a summer 303, an amplifier 304, a sample and hold circuit ( 305).

According to one embodiment, the input voltage is converted by the sub-flash analog-to-digital converter 301 into a 2.8-bit digital code. The sub flash digital analog converter 301 generates a corresponding reference voltage in the digital analog converter 302. The summer 303 performs a process of subtracting the reference voltage from the input voltage. The subtracted value is called the residue value and is amplified four times in the amplifier 304 and then sampled in the sample and circuit 305.

According to one embodiment, a conventional multiplying digital-to-analog converter 400 includes four

capacitors

401, 402, 403, 404, an amplifier, four sample and hold

circuits

411, 412, 413, 414 and an output voltage. Is composed of a sample and circuit 415 for sampling.

According to one embodiment, the multiplying analog-to-digital converter requires two non-overlapping clocks 430. The input voltage is applied through the input 424. In the sampling phase 431, the input signal is sampled, and in the amplifying paging 432, the reference voltage generated by the sub-flash digital-to-analog converter is subtracted and amplified from the input voltage. The amplified value is output through the output unit 425.

According to another embodiment, the multiplying digital-to-analog converter stores charges by receiving an input voltage at one end of the sampling phase 431, and stores charges by receiving the digital voltage D * VREF of the amplifier part in the amplifying phase 432.

Capacitors

401, 402, and 403, a capacitor 404 having one end of an input voltage stored at a sampling phase 431, storing charges, and one end of which is connected to an output node of an amplifying unit at an amplifying phase 432, and an amplifying phase. In operation 432, the amplifier amplifies a difference between the input voltage and the digital voltage D * VREF and outputs a residual voltage.

In addition, the other end of the capacitor (401, 402, 403, 404) is connected to the input node of the amplifier. According to the number of capacitors connected in parallel, a digital voltage (D * VREF) representing a digital code value of a digital signal of N (N is an integer of 3 or more) bits may be input. The

capacitors

401, 402, and 403 may be input with VREF, GND, and -VREF, respectively, according to the digital code value of the digital signal. Table 1 shows the subtracted results according to the digital code.

Table 1

Resolved digital code, D	Equivalent Value	Equivalent resultant reference voltage
000	-3/4	-3 / 4 * Vref
001	-2/4	-2 / 4 * Vref
010	-1/4	-1 / 4 * Vref
011	0	GND
100	+1/4	+ 1/4 * Vref
101	+2/4	+ 2/4 * Vref
110	+3/4	+ 3/4 * Vref

In the sampling phase 431, the sampling phase switch is turned on to operate as a short circuit, and the amplifying phase switch is turned off to operate as an open circuit, as shown in FIG. The amount of charge stored in the negative terminal of the amplifier is shown in [Equation 1].

Equation 1

In the amplifying phase 432, the amplifying phase switch is turned on to operate as a short circuit, and the sampling phase switch is turned off to operate as an open circuit, as shown in FIG. The amount of charge stored in the negative terminal of the amplifier is shown in [Equation 2].

Equation 2

[Equation 1] and [Equation 2] are the same according to the law of conservation of charge amount. In summary, Equation 3 is shown.

Equation 3

According to one embodiment, the multiplying digital analog converter 710 requires four

unit capacitors

701, 702, 703, 704 to form a closed loop of sampling and amplifier. The positive terminal of the two

capacitors

703 and 704 is connected to the amplifier, and this node is IN. The positive terminal of the two

capacitors

701 and 702 is connected to the negative terminal of the other capacitor 703, and this node is referred to as VX. Three

capacitors

701, 702, 703 form a Y connection. The negative terminal of capacitor 701 is always connected to ground. The multiplying analog-to-digital converter 710 requires two non-overlapping clocks 720. During the sampling phase 740, two

capacitors

702, 704 are connected to the input signal through sample and hold

circuits

711, 712. During the amplifying phase 750, the negative terminal of the capacitor 704 is connected to a reference voltage based on a code generated by the sub flash analog to digital converter. The negative terminal of the capacitor 702 is connected to the output terminal of the amplifier through the sample and hold circuit 713.

The multiplying digital-to-analog converter 710 may include a

first capacitor unit

701, 702, and 703, a second capacitor unit 704, a first sample and hold unit 711, a second sample and hold unit 713, The third sample and hold part 712 may be included.

The

first capacitors

701, 702, and 703 may sample and hold an input voltage in the sampling phase 740, and amplify the difference between the input voltage and the reference voltage in the amplifying phase 750 and transmit the amplified phase to the output terminal. The

first capacitor unit

701, 702, 703 may include three Y-

type capacitors

701, 702, 703.

The second capacitor unit 704 samples and holds the input voltage in the sampling phase 740, and subtracts the voltage difference obtained by subtracting the reference voltage from the input voltage in the amplifying phase 750. 701, 702, and 703.

The first sample and hold unit 711 may transfer the input voltage to the first capacitor 702 of the three Y-connected capacitors in the sampling phase 740. The second sample and hold unit 713 may connect the first capacitor to the output terminal in the amplifying phase 750. The third sample and hold unit 712 may transfer the input voltage to the second capacitance unit 704 in the sampling phase 740. In addition, at least one of the first sample and hold unit 711, the second sample and hold unit 713, and the third sample and hold unit 712 may include a bootstrap switch.

The second capacitor 703 that is different from the first capacitor 702 of the second capacitor unit 704 and the three Y-connected capacitors is connected to the negative input of the OP AMP, and the positive input of the OP AMP is Can be grounded.

The existing multiplying digital-to-analog converter 400 shown in FIG. 4 required four unit capacitors and five sample and hold circuits. The multiplying digital-to-analog converter 710 illustrated in FIG. 7 requires four unit capacitors as in FIG. 4, but only three sample and hold circuits are required.

Accordingly, the multiplying digital analog converter 710 requires about 40% less circuitry than the conventional multiplying digital analog converter 400 shown in FIG. Therefore, the clock distribution circuit, the silicon area and the low power operation can be expected.

According to one embodiment, the sampling phase switch is turned on to operate as a short circuit, and the amplifying phase switch is turned off to operate as an open circuit.

According to one embodiment, the sampling phase switch is turned on to ground the VX node. Therefore, the voltage at both ends of the capacitor 801 becomes 0V to act as a short circuit. Similarly, the VIN node goes to 0V when the sampling phase switch is turned on. The voltage across the capacitor 803 is 0V, which acts as a short circuit.

According to one embodiment, the applied voltage is applied to the

capacitors

802 and 804 to charge the amount of charge. During the sampling phase, the sample and hold circuit 713 is open, and the other sample and hold

circuits

711, 712 are shorted. The sample and hold

circuits

711 and 712 sample the applied voltage.

According to one embodiment, two

capacitors

802 and 804 are connected to the input signal and nodes VX and VIN are connected to ground. The charge stored in each node is as shown in [Equation 4] and [Equation 5].

Equation 4

Equation 5

Since the number of capacitors that sample and hold the initial VIN has been reduced from four to two during the operation of conventional multiplying digital-to-analog converters, input loading can be reduced and power required for VIN sampling can be reduced.

According to one embodiment, the amplifying phase switch is turned on to operate as a short circuit, and the sampling phase switch is turned off to operate as an open circuit.

According to one embodiment, the sampling phase switch is opened so that one end of

capacitors

901, 902, 903 is connected to the VX node. The

capacitors

901, 902, 903 form a Y coupling. The other end of the capacitor 901 is connected to ground and the other end of the capacitor 902 is connected to the sample and hold circuit 713. The other end of the capacitor 903 is connected to the VIN node. The sample and hold circuit 713 is connected to the output terminal 920 to form a feedback structure.

According to one embodiment, one end of the capacitor 904 is connected to the digital voltage 910, the other end is connected to the VIN node. The digital voltage is the value of (+ (3/2) * Vref or + Vref or + (1/2) * Vref or GND or-(1/2) * Vref or + Vref or-(3/2) * Vref) to be. The digital voltage is determined based on a code generated by the sub flash analog to digital converter.

According to one embodiment, the capacitor 904 is connected to a reference voltage and the capacitor 902 is connected to the output terminal of the amplifier. Charges stored in each node are as shown in [Equation 6] and [Equation 7].

Equation 6

Equation 7

[Equation 4] and [Equation 6] are the same, and [Equation 5] and [Equation 7] are the same, respectively. The nodes VX and OUT can be summarized as in [Equation 8] and [Equation 9].

Equation 8

Equation 9

[Equation 8] is substituted into [Equation 9] to summarize the same as [Equation 10].

Equation 10

And sum up [Equation 10] is the same as [Equation 11].

Equation 11

[Equation 11] can be seen that the same as [Equation 3]. Therefore, the existing multiplying digital analog converter can be replaced with the multiplying digital analog converter shown in FIG. 7. Compared with the existing multiplying digital-to-analog converters, the number of capacitors did not change, but the number of sample and hold circuits was reduced from five to three. The driving path of the clock distribution circuit is reduced, and the space of the clock distribution circuit can be reduced to 3/5. That is, sample and hold circuits typically use bootstrap switches, which are much larger in area than conventional transistors. For example, it may have an area of 20 times or more than a conventional transistor. In addition, the driving power consumption is large, and since the bootstrap switch must receive a negative input as well as a positive input, the driving power is also large.

Thus, by reducing the number of sample and hold circuits, the overall circuit area, power for driving the bootstrap switch, and the like can be reduced by about 40%.

Table 2 shows the subtraction values for the digital codes generated by the sub-flash analog-to-digital converters of the multiplying digital-to-analog converters.

TABLE 2

Resolved digital code, D	Equivalent Value	Equivalent resultant reference voltage
000	-3/2	-3 / 2 * Vref
001	-One	-1 * Vref
010	-1/2	-1 / 2 * Vref
011	0	GND
100	+1/2	+ 1/2 * Vref
101	+1	+ 1 * Vref
110	+3/2	+ 3/2 * Vref

According to one embodiment, the differential mode multiplying digital-to-analog converter may include an input voltage multiplying digital-to-analog converter 1001 and a surf flash analog-to-digital converter 1002. The differential mode input voltages VINP and VINN are applied to the multiplying digital analog converter 1001 and the sub flash analog digital converter 1002.

According to an embodiment, the sub-flash analog-to-digital converter 1002 receives a differential mode analog input voltage and converts it into a digital voltage to provide a digital value to the multi-flying digital-to-analog converter 1001.

According to one embodiment, the multiplying digital-to-analog converter 1001 subtracts an input signal and a digital value provided to the sub-flash analog-to-digital converter. The subtracted value is called the residue, and the residue is amplified. The amplified value is output from the output.

The differential mode multiplying digital analog converter 1001 requires about 40% less circuitry than conventional differential mode multiplying digital analog converters. Therefore, the clock distribution circuit, the silicon area and the low power operation can be expected.

According to one embodiment, the differential mode multiplying digital analog converter can be represented using two multiplying digital analog converters as described above. Multiplying digital-to-analog converters can be connected via a common mode voltage (VCM). A sampling phase turn-on switch that is turned on during the sampling phase may be connected to a node of a common mode voltage (VCM).

According to an embodiment, the differential mode multiplying digital-to-analog converter 1101 may include eight

capacitors

1111, 1112, 1113, 1114, 1121, 1122, 1123, and 1124, an amplifier 1100, a sample and hold

circuit

1115, 1116, 1117, 1125, 1126, and 1127), and may be configured as a switch. The

unit capacitors

1111, 1112, 1113, and 1114 sample and amplify the positive input voltage to generate a negative output voltage. Sub-flash analog-to-digital converters provide positive digital values.

According to another embodiment, the

unit capacitors

1121, 1122, 1123, and 1124 sample and amplify the negative input voltage to produce a positive output voltage. Sub-flash analog-to-digital converters provide negative digital values.

According to one embodiment, the amplifier 1100 amplifies the residue in a differential mode. Multiplying digital-to-analog converter 1101 requires two non-overlapping clocks 1102. During sampling paging 1130, the differential input voltage is sampled to capacitor pair {(1112, 1114)}, {(1122, 1124)}, respectively, and during the next amplification paging 1140, a pair of

sampling capacitors

1114, 1124 Reference voltage (+ (3/2) * Vref or + Vref or + (1/2) * Vref or GND or-(1/2) * Vref or -Vref or-based on the digital code of the sub-flash analog-to-digital converter (3/2) * Vref). The

other capacitor pairs

1112 and 1122 are connected to output nodes, respectively. During amplification paging, a residue is generated in which the reference voltage is subtracted from the input voltage, and the residue is amplified.

The first

positive capacitors

1111, 1112, and 1113 sample and hold a positive input voltage in the sampling phase 1130, and amplify the difference between the input voltage and the first reference voltage in the amplifying phase 1140 to output a first output. Can be delivered to the terminal. The second positive capacitor unit 1114 samples and holds the positive input voltage in the sampling phase 1130, and subtracts the first reference voltage from the positive input voltage in the amplifying phase 1140. The difference may be transferred to the first capacitor unit. The first

positive capacitor parts

1111, 1112, and 1113 may include three capacitors connected to a first Y-type capacitor.

The

first capacitor parts

1121, 1122, and 1123 sample and hold a negative input voltage in the sampling phase 1130, and amplify the difference between the negative input voltage and the second reference voltage in the amplification phase 1140. To the second output terminal. The second capacitor unit samples and holds the negative input voltage in the sampling phase 1130, and subtracts the voltage difference obtained by subtracting the second reference voltage from the negative input voltage in the amplifying phase 1140. It may be transferred to the

subcapacitors

1121, 1122, and 1123. The first

part capacitor parts

1121, 1122, and 1123 may include three capacitors connected to a second Y-type.

The first positive sample and hold 1115 may transfer the positive input voltage to the first positive capacitor among the three Y-connected capacitors in the sampling phase 1130. The second positive sample and hold 1117 may connect the first positive capacitor to the first output terminal in the amplifying phase 1140. The third positive sample and hold 1116 may transmit the positive input voltage to the second positive capacitance unit 1114 in the sampling phase 1130.

The first part sample and hold unit 1125 may transfer the negative input voltage to the first part capacitor among the three Y-connected capacitors in the sampling phase 1130. The second unit sample and hold unit 1127 may connect the first unit capacitor to the second output terminal in the amplifying phase 1140. The third part sample and hold 1126 may transfer the negative input voltage to the second part capacitance part 1124 in the sampling phase 1130.

According to one embodiment, the first tablet sample and hold 1115, the second tablet sample and hold 1117, the third tablet sample and hold 1116, and the first sample and hold ( At least one of the part, the second part sample and hold 1127, and the third part sample and hold 1126 may include a bootstrap switch.

In addition, a second positive capacitor 1113 which is different from the first positive capacitor 1112 among the second positive capacitor unit 1114 and the first Y-connected three capacitors is connected to the positive input of the OP AMP, The second part capacitor 1123 different from the first part capacitor 1122 among the second part capacitor part 1124 and the three Y-type connected capacitors may be connected to the negative input of the OP AMP.

The first reference voltage is an analog voltage level determined according to a first digital value of a previous step measured by the positive input voltage in a previous step of the differential mode multiplying digital-analog converter, and the second reference voltage is The negative input voltage may be an analog voltage level determined according to the second digital value of the previous step measured in the previous step of the differential mode multiplying digital-analog converter.

According to one embodiment, the sampling phase switch is turned on to connect the VPX node with a node of a common mode voltage (VCM). Therefore, the voltage across the capacitor 1211 becomes equal to the voltage of the VCM and acts as a short circuit. In addition, the VINP node is turned on by the sampling phase switch to be the same as the voltage of the VCM, which acts as a short circuit. The voltage across the capacitor 1213 acts as a short circuit to VCM. The applied voltage is applied to the

capacitors

1212 and 1214 to charge the amount of charge.

According to one embodiment, the sampling phase switch is turned on to connect the VNX node with a node of a common mode voltage (VCM). Therefore, the voltage at both ends of the capacitor 1221 is equal to the voltage of the VCM to act as a short circuit. The VINN node also turns on the sampling phase switch to equal the voltage at VCM and acts as a short circuit. The voltage across the capacitor 1223 acts as a short circuit to VCM. The applied voltage is charged to the

capacitors

1222 and 1224 to charge the amount of charge.

capacitors

1311, 1312, 1313 is connected to the VPX node. The

capacitors

1311, 1312, and 1313 form a Y coupling. The other end of the capacitor 1311 is connected to a node of a common mode voltage (VCM), and the capacitor 1312 is connected to a sample and hold circuit. The other end of the capacitor 1313 is connected to the VINP node. The sample and hold circuit connected to the capacitor 1312 is connected to the output terminal to form a feedback structure.

According to one embodiment, one end of the capacitor 1314 is connected with a digital voltage and the other end is connected with a VINP node. The digital voltage is the value of (+ (3/2) * Vref or + Vref or + (1/2) * Vref or GND or-(1/2) * Vref or + Vref or-(3/2) * Vref) to be. The digital voltage is determined based on a code generated in the sub flash analog to digital converter.

According to one embodiment, the sampling phase switch is opened so that one end of the capacitors 1321, 1322, 1323 are connected to the VNX node. The capacitors 1321, 1322, and 1323 form a Y-coupling. The other end of the capacitor 1321 is connected to a node of a common mode voltage (VCM), and the capacitor 1322 is connected to a sample and hold circuit. The other end of the capacitor 1323 is connected to the VINP node. The sample and hold circuit connected to the capacitor 1322 is connected to the output terminal to form a feedback structure.

According to one embodiment, one end of the capacitor 1324 is connected with a digital voltage and the other end is connected with a VINP node. The digital voltage is the value of (+ (3/2) * Vref or + Vref or + (1/2) * Vref or GND or-(1/2) * Vref or + Vref or-(3/2) * Vref) to be. The digital voltage is determined based on a code generated in the sub flash analog to digital converter.

The existing differential mode multiplying digital analog converter can be replaced with the differential mode multiplying digital analog converter shown in FIG. Compared with conventional differential mode multiplying digital-to-analog converters, the number of capacitors did not change, but the number of sample and hold circuits was reduced from ten to six. The driving path of the clock distribution circuit is reduced, and the space of the clock distribution circuit can be reduced by 3/5. That is, the sample and hold circuit usually uses a bootstrap switch, which has a larger area than a conventional transistor. Much bigger. For example, it may have an area of 20 times or more than a conventional transistor. In addition, the driving power consumption is large, and since the bootstrap switch must receive a negative input as well as a positive input, the driving power is also large.

The system described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the systems and components described in the embodiments may include, for example, processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable arrays (FPAs), It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other system capable of executing and responding to instructions. The processing system may run an operating system (OS) and one or more software applications running on the operating system. The processing system may also access, store, manipulate, process and generate data in response to the execution of the software. For ease of understanding, one processing system may be described as being used, but one of ordinary skill in the art will appreciate that the processing system includes a plurality of processing elements and / or multiple types of processing elements. It can be seen that it may include. For example, the processing system may include a plurality of processors or one processor and one controller. In addition, other processing configurations are possible, such as parallel processors.

The software may include a computer program, code, instructions, or a combination of one or more of the above, and configure the processing device to operate as desired, or process it independently or collectively. You can command the device. Software and / or data may be any type of machine, component, physical device, virtual equipment, computer storage medium or system for the purpose of interpreting or providing instructions or data to the processing system. Or may be permanently or temporarily embodied in a signal wave to be transmitted. The software may be distributed over networked computer systems so that they may be stored or executed in a distributed manner. Software and data may be stored on one or more computer readable recording media.

The method according to the embodiment may be embodied in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the media may be those specially designed and constructed for the purposes of the embodiments, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

Although the embodiments have been described by the limited embodiments and the drawings as described above, various modifications and variations are possible to those skilled in the art from the above description. For example, the described techniques may be performed in a different order than the described method, and / or components of the described systems, structures, devices, circuits, etc. may be combined or combined in a different form than the described method, or other components. Or even if replaced or substituted by equivalents, an appropriate result can be achieved.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

Claims

A first capacitor unit for sampling and holding an input voltage in a sampling phase and amplifying a difference between the input voltage and a reference voltage in an amplifying phase and transferring the same to an output terminal; And

A second capacitor unit configured to sample and hold the input voltage in the sampling phase, and to transfer the voltage difference obtained by subtracting the reference voltage from the input voltage in the amplifying phase to the first capacitor unit;

Including,

And the first capacitor portion comprises three Y-connected capacitors.
The method of claim 1,

A first sample and hold unit configured to transfer the input voltage to a first one of the three Y-connected capacitors in the sampling phase;

A second sample and hold unit connecting the first capacitor to the output terminal in the amplifying phase; And

A third sample and hold unit transferring the input voltage to the second capacitance unit in the sampling phase

Multi-flying digital-to-analog converter further comprising.
The method of claim 2,

And at least one of the first sample and hold section, the second sample and hold section, and the third sample and hold section comprises a bootstrap switch.
The method of claim 2,

And a second capacitor different from the first capacitor among the second capacitor unit and the three Y-connected capacitors is connected to the negative input of the OP AMP, and the positive input of the OP AMP is grounded.
The method of claim 1,

And the capacitors included in the Y-connected three capacitors and the second capacitor part have the same capacitance.
The method of claim 1,

And the reference voltage is an analog voltage level that is determined according to the digital value of the previous step measured the input voltage in a previous step of the multiplying digital-to-analog converter.
A first positive capacitor unit configured to sample and hold a positive input voltage in a sampling phase, and amplify a difference between the input voltage and the first reference voltage in an amplifying phase and transfer the same to a first output terminal;

A second positive capacitor unit configured to sample and hold the positive input voltage in the sampling phase, and to transfer the voltage difference obtained by subtracting the first reference voltage from the positive input voltage in the amplifying phase to the first capacitor unit; ;

A first sub-capacitor for sampling and holding a negative input voltage in the sampling phase and amplifying a difference between the negative input voltage and a second reference voltage in the amplifying phase and transferring the negative input voltage to a second output terminal; And

A second part capacitor configured to sample and hold the negative input voltage in the sampling phase, and to transfer the voltage difference obtained by subtracting the second reference voltage from the negative input voltage in the amplifying phase to the first part capacitor part; part

Including,

And the first positive capacitor portion comprises three first Y-connected capacitors, and the first sub capacitor portion comprises three second Y-type connected capacitors.
The method of claim 7, wherein

A first positive sample and hold unit configured to transfer the positive input voltage to a first positive capacitor among the three Y-connected capacitors in the sampling phase;

A second positive sample and hold unit connecting the first positive capacitor to the first output terminal in the amplifying phase;

A third positive sample and hold unit transferring the positive input voltage to the second positive capacitance unit in the sampling phase;

A first part sample and hold part configured to transfer the negative input voltage to a first part capacitor among the two Y-type connected capacitors in the sampling phase;

A second part sample and hold part connecting the first part capacitor to the second output terminal in the amplifying phase; And

A third part sample and hold part transferring the negative input voltage to the second part capacitance part in the sampling phase;

Differential mode multiplying digital-to-analog converter further comprising.
The method of claim 8,

The first tablet sample and hold part, the second tablet sample and hold part, the third tablet sample and hold part, the first part sample and hold part, the second part sample and hold part, and the third part sample And at least one of the end-hold portions includes a bootstrap switch.
The method of claim 8,

A second positive capacitor different from the first positive capacitor of the second positive capacitor unit and the three Y-type connected three capacitors is connected to the positive input of the OP AMP,

And a second part capacitor different from the first part capacitor of the second part capacitor part and the three Y-type connected capacitors is connected to the negative input of the OP AMP.
The method of claim 7, wherein

The first reference voltage is an analog voltage level that is determined according to a first digital value of a previous step measured the positive input voltage in a previous step of the differential mode multiplying digital-to-analog converter,

And the second reference voltage is an analog voltage level determined by the second digital value of the previous step measured the negative input voltage in a previous step of the differential mode multiplying digital-analog converter.
Sampling and holding the input voltage of the sampling phase in the second capacitor unit;

Transferring, by the second capacitor unit, a voltage difference obtained by subtracting a reference voltage from the input voltage of an amplifying phase;

Sampling and holding the input voltage of the sampling phase in the first capacitor unit; And

Amplifying the difference between the input voltage of the amplifying phase and the reference voltage at the first capacitor unit and transferring the difference to the output terminal;

Including,

And the first capacitor portion comprises three Y-type connected capacitors.
The method of claim 12,

Transferring the input voltage of the sampling phase to a first one of the three Y-connected capacitors in a first sample and hold unit; And

Connecting the first capacitor of the amplifying phase to the output terminal in a second sample and hold section, and transferring the input voltage of the sampling phase to the second capacitance section in a third sample and hold section;

Multi-flying digital to analog conversion method further comprising.
The method of claim 13,

The second capacitor unit and the second capacitor of the three Y-connected capacitors different from the first capacitor is connected to the negative input of the OP AMP, the positive input of the OP AMP is a multiply digital-to-analog conversion method .
The method of claim 12,

Determining the reference voltage according to the digital value of the previous step measured the input voltage in a previous step of the multiplying digital-to-analog converter

Multi-flying digital to analog conversion method further comprising.