WO2020235731A1

WO2020235731A1 - Output driver of display device

Info

Publication number: WO2020235731A1
Application number: PCT/KR2019/006390
Authority: WO
Inventors: 이민재
Original assignee: 주식회사 에이코닉
Priority date: 2019-05-21
Filing date: 2019-05-28
Publication date: 2020-11-26
Also published as: KR102112328B1; CN113678188A; CN113678188B

Abstract

An output driver of a display device according to an embodiment of the present application comprises: a digital-to-analog converter which generates a coarse voltage and a fine voltage; a control unit which alternately charges first and second capacitors on the basis of the voltage difference between the coarse voltage and the fine voltage; and an amplifying unit which alternately receives the respective charging voltages charged in the first and second capacitors, and continuously outputs an output voltage. The control unit outputs a second charging voltage charged in the second capacitor to an output node of the amplifying unit during a first charging period for charging a first charging voltage in the first capacitor.

Description

Display device output driver

The present application relates to an output driver of a display device.

In recent years, as the size and resolution of display panels increase, there is a demand for flexible gamma curve setting and increasing color depth. In order to meet this demand, an output driver occupying a larger area must be used in a driving circuit of a display device.

In addition, the capacity of the load resistor and the load capacitor connected to the output driver increases, and the target voltage of the image signal increases accordingly. In particular, due to an increase in load resistance and load capacity, the slew rate of the amplifier of the output driver may decrease.

Accordingly, a pre-emphasis operation for increasing the slew rate of the amplifier is possible, and an output driver of the display device capable of reducing the decoding time and circuit area is required.

An object of the present application is to provide an output driver of a display device capable of high-speed driving by performing a sampling operation and a driving operation in parallel.

An object of the present application is to provide an output driver of a display device capable of a pre-emphasis operation.

An object of the present application is to provide an output driver of a display device that can be implemented in a small area while supporting high resolution.

An object of the present application is to provide an output driver of a display device capable of reducing an inter-channel deviation through at least two-step decoding.

An output driver according to an exemplary embodiment of the present application includes: a digital-analog converter generating a first voltage and a second voltage different from the first voltage; A controller that alternately charges the first and second capacitors based on a voltage difference between the first voltage and the second voltage; And an amplifying unit that alternately receives and outputs each charging voltage charged to the first and second capacitors, wherein the control unit comprises: during a first charging time for charging the first charging voltage to the first capacitor, the first 2 The second charging voltage charged in the capacitor is output to the output node of the amplifier.

In an embodiment, the controller connects one side of the second capacitor to an inverting input terminal of the amplification unit and the other side of the second capacitor to the output node during the first charging time.

In an embodiment, the control unit outputs the charging voltage charged in the first capacitor to the output node during a second charging time when the second capacitor is charged.

In an embodiment, the controller connects one side of the first capacitor to an inverting input terminal of the amplification unit and the other side of the first capacitor to the output node during the second charging time.

In an embodiment, the amplification unit receives the second charging voltage through the inverting input terminal, receives a preset middle voltage through the non-inversion input terminal, and outputs it through the output node.

In an embodiment, the controller electrically connects the non-inverting input terminal and the inverting input terminal to each other between the first charging time and the second charging time.

In an embodiment, it further includes a delay unit delaying the time that the output voltage is output to the display panel for a predetermined time.

In an embodiment, the control unit includes a pre-emphasis control unit for switching the middle voltage applied to the non-inverting input terminal to one of the first voltage and the second voltage at each of the first and second charging times. Include more.

An output driver according to an exemplary embodiment of the present application includes: a digital-analog converter generating a first voltage and a second voltage different from the first voltage; A controller for sequentially charging a charging voltage to the first to fourth capacitors based on a voltage difference between the first voltage and the second voltage; And an amplifying unit configured to output a charging voltage charged in the first to fourth capacitors to an output node, wherein the control unit connects the second capacitor to the output node of the amplifying unit while charging the first capacitor, , While charging the third capacitor, the fourth capacitor is connected to the output node of the amplification unit.

In an embodiment, the control unit, while charging the second capacitor, connects the third capacitor to the output node of the amplification unit, and while charging the fourth capacitor, the first capacitor is output to the amplification unit Connect to the node.

The output driver of the display device according to the exemplary embodiment of the present application performs a sampling operation and a driving operation in parallel, thereby reducing time consumed for decoding and driving at a high speed.

The output driver of the display device according to the exemplary embodiment of the present application supports a pre-emphasis operation and may increase a slew rate according to a distance between the data driver and the display panel.

The output driver of the display device according to the exemplary embodiment of the present application connects one end of the capacitor to an inverting input terminal of an amplifier operating as a virtual ground, thereby reducing an effect of parasitic components of the capacitors.

The output driver of the display device according to the exemplary embodiment of the present application may implement an output voltage corresponding to a desired driving voltage despite variations between different first and second capacitors.

The output driver of the display device according to the exemplary embodiment of the present application stores a desired data voltage in one capacitor through a course decoder and a fine decoder, and outputs a data voltage in a pixel of the display device through an amplifier. In this case, since the data voltage is stored in one capacitor, there is no error in the data voltage within one channel. Accordingly, an output deviation in a driver including a plurality of channels can be reduced.

1 is a block diagram of an output driver of a display device according to an exemplary embodiment of the present application.

2 is a circuit diagram specifically showing an output driver of the display device of FIG. 1.

3 is a diagram illustrating an operation timing of the control unit of FIG. 2.

4 is a first equivalent circuit diagram of a control unit in the reset section of FIG. 3.

5 is a second equivalent circuit diagram of the control unit at the first charging time of FIG. 3.

6 is a third equivalent circuit diagram of the control unit at the first charging time of FIG. 3.

7 is a circuit diagram according to another embodiment of the control unit of FIG. 1.

8 is a diagram illustrating an operation timing of the delay unit of FIG. 7.

9 is a circuit diagram according to another embodiment of the control unit of FIG. 1.

10 is a diagram showing an operation timing of the pre-emphasis control unit of FIG. 9.

11 is another embodiment of the pre-emphasis control unit of FIG. 10.

12A is another embodiment of the pre-emphasis control unit of FIG. 10.

12B is another embodiment of the pre-emphasis control unit of FIG. 10.

13 is a circuit diagram showing another embodiment of the control unit of FIG. 2.

14 is a diagram illustrating an operation timing of the control unit of FIG. 13.

15 is a first equivalent circuit diagram of a control unit in the first charging section of FIG. 14.

16 is a second equivalent circuit diagram of the control unit in the second charging section of FIG. 14.

17 is a third equivalent circuit diagram of the control unit in the third charging section of FIG. 14.

18 is a fourth equivalent circuit diagram of the control unit in the fourth charging section of FIG. 14.

19 is a diagram illustrating a display device to which an output driver is applied.

20 is a diagram illustrating an example of an output driver to which a control unit and an amplification unit described in FIGS. 1 to 18 are applied.

21 is a diagram showing the DAC of FIG. 20 in more detail.

An output driver according to an exemplary embodiment of the present application includes: a digital-analog converter generating a first voltage and a second voltage different from the first voltage; A controller that alternately charges the first and second capacitors based on a voltage difference between the first voltage and the second voltage; And an amplifying unit that alternately receives and outputs each charging voltage charged to the first and second capacitors, wherein the control unit comprises: during a first charging time for charging the first charging voltage to the first capacitor, the first 2 The second charging voltage charged in the capacitor is output to the output node of the amplifier. The output driver of the display device according to the exemplary embodiment of the present application performs a sampling operation and a driving operation in parallel, thereby reducing time consumed for decoding and driving at a high speed.

Specific structural or functional descriptions of the embodiments according to the concept of the present application disclosed in the present specification are exemplified only for the purpose of describing the embodiments according to the concept of the present application, and the embodiments according to the concept of the present application are It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present application can apply various changes and have various forms, the embodiments will be illustrated in the drawings and described in detail in the present specification. However, this is not intended to limit the embodiments according to the concept of the present application to specific disclosed forms, and includes all changes, equivalents, or substitutes included in the spirit and scope of the present application.

Terms such as first or second may be used to describe various elements, but the elements should not be limited by the terms. The terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of the rights according to the concept of the present application, the first component may be named as the second component, and similarly The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

The terms used in this specification are only used to describe specific embodiments, and are not intended to limit the present application. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate the presence of implemented features, numbers, steps, actions, components, parts, or a combination thereof, but one or more other features or numbers It is to be understood that the possibility of addition or presence of, steps, actions, components, parts, or combinations thereof is not preliminarily excluded.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this specification. Does not.

Hereinafter, the present application will be described in detail by describing a preferred embodiment of the present application with reference to the accompanying drawings.

1 is a block diagram of an output driver 500 of a display device according to an exemplary embodiment of the present application.

Referring to FIG. 1, the output driver 500 may include a digital-analog converter 100, a control unit 200, and an amplification unit 300.

First, the digital-analog converter 100 may generate a coarse voltage V _COARSE and a fine voltage V _FINE .

Here, the course voltage (V _COARSE ) is voltages corresponding to a wide range of voltages controlled in units of a predetermined voltage level or more, and the fine voltage (V _FINE ) is at any one of the voltages of the course voltage (V _COARSE ). , It may be voltages corresponding to a voltage section of a detailed range that is adjusted in units less than a preset voltage level. For example, the course voltage (V _COARSE ) corresponds to any one voltage (eg, 3V) among voltages (eg, 0V to 10V) controlled in units of 1V voltage, and the fine voltage (V _FINE ) corresponds to the course voltage ( V _COARSE ) may correspond to a voltage (eg, 0.5V) adjusted in 0.1V units from 3V.

Hereinafter, the digital-analog converter 100 will be described in more detail with reference to FIG. 20.

Next, the control unit 200 based on the voltage difference (V _COARSE -V _FINE ) between the coarse voltage (V _COARSE ) and the fine voltage (V _FINE ) generated through the digital-analog converter 100, the first and The

second capacitors

201 and 202 may be charged alternately. Here, a course voltage V _COARSE may be applied to one side of the first and

second capacitors

201 and 202, and a fine voltage V _FINE may be applied to the other side.

Specifically, the control unit 200 is based on the voltage difference (V _COARSE -V _FINE ) between the course voltage (V _COARSE ) and the fine voltage (V _FINE ), during the first charging time (H1), the first capacitor 201 ) May be charged with the first charging voltage V _C1 , and the second capacitor 202 may be charged with the second charging voltage V _C2 during the second charging time H2. For example, as shown in FIG. 3, a first charging time H1 for charging the first capacitor 201 and a second charging time H2 for charging the second capacitor 202 may be complementary to each other. have.

Next, the amplifying unit 300 is alternately applied to each of the charging voltages V _C1 and V _C2 charged to the first and

second capacitors

201 and 202, and continuously outputs the output voltage V _OUT . I can. Specifically, the amplification unit 300 receives the second charging voltage V _C2 from the controller 200 through the inverting input terminal (-) during the first charging time H1, and the second charging time H2 During the period, the first charging voltage V _C1 may be applied from the controller 200 through the inverting input terminal (-).

In addition, the amplification unit 300 may receive a preset middle voltage V _MID through a non-inverting input terminal (+). Here, the preset middle voltage V _MID may be a voltage smaller than the coarse voltage V _COARSE and the fine voltage V _FINE .

At this time, the amplification unit 300 includes a preset middle voltage (V _MID ) applied through the non-inverting input terminal (+) and each charging voltage (V _C1 , V _C2 ) alternately applied through the inverting input terminal (-). ), a first output voltage VOUT1 and a second output voltage VOUT2 may be alternately generated. That is, the amplification unit 300 may continuously generate an output voltage V _OUT according to each charging voltage V _C1 and V _C2 alternately applied through the inverting input terminal (-).

In an embodiment according to the technical idea of the present application, the control unit 200 includes a second charging voltage V charged in the second capacitor 202 during the first charging time H1 when the first capacitor 201 is charged. _C2 ) may be output to the output node 301 of the amplifying unit 300. In addition, the control unit 200 outputs the first charging voltage V _C1 charged in the first capacitor 201 during the second charging time H2 in which the second capacitor 202 is charged. It can be output to the node 301.

Accordingly, the control unit 200 performs a sampling operation for charging the first capacitor 201 and a second charging voltage (eg, V _C2 ) charged in the second capacitor 202 to the output node 301 of the amplifying unit 300. By performing the driving operation output to) in parallel, it is possible to drive at high speed and reduce the area of a circuit used for decoding.

FIG. 2 is a circuit diagram specifically showing the control unit 200 of FIG. 1, FIG. 3 is a diagram showing an operation timing of the control unit 200 of FIG. 2, and FIG. 4 is a reset section RST of FIG. Is a first equivalent circuit diagram of the controller 200 of FIG. 5 is a second equivalent circuit diagram of the controller 200 at the first charging time H1 of FIG. 3, and FIG. 6 is a second charging time of FIG. It is a 3rd equivalent circuit diagram of the control part 200 in (H2).

Referring to FIG. 2, the controller 200 includes first and

second capacitors

201 and 202, first to sixth main switches SW1 to SW6, first and second sub switches 211_1 and 211_2, and Reset switches SWrst_1 to SWrst_3 may be included.

First, in the period T0 to T1, when the reset switches SWrst_1 to SWrst_3 are switched according to the reset signal RST, the controller 200 may form a first equivalent circuit, as shown in FIG. 4. .

Specifically, the reset switches SWrst_1 to SWrst_3 may reset the parasitic capacitance of the capacitor based on the reset signal RST. The reset signal RST may be a control signal for resetting the parasitic capacitance of at least one of the first and

second capacitors

201 and 202.

For example, as shown in FIG. 4, among the reset switches SWrst_1 to SWrst_3, the first reset switch SWrst_1 is based on the reset signal RST, and the other side of the first capacitor 201 is a preset middle By connecting to the voltage V _MID , the parasitic capacitance of the node Vy connected to the first capacitor 201 may be reset to the middle voltage V _MID .

In addition, the second reset switch SWrst_2 connects the other side of the second capacitor 202 to a preset middle voltage V _MID based on the reset signal RST, so that Vx connected to the second capacitor 202 The parasitic capacitance of the node can be reset to the middle voltage (V _MID ). In addition, the third reset switch SWrst_3 connects the inverting input terminal (-) of the amplifying unit 300 to the middle voltage V _MID through the non-inverting input terminal (+) based on the reset signal RST. I can.

Next, in the period T1 to T2 (H1), the first to third main switches SW1 to SW3 and the first sub switch 211_1 are the first main control signal Φ1 and the first sub control signal Φ1e. In the case of switching according to, the controller 200 may form a second equivalent circuit, as shown in FIG. 5.

Specifically, in the period T1 to T2 (H1), the first main switch SW1 and the first sub switch 211_1 are based on the first main control signal Φ1 and the first sub-control signal Φ1e. The charging voltage V _C1 may be generated by applying a voltage difference V _COARSE -V _FINE between the voltage V _COARSE and the fine voltage V _FINE to the first capacitor 201.

Here, the first main control signal Φ1 and the first sub-control signal Φ1e are control signals for charging the first capacitor 201, and for easy charging of the first capacitor 201, the first The time during which the sub control signal Φ1e is activated may be less than the first main control signal Φ1e.

As shown in FIG. 5, in the period T1 to T2 (H1), the first main switch SW1 connects one side of the first capacitor 201 to the course voltage node based on the first main control signal Φ1. 111_1). Also, in the period T1 to T2 (H1), the first sub-switch 211_1 may connect the other side of the first capacitor 201 to the fine voltage node 121_1 based on the first sub-control signal Φ1e. . That is, in the period T1 to T2 (H1), the first main switch (SW1) and the first sub-switch (211_1) to apply the course voltage (V _COARSE ) and the fine voltage (V _FINE ) to the first capacitor 201. I can.

At this time, in the period T1 to T2 (H1), the second and third main switches SW2 and SW3 are based on the first main control signal Φ1, and the second charging voltage charged in the second capacitor 202 ( V _C2 ) may be applied to the inverting input terminal (-) of the amplifying unit 300 and the output node 301 of the amplifying unit 300.

The first main control signal Φ1 according to the embodiment converts the second charging voltage VC2 charged in the second capacitor 202 into an inverted input terminal (-) of the amplifying unit 300 and an output of the amplifying unit 300 It may be a control signal to be applied to the node 301.

As shown in FIG. 5, the second main switch SW2 connects one side of the second capacitor 202 to the inverting input terminal (-) of the amplifying unit 300 based on the first main control signal Φ1. I can connect. Further, the third main switch SW3 may connect the other side of the second capacitor 202 to the output node 301 based on the first main control signal Φ1.

Accordingly, in the period T1 to T2 (H1), the amplification unit 300 outputs the second charging voltage V _C2 and the first output voltage V _OUT1 for the preset middle voltage V _MID at the output node 301 You can print it through Here, the first output voltage V _OUT1 is a sum (Vcoarse-) between the second charging voltage V _C2 applied to the amplifying unit 300 and a preset middle voltage V _MID applied to the amplifying unit 300. Vfine+Vmid). That is, in the period T1 to T2 (H1), the first main switch SW1 and the first sub switch 211_1 charge the first capacitor 201, and the second main switch SW2 and the third main switch ( 210_3) may output the first output voltage V _OUT1 through the amplifying unit 300.

Then, in the period T2 to T3, the reset switches SWrst_1 to SWrst_3 are, similar to the period T0 to T1, based on the reset signal RST, at least one of the first and

second capacitors

201 and 202 It is possible to reset the parasitic capacitance of the capacitor. For example, by switching the reset switches SWrst_1 to SWrst_3 according to the reset signal RST, an equivalent circuit identical to the first equivalent circuit of FIG. 4 may be formed.

Then, in the period T3 to T4 (H2), the fourth to sixth main switches SW4 to SW6 and the second sub-switch 211_2 are the second main control signal Φ2 and the second sub-control signal Φ2e. In the case of switching according to, the control unit 200 may form a third equivalent circuit, as shown in FIG. 6.

Specifically, the fourth main switch SW4 and the second sub-switch 211_2 are based on the second main control signal Φ2 and the second sub-control signal Φ2e, the course voltage V _COARSE and the fine voltage ( A voltage difference V _COARSE -V _FINE between V _FINE ) may be applied to the second capacitor 202 to generate a charging voltage V _C2 .

Here, the second main control signal Φ2 and the second sub-control signal Φ2e are control signals for charging the second capacitor 202, and for easy charging of the second capacitor 202, the second The time during which the sub control signal Φ2e is activated may be less than the second main control signal Φ2.

As shown in Fig. 6, in the period T3 to T4 (H2), the fourth main switch (SW4) is based on the second main control signal (Φ2), one side of the second capacitor 202 is a course voltage node ( 111_1). In addition, in the period T3 to T4, the second sub switch 211_2 may connect the other side of the second capacitor 202 to the fine voltage node 121_1 based on the second sub control signal Φ2e. That is, in the period T3 to T4, the fourth main switch SW4 and the second sub switch 211_2 apply a course voltage V _COARSE and a fine voltage V _FINE to both sides of the second capacitor 202, The charging voltage V _C2 can be charged.

At this time, in the period T3 to T4 (H2), the fifth and sixth main switches (SW5, SW6) are based on the second main control signal (Φ2), based on the first charging voltage ( V _C1 ) may be output to the output node 301 of the amplifying unit 300.

The second main control signal Φ2 according to the embodiment may be a control signal for outputting the first charging voltage V _C1 charged in the first capacitor 201 to the output node 301 of the amplifying unit 300. .

Specifically, the fifth main switch SW5 may connect one side of the first capacitor 201 to the inverting input terminal (-) of the amplifying unit 300 based on the second main control signal Φ2. Further, the sixth main switch SW6 may connect the other side of the first capacitor 201 to the output node 301 based on the second main control signal Φ2. Accordingly, in the period T3 to T4 (H2), the amplification unit 300 outputs the first charging voltage V _C1 and the second output voltage V _OUT2 for the preset middle voltage V _MID at the output node 301 You can print it through Here, the second output voltage V _OUT2 is a sum (Vcoarse-) between the first charging voltage V _C1 applied to the amplifying unit 300 and a preset middle voltage V _MID applied to the amplifying unit 300. Vfine+Vmid). That is, in the period T3 to T4, the fourth main switch SW4 and the second sub switch 211_2 charge the second capacitor 202, and at the same time, the fifth main switch SW5 and the sixth main switch SW6 ) May output the second output voltage V _OUT2 through the amplifier 300.

Then, in the period T4 to T5, the reset switches SWrst_1 to SWrst_3 are similar to the period T0 to T1, based on the reset signal RST, at least one of the first and

second capacitors

201 and 202 The parasitic capacitance of can be reset.

Then, in the period T5 to T6 (H1), the first main switch (SW_1) and the first sub-switch (211_1) is based on the first main control signal (Φ1) and the first sub-control signal (Φ1e), One charging voltage V _C1 may be charged in the first capacitor 201. At the same time, the second and third main switches SW2 and SW3 may output the first output voltage V _OUT1 through the amplifier 300 based on the first main control signal Φ1.

FIG. 7 is a circuit diagram of the controller 200 of FIG. 1 according to another exemplary embodiment, and FIG. 8 is a diagram illustrating an operation timing of the delay unit 240 of FIG. 7.

7 and 8, the controller 200 includes first and

second capacitors

201 and 202, first to sixth main switches SW1 to SW6, and first and second sub switches 211_1, 211_2), reset switches SWrst_1 to SWrst_3, and a delay unit 240 may be included.

The circuit of FIG. 7 is similar to the circuit of FIG. 2. Thus, for brief description, the first and

second capacitors

201 and 202, the first to sixth main switches 210_1 to 210_6, the first and second capacitors of the same reference numerals described in FIGS. 1 to 6 Redundant descriptions of the sub switches 211_1 and 211_2 and the reset switches 230_1 to 230_3 will be omitted.

The delay unit 240 may delay an output time for the first output voltage V _OUT1 or the second output voltage V _OUT2 output to the display panel 700 through the amplification unit 300 for a predetermined time.

More specifically, as shown in FIG. 8, the delay unit 240 may electrically connect the output node 301 of the amplification unit 300 and the display panel 700 to each other based on the delay signal HIGH_Z_SW. have. Here, the delay signal (HIGH_Z_SW) is the activation of the first and second switching signals (Φ1, Φ2) in order to delay the output time for the first output voltage (V _OUT1 ) or the second output voltage (V _OUT2 ) for a certain time. It may be a signal that is activated at each predetermined point in the section.

For example, as shown in FIG. 8, the delay unit 240 includes the output node 301 and the display panel of the amplifying unit 300 until a certain point in time (eg, T1.5) in the period T1 to T2. 700) may be electrically shorted, and the output node 301 of the amplifying unit 300 and the display panel 700 may be electrically connected to each other from the predetermined point in time (eg, T1.5) to the T2 section.

That is, the delay unit 240 is in response to the delay signal (HIGH_Z_SW) that is activated at a predetermined time in the activation period of the first and second switching signals (Φ1, φ2), the first output output through the amplifier 300 The voltage V _OUT1 or the second output voltage V _OUT2 may be output to the display panel 700.

9 to 12 are views showing another embodiment of the control unit 200 of FIG. 1. For example, unlike the circuits described in FIGS. 2 to 8, the circuits of FIGS. 9 to 12 may further support a pre-emphasis operation.

Specifically, FIG. 9 is a circuit diagram showing the control unit 200 including the pre-emphasis control unit 250, and Fig. 10 is a view showing the operation timing of the pre-emphasis control unit 250 of Fig. 9. In addition, FIG. 11 is another embodiment of the pre-emphasis control unit 250 of FIG. 9, and FIG. 12 is another embodiment of the pre-emphasis control unit 250 of FIG. 9.

First, referring to FIGS. 9 and 10, the controller 200 includes first and

second capacitors

201 and 202, first to sixth main switches 210_1 to 210_6, and first and second sub switches ( 211_1 and 211_2), reset switches 230_1 to 230_3, and a pre-emphasis control unit 250 may be included.

Hereinafter, the first and

second capacitors

201 and 202, the first to sixth main switches 210_1 to 210_6, the first and second sub switches 211_1, having the same reference numerals described in FIGS. 2 to 7, 211_2) and the redundant descriptions of the reset switches 230_1 to 230_3 will be omitted.

The pre-emphasis control unit 250 according to the embodiment may include a first pre-emphasis switch 251 and a second pre-emphasis switch 252.

According to an embodiment, the pre-emphasis control unit 250 is a non-inverting input terminal (+) of the amplifying unit 300 for pre-emphasis operation for the first and second output voltages V _OUT1 and V _OUT2 . It is possible to switch the preset middle voltage V _MID applied to the course voltage V _COARSE .

Specifically, the first pre-emphasis switch 251 may electrically connect the non-inverting input terminal (+) of the amplifying unit 300 to the course voltage node 111_1 based on the pre-emphasis control signal PREM_ON. have. Here, the pre-emphasis control signal PREM_ON may be a signal activated for a predetermined time according to the reset signal RST. In this case, the second pre-emphasis switch 252 may short-circuit the non-inverting input terminal (+) of the amplifying unit 300 and the middle voltage node 250_1 to each other based on the pre-emphasis control signal PREM_ON. .

Then, the second pre-emphasis switch 252 is based on the pre-emphasis inverted signal (/PREM_ON), the non-inverting input terminal (+) of the amplifying unit 300 is applied to the middle voltage (V _MID ). It can be electrically connected to the voltage node 250_1. Here, the pre-emphasis inversion signal /PREM_ON may be an inversion signal for the pre-emphasis control signal PREM_ON. At this time, the first pre-emphasis switch 251 may short-circuit the non-inverting input terminal (+) of the amplifying unit 300 and the middle voltage node 250_1 to each other based on the pre-emphasis inversion signal (/PREM_ON). have.

As shown in FIG. 9, the pre-emphasis control unit 250 may apply the course voltage V _COARSE to the non-inverting input terminal (+) based on the pre-emphasis control signal PREM_ON. Accordingly, the amplification unit 300 may output the first pre-emphasis voltage V _PREOUT1 . Here, the first pre-emphasis voltage V _PREOUT1 may be a voltage greater than the second output voltage V _OUT2 (V _COARSE -V _FINE +V _COARSE ).

Meanwhile, the above description is exemplary, and the technical idea of the present application is not limited thereto. For example, in FIGS. 9 and 10, it has been exemplarily described that a pre-emphasis operation is performed using a course voltage. However, in another embodiment, the pre-emphasis control unit 250 may perform a pre-emphasis operation using a fine voltage. That is, the pre-emphasis control unit 250 is a device applied to the non-inverting input terminal (+) of the amplifying unit 300 for pre-emphasis operation for the first and second output voltages V _OUT1 and V _OUT2 . The set middle voltage (V _MID ) can be switched to a fine voltage (V _FINE ).

For example, as shown in FIG. 11, the first pre-emphasis switch 251 applies a fine voltage to the non-inverting input terminal (+) of the amplifying unit 300 based on the pre-emphasis control signal PREM_ON. It can be electrically connected to the node 121_1. In this case, the second pre-emphasis switch 252 may short-circuit the non-inverting input terminal (+) of the amplifying unit 300 and the fine voltage node 121_1 to each other based on the pre-emphasis control signal PREM_ON. .

Then, the second pre-emphasis switch 252 applies a preset middle voltage (V _MID ) to the non-inverting input terminal (+) of the amplification unit 300 based on the pre-emphasis inversion signal (/PREM_ON). It may be electrically connected to the middle voltage node 250_1. At this time, the first pre-emphasis switch 251 may short-circuit the non-inverting input terminal (+) of the amplifying unit 300 and the fine voltage node 121_1 to each other based on the pre-emphasis inversion signal (/PREM_ON). have.

That is, the pre-emphasis control unit 250 may apply the fine voltage V _FINE to the non-inverting input terminal (+) based on the pre-emphasis control signal PREM_ON. Accordingly, the amplification unit 300 may output the second pre-emphasis voltage V _PREOUT2 . Here, the second pre-emphasis voltage V _PREOUT2 may be a voltage greater than the second output voltage VOUT2 (V _COARSE -V _FINE +V _FINE ).

In addition, in another embodiment of the present application, the pre-emphasis control unit 250 may be implemented to perform a pre-emphasis operation by selecting either a coarse voltage or a fine voltage. That is, the pre-emphasis control unit 250 applies a preset middle voltage (V _MID ) applied to the non-inverting input terminal (+) of the amplifying unit 300 to any one of a course voltage (V _COARSE ) and a fine voltage (V _FINE ). It can also be implemented to switch to one.

For example, as shown in FIG. 12A, the pre-emphasis control unit 250 may further include first and second selection switches 253_1 and 253_2. Specifically, the first and second selection switches 253_1 and 253_2 turn on any one of the fine voltage node 111_1 and the fine voltage node 121_1 to the second according to the first and second selection signals SEL1 and SLE2. It can be connected to the pre-emphasis switch 252.

That is, the pre-emphasis control unit 250 _applies any one of the coarse voltage V _COARSE and the fine voltage V _FINE to the non-inverting input terminal (+) based on the first and second selection signals SEL1 and _SLE2 . ) Can be applied. Accordingly, the amplification unit 300 may generate a pre-emphasis voltage based on any one of the coarse voltage V _COARSE and the fine voltage V _FINE .

Meanwhile, it will be understood that the above description is illustrative, and the technical idea of the present application is not limited thereto. For example, in FIGS. 9 to 12A, it has been described that a pre-emphasis operation is performed using a coarse voltage and a fine voltage. In this case, the coarse voltage may be defined as a voltage output through the coarse DAC, and the fine voltage may be defined as a voltage output through the fine DAC. However, in another embodiment of the present application, the control unit may generate a voltage to be used for the pre-emphasis operation using a separate circuit other than the coarse DAC or the fine DAC.

For example, the controller according to another embodiment of the present application may further include a separate circuit for generating a pre-emphasis voltage. In this case, as shown in FIG. 12B, the controller may perform a pre-emphasis operation using a pre-emphasis voltage received through a separate circuit.

Meanwhile, in FIGS. 2 to 12, it has been described that the control unit includes two capacitors. However, it will be understood that this is exemplary, and the technical idea of the present application is not limited thereto. For example, the control unit according to another embodiment of the present application may be implemented to include four or more capacitors, which will be described in more detail with reference to FIGS. 13 to 18 below.

FIG. 13 is a circuit diagram showing another embodiment of the controller 200 of FIG. 2, and FIG. 14 is a diagram illustrating an operation timing of the controller 200 of FIG. 13. FIG. 15 is a first equivalent circuit diagram of the controller 200 in the first charging section (TΦ _PRE1 ) of FIG. 14, and FIG. 16 is a diagram for the controller 200 in the second charging section (TΦ _PRE2 ) of FIG. 14 2 is an equivalent circuit diagram, Figure 17 in a fourth charging segment (TΦ _PRE4) of the third and the equivalent circuit diagram, Fig. 18 Fig. 14 for the control unit 200 in the third charge section (TΦ _PRE3) of 14 It is a fourth equivalent circuit diagram of the control unit 200.

13 to 18, the control unit 200 includes first to fourth capacitors C1 to C4, first to tenth preamp main switches SW_P1 to SW_P10, and first to fourth preamp sub switches. (211_3 to 211_6), a reset switch 230_1, and the first to fourth reference voltage switches 260_1 to 260_4 may be included.

First, in the period T0 to T1, the reset switch 230_1 may reset the parasitic capacitance of the capacitor based on the reset signal RST.

Then, in the period T1 to T2 (TΦ _PRE1 ), the first to third pream main switches (SW_P1 to SW_P3) and the first pream sub switch 211_3 are configured according to the first pream control signal (Φ _PRE1 ). In the case of switching, as shown in FIG. 15, the controller 200 may form a fourth equivalent circuit.

Specifically, in the period T1 to T2 (TΦ _PRE1 ), the first pre-am main switch (SW_P1) and the first pre-am sub-switch (211_3) are based on the first pre-am control signal (Φ _PRE1 ), the first capacitor The first charging voltage V _C1 may be charged in ( _C1 ).

At this time, the second and third pre-am main switches SW_P2 to SW_P3 amplify the second charging voltage V _C2 charged in the second capacitor 202 based on the first pre-am control signal Φ _PRE1 It may be applied to the inverting input terminal (-) of the unit 300 and the output node 301 of the amplifying unit 300. Accordingly, the amplification unit 300 may output the first output voltage V _OUT1 . In this case, similar to the above description, the first output voltage V _OUT1 may have a voltage level of Vcoarse-Vfine+Vmid.

Then, in the period T2 to T3, the reset switch 230_1 may reset the parasitic capacitance of the capacitor based on the reset signal RST.

Then, in the period T3 to T4 (TΦ _PRE2 ), the fourth to sixth pre-am main switches (SW_P4 to SW_P5) and the second pre-am sub-switch (211_4) according to the second pre-am control signal (Φ _PRE2 ). When switched, as shown in FIG. 16, the control unit 200 may form a fifth equivalent circuit.

Specifically, in the period T3 to T4 (TΦ _PRE2 ), the fourth pre-am main switch (SW_P4) and the second pre-am sub-switch (211_4) are based on the second pre-am control signal (Φ _PRE2 ), the third capacitor The third charging voltage V _C3 may be charged to 203. Here, the section T1 to T4 may correspond to the first charging section H1 of FIG. 1.

At this time, the fifth and sixth pre-am main switches SW_P5 and SW_P6 convert the fourth charging voltage V _C4 charged in the fourth capacitor 204 into the inverting input terminal (-) of the amplifying unit 300 and the amplifying unit. It can be applied to the output node 301 of 300. Accordingly, the amplification unit 300 may output the second output voltage V _OUT2 .

At this time, also the voltage level of the first output voltage (V _OUT1), as shown at 14 can be driven to higher than the voltage level of the second output voltage (V _OUT2). That is, it may be driven to perform the pre-emphasis operation in the period T1 to T2.

Then, in the period T4 to T5, the reset switch 230_1 may reset the parasitic capacitance of the capacitor based on the reset signal RST.

Then, in the period T5 to T6 (TΦ _PRE3 ), the seventh to ninth pre-am main switches (SW_P7 to SW_P9) and the third pre-am sub-switch (211_5) according to the third pre-am control signal (Φ _PRE3 ) When switched, as shown in FIG. 17, the controller 200 may form a sixth equivalent circuit.

Specifically, in the period T5 to T6 (TΦ _PRE3 ), the seventh pre-am main switch (SW_P7) and the third pre-am sub-switch (211_5) are based on the third pre-am control signal (Φ _PRE3 ), the second capacitor The second charging voltage V _C2 may be charged in ( _C2 ).

In addition, in the period T5 to T6 (TΦ _PRE3 ), the eighth and ninth pre-am main switches (SW_P8 to SW_P9) are charged in the first capacitor (C1) based on the third pre-am control signal (Φ _PRE3 ). The first charging voltage V _C1 may be applied to the inverting input terminal (-) of the amplifying unit 300 and the output node 301 of the amplifying unit 300.

Then, in the period T6 to T7, the reset switch 230_1 may reset the parasitic capacitance of the capacitor based on the reset signal RST.

Then, in the period T7 to T8 (TΦ _PRE4 ), the tenth to twelfth pream main switches (SW_P10 to SW_P12) and the fourth pream sub-switch 211_6 are operated according to the fourth _pream control signal (Φ _PRE4 ). When switched, as illustrated in FIG. 18, the controller 200 may form a seventh equivalent circuit.

Specifically, in the period T7 to T8 (TΦ _PRE4 ), the tenth pre-am main switch (SW_P10) and the fourth pre-am sub-switch (211_6) are based on the fourth pre-am control signal (Φ _PRE4 ), the fourth capacitor The fourth charging voltage V _C4 may be charged to 204. Here, the section T5 to T8 may correspond to the second charging section H2 of FIG. 1.

At this time, the 11th and 12th pre-am main switches SW_P11 and SW_P12 convert the third charging voltage V _C3 charged in the third capacitor 203 into the inverting input terminal (-) of the amplifying unit 300 and the amplifying unit. It can be applied to the output node 301 of 300. Accordingly, the amplification unit 300 may output the fourth output voltage V _OUT4 .

19 is a diagram illustrating a display device 1000 to which the output driver described in FIGS. 1 to 18 is applied. Referring to FIG. 19, the display device 1000 may include an output driver 1100, a data driver 1200, and a display panel 1300.

The data driver 1200 may receive pixel data for driving the display panel 1300 and transmit a digital signal to the output driver 1100. For example, the digital signal may be a signal for generating a coarse voltage and a fine voltage.

The display panel 1300 may display an image in a frame unit based on an output voltage output through the output driver 1100. For example, the display panel 1300 may be implemented as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, a flexible display, and the like. Alternatively, it may be implemented with a flat panel display other than those described above.

In an embodiment according to the technical idea of the present application, the output driver 1100 may be driven through the output driver described in FIGS. 1 to 18.

FIG. 20 is a diagram illustrating an example of an output driver to which a control unit and an amplification unit described in FIGS. 1 to 18 are applied, and FIG. 21 is a view showing the DAC 2300 of FIG.

As shown in FIG. 20, the output driver 2000 includes a shift register 2100, a data latch 2200, a digital-to-analog converter 2300: Digital Analog Converter; hereinafter, a DAC, and an output buffer 2400. can do.

The shift register 2100 may include a plurality of stages (not shown) that are dependently connected. The plurality of stages may receive a data clock signal CLK. A horizontal start signal may be applied to a first stage among the plurality of stages. When the operation of the first stage is started by the horizontal start signal, the plurality of stages may sequentially output control signals in response to the data clock signal CLK.

The data latch 2200 may include a plurality of latch circuits. The plurality of latch circuits may sequentially receive control signals from the plurality of stages. The data latch 2200 may store the image data RGB in units of pixel rows. The plurality of latch circuits may respectively store corresponding image data among the image data RGB in response to each of the control signals. The latch 320 may provide the stored image data RGB for the amount of the pixel row to the DAC 2300.

The DAC 2300 receives reference gray voltages generated from the gray voltage generator. The DAC 2330 may include a plurality of digital-to-analog converter circuits corresponding to a plurality of data latch circuits. The DAC 2300 may convert image data of the amount of the pixel row supplied from the data latch 2200 into gray voltages.

The output buffer 2400 receives gradation voltages from the DAC 2300. The output buffer 2400 may buffer the gray voltages and provide them to data lines.

In an embodiment according to the technical idea of the present application, the output buffer 2400 may be implemented to include the control unit and the amplification unit described in FIGS. 1 to 18.

Referring to FIG. 21, the DAC 2300 may include an M-bit decoder 2310 and an N-bit decoder 2320. For example, the M-bit decoder 2310 may generate the course voltages described in FIGS. 1 to 18. The N-bit decoder 2320 may generate the fine voltage described in FIGS. 1 to 18.

For example, the M-bit decoder 2310 may generate a course voltage based on a data signal transmitted from the gamma generator 3000 by a voltage distribution method and output the generated course voltage. In addition, the N-bit decoder 2320 may generate a fine voltage based on a data signal transmitted from the gamma generator 3000 by a voltage distribution method and output the generated fine voltage.

As described above, the output driver of the display device according to the exemplary embodiment of the present application performs a sampling operation and a driving operation in parallel, thereby reducing the time required for decoding and driving at high speed. In addition, since the feedback factor in the configuration of the feedback amplifier is “1”, the bandwidth of the amplifier can be utilized to the maximum, thereby enabling high-speed driving.

Also, the output driver of the display device according to the exemplary embodiment of the present application supports a pre-emphasis operation and may increase a slew rate according to a distance between the data driver and the display panel.

In addition, the output driver of the display device according to the exemplary embodiment of the present application connects one end of the capacitor to an inverting input terminal of an amplifier operating as a virtual ground, thereby reducing an effect of parasitic components of the capacitors.

In addition, the output driver of the display device according to the exemplary embodiment of the present application may implement an output voltage corresponding to a desired driving voltage despite variations between different first and second capacitors.

In addition, the output driver of the display device according to the exemplary embodiment of the present application stores a desired data voltage in one capacitor through a course decoder and a fine decoder, and outputs the data voltage in a pixel of the display device through an amplifier. In this case, since the data voltage is stored in one capacitor, there is no error in the data voltage within one channel. Accordingly, an output deviation in a driver including a plurality of channels can be reduced.

The embodiments of the present invention disclosed in the present specification and drawings are only provided for specific examples to easily explain the technical content of the present invention and to aid understanding of the present invention, and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is obvious to those of ordinary skill in the art that other modified examples based on the technical idea of the present invention may be implemented.

The present application relates to an output driver of a display device, which reduces decoding time and enables high-speed driving, and thus has industrial applicability.

Claims

A digital-analog converter that generates a first voltage and a second voltage different from the first voltage;

A controller that alternately charges the first and second capacitors based on a voltage difference between the first voltage and the second voltage; And

And an amplifying unit that alternately receives and outputs each charging voltage charged to the first and second capacitors,

The control unit outputs a second charging voltage charged in the second capacitor to an output node of the amplifying unit during a first charging time for charging the first charging voltage in the first capacitor.
The method of claim 1,

The control unit, during the first charging time, connects one side of the second capacitor to an inverting input terminal of the amplification unit, and connects the other side of the second capacitor to the output node.
The method of claim 1,

The control unit outputs the charging voltage charged in the first capacitor to the output node during a second charging time when the second capacitor is charged.
The method of claim 3,

The control unit, during the second charging time, connects one side of the first capacitor to an inverting input terminal of the amplification unit, and connects the other side of the first capacitor to the output node.
The method of claim 1,

The amplifying unit, the second charging voltage is applied to the inverting input terminal, a preset middle voltage is applied to the non-inverting input terminal, and outputs through the output node.
The method of claim 5,

The control unit electrically connects the non-inverting input terminal and the inverting input terminal to each other between the first charging time and the second charging time.
The method of claim 5,

The output driver further comprising a delay unit for delaying a predetermined time for the output voltage to be output to the display panel.
The method of claim 5,

The control unit further comprises a pre-emphasis control unit for switching the middle voltage applied to the non-inverting input terminal to one of the first voltage and the second voltage at each of the first and second charging times. driver.
A digital-analog converter that generates a first voltage and a second voltage different from the first voltage;

A controller for sequentially charging a charging voltage to the first to fourth capacitors based on a voltage difference between the first voltage and the second voltage; And

An amplifying unit for outputting the charging voltage charged in the first to fourth capacitors to an output node,

The control unit, while charging the first capacitor, connects the second capacitor to the output node of the amplification unit, and while charging the third capacitor, connects the fourth capacitor to the output node of the amplification unit, Output driver.
The method of claim 9,

The control unit, while charging the second capacitor, connects the third capacitor to the output node of the amplification unit, and while charging the fourth capacitor, connects the first capacitor to the output node of the amplification unit, Output driver.