CN113678188B - Output driver of display device - Google Patents
Output driver of display device Download PDFInfo
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- CN113678188B CN113678188B CN201980095418.6A CN201980095418A CN113678188B CN 113678188 B CN113678188 B CN 113678188B CN 201980095418 A CN201980095418 A CN 201980095418A CN 113678188 B CN113678188 B CN 113678188B
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- 239000003990 capacitor Substances 0.000 claims abstract description 148
- 238000010586 diagram Methods 0.000 description 44
- 230000001360 synchronised effect Effects 0.000 description 27
- 238000009966 trimming Methods 0.000 description 25
- 230000003071 parasitic effect Effects 0.000 description 12
- 101150065808 pre3 gene Proteins 0.000 description 7
- 101150086396 PRE1 gene Proteins 0.000 description 6
- 101000617541 Danio rerio Presenilin-2 Proteins 0.000 description 5
- 101150005253 PRE4 gene Proteins 0.000 description 5
- 238000005070 sampling Methods 0.000 description 5
- 230000001105 regulatory effect Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 description 2
- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2230/00—Details of flat display driving waveforms
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0828—Several active elements per pixel in active matrix panels forming a digital to analog [D/A] conversion circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0833—Several active elements per pixel in active matrix panels forming a linear amplifier or follower
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
- G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Amplifiers (AREA)
Abstract
The output driver of the display device of the embodiment of the invention comprises: the digital-analog converter is used for generating a coarse tuning voltage and a fine tuning voltage; a control unit that alternately charges the first capacitor and the second capacitor based on a voltage difference between the rough adjustment voltage and the fine adjustment voltage; and an amplifying unit configured to alternately receive the respective charge voltages charged in the first capacitor and the second capacitor and continuously output an output voltage, wherein the control unit outputs the second charge voltage charged in the second capacitor to an output node of the amplifying unit during a first charge time period in which the first charge voltage is charged in the first capacitor.
Description
Technical Field
The present application relates to an output driver of a display device.
Background
Recently, as the size and resolution of display panels are increased, flexible gamma curve setting and increased color depth are required. In order to meet the above-described demand, an output driver occupying a larger area should be used in a driving circuit of a display device.
The capacities of the load resistor and the load capacitor connected to the output driver are increased, and accordingly, the target voltage of the image signal is increased. In particular, the slew rate (slew rate) of the amplifier of the output driver may be reduced due to an increase in load resistance and load capacity.
Accordingly, there is a need for an output driver of a display device that can increase a slew rate of an amplifier by pre-emphasis (pre-emphsi) operation, and can reduce a decoding time and a circuit area.
Disclosure of Invention
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an output driver of a display device capable of realizing high-speed driving by performing sampling work and driving work in parallel; providing an output driver of the display device capable of performing a pre-emphasis operation; providing an output driver of a display device which can support high resolution and can be embodied in a small area; an output driver of a display device is provided which can reduce inter-channel skew by at least two-step decoding.
Solution for solving the problem
The output driver of the embodiment of the invention comprises: a digital-to-analog converter for generating a first voltage and a second voltage different from the first voltage; a control unit that alternately charges a first capacitor and a second capacitor based on a voltage difference between the first voltage and the second voltage; and an amplifying unit that alternately receives and outputs the respective charge voltages charged to the first capacitor and the second capacitor, wherein the control unit outputs the second charge voltage charged to the second capacitor to an output node of the amplifying unit during a first charge time period in which the first charge voltage is charged to the first capacitor.
In an embodiment, the control section connects one side of the second capacitor to an inverting input terminal of the amplifying section, and connects the other side of the second capacitor to the output node.
In an embodiment, the control section outputs the charging voltage to charge the first capacitor to the output node during a second charging time to charge the second capacitor.
In an embodiment, the control section connects one side of the first capacitor to the inverting input terminal of the amplifying section and connects the other side of the first capacitor to the output node during the second charging time.
In an embodiment, the amplifying part receives the second charging voltage through an inverting input terminal, receives a preset medium voltage through a non-inverting input terminal, and outputs through the output node.
In an embodiment, the control section electrically connects the non-inverting input terminal and the inverting input terminal between the first charging time and the second charging time.
In an embodiment, the present invention further includes a delay unit for delaying a time for outputting the output voltage to the display panel by a predetermined time.
In an embodiment, the control section further includes a pre-emphasis control section that switches the medium voltage applied to the non-inverting input terminal to one of the first voltage and the second voltage at each of the first charging time and the second charging time.
The output driver of the embodiment of the invention comprises: a digital-to-analog converter for generating a first voltage and a second voltage different from the first voltage; a control unit that sequentially charges the first to fourth capacitors with a charging voltage based on a voltage difference between the first voltage and the second voltage; and an amplifying section for outputting a charging voltage for charging the first to fourth capacitors to an output node, the control section connecting the second capacitor to the output node of the amplifying section during charging of the first capacitor, and the control section connecting the fourth capacitor to the output node of the amplifying section during charging of the third capacitor.
According to an embodiment, the control section connects the third capacitor to the output node of the amplifying section during charging of the second capacitor, and connects the first capacitor to the output node of the amplifying section during charging of the fourth capacitor.
Effects of the invention
In the output driver of the display device of an embodiment of the present invention, the time required for decoding can be reduced and high-speed driving can be performed by performing sampling work and driving work in parallel.
In the output driver of the display device according to an embodiment of the present invention, a pre-emphasis operation can be supported and a Slew Rate (Slew Rate) based on a distance between the data driver and the display panel can be increased.
In the output driver of the display device of an embodiment of the present invention, an influence due to a parasitic effect of the capacitor can be reduced by connecting one end of the capacitor to the inverting input terminal of the amplifier serving as the virtual ground.
In the output driver of the display device according to an embodiment of the present invention, although there is a deviation between the first capacitor and the second capacitor, an output voltage corresponding to a desired driving voltage can be realized.
In the output driver of the display device according to the embodiment of the present invention, the required data voltage can be stored in one capacitor by the coarse tuning decoder and the fine tuning decoder, and the data voltage in the pixel of the display device can be output by the amplifying section. In this case, since the data voltage is stored in one capacitor, an error of the data voltage in one channel is eliminated. Thus, output variations within a driver including a plurality of channels can be reduced.
Drawings
Fig. 1 is a block diagram of an output driver of a display device according to an embodiment of the present invention.
Fig. 2 is a circuit diagram specifically illustrating an output driver of the display device of fig. 1.
Fig. 3 is a diagram of operation timings of the control unit of fig. 2.
Fig. 4 is a first equivalent circuit diagram of the control section in the reset segment of fig. 3.
Fig. 5 is a second equivalent circuit diagram of the control section in the first charging time of fig. 3.
Fig. 6 is a third equivalent circuit diagram of the control section in the first charging time of fig. 3.
Fig. 7 is a circuit diagram of still another embodiment of the control section of fig. 1.
Fig. 8 is a diagram of the operation timing of the delay unit of fig. 7.
Fig. 9 is a circuit diagram of another embodiment of the control section of fig. 1.
Fig. 10 is a diagram of operation timings of the pre-emphasis control unit of fig. 9.
Fig. 11 is a circuit diagram of still another embodiment of the pre-emphasis control section of fig. 10.
Fig. 12A is a circuit diagram of another embodiment of the pre-emphasis control section of fig. 10.
Fig. 12B is a circuit diagram of yet another embodiment of the pre-emphasis control section of fig. 10.
Fig. 13 is a circuit diagram of still another embodiment of the control section of fig. 2.
Fig. 14 is a diagram of operation timings of the control unit of fig. 13.
Fig. 15 is a first equivalent circuit diagram of the control section in the first charging section of fig. 14.
Fig. 16 is a second equivalent circuit diagram of the control section in the second charging section of fig. 14.
Fig. 17 is a third equivalent circuit diagram of the control section in the third charging section of fig. 14.
Fig. 18 is a fourth equivalent circuit diagram of the control unit in the fourth charging section of fig. 14.
Fig. 19 is a diagram showing a display device to which an output driver is applied.
Fig. 20 is a diagram showing an example of an output driver applied to the control section and the amplifying section described in fig. 1 to 18.
Fig. 21 is a diagram of the digital-to-analog converter of fig. 20 in greater detail.
Detailed Description
The output driver of the embodiment of the invention comprises: a digital-to-analog converter for generating a first voltage and a second voltage different from the first voltage; a control unit that alternately charges a first capacitor and a second capacitor based on a voltage difference between the first voltage and the second voltage; and an amplifying unit that alternately receives and outputs the respective charge voltages charged to the first capacitor and the second capacitor, wherein the control unit outputs the second charge voltage charged to the second capacitor to an output node of the amplifying unit during a first charge time period in which the first charge voltage is charged to the first capacitor. The output driver of the display device according to an embodiment of the present invention can reduce the time required for decoding and realize high-speed driving by performing sampling work and driving work together.
The specific structural and functional descriptions of the embodiments of the present inventive concept disclosed in the present specification are presented for the purpose of illustration of the embodiments of the present inventive concept, and the embodiments of the present inventive concept can be implemented in various forms and are not limited to the embodiments described in the present specification.
Various modifications and numerous forms of embodiments of the inventive concept are possible and, therefore, various embodiments are illustrated in the accompanying drawings and described in detail in the present specification. However, the present invention is not limited to the embodiments of the inventive concept, but includes all modifications, equivalents, or alternatives falling within the spirit and scope of the invention.
Although terms such as "first" or "second" may be used to describe various structural elements, the structural elements are not limited to the terms. The term is used merely to distinguish one structural element from other structural elements, for example, a first structural element may be named a second structural element, and similarly, a second structural element may also be named a first structural element without departing from the scope of the inventive concept.
When a certain component is "connected" or "in contact with" another component, it is understood that the other component is present in the middle, although the component may be directly connected or in contact with the other component. Conversely, when a component is expressed as being "directly connected" or "directly contacted" with another component, it is to be understood that the other component is not present in the middle. That is, other expressions for describing the relationship between constituent elements such as "between", "directly between", "adjacent", "directly adjacent", and the like should be construed as well.
The terminology used in the description presented herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should be understood that the terms "comprises" and "comprising," when used in this specification, are taken to specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, acts, elements, components, or groups thereof.
Unless defined otherwise, all terms used herein including technical or scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms defined in a dictionary generally used should be interpreted as having the same meaning as the related art having on the text, and should not be interpreted in an idealized or overly formal sense unless expressly so defined in the specification.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a block diagram of an output driver 500 of a display device according to an embodiment of the present invention.
Referring to fig. 1, the output driver 500 may include a digital-to-analog converter 100, a control part 200, and an amplifying part 300.
First, the DAC 100 can generate a coarse tuning voltage V COARSE And trimming voltage V FINE 。
Wherein the voltage V is coarsely regulated COARSE The voltage V may be finely adjusted to a voltage corresponding to a wide voltage range adjusted in units of a preset voltage or more FINE May be a voltage corresponding to a voltage interval in a local range adjusted in less than a preset voltage unit. For example, coarse tuning voltage V COARSE Can correspond to one voltage (e.g., 3V) among voltages (e.g., 0V-10V) regulated in 1V voltage unit, trimming the voltage V FINE Can correspond to a coarse adjustment voltage V at 3V COARSE Is regulated to a voltage of 0.1V unit (e.g., 0.5V).
In the following description, the digital-analog converter 100 will be described in further detail with reference to fig. 20.
Then, the coarse adjustment voltage V generated by the DAC 100 is used COARSE And trimming voltage V FINE Voltage difference V between COARSE -V FINE Based on this, the control part 200 can control the first capacitor201 and the second capacitor 202 are alternately charged. Wherein the first capacitor 201 and the second capacitor 202 can apply a rough adjustment voltage V to one side COARSE Applying a trimming voltage V to the other side FINE 。
Specifically, the voltage V is coarsely regulated COARSE And trimming voltage V FINE Voltage difference V between COARSE -V FINE Based on this, the control part 200 can use the first charging voltage V in the first charging time H1 C1 Charge the first capacitor 201 and at a second charging voltage V for a second charging time H2 C2 The second capacitor 202 is charged. For example, as shown in fig. 3, a first charging time H1 for charging the first capacitor 201 and a second charging time H2 for charging the second capacitor 202 may be complementary.
Subsequently, the amplifying section 300 may alternately receive the respective charging voltages V for charging the first capacitor 201 and the second capacitor 202 C1 、V C2 To continuously output the output voltage V OUT . Specifically, the amplifying part 300 may receive the second charging voltage V from the control part 200 through the inverting input terminal (-) within the first charging time H1 C2 The first charging voltage V may be received from the control portion 200 through the input terminal (-) during the second charging time H2 C1 。
Also, the amplifying part 300 may receive a preset medium voltage V through a non-inverting input terminal (+) MID . Wherein, the preset medium voltage V MID May be less than the coarse tuning voltage V COARSE Trimming voltage V FINE Is set in the above-described voltage range.
In this case, at a preset medium voltage V received through the non-inverting input terminal (+) MID And charging voltages V alternately received through the inverting input terminals (-) respectively C1 、V C2 Based on this, the amplifying section 300 can alternately generate the first output voltage V OUT1 And a second output voltage V OUT2 . That is, according to the respective charging voltages V alternately received through the inverting input terminal (-) C1 、V C2 The amplifying section 300 can continuously generate the output voltage V OUT 。
In the embodiment of the technical idea of the present invention, the first capacitor 201 is subjected toDuring the first charging time H1, the control unit 200 may output the second charging voltage V to the second capacitor 202 to the output node 301 of the amplifying unit 300 C2 . Further, during the second charging time H2 for charging the second capacitor 202, the control unit 200 may output the first charging voltage V for charging the first capacitor 201 to the output node 301 of the amplifying unit 300 C1 。
Thus, the control section 200 can output the second charging voltage (e.g., V) charged to the second capacitor 202 to the output node 301 of the amplifying section 300 by performing the sampling operation of charging the first capacitor 201 in parallel C2 ) To achieve high-speed driving and to reduce the circuit area for decoding.
Fig. 2 is a circuit diagram for specifically illustrating the control unit 200 of fig. 1, fig. 3 is a diagram illustrating an operation timing of the control unit 200 of fig. 2, fig. 4 is a first equivalent circuit diagram of the control unit 200 in the reset interval RST of fig. 3, fig. 5 is a second equivalent circuit diagram of the control unit 200 in the first charging time H1 of fig. 3, and fig. 6 is a third equivalent circuit diagram of the control unit 200 in the second charging time H2 of fig. 3.
Referring to fig. 2, the control part 200 may include a first capacitor 201, a second capacitor 202, first to sixth main switches SW1 to SW6, a first sub switch 211_1, a second sub switch 211_2, and a plurality of reset switches swrst_1 to swrst_3.
First, as shown in fig. 4, in the interval T0 to T1, when the plurality of reset switches swrst_1 to swrst_3 are switched according to the reset signal RST, the control section 200 may form a first equivalent circuit.
Specifically, the plurality of reset switches swrst_1 to swrst_3 can reset the parasitic capacitance based on the reset signal RST. The reset signal RST may be a control signal for resetting a parasitic capacitance of at least one of the first capacitor 201 and the second capacitor 202.
For example, as shown in fig. 4, a first reset switch swrst_1 of the plurality of reset switches swrst_1 to swrst_3 can connect the other side of the first capacitor 201 to a preset medium voltage V based on a reset signal RST MID So that the Vy node connected to the first capacitor 201The parasitic capacitance is reset to medium voltage V MID 。
And, the second reset switch swrst_2 can connect the other side of the second capacitor 202 to a preset medium voltage V based on the reset signal RST MID So that the parasitic capacitance of the Vx node connected to second capacitor 202 is reset to medium voltage V MID . The third reset switch swrst_3 can connect the inverting input terminal (-) of the amplifying unit 300 to the medium voltage V through the non-inverting input terminal (+) based on the reset signal RST MID 。
Next, as shown in fig. 5, in the interval T1 to T2, when the first main switch SW1, the second main switch SW2, the third main switch SW3 and the first sub-switch 211_1 are switched according to the first main control signal Φ1 and the first sub-control signal Φ1e, the control unit 200 may form a second equivalent circuit.
Specifically, in the interval T1 to T2H 1, the first main switch SW1 and the first sub-switch 211_1 can apply the rough adjustment voltage V to the first capacitor 201 based on the first main control signal Φ1 and the first sub-control signal Φ1e COARSE And trimming voltage V FINE Voltage difference V between COARSE -V FINE To generate the charging voltage V C1 。
Wherein the first main control signal Φ1 and the first sub control signal Φ1e are control signals for charging the first capacitor 201, the time for which the first sub control signal Φ1e is activated may be smaller than the time for which the first main control signal Φ1 is activated, so that the first capacitor 201 is easily charged.
As shown in fig. 5, in the interval T1 to T2H 1, the first main switch SW1 can connect one side of the first capacitor 201 to the coarse tuning voltage node 111_1 based on the first main control signal Φ1. In the interval T1 to T2H 1, the first sub-switch 211_1 can connect the other side of the first capacitor 201 to the trimming voltage node 121_1 based on the first sub-control signal Φ1e. That is, in the interval T1 to T2, the first main switch SW1 and the first sub-switch 211_1 can apply the rough adjustment voltage V to the first capacitor 201 COARSE And trimming voltage V FINE 。
In this case, the range is from T1 to T2H1, the second main switch SW2 and the third main switch SW3 can apply the second charging voltage V for charging the second capacitor 202 to the inverting input terminal (-) of the amplifying section 300 and the output node 301 of the amplifying section 300 based on the first main control signal Φ1 C2 。
The first main control signal Φ1 of the embodiment of the present invention may be a voltage for applying the second charging voltage V for charging the second capacitor 202 to the inverting input terminal (-) of the amplifying section 300 and the output node 301 of the amplifying section 300 C2 Is controlled by a control signal of (a).
As shown in fig. 5, the second main switch SW2 can connect one side of the second capacitor 202 to the inverting input terminal (-) of the amplifying section 300 based on the first main control signal Φ1. And, the third main switch SW3 can connect the other side of the second capacitor 202 to the output node 301 based on the first main control signal Φ1.
In contrast, in the interval T1 to T2H 1, the amplifying unit 300 may output the second charging voltage V through the output node 301 C2 And for a preset medium voltage V MID Is set to the first output voltage V OUT1 . Wherein the first output voltage V OUT1 May be the second charging voltage V applied to the amplifying section 300 C2 And a preset medium voltage V applied to the amplifying section 300 MID Sum (V) COARSE -V FINE +V MID ). That is, in the interval T1 to T2H 1, the first main switch SW1 and the first sub-switch 211_1 can charge the first capacitor 201, and the second main switch SW2 and the third main switch 210_3 can output the first output voltage V through the amplifying section 300 OUT1 。
Then, similarly to the period T0 to T1, in the period T2 to T3, the plurality of reset switches swrst_1 to swrst_3 can reset the parasitic capacitance of at least one of the first capacitor 201 and the second capacitor 202 based on the reset signal RST. For example, the plurality of reset switches swrst_1 to swrst_3 are switched according to the reset signal RST, so that the same equivalent circuit as the first equivalent circuit of fig. 4 can be formed.
Next, as shown in fig. 6, in the interval T3 to T4, H2, when the fourth main switch SW4, the fifth main switch SW5, the sixth main switch SW6 and the second sub-switch 211_2 are switched by the second main control signal Φ2 and the second sub-control signal Φ2e, the control unit 200 can form a third equivalent circuit.
Specifically, the fourth main switch SW4 and the second sub-switch 211_2 can apply the coarse tuning voltage V to the second capacitor 202 based on the second main control signal Φ2 and the second sub-control signal Φ2e COARSE And trimming voltage V FINE Voltage difference V between COARSE -V FINE And generates a charging voltage V C2 。
Wherein the second main control signal Φ2 and the second sub control signal Φ2e are control signals for charging the second capacitor 202, the time for which the second sub control signal Φ2e is activated may be smaller than the time for which the second main control signal Φ2 is activated, so as to easily charge the second capacitor 202.
As shown in fig. 6, in the interval H2 from T3 to T4, the fourth main switch SW4 can connect one side of the second capacitor 202 to the coarse tuning voltage node 111_1 based on the second main control signal Φ2. In the interval T3 to T4, the second sub-switch 211_2 can connect the other side of the second capacitor 202 to the trimming voltage node 121_1 based on the second sub-control signal Φ2e. That is, in the interval T3 to T4, the fourth main switch SW4 and the second sub-switch 211_2 can be controlled by applying the rough adjustment voltage V to both sides of the second capacitor 202 COARSE And trimming voltage V FINE To be charged with voltage V C2 Charging is performed.
In this case, in the interval H2 from T3 to T4, the fifth main switch SW5 and the sixth main switch SW6 can output the first charging voltage V for charging the first capacitor 202 to the output node 301 of the amplifying section 300 based on the second main control signal Φ2 C1 。
The second main control signal Φ2 of the embodiment may be a first charging voltage V for charging the first capacitor 201 to the output node 301 of the amplifying section 300 C1 Is controlled by a control signal of (a).
Specifically, the fifth main switch SW5 can connect one side of the first capacitor 201 to the inverting input terminal (-) of the amplifying section 300 based on the second main control signal Φ2. And, the sixth main switch SW6 canThe other side of the first capacitor 201 is connected to the output node 301 based on the second main control signal Φ2. In contrast, in the interval H2 from T3 to T4, the amplifying unit 300 may output the first charging voltage V through the output node 301 C1 And for a preset medium voltage V MID Is a second output voltage V of (2) OUT2 . Wherein the second output voltage V OUT2 May be the first charging voltage V applied to the amplifying section 300 C1 And a preset medium voltage V applied to the amplifying section 300 MID Sum (V) COARSE -V FINE +V MID ). That is, in the interval T3 to T4, the fourth main switch SW4 and the second sub switch 211_2 may be used to charge the second capacitor 202, and at the same time, the fifth main switch SW5 and the sixth main switch SW6 may output the second output voltage V through the amplifying section 300 OUT2 。
Next, similarly to the period T0 to T1, the plurality of reset switches swrst_1 to swrst_3 can reset the parasitic capacitance of at least one of the first capacitor 201 and the second capacitor 202 based on the reset signal RST in the period T4 to T5.
Subsequently, in the interval T5 to T6H 1, the first main switch SW1 and the first sub-switch 211_1 can be based on the first main control signal Φ1 and the first sub-control signal Φ1e with the first charging voltage V C1 The first capacitor 201 is charged. Meanwhile, the second main switch SW2 and the third main switch SW3 can output the first output voltage V through the amplifying section 300 based on the first main control signal Φ1 OUT1 。
Fig. 7 is a circuit diagram of still another embodiment of the control unit 200 of fig. 1, and fig. 8 is a diagram showing the operation timing of the delay unit 240 of fig. 7.
Referring to fig. 7 and 8, the control part 200 may include a first capacitor 201, a second capacitor 202, first to sixth main switches SW1 to SW6, a first sub switch 211_1, a second sub switch 211_2, a plurality of reset switches swrst_1 to swrst_3, and a delay part 240.
The circuit of fig. 7 is similar to the circuit of fig. 2. In this regard, for convenience of explanation, repeated explanation of the same reference numerals explained in fig. 1 to 6 will be omitted, for example, the first capacitor 201, the second capacitor 202, the first to sixth main switches SW1 to SW6, the first to second sub switches 211_1, 211_2, and the plurality of reset switches 230_1 to 230_3.
The delay part 240 may output the first output voltage V to the display panel 700 through the amplifying part 300 OUT1 Or a second output voltage V OUT2 Is delayed by a prescribed time.
More specifically, as shown in fig. 8, the delay section 240 can electrically interconnect the output node 301 of the amplifying section 300 and the display panel 700 based on the delay signal high_z_sw. Wherein the delay signal HIGH_Z_SW may be for the first output voltage V OUT1 Or a second output voltage V OUT2 The output time of the first switching signal phi 1 and the second switching signal phi 2 is delayed by a predetermined time and is activated at a predetermined time point of the activation interval of each of the first switching signal phi 1 and the second switching signal phi 2.
For example, as shown in fig. 8, the delay unit 240 may electrically short-circuit the output node 301 of the amplifying unit 300 and the display panel 700 to a predetermined time point (e.g., T1.5) in the period of T1 to T2, and may electrically connect the output node 301 of the amplifying unit 300 and the display panel 700 from the predetermined time point (e.g., T1.5) to the period of T2.
That is, in response to the delay signal high_z_sw activated at a predetermined time point of the activation section of each of the first switching signal Φ1 and the second switching signal Φ2, the delay section 240 may output the first output voltage V output through the amplifying section 300 to the display panel 700 OUT1 Or a second output voltage V OUT2 。
Fig. 9 to 12 are diagrams showing another embodiment of the control section 200 of fig. 1. For example, unlike the circuits illustrated in fig. 2-8, the circuits of fig. 9-12 may also support pre-emphasis operation.
Specifically, fig. 9 is a diagram showing a control section 200 including a pre-emphasis control section 250, and fig. 10 is a diagram showing the timing at which the pre-emphasis control section 250 of fig. 9 operates. Also, fig. 11 is a circuit diagram of still another embodiment of the pre-emphasis control section 250 of fig. 9, and fig. 12 is a circuit diagram of another embodiment of the pre-emphasis control section 250 of fig. 9.
First, referring to fig. 9 and 10, the control part 200 may include a first capacitor 201, a second capacitor 202, first to sixth main switches SW1 to SW6, a first sub-switch 211_1, a second sub-switch 211_2, a plurality of reset switches 230_1 to 230_3, and a pre-emphasis control part 250.
Hereinafter, for convenience of explanation, repeated explanation of the same reference numerals explained in fig. 2 to 7 will be omitted, for example, the first capacitor 201, the second capacitor 202, the first to sixth main switches SW1 to SW6, the first sub switch 211_1, the second sub switch 211_2, and the plurality of reset switches 230_1 to 230_3.
The pre-emphasis control section 250 of an embodiment may include a first pre-emphasis switch 251 and a second pre-emphasis switch 252.
According to an embodiment, the pre-emphasis control part 250 may control the pre-set medium voltage V by applying the pre-set medium voltage V to the non-inverting input terminal (+) of the amplifying part 300 MID Switching to coarse voltage V COARSE In order to perform a voltage regulation for the first output voltage V OUT1 A second output voltage V OUT2 Is used for pre-emphasis operation.
Specifically, the first pre-emphasis switch 251 can electrically connect the non-inverting input terminal (+) of the amplifying section 300 with the coarse voltage node 111_1 based ON the pre-emphasis control signal prem_on. The pre-emphasis control signal pre_on may be a signal activated for a prescribed time according to the reset signal RST. In this case, the second pre-emphasis switch 252 can short-circuit the non-inverting input terminal (+) of the amplifying section 300 and the medium voltage node 250_1 with each other based ON the pre-emphasis control signal prem_on.
Then, the second pre-emphasis switch 252 can make the non-inverting input terminal (+) of the amplifying section 300 and apply the medium voltage V based ON the pre-emphasis inversion signal/pre_on MID Is electrically connected to the medium voltage node 250_1. Wherein the pre-emphasis inversion signal/pre_on may be an inversion signal for the pre-emphasis control signal pre_on. In this case, the first pre-emphasis switch 251 can short-circuit the non-inverting input terminal (+) of the amplifying section 300 and the medium voltage node 250_1 with each other based ON the pre-emphasis inversion signal/pre_on.
As shown in fig. 9, the pre-emphasis control section 250 can apply a coarse tuning voltage V to the non-inverting input terminal (+) based ON the pre-emphasis control signal prem_on COARSE . Thus, the amplifying section 300 can output the first pre-emphasis voltage V PREOUT1 . Wherein the first pre-emphasis voltage V PREOUT1 May be greater than the second output voltage V OUT2 Voltage (V) COARSE -V FINE +V COARSE )。
On the other hand, the above description is illustrative, and the technical idea of the present invention is not limited thereto. For example, performing pre-emphasis with a coarse tuning voltage is illustrated in fig. 9 and 10. However, according to still another embodiment, the pre-emphasis control section 250 may perform the pre-emphasis operation using the trimming voltage. I.e. to achieve a first output voltage V OUT1 A second output voltage V OUT2 Pre-emphasis control section 250 may apply a preset medium voltage V to the non-inverting input terminal (+) of amplifying section 300 MID Switching to trimming voltage V FINE 。
For example, as shown in fig. 11, the first pre-emphasis switch 251 may electrically connect the non-inverting input terminal (+) of the amplifying section 300 with the trimming voltage node 121_1 based ON the pre-emphasis control signal prem_on. In this case, the second pre-emphasis switch 252 can short-circuit the non-inverting input single side (+) of the amplifying section 300 and the trimming voltage node 121_1 with each other based ON the pre-emphasis control signal prem_on.
Subsequently, the second pre-emphasis switch 252 can make the non-inverting input terminal (+) of the amplifying section 300 and apply a preset medium voltage V based ON the pre-emphasis inversion signal/pre_on MID Is electrically connected to the medium voltage node 250_1. In this case, the first pre-emphasis switch 251 can short-circuit the non-inverting input terminal (+) of the amplifying section 300 and the trimming voltage node 121_1 with a pre-emphasis inversion signal/pre_on.
That is, the pre-emphasis control section 250 can apply the trimming voltage V to the non-inverting input terminal (+) based ON the pre-emphasis control signal prem_on FINE . Thus, the amplifying section 300 can output the second pre-emphasis voltage V PREOUT2 . Wherein the second pre-emphasis voltage V PREOUT2 May be greater than the second output voltage V OUT2 Voltage (V) COARSE -V FINE +V FINE )。
In still another embodiment of the present invention, the pre-emphasis control section 250 may perform the pre-emphasis operation by selecting one of the coarse tuning voltage and the fine tuning voltage. That is, the pre-emphasis control section 250 may apply a preset medium voltage V to the non-inverting input terminal (+) MID Switching to coarse voltage V COARSE Trimming voltage V FINE One of which is a metal alloy.
For example, as shown in fig. 12A, the pre-emphasis control section 250 may further include a first selection switch 253_1 and a second selection switch 253_2. Specifically, the first and second selection switches 253_1 and 253_2 may connect one of the trimming voltage node 111_1 and the trimming voltage node 121_1 to the second pre-emphasis switch 252 by the first and second selection signals SEL1 and SLE 2.
That is, the pre-emphasis control unit 250 can apply the rough adjustment voltage V to the non-inverting input sheet (+) based on the first selection signal SEL1 and the second selection signal SLE2 COARSE Trimming voltage V FINE Is set in the voltage range. Thereby, the amplifying unit 300 can coarsely adjust the voltage V COARSE Trimming voltage V FINE To generate a pre-emphasis voltage based on the voltage of the capacitor.
On the other hand, it should be understood that the above description is illustrative, and the technical idea of the present invention is not limited thereto. For example, performing pre-emphasis operation using a coarse tuning voltage and a fine tuning voltage is illustrated in fig. 9 to 12A. In this case, the coarse tuning voltage may be a voltage output through the coarse tuning digital-to-analog converter, and the fine tuning voltage may be a voltage output through the fine tuning digital-to-analog converter. However, in still another embodiment of the present invention, the control section may use an additional circuit to generate the voltage for the pre-emphasis operation instead of the coarse digital-to-analog converter or the fine digital-to-analog converter.
For example, the control part of still another embodiment of the present invention may further include an additional circuit for generating the pre-emphasis voltage. In this case, as shown in fig. 12B, the control section may also perform the pre-emphasis operation by the pre-emphasis voltage received by the additional circuit.
On the other hand, it is illustrated in fig. 2 to 12 that the control section includes two capacitors. However, it should be understood that this is only an example, and the technical idea of the present invention is not limited thereto. For example, the control unit according to still another embodiment of the present invention may include 4 or more capacitors, which will be described in further detail below with reference to fig. 13 to 18.
Fig. 13 is a circuit diagram illustrating still another embodiment of the control unit 200 of fig. 2, and fig. 14 is a diagram illustrating an operation timing of the control unit 200 of fig. 13. Fig. 15 shows the first charging interval tΦ of fig. 14 PRE1 Fig. 16 is a first equivalent circuit diagram of the control unit 200 in fig. 14, showing a second charging interval tΦ PRE2 Fig. 17 is a second equivalent circuit diagram of the control unit 200 in fig. 14, showing the third charging interval tΦ PRE3 Fig. 18 is a third equivalent circuit diagram of the control unit 200 in fig. 14, in which the fourth charging section tΦ is PRE4 A fourth equivalent circuit diagram of the control unit 200.
Referring to fig. 13 to 18, the control part 200 may include first to fourth capacitors C1 to C4, first to tenth synchronization main switches sw_p1 to sw_p10, first to fourth synchronization sub-switches 211_3 to 211_6, a reset switch 230_1, and first to fourth reference voltages 260_1 to 260_4.
First, in the interval T0 to T1, the reset switch 230_1 can reset the parasitic capacitance of the capacitor based on the reset signal RST.
Next, as shown in fig. 15, T Φ is a section T1 to T2 PRE1 When the first to third synchronous main switches SW_P1 to SW_P3 and the first synchronous sub-switch 211_3 are in accordance with the first synchronous control signal Φ PRE1 When switching is performed, the control unit 200 may form a fourth equivalent circuit.
Specifically, T phi is within the interval T1-T2 PRE1 The first synchronization main switch sw_p1 and the first synchronization auxiliary switch 211_3 can be controlled by the first synchronization control signal Φ PRE1 Based on the first charging voltage V C1 The first capacitor C1 is charged.
In this case, the second and third synchronous main switches SW_P2 and SW_P3 can be controlled by the first synchronous control signal Φ PRE1 An inverting input terminal (i.e., a power-on/off terminal) to the amplifying section 300) And an output node 301 of the amplifying section 300 applies a second charging voltage V that charges the second capacitor 202 C2 . Thereby, the amplifying section 300 can output the first output voltage V OUT1 . In this case, similar to the case described above, the first output voltage V OUT1 Can have V COARSE -V FINE +V MID Is set in the above-described voltage level.
Subsequently, in the interval T2 to T3, the reset switch 230_1 can reset the parasitic capacitance of the capacitor based on the reset signal RST.
Then, as shown in FIG. 16, T phi is set in the interval T3 to T4 PRE2 When the fourth to sixth synchronous main switches SW_P4 to SW_P5 and the second synchronous sub-switch 211_4 are in accordance with the second synchronous control signal Φ PRE2 When the switching is performed, the control unit 200 may form a fifth equivalent circuit.
Specifically, T phi is within the interval T3-T4 PRE2 The fourth synchronous main switch sw_p4 and the second synchronous auxiliary switch 211_4 can be controlled by the second synchronous control signal Φ PRE2 Based on the third charging voltage V C3 The third capacitor 203 is charged. The interval T1 to T4 may correspond to the first charging interval H1 of fig. 1.
In this case, the fifth and sixth synchronous main switches sw_p5 and sw_p6 may apply the fourth charging voltage V charged to the fourth capacitor 204 to the inverting input terminal (-) of the amplifying section 300 and the output node 301 of the amplifying section 300 C4 . Thereby, the amplifying section 300 can output the second output voltage V OUT2 。
In this case, as shown in FIG. 14, the first output voltage V OUT1 May be greater than the second output voltage V OUT2 Is set in the above-described voltage level. That is, in the section T1 to T2, the pre-emphasis operation can be driven.
Then, in the interval T4 to T5, the reset switch 230_1 can reset the parasitic capacitance of the capacitor based on the reset signal RST.
Next, as shown in fig. 17, T Φ is a section T5 to T6 PRE3 When the first to ninth synchronous main switches SW_P7 to SW_P9 and the third synchronous sub-switch 211_5 are in accordance with the third synchronous control signal Φ PRE3 When the switching is performed, the control unit 200 may form a sixth equivalent circuit.
Specifically, T phi is within the interval T5-T6 PRE3 The seventh synchronous main switch sw_p7 and the third synchronous auxiliary switch 211_5 can be controlled by the third synchronous control signal Φ PRE3 Based on the second charging voltage V C2 The second capacitor C2 is charged.
And, in the interval T5-T6T phi PRE3 The eighth and ninth synchronous switches SW_P8 and SW_P9 can be controlled by the third synchronous control signal Φ PRE3 The first charging voltage V for charging the first capacitor C1 is applied to the inverting input terminal (-) of the amplifying section 300 and the output terminal 301 of the amplifying section 300 on the basis of the first charging voltage V C1 。
Subsequently, in the interval T6 to T7, the reset switch 230_1 can reset the parasitic capacitance of the capacitor based on the reset signal RST.
Then, as shown in FIG. 18, T phi is set in the interval T7 to T8 PRE4 When the tenth to twelfth synchronous main switches sw_p10 to sw_p12 and the fourth synchronous sub-switch 211_6 are in accordance with the fourth synchronous control signal Φ PRE4 When switching is performed, the control section 200 may form a seventh equivalent circuit.
Specifically, T phi is within the interval T7-T8 PRE4 The tenth synchronous main switch sw_p10 and the fourth synchronous auxiliary switch 211_6 can be controlled by the fourth synchronous control signal Φ PRE4 Based on the fourth charging voltage V C4 The fourth capacitor 204 is charged. The interval T5 to T8 may correspond to the second charging interval H2 of fig. 1.
In this case, the eleventh and twelfth synchronous main switches sw_p11 and sw_p12 may apply the third charging voltage V to charge the third capacitor 203 to the inverting input terminal (-) of the amplifying section 300 and the output node 301 of the amplifying section 300 C3 . Thus, the amplifying section 300 can output the fourth output voltage V OUT4 。
Fig. 19 is a diagram showing a display device 1000 to which the output driver described in fig. 1 to 18 is applied. Referring to fig. 19, the display device 1000 may include an output driver 1100, a data driver 1200, and a display panel 1300.
The data driver 1200 may receive pixel data for driving the display panel 1300 and transmit a digital signal to the output driver 1100. For example, the digital signal may be a signal for generating a coarse voltage and a fine voltage.
The display panel 1300 can display an image in frame units based on the output voltage received through the output driver 1100. For example, the display panel 1300 may be a liquid crystal display (LCD, liquid crystal display), a light emitting diode (LED, light emitting diode) display, an Organic Light Emitting Diode (OLED) display, an active-matrix organic light emitting diode (AMOLED) display, a flexible (flexible) display, or the like, but may be other types of flat panel displays.
In an embodiment of the technical idea of the present invention, the output driver 1100 may be driven by the output driver illustrated in fig. 1 to 18.
Fig. 20 is a diagram showing an example of an output driver applied to the control unit and the amplifying unit described in fig. 1 to 18, and fig. 21 is a diagram showing the digital-analog converter 2300 in fig. 20 in further detail.
As shown in fig. 20, the output driver 2000 may include a shift register 2100, a data latch 2200, a digital-to-analog converter 2300 (DAC, digital Analog Converter), and an output buffer 2400.
The shift register 2100 may include a plurality of stages (not shown) that are attached. The plurality of stages may receive a data clock signal. A horizontal start signal may be applied to a first stage of the plurality of stages. If the operation of the first stage is started by the horizontal start signal, the plurality of stages may sequentially output control signals in response to the data clock signal (CLK).
The data latch 2200 may include a plurality of latch circuits. The plurality of latch circuits may sequentially receive control signals from the plurality of stages. The data latch 2200 may store the image data (RGB) in pixel units. The plurality of latch circuits may store video data corresponding to the video data (RGB) by responding to the control signals, respectively. The latch 320 may provide the digital-to-analog converter 2300 with image data (RGB) corresponding to the stored pixel row size.
The digital-analog converter 2300 may receive the reference demodulation voltage generated from the gradation voltage generation section. The digital-to-analog converter 2300 may include a plurality of digital-to-analog converter circuits corresponding to a plurality of data latch circuits. The digital-to-analog converter 2300 converts the image data of the pixel row size supplied from the data latch 2200 into a gradation voltage.
The output buffer 2400 receives the demodulation voltage from the digital-to-analog converter 2300. The output buffer 2400 may buffer the gradation voltage and provide the same to the data line.
In an embodiment of the technical idea of the present invention, the output buffer 2400 may include the control section and the amplifying section described in fig. 1 to 18.
Referring to fig. 21, the digital-to-analog converter 2300 may include an M-bit decoder 2310 and an N-bit decoder 2320. For example, the M-bit decoder 2310 may generate the coarse tuning voltages illustrated in fig. 1-18. The N-bit decoder 2320 may generate the trim voltages illustrated in fig. 1-18.
For example, the M-bit decoder 2310 may generate a coarse adjustment voltage based on the data signal received from the gamma generation unit 3000 by a voltage division method and output the generated coarse adjustment voltage. The N-bit decoder 2320 can generate a trimming voltage by a voltage distribution method based on the data signal received from the gamma generation unit 3000 and output the generated trimming voltage.
As described above, the output driver of the display device of an embodiment of the present invention can reduce the time required for decoding and can be driven at high speed by performing sampling work and driving work in parallel. Furthermore, the present invention has an advantage in that since the feedback factor in the feedback amplifier configuration is "1", the bandwidth of the amplifier can be maximally utilized, and thus high-speed driving can be achieved.
In addition, the output driver of the display device according to an embodiment of the present invention may support the pre-emphasis operation and may increase a Slew Rate (Slew Rate) based on a distance between the data driver and the display panel.
Also, the output driver of the display device of an embodiment of the present invention can reduce an influence due to parasitic effects of the capacitor by connecting one end of the capacitor to the inverting input terminal of the amplifier serving as a virtual ground.
Also, the output driver of the display device according to an embodiment of the present invention may realize an output voltage corresponding to a desired driving voltage, although there is a deviation between the first capacitor and the second capacitor.
The output driver of the display device according to the embodiment of the present invention may store the required data voltage in one capacitor through the coarse tuning decoder and the fine tuning decoder, and output the data voltage in the pixel of the display device through the amplifying section. In this case, since the data voltage is stored in one capacitor, an error of the data voltage in one channel is eliminated. Thus, output variations within a driver including a plurality of channels can be reduced.
The embodiments of the present invention disclosed in the present specification and the accompanying drawings are merely specific examples for easily explaining the technical contents of the present invention and are provided to aid understanding of the present invention, and do not limit the scope of the present invention. It is apparent that other modifications based on the technical idea of the present invention can be implemented by those skilled in the art to which the present invention pertains in addition to the embodiments disclosed herein.
Industrial applicability
The invention relates to an output driver of a display device, which can reduce decoding time and realize high-speed driving, and has industrial applicability.
Claims (9)
1. An output driver, comprising:
a digital-to-analog converter for generating a first voltage and a second voltage different from the first voltage;
a control unit that alternately charges a first capacitor and a second capacitor based on a voltage difference between the first voltage and the second voltage; and
an amplifying section for alternately receiving and outputting the respective charging voltages charged in the first capacitor and the second capacitor,
wherein the control section outputs the second charging voltage charged in the second capacitor to the output node of the amplifying section at a first charging time for charging the first capacitor with the first charging voltage,
The control unit further includes a pre-emphasis control unit that performs a switching operation of applying one of the first voltage and the second voltage to a non-inverting input terminal of the amplifying unit in a partial section of the first charging time and the second charging time for charging the second capacitor, and applying a predetermined medium voltage to the non-inverting input terminal in a remaining section other than the partial section.
2. The output driver of claim 1, wherein,
at the first charging time, the control section connects one side of the second capacitor to an inverting input terminal of the amplifying section, and connects the other side of the second capacitor to the output node.
3. The output driver of claim 1, wherein,
at a second charging time for charging the second capacitor, the control section outputs a charging voltage charged in the first capacitor to the output node.
4. The output driver of claim 3, wherein,
at the second charging time, the control section connects one side of the first capacitor to an inverting input terminal of the amplifying section, and connects the other side of the first capacitor to the output node.
5. The output driver of claim 1, wherein,
the amplifying section receives the second charging voltage through an inverting input terminal, receives the medium voltage through the non-inverting input terminal, and outputs the medium voltage through the output node.
6. The output driver of claim 5, wherein the output driver is configured to,
the control unit electrically connects the non-inverting input terminal and the inverting input terminal between the first charging time and the second charging time.
7. The output driver of claim 5, wherein the output driver is configured to,
the display device further includes a delay unit for delaying a time for outputting the output voltage to the display panel by a predetermined time.
8. An output driver, comprising:
a digital-to-analog converter for generating a first voltage and a second voltage different from the first voltage;
a control part for sequentially charging the first to fourth capacitors with a charging voltage based on a voltage difference between the first voltage and the second voltage; and
an amplifying section for outputting the charging voltages charged in the first to fourth capacitors to an output node,
wherein the control section connects the second capacitor to the output node of the amplifying section during charging of the first capacitor, connects the fourth capacitor to the output node of the amplifying section during charging of the third capacitor,
The control unit further includes a pre-emphasis control unit that performs a switching operation in which one of the first voltage and the second voltage is applied to a non-inverting input terminal of the amplifying unit during a partial section of a first charging time for charging the first capacitor and the third capacitor and a second charging time for charging the second capacitor and the fourth capacitor, and a predetermined medium voltage is applied to the non-inverting input terminal during a remaining section other than the partial section.
9. The output driver of claim 8, wherein the output driver is configured to,
the control section connects the third capacitor to the output node of the amplifying section during charging of the second capacitor, and connects the first capacitor to the output node of the amplifying section during charging of the fourth capacitor.
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| KR10-2019-0059745 | 2019-05-21 | ||
| KR1020190059745A KR102112328B1 (en) | 2019-05-21 | 2019-05-21 | The output driver of display device |
| PCT/KR2019/006390 WO2020235731A1 (en) | 2019-05-21 | 2019-05-28 | Output driver of display device |
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Also Published As
| Publication number | Publication date |
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| CN113678188A (en) | 2021-11-19 |
| KR102112328B1 (en) | 2020-05-19 |
| WO2020235731A1 (en) | 2020-11-26 |
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