JP2010117466A - Data driver, integrated circuit device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data driver for eliminating color irregularity of a display image, and electronic equipment. <P>SOLUTION: This data driver includes driver circuits 100-1 to 100-k (k is a natural number of 2 or more) for driving a plurality of data lines of an electro-optical panel. The plurality of data lines are divided into first to n-th blocks (n is a natural number of 2 or more) each of which has first to k-th data lines. The driver circuits 100-1 to 100-k drive the first to k-th data lines of the i-th block (i is a natural number of n-1 or less), then perform scan driving of driving the first to k-th data lines of the i+1-th block. The driver circuit 100-k, when driving the k-th data line of the i-th block, outputs data voltage Vki-ΔV corrected based on data GD1i+1 for correction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a data driver, an integrated circuit device, an electronic device, and the like.

  In a liquid crystal panel (electro-optical panel), it is known that a parasitic capacitance exists between data lines for the structural reason. The parasitic capacitance between the data lines causes color unevenness in the display image and causes image quality to deteriorate.

  For example, the present applicant has developed a data driver of a scan driving system that divides a data line of a liquid crystal panel into a plurality of blocks and sequentially drives the blocks. However, it has been found that this scan driving method has a problem that color unevenness occurs at the boundary between blocks. Specifically, when one block is driven and the next block is driven, the driven data voltage causes the data voltage of the previous block to fluctuate via the parasitic capacitance between the data lines, resulting in color unevenness. There is a problem of making it.

  Patent Document 1 discloses a technique for reducing the influence of parasitic capacitance by devising the arrangement of data lines and pixels inside a liquid crystal panel. However, this method has a problem of reducing the aperture ratio of the pixel while reducing the influence of the parasitic capacitance.

Here, in the data driver of the liquid crystal panel, there is also a problem that color unevenness occurs in the display image due to the offset of the data line driving circuit (operational amplifier). In addition, the scan drive type data driver has a problem that color unevenness due to offset occurs in addition to color unevenness at the block boundary due to parasitic capacitance.
JP 2000-10123 A

  According to some embodiments of the present invention, it is possible to provide a data driver, an integrated circuit device, an electronic device, and the like that eliminate uneven color in a display image.

  One embodiment of the present invention includes first to k-th (k is a natural number of 2 or more) driver circuits for driving a plurality of data lines of an electro-optical panel, and the plurality of data lines are arranged in first to first blocks. The first to nth blocks (n is a natural number of 2 or more) including the kth data line are divided into blocks, and the first to kth driver circuits are included in the first to nth blocks. After driving the 1st to k-th data lines of the i-th block (i is a natural number equal to or less than n−1), the 1st to k-th blocks of the i + 1-th block among the first to n-th blocks. Scan driving for driving the data line is performed, and when the k-th driver circuit among the first to k-th driver circuits drives the k-th data line of the i-th block, the correction data is used as the correction data. The present invention relates to a data driver that outputs a corrected data voltage.

  Here, when the electro-optical panel is driven by the scan driving type data driver, the voltage of the kth data line of each block varies from the first data line of the next driven block through the parasitic capacitance. As a result, there is a problem that uneven color occurs at the boundary of the block.

  In this regard, according to one aspect of the present invention, the first to kth driver circuits sequentially drive the first to nth blocks of the plurality of data lines of the electro-optical panel, and at this time, the kth driver circuit Outputs a data voltage corrected based on the correction data, and drives the kth data line which is the data line at the end of each block of the first to nth blocks.

  As described above, according to an aspect of the present invention, the kth driver circuit outputs the data voltage corrected based on the correction data, and the kth data of each of the first to nth blocks is output. Drive the line. Therefore, the k-th driver circuit can correct and output the data voltage of the k-th data line of each block in advance for the voltage fluctuation received from the first data line of the next block. When the first data line of the next block is driven, the correction amount and the voltage fluctuation amount cancel each other, and the voltage of the kth data line of each block can be set to a desired data voltage. As a result, the data voltage can be written to the pixels at the block boundary with high accuracy, and color unevenness at the block boundary can be prevented.

  In one embodiment of the present invention, each of the first to kth driver circuits receives grayscale data and a data line driving circuit that drives a data line, and performs D / A conversion of the grayscale data. A D / A conversion circuit, and the k-th driver circuit further includes a correction D / A conversion circuit that receives the correction data and performs D / A conversion of the correction data. The data line driving circuit of the k-th driver circuit outputs a data voltage based on the voltage from the D / A conversion circuit of the k-th driver circuit and the voltage from the correction D / A conversion circuit May be.

  According to one aspect of the present invention, in the k-th driver circuit, the correction D / A conversion circuit D / A converts the correction data, and the data line driving circuit is based on the D / A converted voltage. The corrected data voltage can be output. Accordingly, it is possible to realize that the kth driver circuit outputs the data voltage corrected based on the correction data and drives the kth data line of each block.

  In the aspect of the invention, the correction D / A converter circuit may include gradation data corresponding to the first data line of the i + 1th block, or the first data line of the i + 1th block. Data generated by performing predetermined arithmetic processing on the corresponding gradation data may be input as the correction data.

  Thereby, the correction data can be realized. Specifically, the D / A conversion circuit for correction performs D / A conversion on the correction data, so that the kth data line of each block starts from the first data line of the block to be driven next. A voltage corresponding to the received voltage fluctuation can be output to the data line driving circuit.

  In one embodiment of the present invention, the data line driver circuit of the kth driver circuit includes an operational amplifier, a first input terminal of the operational amplifier, and the D / A converter circuit of the kth driver circuit. An input capacitor provided between the output node and a correction capacitor provided between the first input terminal and the output node of the correction D / A converter circuit may be included. .

  According to one embodiment of the present invention, a kth driver circuit that outputs a data voltage based on a voltage from a D / A conversion circuit and a voltage from a correction D / A conversion circuit can be realized. Further, the offset of the operational amplifier can be canceled by using the input capacitor and the correction capacitor. As a result, the data line driving circuit can output the data voltage with high accuracy.

  In one embodiment of the present invention, a gradation voltage generation circuit that outputs a gradation voltage to the D / A conversion circuit of the first to kth driver circuits, and the correction circuit for the kth driver circuit. A correction voltage generation circuit that outputs a correction voltage to the D / A conversion circuit.

  As a result, the gradation voltage for the D / A conversion circuit to D / A convert the gradation data and the correction voltage for the correction D / A conversion circuit to D / A convert the correction data can be generated. . Further, by including the correction D / A conversion circuit, the correction voltage can be generated independently of the gradation voltage, and the kth driver circuit can appropriately correct the data voltage.

  In the aspect of the invention, the correction voltage generation circuit may output a correction voltage corresponding to a gradation characteristic of the gradation voltage output from the gradation voltage generation circuit.

  Here, the magnitude and sign of the voltage fluctuation received by the kth data line of each block depend on the data voltage output to the first data line of the next driven block. Since this data voltage is determined by the gradation characteristics of the gradation voltage output from the gradation voltage generation circuit, the magnitude and sign of the voltage fluctuation received by the kth data line of each block also depend on the gradation characteristics. .

  In this regard, according to one aspect of the present invention, the correction voltage generation circuit outputs a correction voltage corresponding to the gradation characteristics of the gradation voltage output from the gradation voltage generation circuit. Therefore, the correction corresponding to the voltage fluctuation can be performed by correcting the data voltage using the correction voltage.

  In the aspect of the invention, when the gradation voltage generation circuit outputs a gradation voltage that monotonously increases with respect to the gradation data, the correction voltage generation circuit monotonously decreases with respect to the gradation data. When the gradation voltage is output as the correction voltage and the gradation voltage generation circuit outputs a gradation voltage that monotonously decreases with respect to the gradation data, the correction voltage generation circuit outputs the gradation voltage to the gradation data. Alternatively, a gradation voltage that monotonously increases may be output as the correction voltage.

  In this way, a correction voltage corresponding to the gradation characteristics of the gradation voltage output from the gradation voltage generation circuit can be realized. Specifically, by using a correction voltage whose increase and decrease is opposite to the gradation characteristics of the gradation voltage, the voltage fluctuation and the sign are opposite to the voltage fluctuation depending on the gradation characteristics of the gradation voltage. Can be realized. Thereby, the correction | amendment which offsets a voltage fluctuation is realizable.

  In the aspect of the invention, the correction voltage generation circuit may multiply the gradation characteristic that is line-symmetric with respect to a predetermined voltage with respect to the gradation characteristic of the gradation voltage output from the gradation voltage generation circuit by a proportional coefficient. The correction voltage having the above-described gradation characteristics may be output.

  In this way, it is possible to realize a correction voltage that monotonously decreases with respect to a monotonically increasing gradation voltage or a correction voltage that monotonously increases with respect to a monotonously decreasing gradation voltage. Further, it is possible to realize correction using gradation data corresponding to the first data line of the next driven block (i + 1th block) as correction data.

  In one embodiment of the present invention, the gradation voltage generation circuit outputs a gradation voltage having a non-linear gradation characteristic, and the correction voltage generation circuit outputs a correction voltage having a linear gradation characteristic. May be.

  As a result, correction is performed using the data generated by performing predetermined arithmetic processing on the gradation data corresponding to the first data line of the next driven block (i + 1th block) as correction data. realizable. By performing predetermined arithmetic processing, the correction D / A conversion circuit can output the correction voltage corresponding to the gradation characteristics of the gradation voltage output from the gradation voltage generation circuit.

  In one embodiment of the present invention, the data line driver circuit of the kth driver circuit has a summing node connected to the first input terminal, an analog reference power supply supplied to the second input terminal, and an output terminal An operational amplifier to which an output node is connected, and a first switch provided between an input node to which a grayscale voltage from the D / A converter circuit of the kth driver circuit is supplied and a first node An input capacitor provided between the first node and the summing node; a second switch element provided between the first node and an analog reference power supply; and the summing node. A feedback capacitor provided between the second node and the second node; a third switch element provided between the second node and the output node; the second node; an analog reference power supply; Between A fourth switching element provided; a fifth switching element provided between the summing node and the output node; and a correction voltage to which a correction voltage from the correction D / A conversion circuit is input. A first correction switch element provided between an input node and a third node; a correction capacitor provided between the third node and the summing node; and the third node; And a second correction switch element provided between the correction reference voltage node to which the correction reference voltage is supplied.

  In this way, a data line driving circuit of the kth driver circuit having the input capacitor and the correction capacitor can be realized. In addition, a switched capacitor circuit including an input capacitor, a correction capacitor, and a feedback capacitor can be configured. Thereby, the offset of the operational amplifier can be canceled, and an offset-free data line driving circuit can be realized.

  In the aspect of the invention, the correction D / A conversion circuit may output a voltage corresponding to a precharge voltage as the correction reference voltage at the time of initialization.

  In this way, the correction reference voltage can be supplied to the data line driving circuit. Further, by using the correction D / A conversion circuit, the correction reference voltage can be adjusted, and the optimum correction reference voltage can be supplied to the data line driving circuit.

  Another aspect of the present invention relates to an integrated circuit device including the data driver described above.

  Another aspect of the invention relates to an electronic apparatus including the integrated circuit device described above.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Scan driving 1.1. Electro-Optical Device Before describing the data driver of this embodiment, scan driving will be described with reference to FIGS. Hereinafter, a liquid crystal display device that drives a liquid crystal panel will be described as an example of the electro-optical device. However, the present invention can also be applied to an electro-optical device that drives an electro-optical panel other than the liquid crystal panel. For example, the present invention can also be applied to an electro-optical device that drives an EL panel using a self-luminous element such as an organic EL (Electro Luminescence) element or an inorganic EL element.

  FIG. 1 shows a configuration example of a liquid crystal display device (in a broad sense, an electro-optical device) to which the data driver of this embodiment can be applied. This configuration example includes a liquid crystal panel 12 (electro-optical panel and display panel in a broad sense), a driver 60 (integrated circuit device in a broad sense), a display controller 40, and a power supply circuit 50. Note that it is not necessary to include all these circuit blocks in the liquid crystal display device, and some of the circuit blocks may be omitted.

  The liquid crystal panel 12 (LCD: Liquid Crystal Display) can be composed of an active matrix panel or a simple matrix panel. For example, in an active matrix panel, the liquid crystal panel 12 is formed on an active matrix substrate (for example, a glass substrate). The active matrix substrate includes a plurality of scanning lines G1 to Gm (m is a natural number of 2 or more) extending in the X direction in FIG. 1 and a plurality of data lines SR1, SG1, SB1,. SGn and SBn (n is a natural number of 2 or more) are arranged. The active matrix substrate includes switch elements SWR1, SWG1, SWB1,..., SWRn, SWGn, SWBn, a shift register SF, and data voltage supply lines SR, SG, SB (source voltage supply) corresponding to each data line. Line).

  Thin film transistors (TFT: Thin Film Transistor, switching elements in a broad sense) and liquid crystal capacitors (liquid crystal elements, electro-optical elements in a broad sense) are provided at positions corresponding to the intersections of scanning lines and data lines. For example, a thin film transistor TR and a liquid crystal capacitor CL are provided at a position corresponding to the intersection of the scanning line G1 and the data line SR1. The gate electrode of TR is connected to the scanning line G1, the source electrode of TR is connected to the data line SR1, and the drain electrode of TR is connected to the pixel electrode PE. A liquid crystal capacitor CL is formed between the pixel electrode PE and the counter electrode CE (common electrode, common electrode). The counter electrode CE is formed on a counter substrate facing the active matrix substrate, and liquid crystal (electro-optical material in a broad sense) is sealed between the active matrix substrate and the counter substrate.

  Here, the data lines SR1, SG1, SB1,..., SRn, SGn, SBn are divided into blocks (groups) from the first block (SR1, SG1, SB1) to the nth block (SRn, SGn, SBn). It is assumed that it is divided and divided. The liquid crystal panel 12 is driven by a scan driving method in which the data lines of the first to nth blocks are sequentially driven.

  Specifically, the switch elements SWR1, SWG1, SWB1,..., SWRn, SWGn, SWBn receive the grayscale voltages (grayscale signals) supplied to the data voltage supply lines SR, SG, SB in a time division manner. The data lines are divided and supplied to data lines of 1st to nth blocks.

  The shift register SF outputs a control signal for on / off control of the switch elements SWR1, SWG1, SWB1,..., SWRn, SWGn, SWBn. The shift register SF receives the scan drive clock signal CLK from the data driver 20, and sequentially activates the control signals Sig1 to Sign (first logic level).

  When the control signal Sig1 is activated, the switch elements SWR1, SWG1, and SWB1 are turned on, and the data lines SR1, SG1, and SB1 of the first block are driven. When the control signal Sig2 is activated, the switch elements SWR2, SWG2, and SWB2 are turned on, and the data lines SR2, SG2, and SB2 of the second block are driven. When the control signal Sign is activated, the switch elements SWRn, SWGn, SWBn are turned on, and the data lines SRn, SGn, SBn of the nth block are driven. In this way, the data lines of the first to nth blocks are sequentially driven, and scan driving is performed.

  Note that the switch elements SWR1, SWG1, SWB1,..., SWRn, SWGn, SWBn and the shift register SF can be configured using, for example, thin film transistors TFT.

  The driver 60 includes a data driver 20 (source driver) and a scan driver 38 (gate driver). The data driver 20 drives the data voltage supply lines SR, SG, SB of the liquid crystal panel 12 based on the gradation data (image data). As described above, the data driver 20 performs scan driving for sequentially driving the data lines of the first to nth blocks. The scanning driver 38 scans (sequentially drives) the scanning lines G1 to Gm of the liquid crystal panel 12. Note that a data driver of the present embodiment described later can be applied to the driver 60.

  The display controller 40 controls the data driver 20, the scan driver 38, and the power supply circuit 50 according to the contents set by a host controller such as a CPU (Central Processing Unit) (not shown). Specifically, the display controller 40 supplies, for example, an operation mode setting and internally generated vertical synchronization signal and horizontal synchronization signal to the data driver 20 and the scan driver 38. For the power supply circuit 50, for example, the voltage level of the common electrode voltage VCOM applied to the common electrode CE is controlled.

  The power supply circuit 50 generates various voltage levels necessary for driving the liquid crystal panel 12 and the voltage level of the common electrode voltage VCOM of the common electrode CE based on a power supply voltage supplied from the outside. For example, the gradation voltage generation circuit is built in the data driver 20, and the power supply circuit 50 can generate the voltage level of the power supply voltage of the gradation voltage generation circuit.

  The data driver 20 may drive the liquid crystal panel 12 with polarity inversion. At this time, the gradation voltage generation circuit may include a gradation voltage generation circuit for positive polarity and negative polarity. Alternatively, the high-voltage side power supply voltage and the low-voltage side power supply voltage of the grayscale voltage generation circuit may be alternately switched to generate positive and negative grayscale voltages.

  Here, in FIG. 1, the data driver 20 has been described as sequentially driving three data lines for each of RGB color components via the data voltage supply lines SR, SG, and SB. However, in the present invention, the data driver 20 may sequentially drive k data lines one by one via the data voltage supply lines S1 to Sk (k is a natural number of 2 or more).

  In FIG. 1, the display controller 40 and the power supply circuit 50 are provided inside the liquid crystal display device 10. However, in the present invention, the display controller 40 and the power supply circuit 50 may be provided outside the liquid crystal display device 10. Further, in the present invention, some or all of the data driver 20, the scan driver 38, the display controller 40, and the power supply circuit 50 may be formed on the liquid crystal panel 12, and the data driver 20, the scan driver 38, the display controller 40, the power supply A part or all of the circuit 50 may be configured as a semiconductor device (integrated circuit, IC).

1.2. Data Driver FIG. 2 shows a configuration example of the data driver 20. This configuration example includes a shift register 22, line latches 24 and 26, a multiplexing circuit 28, a gradation voltage generation circuit 30 (reference voltage generation circuit), a DAC 32 (DAC: Digital to Analog Converter, data voltage generation circuit), a data line. A drive circuit 34 (source line drive circuit) and a scan drive control unit 36 are included.

  The shift register 22 includes a flip-flop corresponding to each data line. The flip-flops are sequentially connected. When the leading flip-flop holds the enable input / output signal EIO, the shift register 22 sequentially shifts the enable input / output signal EIO to adjacent flip-flops in synchronization with the dot clock signal DCLK.

  The line latch 24 includes a latch (image data register) corresponding to each data line. The gradation data DIO is input from the display controller 40 to the line latch 24. Each latch of the line latch 24 latches gradation data corresponding to each data line in synchronization with the sequentially shifted enable input / output signal EIO from the shift register 22.

  The line latch 26 latches the grayscale data for one horizontal scan latched by the line latch 24 in synchronization with the horizontal synchronization signal LP supplied from the display controller 40.

  The multiplexing circuit 28 time-division multiplexes the gradation data corresponding to each data line from the line latch 26, and the time-division multiplexed gradation corresponding to the data voltage supply lines SR, SG, SB (S1 to Sk). Generate data.

  The scan drive control unit 36 generates a scan drive clock signal CLK that defines time division timing of scan drive. Specifically, the scan drive control unit 36 generates n clocks for sequentially driving the first to nth blocks within one horizontal scanning period. Then, the multiplexing circuit 28 receives the CLK and time-division multiplexes the grayscale data for the first to nth blocks in one horizontal scanning period. Further, the shift register SF of the liquid crystal panel 12 receives the CLK and sequentially turns on / off the switch elements of the first to nth blocks.

  The gradation voltage generation circuit 30 (gradation signal generation circuit) generates a gradation voltage (gradation signal) and supplies the gradation voltage to the DAC 32.

  The DAC 32 (D / A conversion circuit) generates a data voltage (source voltage) to be supplied to each data line (source line). Specifically, the DAC 32 selects one of the gradation voltages from the gradation voltage generation circuit 30 based on the digital gradation data from the multiplexing circuit 28, and uses the selected gradation voltage as an analog data voltage. Output.

  The data line driving circuit 34 buffers the data voltage from the DAC 32 and drives the data line. For example, the data line driving circuit 34 includes a voltage follower connection operational amplifier provided for each data line. Each operational amplifier buffers the data voltage from the DAC 32 and outputs it to each data line.

1.3. Explanation of Operation of Scan Drive FIG. 3 is a diagram for explaining the operation of the multiplexing circuit 28.

  In FIG. 3, the gradation data for the data lines SR1 and SG1 of the first block are R1 and G1, and the gradation data for the data lines SR2 and SG2 of the second block are R2 and G2.

  The multiplexing circuit 28 receives the first scan driving clock signal CLK in one horizontal scanning period indicated by A1, and selects the gradation data R1 for the data line SR1 of the first block as indicated by A2. And output. The multiplexing circuit 28 receives the second scan drive clock signal CLK indicated by A3, and selects and outputs the gradation data R2 for the data line SR2 of the second block, as indicated by A4. In this way, the multiplexing circuit 28 outputs multiplexed data for the data voltage supply line SR in which the gradation data R1, R2,... Are time-division multiplexed. Similarly, multiplexed data for the data voltage supply line SG in which the grayscale data G1, G2,... Are time-division multiplexed is output.

  The DAC 32 selects a gradation voltage corresponding to the multiplexed gradation data from the multiplexing circuit 28 from the gradation voltages from the gradation voltage generation circuit 30, and outputs the selected gradation voltage as a multiplexed gradation voltage. To do.

  FIG. 4 is a diagram for explaining the operation of the scan driving type liquid crystal panel.

  The data line driving circuit 34 receives the multiplexed gradation voltage from the DAC 32 and outputs the multiplexed data voltages VR1, VR2,... To the data voltage supply line SR. Similarly, the data line driving circuit 34 outputs the multiplexed data voltages VG1, VG2,... To the data voltage supply line SG.

  The shift register SF of the liquid crystal panel 12 receives the first scan driving clock signal CLK in one horizontal scanning period shown in B1 of FIG. 4 and activates the control signal Sig1 as shown in B2. The switch elements SWR1 and SWG1 are turned on in response to the control signal Sig1. As shown in B3, data voltages VR1 and VG1 are output to the data lines SR1 and SG1 of the first block. Similarly, the control signal Sig2 is activated as shown in B5 by the second scan drive clock signal CLK shown in B4, and the switch elements SWR2 and SWG2 are turned on. As shown in B6, data voltages VR2 and VG2 are output to the data lines SR2 and SG2 of the second block.

  3 and 4, the RG color component of the RGB color components has been described, but the same applies to the B color component. 3 and 4, the data lines of the first and second blocks have been described, but the same applies to the data lines of the third to nth blocks.

1.4. Causes of Color Unevenness When the liquid crystal panel is driven by a scan drive type data driver, there is a problem that color unevenness occurs at the block boundaries. This will be specifically described with reference to FIGS.

  FIG. 5 schematically shows an explanatory diagram of the parasitic capacitance between the data lines. As shown in FIG. 5, there is a parasitic capacitance between adjacent data lines of the liquid crystal panel because the data lines are arranged in parallel at a small pitch. For example, a parasitic capacitance Cp exists between the data line SBi (i is a natural number equal to or less than n−1) and the data line SRi + 1.

  In FIG. 5, after the data lines Ri, SGi, and SBi of the i-th block are driven, the switch elements SWRi, SWGi, and SWBi are turned off, and the data lines SRi, SGi, and SBi are in a high impedance state. Then, the data lines SRi + 1, SGi + 1, SBi + 1 of the i + 1th block are driven. Then, the drive voltage of the data line SRi + 1 is voltage-coupled to the high impedance state data line SBi via the parasitic capacitance Cp, and the data voltage of the data line SBi is changed.

  FIG. 6 schematically shows an explanatory diagram of data voltage fluctuation due to parasitic capacitance. As shown at C1 in FIG. 6, the data voltage VBi of the data line SBi is subjected to a change of ΔV when the data line SRi + 1 is driven, and becomes VBi + ΔV. Since the variation ΔV of the data voltage VBi is due to voltage coupling through the parasitic capacitance Cp, it becomes a voltage proportional to the voltage change VRi + 1−Vpre of the data line SRi + 1. Assuming that the proportionality coefficient is α, the data voltage VBi is subjected to ΔV variation shown in the following equation (1).

ΔV = α (VRi + 1−Vpre) (1)
Vpre is a precharge voltage for precharging the data line. The precharge voltage Vpre is a voltage applied to the data line before writing the data voltage to the pixel in order to write the data voltage to the pixel in a short time. The proportional coefficient α is a coefficient whose size is determined by the liquid crystal panel.

  In the example shown in FIGS. 5 and 6, the data voltage of the data line SBi receives a variation of ΔV, and this ΔV causes color unevenness of the B color component at the block boundary. As described above, the scan drive type data driver has a problem that color unevenness occurs at the boundary between blocks.

2. Data driver 2.1. Configuration Example FIG. 7 shows a configuration example of the present embodiment that can solve the above-described problems. 7 includes first to k-th (k is a natural number of 2 or more) driver circuits 100-1 to 100-k, and scans a plurality of data lines of a liquid crystal panel (electro-optical panel, display panel). A data driver to be driven.

  The driver circuits 100-1 to 100-k sequentially drive the data lines of the first to nth (n is a natural number of 2 or more) blocks as a plurality of data lines. Each of the first to nth blocks includes the first to kth data lines, and the driver circuits 100-1 to 100-k drive the first to kth data lines in each block.

  Specifically, the driver circuits 100-1 to 100-k drive the first to kth data lines (hereinafter, data lines S1i to Ski) of the i-th block (i is a natural number equal to or less than n-1). Thereafter, the first to kth data lines (hereinafter, data lines S1i + 1 to Ski + 1) of the i + 1th block are driven, and the data lines of the first to nth blocks are sequentially driven.

  Multiplexed gradation data (image data) is input to the driver circuits 100-1 to 100-k, for example, from the multiplexing circuit 28 in FIG. For example, when driving the data lines S1i to Ski, the first to (k-1) th driver circuits 100-1 to 100-k-1 receive the grayscale data GD1i to GDk-1i and receive the data voltages V1i to Vk-. 1i (source voltage) is output to the data voltage supply lines S1 to Sk-1 (source voltage supply lines). The kth driver circuit 100-k receives the gradation data GDki and the gradation data GD1i + 1 (correction data) and outputs the data voltage Vki−ΔV to the data voltage supply line Sk.

  More specifically, the driver circuit 100-k corrects the data voltage Vki corresponding to the gradation data GDki based on the gradation data GD1i + 1, and outputs the corrected data voltage Vki−ΔV. ΔV is shown in the following formula (2).

ΔV = α (V1i + 1−Vpre) (2)
As described with reference to FIG. 6 and the like, the data line Ski (for example, SBi) receives a voltage variation of ΔV from the adjacent data line S1i + 1 (SRi + 1) through the parasitic capacitance. In the configuration example of FIG. 7, the data voltage Vki−ΔV (VBi−ΔV) is output to the data line Ski (SBi). Therefore, a desired data voltage Vki (VBi) is finally written to the data line Ski (SBi).

  Thus, according to the present embodiment, when driving the data line Ski, the data voltage Vki−ΔV corrected based on the gradation data GD1i + 1 corresponding to the data line S1i + 1 is output. Therefore, the voltage variation ΔV that the data line Ski receives from the data line S1i + 1 can be corrected in advance. As a result, the data voltage can be written to the pixel at the block boundary with high accuracy, and color unevenness at the block boundary can be prevented to improve the image quality.

  In the present invention, the gradation data GD1i + 1 may be input to the driver circuit 100-k as correction data (correction gradation data) as described above. Data generated by performing predetermined arithmetic processing may be input.

2.2. First Detailed Configuration Example FIG. 8 shows a first detailed configuration example of the present embodiment. This configuration example includes driver circuits 100-1 to 100-k, a gradation voltage generation circuit 160 (gradation signal generation circuit), and a correction voltage generation circuit 180 (correction signal generation circuit).

  Specifically, the driver circuits 100-1 to 100-k-1 include first to k-1th DACs 110-1 to 110-k-1 (D / A conversion circuits), first to k-1th. Data line driving circuits 140-1 to 140-k-1 (source line driving circuits).

  The DACs 110-1 to 110-k-1 receive the gradation data GD1i to GDk-1i and D / A convert the gradation data GD1i to GDk-1i. The DACs 110-1 to 110-k-1 are gradation voltages (gradation currents, in a broad sense, levels corresponding to the gradation data GD1i to GDk-1i among a plurality of gradation voltages from the gradation voltage generation circuit 160. Tone signal) is selected and output to perform D / A conversion of the gradation data GD1i to GDk-1i.

  The data line driving circuits 140-1 to 140-k-1 drive the data lines of the liquid crystal panel (electro-optical panel). The data line driving circuits 140-1 to 140-k-1 receive the gradation voltages from the DACs 110-1 to 110-k-1, and receive data voltages V1i to Vk-1i (source voltages) corresponding to the gradation voltages. ) To the data voltage supply lines S1 to Sk-1 (source voltage supply lines).

  The driver circuit 100-k includes a kth DAC 110-k (D / A conversion circuit), a kth data line driving circuit 140-k, and a correction DAC 120 (correction D / A conversion circuit).

  The DAC 110-k receives the gradation data GDki and D / A converts the gradation data GDki. The DAC 110-k selects and outputs a gradation voltage corresponding to the gradation data GDki, like the DACs 110-1 to 110-k-1.

  The correction DAC 120 receives the gradation data GD1i + 1 (correction data) and D / A converts the gradation data GD1i + 1. The correction DAC 120 selects and outputs a correction voltage (correction current, a correction signal in a broad sense) corresponding to the gradation data GD1i + 1 from the plurality of correction voltages from the correction voltage generation circuit 180. Then, D / A conversion of the gradation data GD1i + 1 is performed.

  The kth data line driving circuit 140-k drives the data lines of the liquid crystal panel (electro-optical panel). The data line driving circuit 140-k receives the gradation voltage from the DAC 110-k and the correction voltage from the correction DAC 120, and outputs the data voltage Vki−ΔV to the data voltage supply line Sk. For example, the data line driving circuit 140-k receives the data voltage Vki as the gradation voltage from the DAC 110-k, receives -ΔV as the correction voltage from the correction DAC 120, and synthesizes them to generate the data voltage Vki-ΔV. Is output.

  The gradation voltage generation circuit 160 generates a plurality of gradation voltages. Specifically, the gradation voltage generation circuit 160 divides the power supply voltage from the power supply circuit (for example, the power supply circuit 50 shown in FIG. 1) and outputs the gradation voltage. For example, the gradation voltage generation circuit 160 may output a gradation voltage corresponding to the gamma characteristic of the liquid crystal panel. Alternatively, the gradation voltage generation circuit 160 may output a gradation voltage having a linear characteristic, and gradation data subjected to gamma correction processing may be input to the DACs 110-1 to 110-k.

  The correction voltage generation circuit 160 generates a plurality of correction voltages. Specifically, the correction voltage generation circuit 180 divides the power supply voltage from the power supply circuit (for example, the power supply circuit 50 shown in FIG. 1) and outputs the correction voltage. For example, the correction voltage generation circuit 180 outputs a correction voltage corresponding to the gamma characteristic of the liquid crystal panel, as described with reference to FIGS. 19A and 19B.

  Note that the DACs 110-1 to 110-k and the correcting DAC 120 can be realized by a selector including, for example, a CMOS transfer gate. The data line driving circuit 140-k can be realized by an inverting amplifier circuit composed of an operational amplifier and a poly resistor, for example. Alternatively, the data line driving circuit 140-k can be realized by a switched capacitor circuit described with reference to FIG. The gradation voltage generation circuit 160 and the correction voltage generation circuit 180 can be realized by a ladder resistance circuit formed of, for example, a poly resistor.

  According to the configuration example of FIG. 8, it is possible to realize the output of the data voltage Vki−ΔV corrected based on the gradation data GD1i + 1 (correction data). Specifically, the correction DAC 120 outputs a correction voltage corresponding to the gradation data GD1i + 1, and the data line driving circuit 140-k outputs the data voltage Vki−ΔV based on the correction voltage. Further, correction based on the gradation data GD1i + 1 can be realized.

  Note that the present invention is not limited to the configuration of FIG. 8, and various modifications such as omitting some of the components (for example, the gradation voltage generation circuit) or adding other components are possible. Is possible. For example, in the present invention, a correction DAC may be added to the driver circuits 100-k-1, 100-k-2, etc., and the driver circuit 100-1 is provided in order to cope with the reverse scan direction in the scan drive. A correction DAC may be added.

2.3. Second Detailed Configuration Example FIG. 9 shows a second detailed configuration example of the present embodiment. The configuration example of FIG. 9 includes DACs 110-1 to 110-k, correction DACs, data line driving circuits 140-1 to 140-k, a gradation voltage generation circuit 160, and a correction voltage generation circuit 180. In the following description, the same components as the DAC described in FIG.

  The data line driving circuits 140-1 to 140-k-1 include first to (k-1) th operational amplifiers OP1 to OPk-1 (operational amplifiers) and first to (k-1) th input capacitors CI1 to CIk-1. (Input capacitance) and first to (k-1) th feedback capacitors CF1 to CFk-1 (feedback capacitance).

  For example, in the data line driving circuit 140-1, the input capacitor CI1 is provided between the input node NI1 (output node of the DAC 110-1) and the summing node NEG1 (reference node). The feedback capacitor CF1 is provided between the summing node NEG1 and the output node S1 (data voltage supply line S1). The operational amplifier OP1 receives the voltage from the summing node NEG1 at its input terminal (first input terminal), and outputs the data voltage V1i to the output node S1 through the output terminal. Then, the data line driving circuit 140-1 multiplies the gradation voltage from the DAC 110-1 by CI1 / CF1 and outputs a data voltage V1i. The same applies to the other data line driving circuits 140-2 to 140-k-1.

  The data line driving circuit 140-k includes a kth operational amplifier OPk (operational amplifier), a kth input capacitor CIk (input capacitance), a correction capacitor CC (correction capacitance), and a kth feedback capacitor CFk ( Including the feedback capacity).

  Input capacitor CIk is provided between input node NIk (output node of DAC 110-k) and summing node NEGk. The correction capacitor CC is provided between the correction input node NIC (output node of the correction DAC 120) and the summing node NEGk. The feedback capacitor CFk is provided between the summing node NEGk and the output node Sk (data voltage supply line Sk). The operational amplifier OPk receives the voltage from the summing node NEGk at its input terminal (first input terminal), and outputs the data voltage Vki−ΔV to the output node Sk via the output terminal. The data line driving circuit 140-k multiplies the voltage from the DAC 110-k by CIk / CFk, multiplies the voltage from the correction DAC 120 by CC / CFk, and outputs the data voltage Vki-ΔV.

  Note that the operational amplifiers OP1 to OPk can be configured by, for example, class A amplifiers or class AB amplifiers configured by CMOS transistors. The input capacitors CI1 to CIk, the correction capacitor CC, and the feedback capacitors CF1 to CFk can be constituted by, for example, a polysilicon capacitor or an MIM (Metal-Insulator-Metal) capacitor.

  According to the configuration example of FIG. 9, the driver circuit 100-k that outputs the data voltage Vki-ΔV based on the voltage from the DAC 110-k and the voltage from the correction DAC 120 can be realized. Further, the offset of the operational amplifier can be canceled by using the input capacitors CI1 to CIk, the correction capacitor CC, and the feedback capacitors CF1 to CFk. Thus, the data voltages V1i to Vk-1i and Vki-ΔV can be output with high accuracy.

3. Data line driving circuit 3.1. Data line driving circuit 140-1 to 140-k-1
FIG. 10 shows a detailed configuration example of the data line driving circuits 140-1 to 140-k-1. Note that the data line driving circuit of the present embodiment is not limited to the configuration of FIG. 10, and various modifications such as omitting some of the components (for example, operational amplifiers) or adding other components are possible. It is.

  The data line driving circuit of FIG. 10 is a circuit that receives an input voltage VIN, outputs an output voltage VQ, and drives a drive target (for example, a data voltage supply line, a data line). A capacitor CF and first to fifth switch elements SW1 to SW5 are included. An operational amplifier OP (operational amplifier) can be included.

  The capacitor CI is provided between the summing node NEG (reference node, negative node, inverting input terminal node, charge storage node) and the first node N1. The capacitor CF is provided between the summing node NEG and the second node N2. Each of these capacitors CI and CF can be constituted by a plurality of unit capacitors, for example.

  The switch element SW1 is provided between the node N1 and the input node NI of the input voltage VIN. The switch element SW2 is provided between the node N1 and AGND (analog reference power supply in a broad sense). Switch element SW3 is provided between node N2 and output node NQ. Switch element SW4 is provided between node N2 and AGND (AGND node). Switch element SW5 is provided between summing node NEG and output node NQ.

  These switch elements SW1 to SW5 can be constituted by, for example, CMOS transistors. Specifically, it can be constituted by a transfer gate composed of a P-type transistor and an N-type transistor. These transistors are turned on / off by a switch control signal from a switch control signal generation circuit (not shown). AGND is, for example, an intermediate voltage (for example, AGND = (VDD + VSS) / 2) between the high potential side power source VDD (second power source) and the low potential side power source VSS (first power source). This AGND is supplied from, for example, the power supply circuit 50 of FIG.

  The operational amplifier OP has its inverting input terminal (first input terminal in a broad sense) connected to a summing node NEG and its non-inverting input terminal (second input terminal in a broad sense) set to AGND (analog reference power supply). The output voltage VQ is output to the output node NQ (output terminal).

  In the data line driving circuit of this embodiment, as shown in FIG. 10, the switch elements SW2, SW4, and SW5 are turned on during the initialization period (period in which initialization voltages are set in CI and CF).

  When the switch element SW2 is turned on in the initialization period, the other end of the capacitor CI whose one end is electrically connected to the summing node NEG is set to AGND (analog reference power supply voltage VA). Similarly, when the switch element SW4 is turned on, the other end of the capacitor CF whose one end is electrically connected to the summing node NEG is set to AGND (VA). When the switch element SW5, which is a feedback switch element, is turned on, the output of the operational amplifier OP is fed back to the inverting input terminal, and the node NEG is set to AGND by the imaginary short function of the operational amplifier OP.

  In the data line driving circuit of the present embodiment, as shown in FIG. 11, the switch elements SW1 and SW3 are turned on in the output period (period in which the output target is output and the drive target is driven).

  When the switch element SW1 is turned on in the output period, the other end of the capacitor CI whose one end is connected to the summing node NEG is set to the input voltage VIN. Further, when the switch element SW3 is turned on, the other end of the capacitor CF whose one end is connected to the summing node NEG is set to the output voltage VQ (OP output).

  FIG. 12 shows an example of signal waveforms for explaining the operation of the data line driving circuit of this embodiment. In FIG. 12, VA is an AGND voltage, for example, VA = (VDD + VSS) / 2. However, VA may be a voltage between VDD and VSS, and is not limited to (VDD + VSS) / 2.

  In the initialization period of FIG. 10, since the feedback switch element SW5 is turned on, the node NEG of the inverting input terminal of OP is the voltage of AGND of the non-inverting input terminal by the imaginary short function of the operational amplifier OP. It becomes equal to VA. However, since the operational amplifier OP has an offset due to process variations or the like, a voltage difference of the offset voltage ΔVof occurs between the voltage of the node NEG and VA as shown in FIG.

  In the data line driving circuit of the present embodiment, the offset voltage ΔVof is stored in the initialization period of FIG. 10, and the offset voltage ΔVof is canceled and the output voltage VQ is output in the output period of FIG. So-called offset free can be realized.

  As shown in FIG. 12, the input voltage VIN is inverted and amplified in the output period. Specifically, when VIN changes to the high potential side (VDD side), the output voltage VQ changes to the low potential side (VSS side), and when VIN changes to the low potential side, VQ changes to the high potential side.

  FIG. 13A shows the basic configuration of the data line driving circuit of this embodiment. As shown in FIG. 13A, the data line driving circuit (data line driving circuits 140-1 to 140-k-1) of this embodiment may include capacitors CI and CF. One end of the CI is connected to the summing node NEG, and the other end may be set to the analog reference voltage VA in the initialization period, and set to the input voltage VIN in the output period. Further, one end of the CF may be connected to the summing node NEG, and the other end may be set to the analog reference voltage VA in the initialization period and set to the output voltage VQ in the output period.

  Note that the summing node NEG (connection node between CI and CF) is set to a given voltage (for example, VA, VA−ΔVof) in the initialization period, and in the high impedance state (floating state) in the output period, Any node may be used as long as it is set to a potential. In order to realize such a function of the node NEG, the operational amplifier OP is used in FIGS. 10 and 11, but such a function may be realized by a circuit other than the operational amplifier OP.

  Next, the relationship between the input voltage VIN and the output voltage VQ in the data line driving circuit of this embodiment will be described with reference to FIGS. 13B and 13C.

  As shown in FIG. 13B, in the initialization period, VA is set at one end of the capacitors CI and CF, and VA−ΔVof is set at the other end. Here, ΔVof is an offset voltage of the operational amplifier OP.

  On the other hand, as shown in FIG. 13C, during the output period, VIN is set at one end of the capacitor CI, VA−ΔVof is set at the other end, VQ is set at one end of the capacitor CF, and VA−ΔVof is set at the other end. Is set. Therefore, the following formula (3) is established by the law of charge conservation.

CI × {VA− (VA−ΔVof)} + CF × {VA− (VA−ΔVof)}
= CI × {VIN− (VA−ΔVof)} + CF × {VQ− (VA−ΔVof)}
(3)
Therefore, the following expression (4) is established.

VQ = VA− (CI / CF) × (VIN−VA) (4)
As apparent from the above equation (4), since the offset voltage ΔVof does not appear in the output voltage VQ, so-called offset free can be realized.

  For example, a flip-around drive circuit can be considered as a drive circuit of a comparative example. The driving circuit of this comparative example includes a sampling capacitor having one end connected to the summing node NEG. Then, an input voltage is applied to the other end of the sampling capacitor in the sampling period, and a flip-around operation is performed in which the other end is connected to the output node in the hold period. In this way, the driving circuit of the comparative example accumulates electric charge according to the input voltage in the sampling capacitor during the sampling period, and outputs a voltage according to the electric charge accumulated in the sampling capacitor during the hold period.

  However, in the driving circuit of this comparative example, the output of the data line driving circuit is in a high impedance state during the sampling period, resulting in a loss in driving time.

  On the other hand, in the data line driving circuit of the present embodiment, the output voltage VQ can be continuously output by using two capacitors CI and CF. That is, in the output period after the initialization period, there is no sampling period, and the output voltage VQ corresponding to the input voltage VIN is output according to the above equation (4), so that the drive target can be continuously driven. become.

3.2. Data line driving circuit 140-k
FIG. 14 shows a detailed configuration example of the data line driving circuit 140-k. The data line driving circuit of the present embodiment is not limited to the configuration shown in FIG. 14, and various modifications such as omitting some of the components (for example, operational amplifiers) and adding other components are possible. It is.

  The data line driving circuit of FIG. 14 includes the components of the data line driving circuit described in FIG. 10 (input capacitor CI, feedback capacitor CF, first to fifth switch elements SW1 to SW5, operational amplifier OP), Further, it includes an input capacitor CC and first and second correction switch elements SWC1 and SWC2. 14 receives the input voltage VIN, receives the correction input voltage VINC, and corrects the output voltage VQ corrected based on the correction input voltage VINC, similarly to the data line drive circuit of FIG. Is a circuit that outputs.

  In the following description, the same components (capacitors CI, CF, switch elements SW1 to SW5, operational amplifier OP, etc.) as those described in FIG. 10, FIG. To do.

  The capacitor CC is provided between the summing node NEG and the third node N3. The capacitor CC can be composed of a plurality of unit capacitors, for example.

  The switch element SWC1 is provided between the node N3 and the input node NIC for correcting the input voltage VINC. The switch element SWC2 is provided between the node N3 and the correction reference voltage node NVc of the correction reference voltage Vc.

  These switch elements SWC1 and SWC2 can be constituted by, for example, CMOS transistors. Specifically, it can be constituted by a transfer gate composed of a P-type transistor and an N-type transistor. These transistors are turned on / off by a switch control signal from a switch control signal generation circuit (not shown). Vc is a voltage corresponding to the precharge voltage Vpre. For example, Vc is a voltage Vc = 2VA−Vpre in which Vpre is axisymmetric with respect to VA (AGND), or a voltage proportional thereto. This Vc is supplied from the correction DAC 120, for example.

  In the data line driving circuit of this embodiment, as shown in FIG. 14, the switch element SWC2 is turned on in the initialization period (period in which initialization voltages are set in CI, CC, and CF). In the initialization period, the node NEG is set to VA (AGND) as in FIG. When the switch element SWC2 is turned on, one end on the node N3 side of the capacitor CC is set to Vc, and the other end on the node NEG side is set to VA.

  In the data line driving circuit of this embodiment, as shown in FIG. 15, the switch element SWC1 is turned on in the output period (period in which the output target is output and the drive target is driven). Then, when the switch element SWC1 is turned on in the output period, one end of the capacitor CC on the node N3 side is set to the input voltage VINC.

  The switch elements SW1 to SW5 and the capacitors CI and CF operate in the same manner as described with reference to FIGS.

  Here, as described with reference to FIG. 12, since the operational amplifier OP has an offset due to process variation or the like, a voltage difference of the offset voltage ΔVof occurs between the voltage of the node NEG and VA. However, the data line driver circuit shown in FIGS. 14 and 15 can realize offset-free as described with reference to FIG.

  Specifically, the following equation (5) is established according to the law of conservation of charge.

CI × {VA− (VA−ΔVof)}
+ CC × {Vc− (VA−ΔVof)}
+ CF × {VA− (VA−ΔVof)}
= CI × {VIN− (VA−ΔVof)}
+ CC × {VINC− (VA−ΔVof)}
+ CF × {VQ− (VA−ΔVof)} (5)
Therefore, the following expression (6) is established.

VQ = VA− (CI / CF) × (VIN−VA)
-(CC / CF) x (VINC-Vc) (6)
As apparent from the above equation (6), since the offset voltage ΔVof does not appear in the output voltage VQ, so-called offset free can be realized.

  14 and 15, the output voltage VQ can be continuously output as compared with the flip-around drive circuit of the comparative example. That is, the use of three capacitors CI, CC, and CF eliminates the need for a sampling period, and the output voltage VQ can be continuously output according to the above equation (6) in the output period.

  FIG. 16 is a diagram for explaining the operation of the data line driving circuit of this embodiment. In FIG. 16, the leading precharge period of the horizontal scanning period (1H) is set to the initialization period described with reference to FIGS. In the output period after the initialization period, the data line driving circuit scans the plurality of data lines in a time division manner.

  Here, the precharge period is a period for precharging the data line. In the precharge period, a precharge voltage Vpre is applied to the data line from, for example, a precharge voltage generation circuit (not shown). The precharge voltage Vpre is, for example, the same voltage as the common voltage VCOM supplied to the counter electrode of the pixel. However, the precharge voltage Vpre may be a voltage different from VCOM.

  For example, in line inversion driving, the polarity of the voltage applied to the pixel is inverted every horizontal scanning period. Therefore, the data line driving circuit must drive a data voltage whose polarity is inverted every horizontal scanning period. In the present embodiment, in order to precharge the data line in the initialization period, the data voltage may be driven using the precharge voltage Vpre as an initial value. Therefore, the data line driving circuit can drive the data line in a short time.

  In this embodiment, the data line driving circuit is initialized by effectively utilizing the precharge period. Then, after the precharge is finished, the data line is switched to the output period and the data line is scan-driven. In this way, efficient data line driving is possible.

4). Correction voltage generation circuit 4.1. Example of correction voltage gradation characteristics A correction voltage generation circuit according to the present embodiment will be described in detail with reference to FIGS.

Here, as described in the above equations (4) and (6), the data line driving circuit inverts and amplifies the gradation voltage from the DAC and the correction voltage from the correction DAC and outputs the result. In the following, in order to simplify the description, the data line driving circuit amplifies the grayscale voltage from the DAC and the correction voltage from the correction DAC and outputs the amplified voltage when CI / CF = 1 and VA = 0. It will be explained as being. That is, from the above equations (4) and (6), the data line driving circuits 140-1 to 140-k-1 are
VQ = VIN (7)
The data line driving circuit 140-k
VQ = VIN + (CC / CF) × (VINC−Vc) (8)
Will be described.

  FIG. 17 shows an example of gradation characteristics of the gradation voltage output from the gradation voltage generation circuit of this embodiment. The gradation voltage generation circuit outputs, for example, a plurality of gradation voltages obtained by dividing the high voltage side power supply voltage VDH and the low voltage side power supply voltage VDL. Then, the DAC selects and outputs a gradation voltage corresponding to gradation data (for example, 256 gradations) from the plurality of gradation voltages. FIG. 17 shows an example of the gradation characteristics of the gradation voltage corresponding to this gradation data.

  As described with reference to FIG. 6 and the like, when the first data line S1i + 1 of the (i + 1) th block is driven in the scan driving, the voltage of the kth data line Ski of the ith block changes by ΔV. receive. Specifically, as shown in FIG. 17, the DAC 110-1 receives the gradation data GD1i + 1 and outputs a gradation voltage V1i + 1. From the above equation (7), the data line driving circuit 140-1 outputs the data voltage V1i + 1, and the voltage of the data line S1i + 1 changes by V1i + 1-Vpre. Then, the voltage of the data line Ski receives a variation of ΔV = α (V1i + 1−Vpre). As described above, the voltage fluctuation ΔV of the data line Ski is proportional to V1i + 1−Vpre, and becomes a voltage depending on the gradation characteristics of the gradation voltage generation circuit.

  Therefore, in the present embodiment, the correction voltage generation circuit generates a correction voltage having a gradation characteristic corresponding to the gradation characteristic of the gradation voltage generation circuit, and thus depends on the gradation characteristic of the gradation voltage generation circuit. ΔV is corrected.

  For example, as indicated by L1 in FIG. 18, the correction voltage generation circuit of the present embodiment has a line with respect to a predetermined voltage Vs (for example, Vs = (VDH + VDL) / 2) with respect to the gradation characteristic L2 of the gradation voltage generation circuit. A correction voltage having a symmetrical gradation characteristic is generated. At this time, a voltage symmetrical to the precharge voltage Vpre with respect to the predetermined voltage Vs is set as a correction reference voltage Vc (Vc = 2Vs−Vpre). Then, as shown in FIG. 19A, the correction DAC receives the gradation data GD1i + 1 (correction data) and outputs the correction voltage VINC. Since VINC-Vc is a voltage symmetrical to V1i + 1-Vpre with respect to Vs, it has an opposite sign to V1i + 1-Vpre, and the following equation (9) is established.

VINC−Vc = − (V1i + 1−Vpre) (9)
From the above equations (8) and (9), the following equation (10) is established.

VQ = VIN− (CC / CF) × (V1i + 1−Vpre) (10)
Therefore, at the time of driving the data line Ski, the data line driving circuit 140-k outputs the data voltage represented by the following expression (11) to the data line Ski.

VQ = Vki− (CC / CF) × (V1i + 1−Vpre) (11)
Here, the proportionality coefficient α of ΔV = α (V1i + 1−Vpre) is a coefficient determined by the electro-optical panel. Therefore, from the above equation (11), if adjusted so that CC / CF = α according to the electro-optical panel,
VQ = Vki-α (V1i + 1-Vpre)
= Vki-ΔV (12)
Therefore, the data voltage of the data line Ski can be corrected in advance by −ΔV. When a change in ΔV is received from the data line S1i + 1, as a result, the voltage of the data line Ski can be set to a desired Vki.

Here, as shown in FIG. 19B, the correction voltage generation circuit may output a correction voltage having gradation characteristics obtained by multiplying the gradation characteristic shown in FIG. 19A by a proportional coefficient β. At this time, Vc is also a voltage obtained by multiplying Vc in FIG. Then, as shown in FIG.
VINC−Vc = −β (V1i + 1−Vpre) (13)
And
VQ = Vki−β × (CC / CF) × (V1i + 1−Vpre) (14)
Holds. Similarly to the case of β = 1 shown in FIG. 19A, if β or CC / CF is adjusted so that β × CC / CF = α, the above equation (12) is established, and the data on the data line Ski is obtained. The voltage can be corrected by -ΔV.

4.2. Configuration Example of Correction Voltage Generation Circuit FIG. 20 shows a configuration example of the correction voltage generation circuit of this embodiment. The correction voltage generation circuit of this embodiment includes a variable resistance element Rs and resistance elements R0 to R256.

  The variable resistance element Rs and the resistance elements R0 to R256 divide the voltage between the high voltage side power supply voltage VDH and the low voltage side power supply voltage VDL by resistance and output correction voltages VG0 to VG255. The high voltage side power supply voltage VDH and the low voltage side power supply voltage VDL are supplied from, for example, a power supply circuit (for example, the power supply circuit 50 in FIG. 1).

  The variable resistance element Rs is provided, for example, between the high-voltage power supply (node to which VDH is supplied) and the resistance elements R0 to R256. At this time, β in the above equation (14) is represented by the following equation (15).

β = (R1 + R2 +... + R256) / (Rs + R0 + R1 +... + R256)
(15)
Therefore, the proportionality coefficient β of the gradation characteristic of the correction voltage can be adjusted by adjusting the resistance value of the variable resistance element Rs. The resistance value of the variable resistance element Rs can be adjusted by, for example, an instruction from a host controller (not shown), laser trimming, or the like. The variable resistance element Rs may be provided between the low voltage side power source (node to which VDL is supplied) and the resistance elements R0 to R256.

  Incidentally, the scan drive type data driver has a problem that the data line Ski at the block boundary receives a voltage variation of ΔV from the adjacent data line S1i + 1.

  In this regard, the present embodiment includes a gradation voltage generation circuit that outputs a gradation voltage to the DAC, and a correction voltage generation circuit that outputs a correction voltage to the correction DAC.

  As a result, the correction voltage can be generated independently of the gradation voltage. Then, by using the correction voltage, it is possible to appropriately correct the voltage fluctuation ΔV received by the data line Ski.

  17 to 20, the correction voltage generation circuit may output the correction voltage having the same number of gradations (for example, 256 gradations) as that of the gradation voltage generation circuit. A correction voltage having a different number of gradations (for example, 128, 64 gradations) from the circuit may be output. Alternatively, the correction voltage generation circuit may output a correction voltage having the same resolution as the gradation voltage resolution (one gradation voltage) of the gradation voltage generation circuit, or may output a correction voltage having a different resolution. May be. In this manner, by generating independent correction voltages, the number of gradations and resolution according to the required correction accuracy can be set.

  According to the present embodiment, the correction voltage generation circuit outputs a correction voltage corresponding to the gradation characteristics of the gradation voltage output from the gradation voltage generation circuit.

  Accordingly, as described with reference to FIG. 17 and the like, ΔV depends on the gradation characteristics of the gradation voltage output from the gradation voltage generation circuit, so that the data line can be obtained by using the correction voltage corresponding to the gradation characteristics. The data voltage of Ski can be corrected by -ΔV.

  For example, according to the present embodiment, when the gradation voltage generation circuit outputs a gradation voltage that monotonously increases with respect to the gradation data, the correction voltage generation circuit applies to the gradation data (correction data). A correction voltage that monotonously decreases may be output. Alternatively, when the gradation voltage generation circuit outputs a gradation voltage that monotonously decreases with respect to the gradation data, the correction voltage generation circuit monotonously increases with respect to the gradation data (correction data). May be output.

  For example, as shown in FIG. 17, the gradation voltage generating circuit outputs a gradation voltage that monotonously increases with respect to the gradation data, and as shown in FIG. A correction voltage that monotonously decreases with respect to the data may be output.

  In this way, a correction voltage corresponding to the gradation characteristics of the gradation voltage output from the gradation voltage generation circuit can be realized. Specifically, the correction voltage generation circuit can generate a correction voltage whose polarity is inverted with respect to the drive voltage V1i + 1−Vpre of the data line S1i + 1. As a result, it is possible to realize a correction of -ΔV having a polarity opposite to that of ΔV received by the data line Ski.

  Further, for example, according to the present embodiment, the correction voltage generation circuit multiplies the gradation characteristic that is line-symmetric with respect to the predetermined voltage with respect to the gradation characteristic of the gradation voltage output from the gradation voltage generation circuit by the proportional coefficient. A voltage for correcting gradation characteristics may be output.

  For example, as described in FIG. 18, the proportionality coefficient β is set to the correction voltage of the gradation characteristic L1 that is axisymmetric to the gradation characteristic L2 of the gradation voltage with respect to the predetermined voltage Vs, as described in FIG. You may multiply.

  In this way, the correction DAC receives the gradation data GD1i + 1 corresponding to the data line S1i + 1 as the correction data, and has a polarity with respect to the drive voltage V1i + 1−Vpre of the data line S1i + 1. The inverted correction voltage VINC−Vc = − (V1i + 1−Vpre) can be output. Thereby, the correction of the data voltage of the data line Ski can be realized using the gradation data GD1i + 1 as the correction data.

  Here, according to the present embodiment, the gradation voltage generation circuit outputs a gradation voltage having non-linear (non-linear characteristics, non-linear characteristics) gradation characteristics, and the correction voltage generation circuit is linear (linear characteristics, A correction voltage having a linear characteristic) may be output.

  For example, as shown in FIG. 17, the gradation voltage generation circuit outputs a gradation voltage having a non-linear characteristic in which one gradation voltage is not equally spaced with respect to the gradation data, and as shown in FIG. The correction voltage generation circuit may output a correction voltage having a linear characteristic in which one gradation voltage is equidistant from the gradation data (correction data).

  At this time, the correction DAC may receive, as correction data, data obtained by performing predetermined arithmetic processing on the gradation data GD1i + 1 by an image processing unit (not shown), and may output the correction voltage VINC. Specifically, the correction voltage VINC satisfying VINC−Vc = − (V1i + 1−Vpre) may be output by receiving data obtained by performing a predetermined calculation process on GD1i + 1.

  In this way, a correction voltage corresponding to the gradation characteristics of the gradation voltage output from the gradation voltage generation circuit can be realized. Further, by using data obtained by performing predetermined arithmetic processing on the gradation data GD1i + 1, a correction voltage generation circuit can be configured with a simple equidistant ladder resistor or the like.

  Further, according to the present embodiment, the correction DAC may output a voltage corresponding to the precharge voltage Vpre at the time of initialization. Specifically, the correction DAC may output the correction reference voltage Vc as a voltage corresponding to the precharge voltage Vpre.

  For example, as described with reference to FIGS. 18, 19A, and 19B, a voltage that is symmetric with respect to Vpre with respect to Vs, or a voltage that is symmetric with respect to Vpre with respect to Vpre is multiplied by β as the correction reference voltage Vc. It may be output. Alternatively, a voltage substantially the same as these voltages may be output as the correction reference voltage Vc. For example, as shown in FIG. 18, in the gradation characteristic L2 of the gradation voltage generation circuit, the gradation voltage closest to Vpre (the gradation voltage closest to the high voltage side and the gradation voltage closest to the low voltage side) is supported. The gradation data to be performed is GDc. Then, as shown in FIGS. 19A and 19B, the correction voltage corresponding to GDc may be output as the correction reference voltage Vc.

5). Electronic Device FIGS. 22A and 22B show a configuration example of a mobile phone (electronic device, electro-optical device) including the integrated circuit device 60 (driver) of this embodiment. Various modifications such as omitting some of the components shown in FIGS. 22A and 22B and adding other components (such as a camera, an operation unit, or a power supply) are possible. It is. The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, PDA, electronic notebook, electronic dictionary, projector, rear projection television, or portable information terminal.

  In FIGS. 22A and 22B, the host controller 410 is, for example, an MPU (Micro Processing Unit), a baseband engine, or the like. The host controller 410 controls the integrated circuit device 60 that is a driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. Further, the image processing controller 420 in FIG. 22B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host controller 410.

  In the case of FIG. 22A, an integrated circuit device 60 with a built-in memory can be used. That is, in this case, the integrated circuit device 60 writes the image data from the host controller 410 into the built-in memory, reads the written image data from the built-in memory, and drives the electro-optical panel 400. On the other hand, in the case of FIG. 22B, an integrated circuit device 60 without a memory can be used. That is, in this case, the image data from the host controller 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 60 drives the electro-optical panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (drivers, liquid crystal panels, source lines) described at least once together with different terms (integrated circuit devices, electro-optical panels, data lines, scan lines, operational amplifiers, etc.) in a broader sense or the same meaning , Gate lines, operational amplifiers, etc.) may be replaced with their different terms anywhere in the specification or drawings. The configuration and operation of electronic devices, electro-optical devices, integrated circuit devices, data drivers, driver circuits, data line driving circuits, DACs, correction DACs, gradation voltage generation circuits, correction voltage generation circuits, and the like are also described in this embodiment. The present invention is not limited to what has been described, and various modifications can be made.

2 is a configuration example of an electro-optical device. Configuration example of data driver. The operation | movement explanatory drawing of a multiplexing circuit. Explanatory drawing of operation | movement of a scan drive. Explanatory drawing of the parasitic capacitance between data lines. Explanatory drawing of the fluctuation | variation of the data voltage by parasitic capacitance. The structural example of this embodiment. The 1st detailed structural example of this embodiment. The 2nd detailed structural example of this embodiment. 2 shows a configuration example of a data line driver circuit. 2 shows a configuration example of a data line driver circuit. 7 is a signal waveform example for explaining the operation of the data line driving circuit. FIG. 13A, FIG. 13B, and FIG. 13C are principle configuration diagrams of a data line driver circuit. 10 shows a configuration example of a k-th data line driving circuit. 10 shows a configuration example of a k-th data line driving circuit. FIG. 6 is an operation explanatory diagram of the data line driving circuit. 6 is a gradation characteristic example of a gradation voltage generated by a gradation voltage generation circuit. Explanatory drawing of the voltage for a correction | amendment which a correction voltage generation circuit produces | generates. 19A and 19B show examples of gradation characteristics of the correction voltage generated by the correction voltage generation circuit. 4 is a configuration example of a correction voltage generation circuit. 6 is a gradation characteristic example of a correction voltage generated by a correction voltage generation circuit. 22A and 22B are structural examples of electronic devices.

Explanation of symbols

12 electro-optic panel, 20 data driver, 22 shift register,
24, 26 line latch, 28 multiplexing circuit, 32 DAC,
34 data line drive circuit, 36 scan drive control unit, 38 scan driver,
40 display controller, 50 power supply circuit, 60 integrated circuit device,
100-1 to 100-k 1st to k-th driver circuits,
110-1 to 110-k 1st to k-th D / A conversion circuits,
120 D / A conversion circuit for correction,
140-1 to 140-k first to k-th data line driving circuits,
160 gradation voltage generation circuit, 180 correction voltage generation circuit, 400 electro-optical panel,
410 host controller, 420 image processing controller SF shift register, SR1 data line, SR, S1 data voltage supply line,
CLK clock signal for scan drive, OP operational amplifier, CI input capacitor,
CC correction capacitor, CF feedback capacitor, SW1 switch element,
SWC1 correction switch element, Vc correction reference voltage, AGND analog reference power supply,
N1 to N3 1st to 3rd node, Vpre precharge voltage

Claims (13)

Including first to k-th (k is a natural number of 2 or more) driver circuits for driving a plurality of data lines of the electro-optic panel;
The plurality of data lines are divided into first to n-th (n is a natural number of 2 or more) blocks including first to k-th data lines in each block,
The first to k-th driver circuits are
After driving the 1st to k-th data lines of the i-th block (i is a natural number equal to or less than n−1) of the 1st to n-th blocks, Performing scan driving for driving the first to kth data lines of the (i + 1) th block;
The k-th driver circuit among the first to k-th driver circuits is
A data driver that outputs a data voltage corrected based on correction data when driving the k-th data line of the i-th block. In claim 1,
Each of the first to kth driver circuits includes:
A data line driving circuit for driving the data lines;
A D / A conversion circuit which receives gradation data and performs D / A conversion of the gradation data;
Have
The kth driver circuit is
A correction D / A conversion circuit that receives the correction data and performs D / A conversion of the correction data;
The data line driving circuit of the k-th driver circuit;
A data driver that outputs a data voltage based on a voltage from the D / A conversion circuit of the k-th driver circuit and a voltage from the correction D / A conversion circuit. In claim 1 or 2,
The correction D / A conversion circuit applies to the gradation data corresponding to the first data line of the i + 1th block or the gradation data corresponding to the first data line of the i + 1th block. A data driver characterized in that data generated by performing predetermined arithmetic processing is input as the correction data. In claim 2 or 3,
The data line driving circuit of the k-th driver circuit;
An operational amplifier;
An input capacitor provided between a first input terminal of the operational amplifier and an output node of the D / A converter circuit of the kth driver circuit;
A correction capacitor provided between the first input terminal and an output node of the correction D / A conversion circuit;
A data driver comprising: In any of claims 2 to 4,
A gradation voltage generation circuit that outputs a gradation voltage to the D / A conversion circuit of the first to kth driver circuits;
A correction voltage generation circuit that outputs a correction voltage to the correction D / A converter circuit of the k-th driver circuit;
A data driver comprising: In claim 5,
The correction voltage generation circuit includes:
A data driver that outputs a correction voltage corresponding to a gradation characteristic of a gradation voltage output from the gradation voltage generation circuit. In claim 6,
When the gradation voltage generation circuit outputs a gradation voltage that monotonously increases with respect to the gradation data, the correction voltage generation circuit converts the gradation voltage that monotonously decreases with respect to the gradation data to the correction voltage. Output as
When the gradation voltage generation circuit outputs a gradation voltage that monotonously decreases with respect to gradation data, the correction voltage generation circuit converts the gradation voltage that monotonously increases with respect to gradation data to the correction voltage. A data driver characterized by outputting as In claim 7,
The correction voltage generation circuit includes:
The correction voltage having a gradation characteristic obtained by multiplying a gradation characteristic axisymmetric with respect to a predetermined voltage with respect to a gradation characteristic of the gradation voltage output from the gradation voltage generation circuit by multiplying by a proportional coefficient is output. Data driver to be used. In claim 5,
The gradation voltage generation circuit includes:
Outputs gradation voltage with non-linear gradation characteristics,
The correction voltage generation circuit includes:
A data driver that outputs a voltage for correcting linear gradation characteristics. In any one of Claims 2 thru | or 9,
The data line driving circuit of the k-th driver circuit;
An operational amplifier having a summing node connected to the first input terminal, an analog reference power supply supplied to the second input terminal, and an output node connected to the output terminal;
A first switch element provided between an input node to which a gradation voltage from the D / A conversion circuit of the k-th driver circuit is supplied and a first node;
An input capacitor provided between the first node and the summing node;
A second switch element provided between the first node and an analog reference power supply;
A feedback capacitor provided between the summing node and the second node;
A third switch element provided between the second node and the output node;
A fourth switch element provided between the second node and an analog reference power supply;
A fifth switch element provided between the summing node and the output node;
A first correction switch element provided between a correction input node to which a correction voltage from the correction D / A conversion circuit is input and a third node;
A correction capacitor provided between the third node and the summing node;
A second correction switch element provided between the third node and a correction reference voltage node to which a correction reference voltage is supplied;
A data driver comprising: In claim 10,
The correction D / A conversion circuit includes:
A data driver that outputs a voltage corresponding to a precharge voltage as the correction reference voltage at the time of initialization.   An integrated circuit device comprising the data driver according to claim 1.   An electronic apparatus comprising the integrated circuit device according to claim 12.

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