CN102237877A

CN102237877A - Two-stage dac architecture and LCD source driver

Info

Publication number: CN102237877A
Application number: CN2011100968733A
Authority: CN
Inventors: 涂能平
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2010-04-23
Filing date: 2011-04-14
Publication date: 2011-11-09
Anticipated expiration: 2031-04-14
Also published as: JP2011234357A; US20110261086A1; JP5076001B2; CN104318906B; US20110261084A1; CN102281072A; JP2011234358A; US20150138182A1; US20110261085A1; CN102237877B; CN104318906A; CN102281073B; US9666156B2; JP2011239378A; US9275598B2; US8970639B2; US9171518B2; CN102281072B; CN102281073A

Abstract

The invention discloses a two-stage DAC architecture and an LCD source driver. The source driver includes the two-stage DAC which includes a 1-bit serial charge-redistribution DAC, a voltage selector and an Gamma Correction Expansion and Decision Logic. The 1-bit serial charge-redistribution DAC includes a first capacitor, a terminal capacitor, a first switch circuit and a second switch circuit. The first capacitor is coupled to a capacitor charging node and a low reference voltage input node. The first switch circuit couples the capacitor charging node to one of the low reference voltage input node and the high reference voltage input node in the capacitor charging period. The second switch circuit links the capacitor charging node to the charge collecting node in the charge rearrangement period.

Description

Two-stage digital analog converter and LCD source electrode driver

Technical field

The present invention generally relates to a kind of source class driver of LCD, particularly relevant for a kind of LCD source class driver of Applied Digital analog converter.

Background technology

Advanced electronic product now, for example high definition television (High Definition Television; HDTV), increasing demand is arranged aspect electronics technology.For example, the client has demand for the high definition television that can show the image with more natural colours.The typical liquid crystal indicator driver that is used for driving the pel array of LCD (LCD) is to use digital analog converter (Digital to AnalogConverter; DAC) digital code with representative voltage position standard is converted to corresponding simulation output.For example, utilize 4 positions to represent 16 binary numbers, to represent the output of digital analog converter.Actual analog output voltage Vout is proportional with the input bit quantity, and can represent by this multiple of importing bit quantity.When the reference voltage Vref of digital analog converter was a constant, output voltage V out only had a discrete value, for example 16 may voltage levels one, to such an extent as to the output of digital analog converter is not really to be an analogue value.Yet the quantity of possible input value can increase by the bit quantity that increases the input data.In output area, the quantity of bigger possible output valve can reduce the difference between the output valve of digital analog converter.

It is apparent that comprise a large amount of relatively figure places when DAC imports, this DAC provides high-resolution relatively output.Yet circuit area and resolution that this DAC consumed are directly proportional.The resolution that increases by one can make the area of the decoder among the DAC double.

The example of the employed known R type of LCD source electrode driver (resistance string) DAC structure is as shown in Figure 1.More particularly, Fig. 1 illustrates 6 DAC structures.This DAC structure has the resistance string that is coupled between reference voltage V0 to V8.The combination of resistance is based on 6 bit digital input D0 to D5 and comes selectedly, so voltage also comes selected based on 6 bit digital input D0 to D5.Operational amplifier is provided to increase driver current.These 6 DAC structures need 64 resistance, 64 signal line and 64x1 decoders.Using this normal structure to make 8 DAC will need to increase by 4 times of big areas, for example: 256 resistance, 256 signal line and 256x1 decoders.Using this normal structure to make 10 DAC will need to increase by 4 times of big areas, for example: 1024 resistance, 1024 signal line and 1024x1 decoders.Therefore, crystal grain or the chip area of many 16 times of these 10 DAC 6 DAC that consumption rate is compared.Known DAC structure accounts for 30% of crystal grain or chip area.Along with more and more high resolution (for example: the resolution more than 10 and 10), can't make us accepting to reach the required size increase of these resolution.

Therefore, need a kind of novel DAC structure that is used in the high-resolution liquid crystal display source electrode driver.

Summary of the invention

An aspect of of the present present invention is that a kind of secondary DAC and LCD source class driver are being provided, to solve the shortcoming of known technology.

According to one embodiment of the invention, this secondary DAC comprises 1 Bits Serial electric charge rerouting DAC and voltage selector.1 Bits Serial electric charge rerouting DAC has the high reference voltage input node that receives high reference voltage and receives the low reference voltage input node of low reference voltage.1 Bits Serial electric charge rerouting DAC comprises first electric capacity, Terminal Capacitance, first switching circuit and second switch circuit.First electric capacity is to be coupled between the first electric capacity charge node and low reference voltage input node.Terminal Capacitance is to be coupled between charge-trapping node and low reference voltage input node.First switching circuit is to be used in the first electric capacity charge cycle, sign indicating number example according to 1 control code that is got by one 1 control code sequences is coupled to one of low reference voltage input node and high reference voltage input node with the first electric capacity charge node, and wherein 1 control code sequence is to derive from M bit digital input code.The second switch circuit is to be used in the electric charge rerouting cycle, the first electric capacity charge node is connected to the charge-trapping node, wherein the electric charge rerouting cycle is to follow the first electric capacity charge cycle, and the electric charge rerouting cycle is to correspond to the electric charge rerouting that utilizes Terminal Capacitance to carry out.Voltage selector is that at least a portion according to M bit digital input code is set to selected voltage with high reference voltage and low reference voltage.

According to another embodiment of the present invention, this LCD source electrode driver comprises secondary DAC, in order to export aanalogvoltage according to M bit digital input code, this secondary DAC comprises 1 Bits Serial electric charge rerouting DAC, voltage selector and Gamma correction and expands and decision logic.1 Bits Serial electric charge rerouting DAC has in order to the high reference voltage input node that receives high reference voltage with in order to receive the low reference voltage input node of low reference voltage.1 Bits Serial electric charge rerouting DAC comprises first electric capacity, Terminal Capacitance, first switching circuit and second switch circuit.First electric capacity is to be coupled between the first electric capacity charge node and low reference voltage input node.Terminal Capacitance is to be coupled between charge-trapping node and low reference voltage input node.First switching circuit is to be used in the first electric capacity charge cycle, sign indicating number example according to 1 control code that is got by one 1 control code sequences is coupled to one of low reference voltage input node and high reference voltage input node with the first electric capacity charge node, and wherein 1 control code sequence is to derive from M bit digital input code.The second switch circuit is to be used in the electric charge rerouting cycle, the first electric capacity charge node is connected to the charge-trapping node, wherein the electric charge rerouting cycle is to follow the first electric capacity charge cycle, and the electric charge rerouting cycle is to correspond to the electric charge rerouting that utilizes Terminal Capacitance to carry out.Voltage selector is according to M bit digital input code high reference voltage and low reference voltage to be set to a plurality of selected accurate positions.Gamma correction expands and decision logic is to finish Gamma correction in order to see through the sign indicating number expansion according to M bit digital input code.

The DAC framework that embodiments of the invention provided can reduce the area of the DAC of high-resolution DAC framework significantly, for example is used in the DAC framework of DAC source electrode driver.For example, thinkable is that for 10 DAC frameworks, than 10 DAC that use known DAC framework to finish, the DAC framework of Jie Luing reduces by 50% area at least herein.The very suitable high speed of this DAC framework, big panel and high-resolution show.

Description of drawings

For above and other objects of the present invention, feature and advantage can be become apparent, above especially exemplified by a preferred embodiment, and cooperate appended accompanying drawing, be described in detail below:

Fig. 1 is the circuit diagram that illustrates the source electrode driver of using known resistor string D/A converter framework with 6 bit resolutions;

Fig. 2 is the Known designs that illustrates the LCD source electrode driver, and Fig. 3 is the digital analog converter that illustrates the LCD source electrode driver of Fig. 2 in more detail;

Fig. 4 illustrates the framework of 10 bit digital analog converters according to an embodiment of the invention, and Fig. 4 A is the continued operation chart that illustrates the digital analog converter framework of Fig. 4;

Fig. 4 B is the chart that illustrates the output voltage that is listed in the digital analog converter framework after each operation that Fig. 4 A illustrated;

Fig. 5 illustrates 10 bit digital analog converter frameworks according to another embodiment of the present invention, and Fig. 5 A is the chart of continued operation that illustrates the digital analog converter framework of Fig. 5;

Fig. 6 illustrates the framework of 10 bit digital analog converters according to another embodiment of the present invention, and Fig. 6 A is the chart of continued operation that illustrates the digital analog converter framework of Fig. 6;

Fig. 7 is the embodiment that illustrates 10 bit digital analog converter frameworks with Fig. 4 that built-in skew eliminates, and Fig. 7 A is the chart of continued operation that illustrates the digital analog converter framework of Fig. 7;

Fig. 8 is the embodiment that illustrates 10 bit digital analog converter frameworks with Fig. 5 that built-in skew eliminates, and Fig. 8 A is the chart of continued operation that illustrates the digital analog converter framework of Fig. 8;

Fig. 9 is the embodiment that illustrates 10 bit digital analog converter frameworks with Fig. 6 that built-in skew eliminates, and Fig. 9 A is the chart of continued operation that illustrates the digital analog converter framework of Fig. 9;

Figure 10 is the non-linear example that illustrates the transfer curve of source electrode driver;

Figure 11 illustrates the Gamma correction operation of digital analog converter according to an embodiment of the invention;

Figure 12 is the embodiment that illustrates the 10 bit digital analog converter frameworks of the Fig. 8 with the reference voltage selector that is modified;

Figure 13 is the embodiment that illustrates the 10 bit digital analog converter frameworks of using 1 pipeline, and Figure 13 A is the chart of continued operation that illustrates the digital analog converter framework of Figure 10;

Figure 14 is the embodiment that illustrates 10 bit digital analog converter frameworks with Figure 13 that built-in skew eliminates, and Figure 14 A is the chart of continued operation that illustrates the digital analog converter framework of Figure 14.

[primary clustering symbol description]

10: source electrode driver 12: shift register

14: sampling register 16: keep register

18: data latch 20: shift register

22: digital analog converter 22a:DAC structure

22b:DAC structure 24: reference voltage generator

25: separate multiplexer 26: output circuit

26a: operational amplifier 26b: operational amplifier

100:DAC structure 100A:DAC structure

100B:DAC structure 102: operational amplifier

104: electric charge rerouting circuit 104A: electric charge rerouting circuit

105: electric capacity charge node 106: voltage selector

106A: voltage selector 107: electric capacity charge node

Decoder 109 in 108: the first: the charge-trapping node

110: register 111: node

112: sign indicating number expands and decision logic 112A: sign indicating number expands and decision logic

112B: sign indicating number expands and decision logic 112C: sign indicating number expands and decision logic

114: the second decoder 114A: second decoder

114B: the second decoder 114C: second decoder

116A: register 116B: register

116C: register 200:DAC structure

200A:DAC structure 200B:DAC structure

200C:DAC structure 300:DAC structure

302: operational amplifier 304: electric charge rerouting circuit

304A: electric charge rerouting circuit 305: electric capacity charge node

306: voltage selector 307: the electric capacity charge node

308: decoder 309: the charge-trapping node

310: register 311: node

312: sign indicating number expands and decision logic 316: register

400:DAC structure C 1, C2, C3, C4: electric capacity

D0～D5: numeral input GMA0～GMA3: gamma zone

HV: high voltage LV: low-voltage

POL: polarity control signal R1～R64: resistance

SH, Switch S L and

Switch

S1, S2, S3, S4: switch

Switch

MV: intermediate voltage V0～V9: reference voltage

V0～V9: reference voltage VSS: low power supply supply voltage

VH: high reference voltage VCOM: common-mode voltage

VL: low reference voltage Vout: output voltage

VDD_P, VDD_N: power supply V1_N: gamma voltage

V64_N: gamma voltage V64_P: gamma voltage

VDD: high power supply supply voltage Y1～Y720: simulation output

Embodiment

Narration in the exemplary embodiments should be read together with additional accompanying drawing, and these additional accompanying drawings should be considered the part of overall description.Relatively term is to use for convenience of description and need not operate on specific direction or the construction device.About linking up, coupling and suchlike term, for example " connection " and " the interior connection " is meant that feature and another feature see through device placed in the middle directly or indirectly and link up, unless special narration is arranged in addition.

Active array type LCD (following will be called LCD) is the field technology knowing and describe for this reason, and for example: the storehouse horse is answered before people's such as (Kumada) the United States Patent (USP) case the 7th, 176, No. 869, incorporates it into this case at this and thinks reference.This LCD has gate drivers, source electrode driver and control circuit, and wherein gate drivers is as the sweep signal driver, in order to supply sweep signal in selecting between pixel period; Source electrode driver is as data signal driver, in order to supplies data signals to LCD; Control circuit is the clock pulse in order to control gate driver and source electrode driver.Except the improvement of source electrode driver described herein, these a little assemblies field are for this reason known and are not needed and describe in detail herein.

In LCD, graph data is to be sent to source electrode driver via control circuit, and wherein pattern data signal is to be simulation and to be supplied to LCD as driving voltage by digital translation.The generating circuit from reference voltage that is connected to source electrode driver produces a voltage, the reference that this voltage is intended as the digital revolving die of pattern data signal.

Fig. 2 is the schematic diagram of a known LCD source electrode driver 10.This source electrode driver 10 comprises the numerical portion of realizing with low-voltage (LV) technology.This part comprises shift register 12, sampling register 14, keeps register 16 and data latches 18.This simulation part branch of realizing with high voltage or voltage comprises a quasi converter 20, DAC22, reference voltage generator 24 and output circuit 26, and this output circuit 26 can comprise operational amplifier as shown in Figure 3.The output of driver 10 is to illustrate to having 720 simulation output Y1 to Y720, and each output corresponds to each bar line of LCD.

Fig. 3 is the detailed maps of a form of output circuit 26 that illustrates the source line driver 10 of DAC22 and Fig. 2, the DAC (P_DAC) that it comprises the DAC (N_DAC) that is made of NMOS, be made of PMOS, have the right operational amplifier (N_OPA) of NMOS input, have the right operational amplifier (P_OPA) of PMOS input, wherein VDD_P is a power supply of representing DAC structure 22b; VDD_N is a power supply of representing DAC structure 22a; V1_N is the 1st gamma voltage representing DAC structure 22a; V64_N is the 64th gamma voltage representing DAC structure 22a; V1_P is the 1st gamma voltage representing DAC structure 22b; V64_P is the 64th gamma voltage representing DAC structure 22b; MV represents intermediate voltage; HV represents high voltage.This DAC and output circuit framework are typically to be configured as differential architecture, this DAC and output circuit framework comprise DAC structure 22a, the 22b based on alternating N MOS and PMOS respectively, and comprise PMOS and NMOS input operational amplifier 26a, 26b alternately respectively.Yet the people that know this design can understand, and track to track operational amplifier output circuit structure can be used for substituting difference structure.Many drivers are arranged in LCD.For example: high definition television 1920x1080 has 8 drivers in display (1920x3 (RGB)/720).Be illustrated in the operation of LCD source electrode driver of Fig. 2 and Fig. 3 and its assembly for this reason those skilled in the art know.Therefore, the detailed description of these assemblies does not need, and need not provide, with the related description of the DAC of the improvement that is used in LCD driver among the present invention that avoids confusion yet.

The DAC of the improvement that herein illustrates is divided into secondary with the function of this DAC.The first order provides the rough output voltage range that roughly corresponds to M bit digital input code, and the second level is to use 2 Bits Serial electric charge rerouting DAC, to provide precision target voltage in rough range.Gamma correction and skew are eliminated and can be built in the DAC structure.Can learn obviously that by following description this DAC structure can provide significant area to save to reach at a high speed, the design of big panel, Gao Xiedu.

Fig. 4 is first embodiment that illustrates high-resolution DAC structure 100, and Fig. 4 A illustrates the operating procedure that this DAC carries out, and this operating procedure produces aanalogvoltage Vout by M bit digital input code.More specifically, Fig. 4 is the embodiment that illustrates 10 DAC structures 100.After 10 embodiment are illustrated, will be understood that, by 10 general rules that embodiment illustrated is to equate to be applicable to high-resolution DAC structure (for example: 11 and more high-order design), even can equate to be applicable to the DAC structure (9 and low wait for design) of low resolution, words of application like this if desired.

10 DAC structures 100 comprise output operational amplifier 102, and it is provided to reach the current gain purpose.The output of operational amplifier 102 (Vout) is the negative input end that is fed back to operational amplifier 102.The positive input terminal of operational amplifier 102 is coupled to the output of serial charge rerouting DAC104, particularly is 2 Bits Serial electric charge rerouting DAC, and it is in more going through to get off.This serial charge rerouting DAC104 has high reference voltage and the input of low reference voltage, and right with the reference voltage that constitutes to accept by reference voltage VH and VL, it defines a rough voltage range.Voltage selector circuit 106 provides reference voltage VH and VL, and in the embodiment that illustrates, reference voltage VH and VL are that an adjacent voltage is right, and this adjacent voltage is to selecting to get from a plurality of adjacent voltage centering of crossing over reference voltage V1 to V9 for voltage selector 106.Scope is provided to sign indicating number by least significant bit (LSB) d0 to 10 input codes of highest significant position (MSB) d9 and expands (Code Expanding) and a decision logic 112.Suppose voltage selector 106 in Y adjacent voltage to selecting, then sign indicating number expands and decision logic 112 is understood by extracting log out in 10 input codes ₂Y highest significant position.For example: if 8 voltages are arranged to by V1 to V9 (for example: V1/V2, V2/V3, V3/V4, V4/V5, V5/V6, V6/V7, V7/V8, V8/V9) among the embodiment of Fig. 4, then, sign indicating number expansion and decision logic 112 are by extracting 3 highest significant positions (d9, d8, d7) in 10 input codes out, to be used for selecting an adjacent voltage right.Sign indicating number expands and decision logic 112 provides these 3 positions to register, and for example register 110.These 3 highest significant positions are provided to first decoder 108, first decoder 108 is these 3 highest significant positions to be decoded as control signal control voltage selector 106, to export one of 8 possible VL and VH centering, wherein these 8 possible VL and VH are to being to correspond to 3 input codes that are input to decoder 108.For example: if [d9 d8 d7] is [1 1 1], then VL/VH is to being V8/V9, and if [d9 d8 d7] be [0 0 0], then VL/VH is to being V1/V2.By the rough voltage range of representing with VL and VH, 2 Bits Serial electric charge rerouting DAC104 can be used to export the accurate position of the specific voltage that is arranged in VL to VH scope, and as described below, wherein this VL to VH scope is to correspond to 10 input codes.

Fig. 4 illustrates the embodiment that an embodiment describes N=1.That is sign indicating number expands and decision logic 112 expands 1 with this 10 bit digital input code.Illustrate among the embodiment at this, use this extension bit as filling up character (filler) or filler (padding bit) behind the least significant bit of 10 bit digital input codes.This position is set to a default value " 0 ".These 7 least significant bits (d6 to d0) and one fill up 8 altogether of character or fillers, and sign indicating number expands and decision logic 112 provides these 8 to second register 116.When sign indicating number expands and decision logic 112 provides the even number least significant digit, for example: 8 least significant bits in the embodiment of 11 bit digital input codes, the embodiment of consideration N=0.Wherein filler is set as 0 always, and the sign indicating number that does not have Gamma correction (following narration) to be provided through 10 bit architectures thus expands and decision logic carries out.In having the N=1 embodiment of Gamma correction, this extension bit can dynamically be set at " 0 " or " 1 " by logical one 12.

Provide this 8 bit code (d6 d5 d4 d3 d2 d1 d0 0) to register 116.The mode that register 116 is controlled to 2 bit combinations [dH dL] sequence provides 8 stored bit code to the second decoders 114 continuously/serially, the mode of this 2 bit combination [dH dL] sequence is the least significant bit since 8 bit codes, for example: combination [d0 0] is first, then [d2 d1] is the second, and [d4 d3] is the 3rd and finally makes up [d6 d5] for last then.The combination of these yards is used by second decoder 114, to control this 2 Bits Serial electric charge rerouting DAC104.

2 Bits Serial electric charge rerouting DAC104 are that the voltage between VL to VH scope is selected in operation, export operational amplifier 102 to provide.This electric charge rerouting DAC104 comprises Terminal Capacitance C3, this Terminal Capacitance C3 is connected between low reference voltage node and the charge-trapping node 109, this charge-trapping node is coupled to the positive input terminal of operational amplifier 102, with a pair of binary weighted capacitance C1, C2, each electric capacity has first end that also is coupled to low reference voltage node and a plurality of the second ends that are coupled to the first electric capacity charge node 105 and the second electric capacity charge node 107 respectively.Between charge cycle, the second end of capacitor C 1 is optionally to be coupled to low reference voltage VL or high reference voltage VH via first switching circuit, this first switching circuit comprise a switch S 1 and a pair of complementary switch SH and Between charge cycle, the second end of capacitor C 2 is optionally to be coupled to low reference voltage VL or high reference voltage VH via the second switch circuit, this second switch circuit comprise switch S 1 and a pair of complementary switch SL and Complementary switch SH and

With complementary switch SL and

Controlled by the output of second decoder 114.

In the electric charge rerouting cycle, the first electric capacity charge node 105 is to be coupled to charge-trapping node 109 via switch S 2, and the second electric capacity charge node 107 is to be coupled to charge-trapping node 109 via second switch S2.For the electric capacity of resetting in the operating period of resetting, switch S 3 is to be coupled between low reference voltage node and the electric charge rerouting node 109.Switch S 1, S2 and S3 can control in many ways, and for example the clock signal that sends by the clock pulse controller is controlled.

For single 2 bit combinations [dH dL], when dH was 1, then switch S H was closed condition and switch

Be opening, and when dH was 0, then switch S H was opening and switch Be closed condition.Similarly, when dL was 1, switch S L was closed condition and switch

Be opening, and when dL was 0, switch S L was opening and switch

Be closed condition.

Capacitor C 2 and C3 have capacitance C and capacitor C 1 that capacitance 2C is arranged.Be apparent that the quantity of electric charge in the electric capacity is the multiple of the capacitance of electric capacity.So the two charges all simultaneously for example to suppose C1 and C2, the quantity of electric charge in the capacitor C 1 is two times of the quantity of electric charge in the capacitor C 2.

The operation of serial charge rerouting DAC104 is illustrated by the auxiliary of Fig. 4 A.

In step 1, switch S 1 is all closed condition for opening and switch S 2 and S3.When two electrodes of each electric capacity all are coupled to voltage VL, this step will reset to 0V across the voltage on capacitor C 1, C2 and the C3.After step 1, switch S 3 is unlocked and keeps opening and carry out once up to this program again, and the capacitor C 3 of need resetting again this moment.

In step 2, for charging capacitor C1 and C2, switch S 1 is a closed condition, and switch S 2 is an opening.The one 2 bit combination [dH dL], for example: [d0 0] that provides by register 116, by second decoder 114 be used for control switch SH, SL and

If dH is 1, then SH is a closed condition, For opening and capacitor C 1 are to be coupled between VH and VL to charge.If dH is 0, then SH is an opening, For closed condition and capacitor C 1 are to be coupled between VL and VL and not to be recharged.If dL is 1, then SL is a closed condition, For opening and capacitor C 2 are to be coupled between VH and VL, to charge.If dL is 0, then SL is an opening,

For closed condition and capacitor C 2 are to be coupled between VL and VL, it means that capacitor C 2 is not recharged.

In step 3, for between capacitor C 1, C2 and terminal/collection capacitor C 3, distribute any electric charge that builds among capacitor C 1 and the C2, and the residual charge (on this aspect is not have residual charge) that distributes capacitor C 3, switch S 1 for opening switch S 2 be closed condition particularly, the switch S 2 of closed condition is that capacitor C 1, C2 and C3 are parallel between charge-trapping node 109 and low reference voltage node.Distribute the total electrical charge in this circuit, so that the electric charge of each electric capacity and its capacitance are proportional.That is capacitor C 1 has total electrical charge (Q _Total) half the quantity of electric charge, and each of capacitor C 2 and C3 has 1/4th total charge dosage, this is because total capacitance value is 4C.The electric charge that is dispensed to capacitor C 3 causes output node to have one to equal VL+V _C3Voltage.Voltage V _C3Be to equal (Q _Total)/4C.During each electric charge rerouting phase place/cycle, the total electrical charge of this circuit 1/4th is dispensed to capacitor C 3.After this step, output node voltage is to equal (2d0+0)/4* (VH-VL)+VL.In this step, register 116 also loads 2 bit combinations [d2 d1] down to second decoder 114, to prepare ensuing electric capacity charging phase place/cycle.

Step 4 be with the method identical with step 2 and only with switch S H,

SL,

Operate, wherein switch S H,

SL

Be continuous 2 bit codes that are subjected to second example, for example: the control of combination [d2d1].According to the value of [d2 d1], step 4 can increase electric charge to being present on the electric charge of capacitor C 1 and C2.In step 5, capacitor C 1, C2 and C3 are connected in parallel once again in low reference voltage node and 109 of nodes.Total electrical charge in the circuit comprises the total electrical charge (for example: the residual charge of these electric capacity when step 3 finishes adds any electric charge that is added to electric capacity in the step 4) that residual charge (when step 3 finishes) in the capacitor C 3 adds capacitor C 1 and C2.These whole total electrical charges reassign to 3 electric capacity again in proportion.This causes staying in the capacitor C 3 divided by 4 residual voltage.The voltage of this output node is to be equal to VL+V once more _C3After step 5, VL+V _C3Be to be equal to total electrical charge in the capacitor C 3 divided by the value of total combination capacitor value 4C of capacitor C 1/C2/C3.After step 5, this output node voltage is to be equal to: (2d2+d1+0.5d0)/and 4* (VH-VL)+VL.

Step 6 should obviously be learnt to the explanation of step 5 by above-mentioned steps 2 to step 9.Each stage on node 109 the corresponding voltage that causes be to be illustrated in Fig. 4 B.Illustrate as Fig. 4 B, this moment, the voltage of output node was 1/128 (64d6+32d5+16d4+8d3+4d2+2d1+d0) * (VH-VL)+VL.That is, this voltage can be VL (if provide to 8 bit codes of register 116 be 0) to VL+127/128 (VH-VL) (if provide to the highest 7 effective bit codes of register 116 be 1 and filler be 0) between any value.

2 Bits Serial electric charge rerouting DAC structures provide the output voltage that meets following sum formula, and wherein " n " and " i " represents the difference variable, and wherein when i=1 di represent d1, if di represents d2 etc. during i=2.

V_{L} + (V_{H} - V_{L}) * Σ_{i = 0}^{n} (2^{i} di) * 2^{- (n + 1)}

Though serial charge rerouting DAC structure described herein is 2 Bits Serial electric charge rerouting DAC, will be understood that when needs compatibility high-order resolution, this structure can be upgraded.For example: 3 Bits Serial electric charge rerouting DAC can have the binary weighted capacitance of extra capacitance 4C, and this electric capacity is to couple with capacitor C 1 and capacitor C 2 identical modes and by each switching circuit control.Decoder 114 can be set and be used as 3 bit decoders and register 116 will provide 3 bit combinations rather than 2 bit combinations.

Fig. 5 and Fig. 5 A illustrate another DAC framework 100A and its continued operation respectively.The each side of framework 100A is identical with framework 100, except N=2.That is 7 least significant bits of the residue of these 10 input codes are to extend to 9 by increasing by 2 extra bits d00 and d01.Expand sign indicating number and decision logic 112A and determine these values of two,, and provide seven d6 to d0 and extra bits d00 and d01 to register 116A by the script input code as following described in detail.Then, register 116A provides 2 bit combination to the second decoder 114A that derived and obtained by 9 bit codes, this 9 bit code is to expand sign indicating number and decision logic 112A provides continuously with the mode cause of 2 bit combinations [dH dL], at first is least significant bit, and with the above-mentioned mode relevant with Fig. 4 come control switch SH,

SL,

That is register 116A provides [d000] earlier, and " 0 " in the dL position is a filler; Then [d0 d01]; Then [d2 d1]; Then [d4 d3]; And be [d6 d5] at last.

The electric charge rerouting circuit 104 of Fig. 5 is identical with the circuit structure ground of the correspondence of Fig. 4.Unique operational difference is for increasing extra electric charge and rerouting

step

10 and 11 shown in Fig. 5 A, and increase employed each bit combination in each step, for example: Fig. 5 A is with [dH dL] bit combination [d00 0] beginning rather than [d0 0] shown in Fig. 4 A.

Fig. 6 and Fig. 6 A illustrate another DAC framework 100B and its continued operation respectively.Framework 100B each side is similar with 100A with framework 100, except N=3.That is it is to extend to 10 by increasing by 3 extra bits d00, d01, d02 that the Retained of this 10 bit code is surplused 7 least significant bits.Expand sign indicating number and decision logic 112B and determine this three place values,, and provide 7 d6 to d0 and these three extra bits d00, d01, d02 to register 116B by 10 input codes originally as following described in detail.Then, register 116B provides 2 bit combination to the second decoder 114B that derived by 10 bit codes, this 10 bit code be with the mode of 2 bit combinations [dH dL] by expand sign indicating number and decision logic 112B provides continuously and, at first be least significant bit, and with the above-mentioned mode relevant with Fig. 4 and Fig. 5 come control switch SH,

SL and

That is register 116B provides [d01 00] earlier; Then [d0 d02]; Then [d2 d1]; Then [d4 d3]; With last [d6 d5].It should be noted that and do not need filler " 0 " among this embodiment.

The electric charge rerouting circuit 104 of Fig. 6 is structurally identical with the corresponding circuits of Fig. 4 and Fig. 5.This unique difference in operation can be found to step 4 in the step 1 that is illustrated in Fig. 5 A, and this difference in operation is used 22 bit codes at first of Fig. 6 rather than 22 bit codes at first of Fig. 5.

Fig. 7 to Fig. 9 is the embodiment of the DAC framework that illustrates among Fig. 4 to Fig. 6 to be illustrated, but this framework is carried out improvement so that migration to be provided.The evolutionary operation of these frameworks is to be illustrated in relevant Fig. 7 A, Fig. 8 A and Fig. 9 A respectively.Except as otherwise noted, the operation of these DAC structures is similar to Fig. 4 A to Fig. 6 A with Fig. 4 to Fig. 6 respectively with structure.Fig. 7 illustrates DAC structure 200 and Fig. 7 A illustrates sequential steps, and this sequential steps illustrates the operation of the DAC structure of Fig. 7.This DAC structure 200 is the DAC frameworks 100 that are same as Fig. 4, except electric charge rerouting circuit 104A.Compared to electric charge rerouting circuit 104, electric charge rerouting circuit 104A comprises: be coupled to the extra switch S2 between the positive input terminal of node 109 and operational amplifier 102; Be coupled to the extra switch S2 of 111 of the output of operational amplifier 102 and nodes; Be coupled to the switch S 4 of 111 of node 109 and nodes; Be coupled to the 4th capacitor C 4 of the positive input terminal of node 111 and operational amplifier 102.These additional assemblies are that operation compensates any offset voltage, and this offset voltage may be original for operational amplifier 102.

Now please refer to Fig. 7 A, the step 1 of Fig. 7 A to step 9 is to be same as the step 1 relevant with Fig. 4 A described above to step 9.That is, execution in step 1 to step 9 with charging capacitor C3 to required voltage, this required voltage and lower voltage VL addition.After execution in step 9, this voltage (VL+V _C3) be the voltage of the node 109 of Fig. 7.It should be noted that for step 1 to step 9, switch S 4 is an opening, means capacitor C 4 and is not connected to node 109.During step 2, step 4, step 6 and step 8, third and fourth switch S 2 that is increased is opening.As capacitor C 1 and C2 during in charging, third and fourth switch S 2 of increase can be disconnected capacitor C 4 by circuit.Yet, during rerouting step 3,5,7 and 9, trigger these extra switch S 2, node 109 being coupled to the positive input terminal of operational amplifier, and create output from operational amplifier 102 via the feedback path of capacitor C 4 to the positive input terminal of operational amplifier 102.This connected mode is to store the offset voltage (VOS) of operational amplifier 102 to capacitor C 4.In this step, the output voltage of operational amplifier 102 is offset voltage (V that the voltage that is equal to node 109 subtracts operational amplifier 102 _OS).Fig. 7 A illustrates additional step S10, and this step is charged fully in capacitor C 3 and (carried out after the step 9).Step 10 is the skew removal process.In step 10, has only trigger switch S4, node 109 is connected to the positive input terminal of operational amplifier 102 via node 111 and capacitor C 4.It should be noted that the voltage of crossing over capacitor C 4 represents the offset voltage (V of operational amplifier 102 _OS).This offset voltage is added to the skew that node 109 is provided with compensated operational amplifier 102.Therefore, the output voltage V out of operational amplifier 102 more closely is matched with the voltage of node 109.That is the output voltage V out of operational amplifier 102 equals: the voltage (V of node 109 ₁₀₉)+V _OS-V _OS, V for example ₁₀₉

Fig. 8 illustrates another DAC structure 200A and Fig. 8 A illustrates a consecutive steps, and this consecutive steps is the operation that illustrates the DAC structure 200A of Fig. 8.This DAC structure 200A is the DAC structure 100A similar in appearance to Fig. 5, except using 2 Bits Serial electric charge rerouting DAC structure 104A of the above-mentioned improvement relevant with Fig. 7.As the above mentioned, the electric charge rerouting DAC 104A of this improvement has built-in skew to eliminate.Now please refer to Fig. 8 A, the step 1 of Fig. 8 A to step 11 is to step 11 similar in appearance to the above-mentioned step 1 relevant with Fig. 5 A.That is, execution in step 1 to step 11 with charging capacitor C3 to required voltage, this required voltage is and low voltage VL addition.This voltage (VL+V _C3) be the voltage of the node 109 of Fig. 8, after execution in step 11.In order to the operation of carrying out the step 12 that skew eliminates is identical with the operation of the step 10 of Fig. 7 A described above.

Fig. 9 illustrates another DAC structure 200B, and Fig. 9 A illustrates consecutive steps, and this consecutive steps illustrates the operation of the DAC structure 200B of Fig. 9.This DAC structure 200B is the DAC structure 100B that is same as Fig. 6, except using 2 Bits Serial electric charge rerouting DAC structure 104A of the improvement relevant with above-mentioned Fig. 7 A.Please refer to Fig. 9 A, the step 1 of Fig. 9 A to step 11 is identical to step 11 with the step 1 of above description correlation diagram 6A.That is, execution in step 1 to step 11 with charging capacitor C3 to required voltage, this required voltage is and low voltage VL addition.After execution in step 11, this voltage (VL+V _C3) be the voltage of the node 111 of Fig. 9.In order to the operation of carrying out the step 12 that skew eliminates is similar with the operation of the step 10 of Fig. 7 A described above.

Figure 12 illustrates another DAC structure 200C, and it is similar in appearance to the DAC structure 200A of Fig. 8 A, and it is 10 DAC with built-in skew elimination and N=2.This DAC structure 200A is similar in appearance to the DAC structure 200A of Fig. 8 A, except removing decoder 108 and register 110; The voltage selector 106A of improvement is replaced voltage selector 106; Utilize sign indicating number to expand and replace expansion sign indicating number and decision logic 112A with decision logic 112C; Utilize register 116C to replace register 116A; And utilize the second decoder 114C to replace beyond the second decoder 114A.

In this embodiment, each VL is to transfer to one of two different accurate positions via voltage selector 106A with VH.Voltage selector 106A receives high power supply supply voltage VDD, common-mode voltage VCOM and supplies voltage VSS as input as the low power supply of polarity control signal POL.On functional, this voltage selector can be considered as a bit decoder, be used to adjacent voltage VSS/VCOM and VCOM/VDD are selected.The signal POL that inputs to voltage selector is polar signal and can (corresponds to positive signal POL (for example: POL=1)) or voltage VCOM/VSS (is corresponded to negative polarity signal POL (for example: POL=0)) VDD/VCOM in order to selected voltage.Know various Different Logic circuit,, can produce signal POL in many ways as the personnel of sequential control circuit.

As shown in Figure 8,10 input codes are provided to sign indicating number expansion and decision logic 112C.This logical one 12C extends to 12 bit codes by increasing by 2 bit code to 10 bit codes, and provides this 12 bit code to register 116C.Register 116C comes serially (Serially) to provide this sign indicating number to the second decoder 114C, to control 2 Bits Serial electric charge rerouting DAC104A with two increments (Increment) [dH dL].The operation of this 2 Bits Serial electric charge rerouting DAC104A is similar in appearance to the above-mentioned electric charge rerouting DAC relevant with Fig. 8, and except without any need for filling character and use extra relevant charging and rerouting step, this is because 6 [dH dL] bit combinations rather than 5 are arranged.

The sign indicating number expansion described above and the further details of decision logic are in following relevant Figure 10 and Figure 11 discussion.So those skilled in the art are known, and LCD comes the converting video signal to light with non-linear method, and this is transformation curve, voltage and light transmissive contrast because of LCD, for non-linear.Gamma characteristic is power time rule relation, and this relation is approximately between the coding brightness (black/ash/white information) of vision signal and actual required image brightness.LCD will typically be used some gamma characteristics to vision signal.Therefore, gamma counter-rotating is applied to the accurate position of output voltage, with in and gamma characteristic, and provide or find out linear relationship between between coding brightness and real image brightness.Figure 10 illustrates the example of the transformation curve of source electrode driver.Y-axis representative voltage and X-axis are represented input code.Be positive polarity and regional GMA2 from regional GMA0 to the scope of regional GMA1 to the scope of regional GMA3 be negative polarity.This curve illustrates linear relationship district and non-linear relation district in the gamma curve.Sign indicating number expansion described herein and decision logic are by increasing by 10 bit codes (for example: illustrate as Figure 10, by 10 to 12) that the N units expands original input.Preferable N value is 1,2 or 3, yet the present invention is not limited to this.Extra N position is the adjustment that is used to provide sign indicating number, and is linear or non-linear to being converted to of next voltage quasi position by a given voltage quasi position with explanation.As shown in figure 10, by increasing by 2, represent 1 original 10 bit codes (0000000001) to become and represent 4 12 bit codes (000000000100); Represent 2 original 10 bit codes (0000000010) to become and represent 8 12 bit codes (000000001000); Represent 3 original 10 bit codes (0000000011) to become and represent 12 12 bit codes (000000001100); Deng.In the range of linearity, directly the sign indicating number of (straight) be converted to suitable, for example: represent 512 10 bit codes (1000000000) to become and represent 2048 12 bit codes (100000000000).Yet in the inelastic region, the adjustment of some yards need illustrate that it is non-linear.For example: correspond to expansion 12 bit codes of 10 bit codes (0000000001) of original representative 1, be by value+/-adjustment of k becomes and represents 4 12 bit codes (000000000100).That is according to the value of K, controlled expansion sign indicating number can be: (000000000001) (for example: K=-3) (000000000010) (for example: K=-2) (000000000110) (for example: K=-1); (000000000100) (for example: K=0) (000000000101) (for example: K=1) (000000000110) (for example: K=2); (000000000111) (for example: K=3).

The transformation curve that Figure 10 illustrates for non-linear, and be a linearity at

sign indicating number

512 and 513 of sign indicating numbers 1/2/3 of sign indicating number 0 and sign indicating number.Will be understood that the transformation curve figure that Figure 10 painted is an example that just illustrates transformation curve, and each LCD can independently transformation curve be relevant with each.

Sign indicating number described above expands and decision logic is that responsible (1) expands input code (for example: by 10 to 12) by the position of N number, and (2) decision is to the suitable adjustment (by the K value) of the sign indicating number that produced, with suitable reach need transformation curve.This processing process is the part of digital revolving die plan conversion and is illustrated among Figure 11.

In step 300, receive M position (for example: 10) input code by sign indicating number expansion and decision logic.

In step 310, this yard expansion and decision logic extend to the M+N position with the M position.

In step 320, derive suitable output code by specific gamma curve.If this output code is positioned at the linear zone of voltage of LCD-transfer function curve, then [code _I+1-code _i] (M+N position)=[code _J+1-code _j] x2 ^N(M position), wherein on behalf of yardage word and " i " representative in the source code, " j " expand yardage word corresponding in the sign indicating number.In the range of linearity, the yardage word difference of adjacent expansion intersymbol is simply by 2 ^NCome weighting to source code.For example: if N=2 embodiment is linear between the curve of second yard and the 3rd intersymbol, second yard is 4 and trigram is 8.Yet, be positioned at the inelastic region of voltage of LCD-transfer function curve, [code as output code _I+1-code _i] (M+N position)=[code _J+1-code _j] x2 ^N± (M position).The yardage word difference of adjacent expansion intersymbol can have 2 ^NWeighting is to source code, but also have and one adjust (+/-K) provide non-linear matches (Nonlinear Fitting).This adjustment is according to voltage of LCD-transfer function curve, and the utilized lookup table of sign indicating number expansion and decision logic or register store the suitable sign indicating number of selection or/and suitably displacement.Will be understood that the k value is not all identical with each expansion sign indicating number and its value is according to nonlinear curve.

Will be appreciated that as the part of sign indicating number expansion/decision handling procedure, this non-linear gamma curve can be come approximate match to the adjustment of V1 to V9 by selectable voltage.

Illustrate as step 330, the M+N bit code of being exported is used by the 2 Bits Serial DAC part of DAC structure, and the voltage that collocation is selected is to (VH/VL), as the above narration relevant with Fig. 4 to Fig. 9, so that Gamma correction output voltage V out to be provided.

Figure 13 is 10 DAC frameworks 300 that illustrate another embodiment of the present invention, and these 10 DAC frameworks 300 are to use 1 electric charge rerouting DAC.As some embodiment in the foregoing description, DAC framework 300 comprises first voltage to selecting level.In the embodiment that illustrates, voltage expands and decision logic 312 selecting level to comprise voltage selector 306, decoder 308, register 310 and sign indicating number.These assemblies the reference voltage of selecting VH and VL in abutting connection with to aspect operation, come detailed ground explain with reference to Fig. 4,5,6,7,8 and 9 embodiment that illustrated.In addition, the voltage selector 106A that VH and VL can utilize Figure 12 to illustrate sets, and is described with reference to Figure 12.In the embodiment that illustrates, N equals 2, so sign indicating number expands and decision logic output 9 positions totally, it comprises a d6 to d0 and two extra bits d01 and d00, with reference to as the DAC framework that Fig. 5 was illustrated finish that gamma as explained above expands and correction.This 9 bit code is provided to register 316 or other device, it can temporarily store sign indicating number and export sign indicating number to 1 Bits Serial electric charge rerouting DAC304 in the mode of serial, it at first is least significant bit, then next position (for example d00, d01, d02 then then, d03 then, d04 then, d05 then, last d06).

One Bits Serial electric charge rerouting DAC304 comprises output operational amplifier 302, and the output feedback of operational amplifier 302 is to be coupled to its negative input end point, and the positive input end points is to be coupled to charge-trapping node 309.First capacitor C 1 is to be coupled between low reference voltage (VL) node and the first electric capacity charge node 305.Terminal Capacitance C2 is coupled between VL node and the charge-trapping node 307.Terminal point electric capacity is to be coupled to VL node and node 309.The capacitance of capacitor C 1 and C2 is to be equal to each other.That is to say that capacitance is not by binary weighting.The operation of circuit 304 is to discuss in further detail with reference to Figure 13 A, and wherein Figure 13 A is the consecutive steps that illustrates the operation of electric charge rerouting DAC304 aspect the generation output voltage.

The switch S H of electric charge rerouting DAC304 and SL are controlled by the position dn that 316 serials of register provide.When dn was " 1 ", switch S H closed, and when dn was " 0 ", switch S L closed.High/low voltage node 307 is to see through switch S 1 to be connected to the first electric capacity charge node 305, and the first electric capacity charge node 305 is to see through second switch to be connected to charge-trapping node 309.Switch S 2 can be considered switch

This is that vice versa because switch S 2 is opening when S1 is closed condition.When switch S 1 is closed condition (being the state of representing S1 with " 1 " in Figure 13 A), switch S 2 is opening (being the state of representing S2 with " 0 ") in Figure 13 A.In the case, capacitor C 1 is that value according to dn is connected to VH or VL to charge.When switch S 1 is opening (being the state of representing S1 with " 0 " in Figure 13 A), switch S 2 is closed condition (being the state of representing S2 with " 1 ") in Figure 13 A.In the case, capacitor C 1 is in parallel with capacitor C 2, to carry out the electric charge rerouting between two electric capacity.Switch S 3 is provided in 309 of lower voltage node VL and nodes, with the replacement capacitance.

As Figure 13 A progressively shown in, output voltage is to see through after the charging that replaces continuously the rerouting cycle again, and utilizes at the switch S 1 that is triggered between charge cycle and SH or SL and the switch S 2 that is triggered during rerouting week and be output.

Get back to Figure 13 A, in step 1, switch S 1 is opened, and switch S 2 is closed, and switch S 3 is closed.The position dn that is exported by register 316 is made as d00 in advance.The switch S 3 that utilization is closed, node 309 is set to VL and capacitor C 1 and C2 all are coupled between node 309 and the VL.This connection is the electric charge in replacement two electric capacity.In remaining step S2 to S19, switch S 3 is opening (being to represent with " 0 ") in the chart of Figure 13 A, promptly till another replacement operation of needs.

In step 2, switch S 1 is closed, and switch S 2 is opened.The switch S 1 that utilization is closed, capacitor C 1 can be recharged according to the value of position d00.That is if d00 is " 1 ", then capacitor C 1 is to be connected to VH, and causes charging voltage (VH-VL) on capacitor C 1.If d00 is " 0 ", 0 charging voltage (VL-VL) is then arranged on capacitor C 1, and do not have electric charge to be increased to capacitor C 1.

In step 3, switch S 1 is an opening, and switch S 2 is a closed condition.The position that is provided to serial charge rerouting DAC304 is made as the next position in 1 Bits Serial, for example d01 in advance.The S2 that utilization is closed, capacitor C 1 is and capacitor C 2 is parallel between node 309 and the lower voltage node VL, to carry out the electric charge rerouting.Because the total capacitance value in this circuit is that (for example, C1+C2), the total electrical charge in the circuit is redistributed (for example separating) in capacitor C 1 and C2 to 2C.Shown in Figure 13 B, after this step, the voltage that is positioned on the node 309 becomes (d00/2) * (VH-VL)+VL.

In step 4, switch S 1 is that closed condition and switch S 2 are opening.The position that is provided to serial charge rerouting DAC304 is d01.The switch S 1 that utilization is closed, capacitor C 1 can be recharged according to the value of d00.Similarly, capacitor C 1 is that value according to d01 is recharged.Voltage on the node 309 still is (d00/2) * (VH-VL)+VL.

In step 5, switch S 1 is unlocked once more, and switch S 2 is a closed condition.The position that is provided to serial charge rerouting DAC304 is made as the next position in 1 Bits Serial, for example d0 in advance.Capacitor C 1 and capacitor C 2 are to be parallel between node 309 and the node VL, to carry out the electric charge rerouting.Total electrical charge in the circuit (for example, the electric charge of storage in capacitor C 1 because of charge step 4, and because rerouting step 3 and the electric charge of storage in capacitor C 2) is divided among capacitor C 1 and the C2.Shown in Figure 13 B, after this step, the voltage on the node 309 is (d01/2+d00/4) * (VH-VL)+VL.So, voltage is to come by binary weighting according to relevant position, position, and this relevant position, position for example is: the voltage contribution of d01 is 2 times of voltage contributions to d00.

Should narrate what obviously learn thus is that 1 Bits Serial electric charge rerouting DAC304 is that operation comes with capacitor C 1 charging, and then to utilize capacitor C 2 to carry out the electric charge rerouting according to present position dn.After the charging alternately again the order of rerouting be to continue to carry out, use up and last rerouting step (carry out step 19) up to the control bit sequence.After step 19, the voltage on the node 309 is each the binary weighting contribution in the control bit sequence, and it is expressed as follows: (d6/2+d5/4+d4/8+d3/16+d2/32+d1/64+d0/128+d01/256+d00/512) * (VH-VL)+VL.If d00 to d06 is 0 entirely, be VL then from the output voltage that DAC300 exported.If d00 to d06 is 1 entirely, is (511/512) * (VH-VL)+VL from the output voltage that DAC300 exported then.

Figure 14 illustrates DAC framework 400, and Figure 14 A is the continued operation step that illustrates the DAC framework of explanation Figure 14.DAC framework 400 is identical with the DAC framework 300 of Figure 13, except serial charge rerouting DAC304A.Compared to serial charge rerouting DAC304, serial charge rerouting DAC304A comprises: be coupled to the extra switch S2 between the positive input terminal of node 309 and operational amplifier 302; Be coupled to the output of operational amplifier 302 and the extra switch S2 between intermediate node; Be coupled to the switch S 4 between node 309 and 311; And capacitor C 3 is eliminated in the skew that is coupled between the positive input terminal of node 311 and operational amplifier 302.By with Fig. 7,8 and 9 relevant narrations as can be known, these extra assemblies are any offset voltages that operation comes operational amplifier 302 originally just to have.

Now please refer to Figure 14 A, the step 1-19 of Figure 13 A is and is same as the step 1-19 relevant with Figure 14 A.Step 20 is added into, to be offset elimination.The second switch S2 that is increased is closed condition during rerouting step (for example odd number step 3,5,9,11,13,15,17 and 19), but is opening during charge step (for example step 2,4,6,8,10,12,14,16 and 18).When switch S 2 was closed condition, capacitor C 3 was based on a voltage difference and is recharged, and this voltage difference is the difference of the output voltage of the voltage of node 309 and operational amplifier 302.This difference is the variation of representing in the operational amplifier 302.In step 20, switch S 2 is a closed condition for opening switch S 4, so can see through intermediate node 311 and the capacitor C 4 of having charged is connected to node 309 positive input terminal of operational amplifier 302.(or causing) bits of offset standard that voltage on the capacitor C 4 represents that operational amplifier 302 just has originally by operational amplifier 302.This offset voltage is added to the voltage on the node 309, to compensate the variation by operational amplifier was provided.So, from the output voltage V out of the operational amplifier output voltage on the matched node 309 more.

When the DAC framework is when being illustrated among Figure 13 of the embodiment that uses N=2 and Figure 14, should be apprehensible be that N can be other integer, even can be 0.In preferred embodiment, N is 1,2 or 3.When with the embodiment of Figure 13 and N=2 shown in Figure 14 relatively the time, in serial charge rerouting DAC304 or DAC304A, embodiment according to the N=1 of this framework only uses the bit sequence [d00 d0 d1 d2d3 d4 d5 d6] of expansion, and the embodiment of N=3 only uses the bit sequence [d00 d01 d02 d0 d1 d2 d3 d4d5 d6] of expansion.Secondly, as mentioned above, the first order of DAC framework can substitute with the voltage selector relevant with the narration of Figure 12, and so VL and VH can import and optionally be set to one of VSS and VCOM respectively according to the M bit digital, or optionally are set to one of VCOM and VDD respectively.Moreover, when this DAC framework illustrates at 10 DAC, should understand, this framework can be adjusted to the higher or low resolution that provides required apace.

Disclosed herein DAC framework can reduce the area of the DAC of high-resolution DAC framework significantly, for example is used in the DAC framework of DAC source electrode driver.For example, thinkable is that for 10 DAC frameworks, than 10 DAC that use known DAC framework to finish, the DAC framework of Jie Luing reduces by 50% area at least herein.The very suitable high speed of this DAC framework, big panel and high-resolution show.

Though the present invention discloses as above with several embodiment; right its is not in order to limit the present invention; in the technical field of the invention any have know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the scope that appending claims defines.

Claims

1. a two-stage digital analog converter is characterized in that, in order to export an aanalogvoltage according to a M bit digital input code, wherein this two-stage digital analog converter comprises:

One 1 Bits Serial electric charge rerouting digital analog converters have a high reference voltage input node that receives a high reference voltage and a low reference voltage input node that receives a low reference voltage, and wherein this 1 Bits Serial electric charge rerouting digital analog converter comprises:

One first electric capacity is coupled to one first electric capacity charge node and is somebody's turn to do low reference voltage and imports between node;

One Terminal Capacitance is coupled to a charge-trapping node and is somebody's turn to do low reference voltage and imports between node;

One first switching circuit, be used in a plurality of first electric capacity charge cycles, sign indicating number example according to 1 control code that is got by one 1 control code sequences is coupled to one of this low reference voltage input node and this high reference voltage input node with this first electric capacity charge node, and wherein this 1 control code sequence is to derive from this M bit digital input code; And

One second switch circuit, be used in a plurality of electric charge rerouting cycles, this first electric capacity charge node is connected to this charge-trapping node, wherein those electric charge rerouting cycles are to follow those first electric capacity charge cycles, and those electric charge rerouting cycles are to correspond to the electric charge rerouting that utilizes this Terminal Capacitance to carry out; And

One voltage selector, this voltage selector are according at least a portion of this M bit digital input code this high reference voltage and this to be hanged down reference voltage be set to selected voltage.

2. two-stage digital analog converter according to claim 1 is characterized in that, this first switching circuit comprises:

One charge cycle switch is coupled between this first an electric capacity charge node and a reference voltage node, and this charge cycle switch is to be provided with to be triggered in those first electric capacity charge cycles;

One height is coupled between this reference voltage node and this high reference voltage input node with reference to voltage switch; And

One low reference voltage switch is coupled to this reference voltage node and is somebody's turn to do low reference voltage and imports between node.

3. two-stage digital analog converter according to claim 2 is characterized in that, this second switch circuit comprises and is coupled to this first electric capacity charge node and the internodal switch of this charge-trapping.

4. two-stage digital analog converter according to claim 1 is characterized in that, also comprises:

One output operational amplifier, have input of one first operational amplifier and the input of one second operational amplifier, wherein this first operational amplifier input is coupled to an output of this output operational amplifier, and this second operational amplifier input is coupled to this charge-trapping node; And

One built-in offset cancellation circuit is coupled to this output operational amplifier, and wherein this offset cancellation circuit comprises:

Electric capacity is eliminated in one skew, has one first end that is coupled to this second operational amplifier input and one second end that is coupled to an intermediate node;

One the 3rd switching circuit is provided with between those first electric capacity charge cycles, and this charge-trapping node is connected to this second operational amplifier input, and this output that this intermediate node is connected to this output operational amplifier; And

One switch is provided with behind a final person in those electric charge rerouting cycles, and this intermediate node is connected to this second end that capacitor is eliminated in this skew.

5. two-stage digital analog converter according to claim 1 is characterized in that, this voltage selector is to be provided with that to select an adjacent reference voltage from a plurality of adjacent reference voltage centerings right, to obtain this high reference voltage and should low reference voltage; Those adjacent reference voltages are right to comprising 8 adjacent reference voltages; This voltage selector selects this adjacent reference voltage right according to 3 highest significant positions of this M bit digital input code.

6. two-stage digital analog converter according to claim 1, it is characterized in that, also comprising a Gamma correction expands and decision logic, finish Gamma correction in order to see through the sign indicating number expansion according to this M bit digital input code, wherein this Gamma correction expansion and decision logic expand 1,2 or 3 with this M bit digital input code.

7. two-stage digital analog converter according to claim 1 is characterized in that, this voltage selector is those adjacent voltage centerings of cause to be set to select an adjacent reference voltage right, to obtain this high reference voltage and low reference voltage; Those adjacent reference voltages are to comprising Y adjacent reference voltage to right; It is right that this voltage selector is selected this adjacent reference voltage according to X highest significant position of this M bit digital input code, and X equals log ₂Y, this two-stage digital analog converter also comprises:

One first logic is in order to select X highest significant position of this M bit digital input code;

One X bit decoder, this X bit decoder are selecteed those X highest significant positions of decoding, to control this voltage selector;

One second logic, in order to select Z least significant bit of this M bit digital input code, wherein Z equals M-X;

One register in order to temporary transient storage those Z least significant bit and a plurality of 1 control code that derived by those Z least significant bits at least are provided serially at least, uses for this 1 Bits Serial electric charge rerouting digital analog converter; And

One yard is expanded and decision logic, comprise in order to select second logic of those Z least significant bit, and according to finishing Gamma correction to next the expansion via sign indicating number of this M bit digital input code, wherein this Gamma correction expansion and decision logic are that this M bit digital input code is expanded 1,2 or 3.

8. a LCD source electrode driver is characterized in that, comprises:

One two-stage digital analog converter, in order to export an aanalogvoltage according to a M bit digital input code, this two-stage digital analog converter comprises:

One 1 Bits Serial electric charge rerouting digital analog converters, have in order to a high reference voltage that receives a high reference voltage and import node and import node in order to a low reference voltage that receives a low reference voltage, this 1 Bits Serial electric charge rerouting digital analog converter comprises:

One second switch circuit, be used in a plurality of electric charge rerouting cycles, this first electric capacity charge node is connected to this charge-trapping node, wherein those electric charge rerouting cycles are to follow those first electric capacity charge cycles, and those electric charge rerouting cycles are to correspond to the electric charge rerouting that utilizes this Terminal Capacitance to carry out;

One voltage selector, this voltage selector are with this high reference voltage with should be set to a plurality of selected accurate positions by low reference voltage according to this M bit digital input code; And

One Gamma correction expands and decision logic, finishes Gamma correction in order to see through the sign indicating number expansion according to this M bit digital input code.

9. LCD source electrode driver according to claim 8 is characterized in that, comprises:

One output operational amplifier, this output operational amplifier has input of one first operational amplifier and the input of one second operational amplifier, this first operational amplifier input is coupled to an output of this output operational amplifier, and this second operational amplifier input is coupled to this charge-trapping node; And

One built-in offset cancellation circuit is coupled to this output operational amplifier.

10. LCD source electrode driver according to claim 8 is characterized in that, this Gamma correction expands with decision logic and expands 1,2 or 3 of this M bit digital input codes; This 1 control code sequence is to be provided by this M bit digital input code institute serial of having expanded, and in this 1 control code sequence, least significant bit is provided earlier.