JP2013538535A - グリッチングが低減された多重化された増幅器 - Google Patents

グリッチングが低減された多重化された増幅器 Download PDF

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Publication number
JP2013538535A
JP2013538535A JP2013529266A JP2013529266A JP2013538535A JP 2013538535 A JP2013538535 A JP 2013538535A JP 2013529266 A JP2013529266 A JP 2013529266A JP 2013529266 A JP2013529266 A JP 2013529266A JP 2013538535 A JP2013538535 A JP 2013538535A
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JP
Japan
Prior art keywords
coupled
multiplexer
transistor
amplifier
circuit
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Pending
Application number
JP2013529266A
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English (en)
Japanese (ja)
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JP2013538535A5 (enExample
Inventor
エフ ペイン ロバート
Original Assignee
日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
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Publication of JP2013538535A publication Critical patent/JP2013538535A/ja
Publication of JP2013538535A5 publication Critical patent/JP2013538535A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
    • H03M1/0872—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches by disabling changes in the output during the transitions, e.g. by holding or latching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/122—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages
    • H03M1/1225—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Amplifiers (AREA)
JP2013529266A 2010-09-13 2011-09-13 グリッチングが低減された多重化された増幅器 Pending JP2013538535A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/880,311 US8248290B2 (en) 2010-09-13 2010-09-13 Multiplexed amplifier with reduced glitching
US12/880,311 2010-09-13
PCT/US2011/051411 WO2012037133A1 (en) 2010-09-13 2011-09-13 Multiplexed amplifier with reduced glitching

Publications (2)

Publication Number Publication Date
JP2013538535A true JP2013538535A (ja) 2013-10-10
JP2013538535A5 JP2013538535A5 (enExample) 2014-10-09

Family

ID=45806145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013529266A Pending JP2013538535A (ja) 2010-09-13 2011-09-13 グリッチングが低減された多重化された増幅器

Country Status (4)

Country Link
US (2) US8248290B2 (enExample)
JP (1) JP2013538535A (enExample)
CN (1) CN103098369B (enExample)
WO (1) WO2012037133A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8248290B2 (en) * 2010-09-13 2012-08-21 Texas Instruments Incorporated Multiplexed amplifier with reduced glitching
KR101809542B1 (ko) * 2011-12-26 2017-12-18 삼성전자주식회사 스위칭 회로, 이를 포함하는 전하량 검출 증폭기 및 광자 계수 검출 장치
US9311867B2 (en) 2012-11-13 2016-04-12 Apple Inc. Devices and methods for reducing power consumption of a demultiplexer
US9065470B2 (en) 2012-12-19 2015-06-23 Intel Corporation Low power analog to digital converter
US8872685B2 (en) * 2013-03-15 2014-10-28 Qualcomm Incorporated Techniques to reduce harmonic distortions of impedance attenuators for low-power wideband high-resolution DACs
EP3174210B1 (en) * 2015-11-24 2022-05-18 Nxp B.V. A data processor
US9755595B1 (en) 2016-04-15 2017-09-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Settling time reduction for low noise amplifier
CN112532250B (zh) * 2019-09-19 2024-10-25 亚德诺半导体国际无限责任公司 用于差分信号的模块化模拟信号多路复用器
US12445141B2 (en) * 2023-10-31 2025-10-14 Texas Instruments Incorporated Voltage-to-delay converter

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06164339A (ja) * 1992-11-17 1994-06-10 Nippondenso Co Ltd デジタル制御遅延装置及びデジタル制御発振装置
JPH0730342A (ja) * 1993-07-13 1995-01-31 Nec Corp 演算増幅回路
JP2000013232A (ja) * 1998-06-19 2000-01-14 Asahi Kasei Microsystems Kk パイプライン型ａ／ｄコンバータ
JP2004343395A (ja) * 2003-05-15 2004-12-02 Fuji Electric Device Technology Co Ltd パルス幅変調回路
JP2006074433A (ja) * 2004-09-02 2006-03-16 Renesas Technology Corp 半導体集積回路装置
JP2007201550A (ja) * 2006-01-23 2007-08-09 Seiko Epson Corp パイプラインａ／ｄ変換器
JP2008228247A (ja) * 2007-03-16 2008-09-25 Renesas Technology Corp パイプライン型ａ／ｄ変換器およびそれを内蔵した半導体集積回路
JP2010135905A (ja) * 2008-12-02 2010-06-17 Asahi Kasei Electronics Co Ltd パイプライン型ａ／ｄコンバータ、ホールド回路

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3877023A (en) 1973-05-21 1975-04-08 Texas Instruments Inc Antiglitch digital to analog converter system
US5180932A (en) 1990-03-15 1993-01-19 Bengel David W Current mode multiplexed sample and hold circuit
US5530444A (en) 1995-01-05 1996-06-25 Analog Devices, Inc. Differential amplifiers which can form a residue amplifier in sub-ranging A/D converters
US6218887B1 (en) 1996-09-13 2001-04-17 Lockheed Martin Corporation Method of and apparatus for multiplexing multiple input signals
US5867053A (en) 1997-03-21 1999-02-02 Motorola Inc. Multiplexed output circuit and method of operation thereof
US6323791B1 (en) * 1999-10-13 2001-11-27 Analog Devices, Inc. Control systems and methods for reducing residue signal offset in subranging analog-to-digital converters
US6489845B1 (en) 2000-04-04 2002-12-03 Goodrich Corporation Multiplexing amplifier
US7868665B2 (en) * 2002-03-05 2011-01-11 Nova R&D, Inc. Integrated circuit and sensor for imaging
US6583747B1 (en) * 2002-05-24 2003-06-24 Broadcom Corporation Subranging analog to digital converter with multi-phase clock timing
US6573853B1 (en) * 2002-05-24 2003-06-03 Broadcom Corporation High speed analog to digital converter
US8094056B2 (en) * 2006-02-02 2012-01-10 Clariphy Communications, Inc. Analog-to-digital converter
TWI333335B (en) * 2006-12-18 2010-11-11 Ind Tech Res Inst Analog to digital converting system
JP4854695B2 (ja) * 2008-03-14 2012-01-18 オンセミコンダクター・トレーディング・リミテッド 差動コンパレータ及びパイプライン型ａ／ｄ変換器
US7990185B2 (en) * 2008-05-12 2011-08-02 Menara Networks Analog finite impulse response filter
US8248290B2 (en) * 2010-09-13 2012-08-21 Texas Instruments Incorporated Multiplexed amplifier with reduced glitching

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06164339A (ja) * 1992-11-17 1994-06-10 Nippondenso Co Ltd デジタル制御遅延装置及びデジタル制御発振装置
JPH0730342A (ja) * 1993-07-13 1995-01-31 Nec Corp 演算増幅回路
JP2000013232A (ja) * 1998-06-19 2000-01-14 Asahi Kasei Microsystems Kk パイプライン型ａ／ｄコンバータ
JP2004343395A (ja) * 2003-05-15 2004-12-02 Fuji Electric Device Technology Co Ltd パルス幅変調回路
JP2006074433A (ja) * 2004-09-02 2006-03-16 Renesas Technology Corp 半導体集積回路装置
JP2007201550A (ja) * 2006-01-23 2007-08-09 Seiko Epson Corp パイプラインａ／ｄ変換器
JP2008228247A (ja) * 2007-03-16 2008-09-25 Renesas Technology Corp パイプライン型ａ／ｄ変換器およびそれを内蔵した半導体集積回路
JP2010135905A (ja) * 2008-12-02 2010-06-17 Asahi Kasei Electronics Co Ltd パイプライン型ａ／ｄコンバータ、ホールド回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JPN4005007757; Ｌａｕｒｉ　Ｓｕｍａｎｅｎ，　Ｍｉｋｋｏ　Ｗａｌｔａｒｉ，　Ｋａｒｉ　Ａ．Ｉ．　Ｈａｌｏｎｅｎ: 'Ａ　１０-ｂｉｔ　２００-ＭＳ／ｓ　ＣＭＯＳ　ｐａｒａｌｌｅｌ　Ｐｉｐｅｌｉｎｅ　Ａ／Ｄ　Ｃｏｎｖｅｒｔｅｒ' ＩＥＥＥ　ＪＯＵＲＮＡＬ　ＯＦ　ＳＯＬＩＤ-ＳＴＡＴＥ　ＣＩＲＣＵＩＴＳ ＶＯＬ．３６，ＮＯ．７, 200107, Ｐ１０４８-１０５５ *

Also Published As

Publication number Publication date
CN103098369A (zh) 2013-05-08
US20130021188A1 (en) 2013-01-24
WO2012037133A1 (en) 2012-03-22
US20120062402A1 (en) 2012-03-15
CN103098369B (zh) 2016-01-06
US8248290B2 (en) 2012-08-21

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