WO2012034394A1 - 一种三维结构非易失存储器阵列及其制备方法 - Google Patents

一种三维结构非易失存储器阵列及其制备方法 Download PDF

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WO2012034394A1
WO2012034394A1 PCT/CN2011/072370 CN2011072370W WO2012034394A1 WO 2012034394 A1 WO2012034394 A1 WO 2012034394A1 CN 2011072370 W CN2011072370 W CN 2011072370W WO 2012034394 A1 WO2012034394 A1 WO 2012034394A1
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layer
memory array
bottom electrode
resistive
dimensional
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PCT/CN2011/072370
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French (fr)
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蔡一茂
黄如
秦石强
唐粕人
张丽杰
唐昱
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北京大学
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Priority to US13/131,601 priority Critical patent/US20120061637A1/en
Publication of WO2012034394A1 publication Critical patent/WO2012034394A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/068—Patterning of the switching material by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present invention relates to the field of nonvolatile memory technology in the manufacturing technology of ultra large scale integrated circuits, and in particular to a three-dimensional structure nonvolatile memory array and a method for fabricating the same.
  • Non-volatile memory represented by flash memory
  • flash memory is widely used in various products, such as mobile phones, notebooks, PDAs, and SSDs, because of its data retention capability during power-off and the ability to erase data multiple times. Communication equipment.
  • flash memory has occupied most of the market share of non-volatile semiconductor memory.
  • Flash memory technology has been difficult to meet the needs of the development of non-volatile memory technology due to its poor precision in preparation technology, high operating voltage, and high power consumption.
  • the resistive memory realizes the function of nonvolatile storage by applying a voltage or current to the resistive material to change its resistance value and maintaining its high resistance or resistance state after the power is turned off.
  • the resistive memory has the advantages of compatibility with the existing large-scale integrated circuit manufacturing technology, strong shrink ratio capability, low operating voltage, fast operation speed, etc., and is a large-capacity, low-cost, high-performance non-easy one with great application potential in the future. Lost memory.
  • the three-dimensional structure can greatly increase the storage density of the nonvolatile memory, thereby reducing the storage cost.
  • the resistive memory memory usually adopts a cross bar structure and a multi-layer stack to realize a three-dimensional structure (see FIG. 1 ). This method requires photolithographic etching of each layer of electrodes to form a cross-hair structure. The number of lithography and etching is proportional to the number of layers in the stack, which greatly increases the difficulty and cost of the process.
  • the invention provides a three-dimensional structure resistive memory array and a manufacturing method thereof, which can improve the storage density of the resistive memory, simplify the process and reduce the process cost.
  • the data storage layer is a resistive material
  • the resistive material is located on the deep trench sidewall formed by the bottom electrode metal layer and the isolation dielectric layer
  • the top electrode and the bottom electrode cross on the deep trench sidewall, two at the intersection
  • There is a resistive material between the electrodes which together form a resistive memory and is isolated by the isolation dielectric layer.
  • a three-dimensional structure resistive memory array comprising: a substrate and a bottom electrode/isolation dielectric stack structure, a deep trench etched on the bottom electrode/isolation dielectric stack structure, and a resistive material deposited on the deep trench sidewall and The top electrode layer, wherein the bottom electrode and the top electrode are crisscrossed on the sidewall of the deep trench, and there is a resistive material between the intersections, and each intersection forms a resistive memory cell.
  • a three-dimensional resistive memory array formed by all memory cells, the three-dimensional resistive memory in the array is isolated by an isolation dielectric layer.
  • the thickness of the top and bottom electrode layers is preferably 50 to 100 nm, and the thickness of the isolation dielectric layer is generally 100 to 200 nm, and the thickness of the resistive material layer is 10 to 50 nm, and the layer of the bottom electrode/isolation dielectric stack structure
  • the number is determined by the level of the process and there is no limit in theory.
  • the deep trench etched on the bottom electrode/isolation dielectric stack structure has a width of 100 to 200 nm.
  • the substrate may be a silicon substrate, or may be quartz, an organic substrate or the like, and the isolation dielectric layer may be any insulating layer such as alumina, silicon oxide or the like.
  • the electrode layer may be selected from any metal or other conductive material which can be grown by evaporation or sputtering, such as metal Ti, Cu and compound TiN, to form a metal elemental film or other conductive film.
  • the method for preparing the three-dimensional structure resistive memory array provided by the present invention is as follows:
  • an isolation dielectric layer silicon dioxide, silicon nitride, etc.
  • an electrode metal layer aluminum, copper, titanium nitride, etc.
  • the stop layer is a dielectric isolation layer above the substrate.
  • a resistive material (such as oxidized ha, zirconia, titania, etc.) is deposited on the deep trench, and then the resistive material is etched such that the resistive material remains only on the side walls of the deep trench.
  • Electrode material electrode deposition is then performed and photolithographically etched to form a top electrode line. Thus there is a resistive material between the intersection of the sidewalls of the electrode material of each of the top and the previous electrodes.
  • a three-dimensional resistive memory array is formed in the vertical direction.
  • the specific steps include:
  • an isolation dielectric layer such as silicon dioxide, silicon nitride, etc.
  • a silicon or other substrate e.g., quartz, flexible substrate
  • Steps alternately deposit multiple layers of isolation dielectric layer and electrode metal layer, the total number of layers can be flexibly controlled, and the uppermost layer is the isolation dielectric layer.
  • a resistive material layer such as oxidized ha, zirconia, titanium oxide, etc.
  • the three-dimensional resistive device and the preparation method thereof have the following advantages: First, the whole The method of depositing the electrode material and the dielectric material, and then photolithographic etching, can effectively reduce the lithography and engraving compared to the prior art, in which each layer of the electrode material needs to be lithographically and etched. The number of eclipses greatly reduces process steps and reduces process costs. Second, the size of the intersection of the bottom electrode and the top electrode is controlled by the deposition thickness of the bottom electrode material, and thus is not limited by the resolution of the lithography, and the device size can be further effectively reduced to increase the storage density.
  • the above three-dimensional structure resistive memory array and its preparation method are economical and efficient methods for increasing the density of the resistive memory.
  • FIG. 1 is a schematic diagram of a three-dimensional structure resistive memory array of the prior art, wherein
  • FIG. 2 is a schematic diagram of a three-dimensional structure resistive memory array of the present invention, wherein
  • 3(a) to (e) are schematic views showing a method of fabricating a three-dimensional structure resistive memory array in accordance with a preferred embodiment of the present invention. detailed description
  • the inventors have found through research that if the three-dimensional technology is suitably applied to a resistive memory device, the advantages of the two technologies of the new memory material and the three-dimensional integrated technology can be combined to solve the existing nonvolatile memory. Reduced shrinkage, high power consumption and high voltage operation, and can further increase the storage density of non-volatile memory devices and improve the performance of memory devices. If the process can be optimized, without increasing the complexity of the process, a three-dimensional resistive memory array and its preparation method will be proposed, which will greatly reduce the storage density and performance of the nonvolatile memory.
  • the present invention provides a novel three-dimensional resistive memory device array and a manufacturing method thereof, which can form a three-dimensional form by alternately depositing a stack of dielectric layer electrode layers and forming a whole lithography etch and a sidewall resistive material.
  • the resistive device structure increases storage density and reduces process steps and costs.
  • the three-dimensional resistive memory device array provided by the present invention is shown in FIG. 2, and includes: 01—silicon substrate, 02—bottom electrode, 03—isolation dielectric layer, 04—resistive material, 05—top electrode.
  • 01 and the top electrode 05 intersect on the deep groove side wall of the bottom electrode/resistive material stack structure with a resistive material 04 between the intersections.
  • Each intersection forms a memory cell, and all cells form an array of three-dimensional resistive memory devices that are isolated by a dielectric layer.
  • the manufacturing method of the above three-dimensional resistive memory device array includes:
  • an isolation dielectric layer silicon dioxide, silicon nitride, etc.
  • an electrode metal layer aluminum, copper, titanium nitride, etc.
  • the top layer is a dielectric layer cover.
  • deep trench etching is performed, and the stop layer is a dielectric isolation layer above the substrate.
  • a resistive material such as oxidized ha, zirconia, titanium oxide, etc. is deposited on the deep trench, and then the resistive material is etched so that the resistive material remains only on the side walls of the deep trench.
  • Electrode material electrode deposition is then performed and photolithographic etching is performed to form a top electrode line.
  • a resistive material between the intersection of each of the top electrodes and the sidewalls of the electrode material of the previous electrode.
  • a three-dimensional resistive memory array is formed in the vertical direction.
  • dielectric layer 100 to 200 nm (in this embodiment, silicon dioxide) on a silicon substrate, the dielectric layer functioning as an electrical isolation;

Abstract

本发明提供一种三维结构阻变存储器阵列及其制造方法，属于超大规模集成电路制造技术中的非易失存储器技术领域。本发明三维结构阻变存储器阵列包括衬底和底电极/隔离介质堆栈结构，在底电极/隔离介质堆栈结构上刻蚀出深槽，在深槽侧壁上淀积阻变材料以及顶电极层，其中底电极和顶电极在深槽侧壁上呈十字交叉，交叉点之间有阻变材料，每个交叉点形成一个阻变存储器单元，所有的阻变存储器单元形成三维阻变存储器阵列，阵列中的三维阻变存储器由隔离介质层隔离。本发明可以提高阻变存储器的存储密度，并且简化工艺，降低工艺成本。

Description

一种三维结构非易失存储器阵列及其制备方法 技术领域
本发明属于超大规模集成电路制造技术中的非易失存储器技术领域， 具体涉及一种三维 结构非易失存储器阵列及其制备方法。
背景技术
以闪存为代表的非易失存储器因为其断电情况下的数据保持能力以及可多次擦写数据等 优点被广泛应用于各种产品中,比如手机， 笔记本， 掌上电脑和固态硬盘等存储及通讯设备。 如今闪存已经占据了非易失半导体存储器的大部分市场份额， 然而随着信息社会中人们对大 容量、 底成本、 底功耗和高性能等方面需求的日益提高以及半导体技术的高速发展， 现有闪 存技术由于其制备技术縮比能力差， 工作电压较高， 功耗较大等因素已经难于满足非易失存 储器技术发展的需求。 阻变存储器通过对阻变材料施加电压或电流改变其阻值， 并在断电后 能够保持其高阻或电阻状态， 从而实现非易失存储的功能。 阻变存储器具有和现有大规模集 成电路制造技术相兼容， 縮比能力强， 操作电压低、 操作速度快等优点， 是未来具有较大应 用潜力的大容量、 低成本、 高性能的非易失存储器。 两外一方面， 采用三维结构可以大大增 加非易失存储器的存储密度， 从而降低存储成本。 阻变存储器通常采用十字线（cross bar) 的 结构和多层堆栈的方式来实现三维架构 （如图 1 ) ， 这种方式需要对每一层电极进行光刻刻 蚀来形成十字线结构， 因此光刻和刻蚀次数和堆栈的层数成正比， 大大增加了工艺的难度和 成本。
总而言之， 如何采用简单的工艺实现三维结构的阻变存储器阵列是非易失存储器技术亟 待解决的难题之一。
发明内容
本发明提供一种三维结构阻变存储器阵列及其制造方法， 可以提高阻变存储器的存储密 度， 并且简化工艺， 降低工艺成本。 其中， 数据存储层为阻变材料， 阻变材料位于由底电极 金属层和隔离介质层形成的深槽侧壁上， 顶电极和底电极在深槽侧壁上交叉， 在交叉点的两 个电极之间有阻变材料， 共同形成阻变存储器， 并通过隔离介质层进行隔离。
上述目的是通过如下技术方案实现的：
一种三维结构阻变存储阵列， 包括： 衬底和底电极 /隔离介质堆栈结构， 在底电极 /隔离介 质堆栈结构上刻蚀出的深槽， 在深槽侧壁上淀积阻变材料以及顶电极层， 其中底电极和顶电 极在深槽侧壁上呈十字交叉， 交叉点之间有阻变材料， 每个交叉点形成一个阻变存储器单元。 所有的存储单元形成的三维阻变存储器阵列， 阵列中的三维阻变存储器由隔离介质层隔离。 上述顶、底电极层的厚度以 50〜100纳米为宜， 而隔离介质层的厚度一般在 100〜200纳 米， 阻变材料层的厚度在 10〜50纳米， 底电极 /隔离介质堆栈结构的层数由工艺水平决定， 理论上并无限制。 底电极 /隔离介质堆栈结构上刻蚀出的深槽宽度为 100~200纳米。
对衬底、 隔离介质层和底、 顶电极层的材料无特殊要求。 衬底可以是硅衬底， 也可以是 石英、 有机性衬底等， 隔离介质层可以是氧化铝、 氧化硅等等任何绝缘层。 电极层可以根据 需要选择任何可通过蒸发或者溅射方式生长的金属或者其它导电材料，例如金属 Ti， Cu和化 合物 TiN， 形成金属单质薄膜或其它导电薄膜。
本发明提供的三维结构阻变存储器阵列的制备方法如下：
通过交替淀积介质和电极材料层后进行深槽刻蚀， 在深槽侧壁上淀积并刻蚀形成阻变材 料， 然后淀积顶电极金属材料并光刻、 刻蚀形成顶电极线条， 在顶电极以及先前淀积的底电 极材料层的交叉位置上形成三维的阻变存储器阵列。 具体的， 在硅或其他衬底上 （如石英、 柔性衬底）交替淀积隔离介质层（二氧化硅， 氮化硅等）和电极金属层（铝、铜、氮化钛等）， 顶层为介质层覆盖。 在介质隔离层和电极材料层交替的堆栈结构上， 进行深槽刻蚀， 停止层 为衬底上方的一层介质隔离层。在深槽上淀积阻变材料（如氧化哈，氧化锆，氧化钛等材料）， 然后进行阻变材料刻蚀， 使得仅在深槽的侧墙上保留阻变材料。 接着进行电极材料电极淀积 并进行光刻刻蚀， 形成顶电极线条。 这样在每个顶电极和先前电极的电极材料侧壁的交叉点 之间都有阻变材料。 在垂直方向上形成了三维阻变存储器阵列。
具体步骤包括：
( 1 ) 在在硅或其他衬底上 （如石英、 柔性衬底） 上生长或淀积隔离介质层 （如二氧化 硅、 氮化硅等）， 该介质层起电学隔离的作用；
(2) 在隔离介质层上淀积电极金属层；
(3) 重复 （1 ) (2) 步骤交替淀积多层隔离介质层、 电极金属层， 总层数可以灵活控 制， 最上层为隔离介质层。
(4) 光刻并刻蚀上面淀积的多层隔离介质层 /电极金属层结构至最底层介质层，从而开 出多个深槽， 其侧壁为离介质层、 电极金属层堆栈结构；
(5) 以深槽为窗口淀积阻变材料层 （如氧化哈， 氧化锆， 氧化钛等材料）， 并且通过 回刻工艺， 仅保留深槽侧壁上的阻变材料层；
淀积电极金属层， 并光刻刻蚀形成顶电极， 该电极和深槽侧壁上的阻变材料和金属层形 成三维的阻变存储器件及其阵列；
与现有技术相比， 本发明提出的三维阻变器件及其制备方法有如下优势： 第一， 先整体 淀积电极材料和介质材料， 然后再光刻刻蚀的方法， 比起现有技术中材料每淀积一层电极材 料都需要进行一次光刻和刻蚀相比， 可以有效减少光刻和刻蚀次数， 大大减少工艺步骤和降 低工艺成本。 第二， 底电极和顶电极交叉点的尺寸由底电极材料的淀积厚度控制， 因此不受 光刻分辨率的限制， 可以进一步有效縮小器件尺寸提高存储密度。
因此， 上述三维结构阻变存储器阵列及其制备方法是经济且高效的提升阻变存储器密度 的方法。
附图说明
通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在全部附图中相同 的附图标记指示相同的部分。 并未刻意按实际尺寸等比例縮放绘制附图， 重点在于示出本发 明的主旨。
图 1 为现有技术的三维结构阻变存储器阵列示意图， 其中
1一顶电极， 2—底电极， 3—阻变材料
图 2 为本发明的三维结构阻变存储器阵列示意图， 其中
01_硅衬底， 02_底电极， 03—阻变材料, 04—阻变材料， 05_顶电极
图 3 ( a) ~ (e) 为本发明优选实施例三维结构阻变存储器阵列的制造方法的示意图。 具体实施方式
为使本发明的上述目的、 特征和优点能够更加明显易懂， 下面结合附图对本发明的具体 实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明， 但是本发明还可以采用其 他不同于在此描述的其它方式来实施， 本领域技术人员可以在不违背本发明内涵的情况下做 类似推广， 因此本发明不受下面公开的具体实施例的限制。
其次， 本发明结合示意图进行详细描述， 在详述本发明实施例时， 为便于说明， 表示器 件结构的剖面图会不依一般比例作局部放大， 而且所述示意图只是示例， 其在此不应限制本 发明保护的范围。 此外， 在实际制作中应包含长度、 宽度及深度的三维空间尺寸。
正如本发明背景技术的介绍， 发明人经过研究发现， 若将三维技术合适地运用在阻变存 储器件， 可以结合新存储材料和三维集成技术两种技术的优势， 解决现有非易失存储器的縮 比能力减弱， 操作功耗和电压高的问题， 并能进一步提高非易失存储器件的存储密度， 提升 存储器件性能。 如果能通过工艺优化， 在不增加工艺复杂性的前提下， 提出三维的阻变存储 器阵列和其制备方法， 将极大地非易失存储器的存储密度和性能。 基于此， 本发明提出一种新的三维阻变存储器件阵列及其制造方法， 可以运用介质层电 极层交替淀积堆栈以及整体光刻刻蚀和侧墙阻变材料形成的方法，可形成三维阻变器件结构， 增加存储密度， 并减少工艺步骤， 降低成本。
本发明提供的三维阻变存储器件阵列如图 2所示，包括 : 01—硅衬底， 02—底电极， 03— 隔离介质层， 04—阻变材料， 05—顶电极。 底电极 01和顶电极 05在底电极 /阻变材料堆栈结 构的深槽侧壁上交叉， 交叉点之间有阻变材料 04。 每个交叉点形成一个存储单元， 所有的单 元形成三维阻变存储器件阵列， 并由介质层进行隔离。
上述三维阻变存储器件阵列的制造方法， 包括：
在硅或其他衬底上 （如石英、 柔性衬底） 交替淀积隔离介质层 （二氧化硅， 氮化硅等） 和电极金属层（铝、 铜、 氮化钛等）， 顶层为介质层覆盖。 在介质隔离层和电极材料层交替的 堆栈结构上， 进行深槽刻蚀， 停止层为衬底上方的一层介质隔离层。 在深槽上淀积阻变材料 (如氧化哈， 氧化锆， 氧化钛等材料）， 然后进行阻变材料刻蚀， 使得仅在深槽的侧墙上保留 阻变材料。 接着进行电极材料电极淀积并进行光刻刻蚀， 形成顶电极线条。 这样在每个顶电 极和先前电极的电极材料侧壁的交叉点之间都有阻变材料。 在垂直方向上形成了三维阻变存 储器阵列。
下面结合附图详细说明本发明提供的三维阻变存储器件阵列的制造方法的优选实施例。
( 1 ) 在硅衬底上上淀积隔离 100~200纳米介质层 （本实施例为二氧化硅）， 该介质层起 电学隔离的作用；
(2) 在隔离介质层上淀积 50~100纳米的 ΉΝ电极层；
(3)重复（1 ) (2)步骤交替淀积多层隔离介质层、 电极金属层， 总层数可以灵活控制， 最上层为隔离介质层， 如图 3(a) 所示。
(4) 光刻并刻蚀上面淀积的多层隔离介质层 /电极金属层结构至最底层介质层， 从而开 出多个深槽， 深槽宽度为 100~200纳米， 其侧壁为离介质层、 电极金属层堆栈结构， 如图 3(b) 所示；
(5) 以深槽为窗口淀积 10~50纳米厚的阻变材料层 （本实施例为为氧化钛）， 并且通过 回刻工艺， 仅保留深槽侧壁上的阻变材料层， 如图 3(c) 所示；
(6) 淀积 50~100纳米的 TiN电极层 （图 3(d)), 并光刻刻蚀形成顶电极， 该电极和深槽 侧壁上的阻变材料和金属层形成三维的阻变存储器件及其阵列，如图 3(e) 所示；
以上所述， 仅是本发明的较佳实施例而已， 并非对本发明作任何形式上的限制。 此外， 所述半导体器件及其制造方法也可以用于其他衬底， 阻变材料。 隔离介质层以及电极材料构 成的阻变存储器阵列， 在此不再赘述。 虽然本发明已以较佳实施例披露如上， 然而并非用以限定本发明。 任何熟悉本领域的技 术人员， 在不脱离本发明技术方案范围情况下， 都可利用上述揭示的方法和技术内容对本发 明技术方案作出许多可能的变动和修饰， 或修改为等同变化的等效实施例。 因此， 凡是未脱 离本发明技术方案的内容， 依据本发明的技术实质对以上实施例所做的任何简单修改、 等同 变化及修饰， 均仍属于本发明技术方案保护的范围内。

Claims

权 利 要 求 书 、 一种三维结构阻变存储器阵列， 其特征在于， 包括衬底和底电极 /隔离介质堆栈结构， 在底电极 /隔离介质堆栈结构上刻蚀而成多个深槽， 在上述深槽内设有阻变材料层和 顶电极材料层， 形成十字交叉的横向底电极和纵向顶电极， 交叉的底电极和顶电极 之间为阻变材料， 每个交叉结构为一个阻变存储单元， 从而形成三维阻变存储器阵 列。
、 如权利要求 1所述的三维结构阻变存储器阵列的存储单元， 其特征在于： 存储单元的 阻变材料层位于底电极 /隔离介质堆栈结构上刻蚀而成的深槽侧壁上。
、 一种三维结构阻变存储器阵列的制备方法， 其步骤包括：
1)在衬底上通过交替淀积介质和底电极材料层， 形成底电极层 /介质层的堆栈结构；
2)在底电极层 /介质层的堆栈结构上进行刻蚀形成多个深槽， 在深槽侧壁上淀积并刻 蚀形成阻变材料层；
3)在深槽内淀积顶电极金属材料并刻蚀形成顶电极线条，顶电极和底电极在深槽侧壁 上交叉， 形成三维的阻变存储器阵列。
、 如权利要求 3所述的三维结构阻变存储器阵列的制备方法， 其特征在于： 在底电极 层 /介质层的堆栈结构上进行光刻和刻蚀形成深槽， 深槽底部位于衬底上的第一层介 质层。
、 如权利要求 3所述的三维结构阻变存储器阵列的制备方法， 其特征在于： 上述底电 极层 /介质层的堆栈结构中底电极材料层的厚度为 50~100纳米。
、 如权利要求 3所述的三维结构阻变存储器阵列的制备方法， 其特征在于： 上述底电 极层 /介质层的堆栈结构中介质层的厚度为 100~200纳米。
、 如权利要求 3所述的三维结构阻变存储器阵列的制备方法， 其特征在于： 上述深槽 宽度为 100~200纳米。
、 如权利要求 3所述的三维结构阻变存储器阵列的制备方法， 其特征在于： 上述阻变 材料层的厚度为 10~50纳米。
、 如权利要求 3所述的三维结构阻变存储器阵列的制备方法， 其特征在于： 上述顶电 极材料层的厚度为 50~100纳米。
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101976676A (zh) * 2010-09-13 2011-02-16 北京大学 一种三维结构非易失存储器阵列及其制备方法
CN102522418B (zh) * 2011-12-29 2013-09-11 北京大学 具有交叉阵列结构的自整流阻变存储器及制备方法
CN102522501A (zh) * 2011-12-29 2012-06-27 北京大学 具有交叉阵列结构的阻变存储器及制备方法
KR20130082344A (ko) * 2012-01-11 2013-07-19 에스케이하이닉스 주식회사 반도체 메모리 장치, 메모리 칩, 메모리 모듈, 메모리 시스템 및 반도체 메모리 장치의 제조방법
KR20140068627A (ko) * 2012-11-28 2014-06-09 삼성전자주식회사 가변저항막을 갖는 저항 메모리 소자 및 그 제조방법
CN102969328B (zh) * 2012-12-06 2015-09-16 北京大学 阻变存储器交叉阵列结构及其制备方法
CN103022350B (zh) * 2012-12-28 2015-01-07 北京大学 忆阻器件及其制备方法
KR102147628B1 (ko) 2013-01-21 2020-08-26 삼성전자 주식회사 메모리 시스템
US8829581B1 (en) 2013-04-19 2014-09-09 Hewlett-Packard Development Company, L.P. Resistive memory devices
US9099648B2 (en) 2013-05-02 2015-08-04 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor memory device and semiconductor memory device
CN104409632B (zh) * 2014-05-31 2017-05-10 福州大学 一种多层结构有机阻变存储器的3d打印制备方法
KR102140788B1 (ko) 2014-07-18 2020-08-03 삼성전자주식회사 저항성 메모리 장치, 저항성 메모리 시스템 및 저항성 메모리 장치의 동작방법
CN106205681A (zh) * 2015-04-29 2016-12-07 复旦大学 用于三维竖直堆叠阻变存储器抑制IR drop电压降和读写干扰的架构和操作算法
US10593600B2 (en) 2016-02-24 2020-03-17 International Business Machines Corporation Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap
CN108305936A (zh) * 2017-01-12 2018-07-20 中芯国际集成电路制造(上海)有限公司 阻变随机存储器存储单元及其制作方法、电子装置
US20180315794A1 (en) * 2017-04-26 2018-11-01 Sandisk Technologies Llc Methods and apparatus for three-dimensional nonvolatile memory
CN109256462B (zh) * 2018-09-11 2022-12-06 西安建筑科技大学 一种集成化阻变存储器及其制备方法
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CN113421963A (zh) * 2021-06-10 2021-09-21 北京大学 一种低功耗三维阻变存储器

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090218558A1 (en) * 2008-02-28 2009-09-03 Jun-Beom Park Semiconductor device and method of forming the same
US20090317540A1 (en) * 2008-06-18 2009-12-24 Gurtej Sandhu Methods Of Forming A Non-Volatile Resistive Oxide Memory Array
US20100178729A1 (en) * 2009-01-13 2010-07-15 Yoon Hongsik Resistance-Type Random Access Memory Device Having Three-Dimensional Bit Line and Word Line Patterning
CN101826545A (zh) * 2009-03-03 2010-09-08 旺宏电子股份有限公司 集成电路自对准三度空间存储阵列及其制作方法
WO2010101340A1 (ko) * 2009-03-05 2010-09-10 광주과학기술원 3차원 구조를 갖는 저항 변화 메모리 소자, 저항 변화 메모리 소자 어레이, 전자제품 및 상기 소자 제조방법
JP2010251479A (ja) * 2009-04-14 2010-11-04 Sharp Corp 不揮発性半導体記憶装置とその製造方法
CN101976676A (zh) * 2010-09-13 2011-02-16 北京大学 一种三维结构非易失存储器阵列及其制备方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2202816B1 (en) * 2008-12-24 2012-06-20 Imec Method for manufacturing a resistive switching memory device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090218558A1 (en) * 2008-02-28 2009-09-03 Jun-Beom Park Semiconductor device and method of forming the same
US20090317540A1 (en) * 2008-06-18 2009-12-24 Gurtej Sandhu Methods Of Forming A Non-Volatile Resistive Oxide Memory Array
US20100178729A1 (en) * 2009-01-13 2010-07-15 Yoon Hongsik Resistance-Type Random Access Memory Device Having Three-Dimensional Bit Line and Word Line Patterning
CN101826545A (zh) * 2009-03-03 2010-09-08 旺宏电子股份有限公司 集成电路自对准三度空间存储阵列及其制作方法
WO2010101340A1 (ko) * 2009-03-05 2010-09-10 광주과학기술원 3차원 구조를 갖는 저항 변화 메모리 소자, 저항 변화 메모리 소자 어레이, 전자제품 및 상기 소자 제조방법
JP2010251479A (ja) * 2009-04-14 2010-11-04 Sharp Corp 不揮発性半導体記憶装置とその製造方法
CN101976676A (zh) * 2010-09-13 2011-02-16 北京大学 一种三维结构非易失存储器阵列及其制备方法

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