WO2021003904A1 - 一种相变存储器及其制作方法 - Google Patents

一种相变存储器及其制作方法 Download PDF

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WO2021003904A1
WO2021003904A1 PCT/CN2019/115202 CN2019115202W WO2021003904A1 WO 2021003904 A1 WO2021003904 A1 WO 2021003904A1 CN 2019115202 W CN2019115202 W CN 2019115202W WO 2021003904 A1 WO2021003904 A1 WO 2021003904A1
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material layer
phase change
change memory
transition
transition material
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PCT/CN2019/115202
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English (en)
French (fr)
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宋志棠
宋三年
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中国科学院上海微系统与信息技术研究所
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Priority to US17/607,892 priority Critical patent/US20220231224A1/en
Publication of WO2021003904A1 publication Critical patent/WO2021003904A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H10N70/8616—Thermal insulation means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the invention belongs to the field of microelectronics technology, and relates to a phase change memory and a manufacturing method thereof.
  • PCM has the advantages of non-volatility, good miniaturization performance, compatibility with CMOS technology, long cycle life, high-speed reading, multi-level storage, and radiation resistance. It is considered to be the most promising next-generation non-volatile storage technology. Especially in SCM applications, there is a broad market prospect.
  • the principle of PCM is to use the huge difference in resistivity before and after the phase change of the material to realize data storage. In PCM, one state (ie, crystalline state) has a low resistivity, and the other state (ie, amorphous state) has a higher resistivity. Logic "1" or logic "0" depends on the resistance state of the phase change material. Internationally, large companies such as Intel, Micron, Samsung, TSMC, and STMicroelectronics are carrying out research and industrialization of PCM memory.
  • phase change memory 3D Xpoint suitable for SCM.
  • Intel and Micron have not announced the use of phase change memory.
  • the phase-change memory cell and the strobe tube unit are made of various materials, and the unit performance of the device is not disclosed. It is very important to develop phase-change memory materials and structures with independent intellectual property rights.
  • the purpose of the present invention is to provide a method for manufacturing a phase change memory, which is used to solve the problem that the phase change memory in the prior art cannot meet the application requirements of storage memory.
  • the present invention provides a method for manufacturing a phase change memory, which includes the following steps:
  • a substrate is provided, and a stacked structure is formed on the substrate.
  • the stacked structure includes a first electrode material layer, a first transition material layer, a threshold gate tube material layer, and a second transition material from bottom to top. Layer, second electrode material layer, third transition material layer, phase change material layer, fourth transition material layer, and third electrode material layer;
  • isolation grooves in the laminated structure opening from the top surface of the laminated structure and extending downward to the surface of the substrate to divide the laminated structure into a plurality of columnar structures;
  • An isolation material layer is formed in the isolation groove, and the isolation material layer surrounds the side surface of the columnar structure.
  • the materials of the first transition material layer, the second transition material layer, the third transition material layer, and the fourth transition material layer respectively include C, Ta, TaC, TaN, Nb, NbN And at least one of SiC.
  • the thickness of the first transition material layer is in the range of 2-10 nm
  • the thickness of the second transition material layer is in the range of 2-10 nm
  • the thickness of the third transition material layer is in the range of 2-10 nm
  • the thickness of the fourth transition material layer is in the range of 2-10 nm.
  • the first electrode material layer, the first transition material layer, the threshold gate tube material layer, the second transition material layer, the second electrode material layer, and the third The methods for the transition material layer, the phase change material layer, the fourth transition material layer, and the third electrode material layer include sputtering, evaporation, atomic layer deposition, chemical vapor deposition, metal organic thermal At least one of decomposition method and laser assisted deposition method.
  • the method of forming the isolation trench includes reactive ion etching.
  • the material layer of the threshold gate tube selects chalcogenide compound materials with switching characteristics, including Ge-Se series materials, Ge-As-Se series materials, Ge-As-Se-Si series materials, Ge-As -One of Se-Si-Te series materials and Ge-As-Se-Si-N series materials, or a compound obtained by doping one or two elements of N and C.
  • the phase change material layer selects a chalcogenide compound material with phase change characteristics, including one of Sb 2 Te 3 , Sb 2 Te and Ge 2 Sb 2 Te 5 , or one of them is doped with Ta , Hf and C one or two elements modified compound.
  • the materials of the first electrode material layer, the second electrode material layer, and the third electrode material layer respectively include at least one of W, TiN, TiSiN, and AlN.
  • the present invention also provides a phase change memory, including:
  • phase change memory cells are located on the substrate, and the phase change memory cells include a first electrode material layer, a first transition material layer, a threshold gate tube material layer, and a second transition material layer in order from bottom to top , The second electrode material layer, the third transition material layer, the phase change material layer, the fourth transition material layer and the third electrode material layer;
  • the isolation material layer is separately arranged on the substrate and surrounds the side surface of the phase change memory cell, and each phase change memory cell is isolated from each other by the isolation material layer.
  • the cross-sectional area of the phase change material layer and the threshold gate tube material layer are the same.
  • the materials of the first transition material layer, the second transition material layer, the third transition material layer, and the fourth transition material layer respectively include C, Ta, TaC, TaN, Nb, NbN And at least one of SiC.
  • the thickness of the first transition material layer is in the range of 2-10 nm
  • the thickness of the second transition material layer is in the range of 2-10 nm
  • the thickness of the third transition material layer is in the range of 2-10 nm
  • the thickness of the fourth transition material layer is in the range of 2-10 nm.
  • the material layer of the threshold gate tube selects chalcogenide compound materials with switching characteristics, including Ge-Se series materials, Ge-As-Se series materials, Ge-As-Se-Si series materials, Ge-As -One of Se-Si-Te series materials and Ge-As-Se-Si-N series materials, or a compound obtained by doping one or two elements of N and C.
  • the phase change material layer selects a chalcogenide compound material with phase change characteristics, including one of Sb 2 Te 3 , Sb 2 Te and Ge 2 Sb 2 Te 5 , or one of them is doped with Ta , Hf and C one or two elements modified compound.
  • the materials of the first electrode material layer, the second electrode material layer, and the third electrode material layer respectively include at least one of W, TiN, TiSiN, and AlN.
  • the transition layer material has lower thermal conductivity, which can improve the thermal efficiency of the phase change memory, thereby reducing the power consumption of the phase change memory cell.
  • the transition layer material has good thermal stability, and has good adhesion to the dielectric material, phase change material, OTS gate material and electrode material, and can prevent the electrode material from the phase change material and OTS gate material The role of mutual diffusion, improving adhesion and increasing cycle life.
  • the transition layer material has good electrical conductivity, which can avoid the introduction of large resistance. Since the phase change material and the OTS material are confined between the dielectric materials, this structure can avoid the diffusion and volatilization of the phase change material and the OTS material element during operation, which is beneficial to prolong the life of the device.
  • the existence of the transition layer avoids the diffusion of elements at the interface, and at the same time reduces the heat loss during device operation, which is beneficial to the reduction of device power consumption.
  • High density can be achieved by reducing the size of phase change materials and OTS materials. Therefore, the phase change memory of the present invention has the characteristics of high density, high speed, low power consumption and long life.
  • FIG. 1 shows a process flow chart of the manufacturing method of the phase change memory of the present invention.
  • FIG. 2 shows a schematic diagram of forming a first electrode material layer on the substrate in the manufacturing method of the phase change memory of the present invention.
  • FIG. 3 shows a schematic diagram of the method for manufacturing a phase change memory of the present invention forming a first transition material layer on the first electrode material layer.
  • FIG. 4 is a schematic diagram of forming a threshold gate tube material layer on the first transition material layer in the manufacturing method of the phase change memory of the present invention.
  • FIG. 5 shows a schematic diagram of forming a second transition material layer on the threshold gate tube material layer in the manufacturing method of the phase change memory of the present invention.
  • FIG. 6 shows a schematic diagram of the method for manufacturing a phase change memory of the present invention to form a second electrode material layer on the second transition material layer.
  • FIG. 7 shows a schematic diagram of forming a third transition material layer on the second electrode material layer in the manufacturing method of the phase change memory of the present invention.
  • FIG. 8 shows a schematic diagram of forming a phase change material layer on the third transition material layer in the manufacturing method of the phase change memory of the present invention.
  • FIG. 9 shows a schematic diagram of a fourth transition material layer formed on the phase change material layer in the manufacturing method of the phase change memory of the present invention.
  • FIG. 10 shows a schematic diagram of a third electrode material layer formed on the fourth transition material layer in the manufacturing method of the phase change memory of the present invention.
  • FIG. 11 is a schematic diagram of forming isolation trenches in the laminated structure in the manufacturing method of the phase change memory of the present invention.
  • FIG. 12 is a schematic diagram of forming an isolation material layer in the isolation trench by the manufacturing method of the phase change memory of the present invention.
  • the present invention provides a manufacturing method of a phase change memory. Please refer to FIG. 1, which shows a process flow chart of the method, including the following steps:
  • the laminated structure includes a first electrode material layer, a first transition material layer, a threshold gate tube material layer, and a second Transition material layer, second electrode material layer, third transition material layer, phase change material layer, fourth transition material layer, and third electrode material layer;
  • step S1 is performed to form the stacked structure on the substrate 1.
  • the substrate 1 includes, but is not limited to, semiconductor materials such as Si, Ge, SiGe, and III-V compounds.
  • the Si substrate is taken as an example.
  • a solution of acetone and alcohol is used to clean the Si substrate for 3 minutes under the action of ultrasonic waves, and then bake at 120°C for 20 minutes. This cleaning step helps to improve the deposition quality of subsequent film layers.
  • the cleaning method may be different, as long as it can meet the requirements of obtaining a clean substrate surface, and the protection scope of the present invention should not be excessively limited here.
  • forming the laminated structure includes the following steps:
  • step S1-1 is performed: forming a first electrode material layer 2 on the substrate 1.
  • the method of forming the first electrode material layer 2 includes but is not limited to at least one of sputtering, evaporation, atomic layer deposition, chemical vapor deposition, metal organic thermal decomposition, and laser assisted deposition .
  • the material of the first electrode material layer 2 includes but is not limited to at least one of W, TiN, TiSiN, and AlN.
  • the magnetron sputtering method is used to deposit the first electrode material layer 2 with a thickness of 50 nm, the background vacuum during sputtering is 4 ⁇ 10 -6 Torr, and the vacuum during sputtering is 0.18 Pa.
  • the electrode material is W.
  • step S1-2 is performed: forming a first transition material layer 3 on the first electrode material layer 2.
  • the method of forming the first transition material layer 3 includes but is not limited to at least one of sputtering, evaporation, atomic layer deposition, chemical vapor deposition, metal organic thermal decomposition, and laser assisted deposition .
  • the material of the first transition material layer 3 includes but is not limited to at least one of C, Ta, TaC, TaN, Nb, NbN, and SiC, such as one, two, three, or four of them.
  • the thickness of the first transition material layer 3 is in the range of 2-10 nm.
  • the magnetron sputtering method is used to deposit the first transition material layer 3 with a thickness of 5 nm, the background vacuum during sputtering is 4 ⁇ 10 -6 Torr, and the vacuum during sputtering is 0.2 Pa.
  • the material of the first transition material layer is C.
  • step S1-3 is performed: forming a threshold gate tube (OTS) material layer 4 on the first transition material layer 3.
  • OTS threshold gate tube
  • the threshold gate tube material layer 4 selects chalcogenide compound materials with switching characteristics, including but not limited to Ge-Se series materials, Ge-As-Se series materials, Ge-As-Se-Si series materials, One of Ge-As-Se-Si-Te series materials and Ge-As-Se-Si-N series materials, or one of them is modified by doping one or two of N and C elements Compound.
  • the magnetron sputtering method is used to deposit OTS material with a thickness of 30nm, the background vacuum during sputtering is 4 ⁇ 10 -6 Torr, the vacuum during sputtering is 0.2Pa, and the OTS material used is Ge- As-Se-Te series materials.
  • step S1-4 is performed: forming a second transition material layer 5 on the threshold gate tube material layer 4.
  • the method for forming the second transition material layer 5 includes but is not limited to at least one of sputtering, evaporation, atomic layer deposition, chemical vapor deposition, metal organic thermal decomposition, and laser assisted deposition .
  • the material of the second transition material layer 5 includes but is not limited to at least one of C, Ta, TaC, TaN, Nb, NbN, and SiC, such as one, two, three or four of them.
  • the thickness of the second transition material layer 5 is in the range of 2-10 nm.
  • the magnetron sputtering method is used to deposit the second transition material layer with a thickness of 5nm, the background vacuum during sputtering is 4 ⁇ 10 -6 Torr, and the vacuum during sputtering is 0.2Pa.
  • the transition material layer material is C.
  • step S1-5 is performed: forming a second electrode material layer 6 on the second transition material layer 5.
  • the method for forming the second electrode material layer 6 includes but is not limited to at least one of sputtering, evaporation, atomic layer deposition, chemical vapor deposition, metal organic thermal decomposition, and laser assisted deposition .
  • the material of the second electrode material layer 6 includes but is not limited to at least one of W, TiN, TiSiN, and AlN.
  • the magnetron sputtering method is used to deposit the second electrode material layer 6 with a thickness of 20 nm, the background vacuum during sputtering is 4 ⁇ 10 -6 Torr, and the vacuum during sputtering is 0.2 Pa.
  • the electrode material is TiN.
  • step S1-6 is performed: forming a third transition material layer 7 on the second electrode material layer 6.
  • the method for forming the third transition material layer 7 includes but is not limited to at least one of sputtering, evaporation, atomic layer deposition, chemical vapor deposition, metal organic thermal decomposition, and laser assisted deposition .
  • the material of the third transition material layer 7 includes but is not limited to at least one of C, Ta, TaC, TaN, Nb, NbN, and SiC, such as one, two, three, or four of them.
  • the thickness of the third transition material layer 7 ranges from 2 to 10 nm.
  • magnetron sputtering is used to deposit the third transition material layer 7 with a thickness of 5 nm, the background vacuum during sputtering is 4 ⁇ 10 -6 Torr, and the vacuum during sputtering is 0.2 Pa.
  • the material of the third transition material layer is TaC.
  • step S1-7 is performed: forming a phase change material layer 8 on the third transition material layer 7.
  • the method of forming the phase change material layer 8 includes, but is not limited to, at least one of sputtering, evaporation, atomic layer deposition, chemical vapor deposition, metal organic thermal decomposition, and laser assisted deposition.
  • the phase change material layer 8 selects chalcogenide compound materials with phase change characteristics, including but not limited to one of Sb 2 Te 3 , Sb 2 Te and Ge 2 Sb 2 Te 5 , or one of them is doped with Ta , Hf and C one or two elements modified compound.
  • the magnetron sputtering method is used to deposit the phase change material, the thickness is 50nm, the background vacuum during sputtering is 4 ⁇ 10 -6 Torr, the vacuum during sputtering is 0.2Pa, and the phase change material used is Ta-Sb-Te series materials.
  • step S1-8 is performed: forming a fourth transition material layer 9 on the phase change material layer 8.
  • the method for forming the fourth transition material layer 9 includes but is not limited to at least one of sputtering, evaporation, atomic layer deposition, chemical vapor deposition, metal organic thermal decomposition, and laser assisted deposition .
  • the material of the fourth transition material layer 9 includes but is not limited to at least one of C, Ta, TaC, TaN, Nb, NbN, and SiC, such as one, two, three or four of them.
  • the thickness of the fourth transition material layer 9 is in the range of 2-10 nm.
  • magnetron sputtering is used to deposit the fourth transition material layer 9 with a thickness of 5 nm, the background vacuum during sputtering is 4 ⁇ 10 -6 Torr, and the vacuum during sputtering is 0.2 Pa.
  • the material of the fourth transition material layer is TaC.
  • step S1-9 is performed: forming a third electrode material layer 10 on the fourth transition material layer 9.
  • the method for forming the third electrode material layer 10 includes but is not limited to at least one of sputtering, evaporation, atomic layer deposition, chemical vapor deposition, metal organic thermal decomposition, and laser assisted deposition .
  • the material of the third electrode material layer 10 includes but is not limited to at least one of W, TiN, TiSiN, and AlN.
  • magnetron sputtering method is used to deposit the third electrode material layer 10 with a thickness of 50 nm, the background vacuum during sputtering is 4 ⁇ 10 -6 Torr, and the vacuum during sputtering is 0.2 Pa.
  • the electrode material is TiN.
  • step S2 is performed to form isolation trenches 11 in the laminated structure.
  • the isolation groove 11 opens from the top surface of the laminated structure and extends downward to the surface of the substrate 1 to divide the laminated structure into a plurality of columnar structures.
  • the isolation trench 11 is formed using micro-nano processing technology, which includes ultraviolet exposure, development, stripping, and reactive ion etching.
  • micro-nano processing technology which includes ultraviolet exposure, development, stripping, and reactive ion etching.
  • extreme ultraviolet exposure is used to etch the mask pattern
  • reactive ion etching is used to etch the laminated structure to obtain a plurality of columnar structures, and each columnar structure corresponds to a memory cell.
  • the cross section of the memory cell is a square with a side length of 100 nm, and the distance between adjacent memory cells is 100 nm.
  • the cross-sectional shape and arrangement of the memory cells can also be adjusted as required, and the protection scope of the present invention should not be excessively limited here.
  • step S3 Please refer to FIG. 12 to perform step S3 to form an isolation material layer 12 in the isolation trench 11.
  • the method for forming the isolation material layer 12 includes but is not limited to at least one of sputtering, evaporation, atomic layer deposition, chemical vapor deposition, metal organic thermal decomposition, and laser assisted deposition.
  • the material of the isolation material layer 12 includes but is not limited to at least one of Si 3 N 4 and SiO 2 .
  • a chemical vapor deposition method is used to deposit the Si 3 N 4 isolation material, and a chemical mechanical polishing method is used to remove the excess Si 3 N 4 film.
  • phase change memory with high density, high speed, low power consumption and long life has been fabricated, in which the phase change material and the OTS material are confined in the same space by the isolation material, which can avoid the operation of the phase change material and the OTS material
  • the diffusion and volatilization of the elements help to extend the life of the device.
  • the transition material layer is located between the phase change material and the electrode material, between the phase change material and the OTS material, and between the OTS material and the electrode material. Because the transition layer material has a low thermal conductivity, it can reduce the heat loss during device operation , Improve the thermal efficiency of the phase change memory, thereby reducing the power consumption of the phase change memory unit.
  • the transition layer material also has good thermal stability, and has good adhesion with the dielectric material, phase change material, OTS gate material and electrode material, so it can prevent the electrode material from the phase change material, OTS gate
  • the transition layer material has better conductive properties, which can avoid the introduction of larger resistance. High density can be achieved by reducing the size of phase change materials and OTS materials.
  • the present invention also provides a phase change memory.
  • FIG. 12 shows a schematic cross-sectional structure of the phase change memory. It includes a substrate 1, an isolation material layer 12, and a plurality of phase change memory cells.
  • the variable memory cells are separately arranged on the substrate 1.
  • the phase change memory cells are in a columnar structure and include a first electrode material layer 2, a first transition material layer 3, and a threshold gate tube material layer 4 from bottom to top.
  • the isolation material layer 12 is located in the On the substrate 1 and surrounding the sides of the phase change memory cells, the phase change memory cells are isolated from each other by the isolation material layer 12.
  • the cross-sectional area of the phase change material layer 8 and the threshold gate material layer 4 are the same.
  • the materials of the first transition material layer 3, the second transition material layer 5, the third transition material layer 7 and the fourth transition material layer 9 respectively include C, Ta, TaC, TaN, At least one of Nb, NbN, and SiC.
  • the thickness of the first transition material layer 3 is in the range of 2-10 nm
  • the thickness of the second transition material layer 5 is in the range of 2-10 nm
  • the thickness of the third transition material layer 7 is in the range of 2-10 nm.
  • the thickness of the fourth transition material layer 9 is in the range of 2-10 nm.
  • the threshold gate tube material layer 4 selects chalcogenide compound materials with switching characteristics, including but not limited to Ge-Se series materials, Ge-As-Se series materials, Ge-As-Se-Si series materials, One of Ge-As-Se-Si-Te series materials and Ge-As-Se-Si-N series materials, or one of them is modified by doping one or two of N and C elements Compound.
  • the phase change material layer 8 selects a chalcogenide compound material with phase change characteristics, including but not limited to one of Sb 2 Te 3 , Sb 2 Te and Ge 2 Sb 2 Te 5 , or one of them Compounds obtained by doping with one or two of Ta, Hf and C.
  • the materials of the first electrode material layer 2, the second electrode material layer 6 and the third electrode material layer 10 respectively include at least one of W, TiN, TiSiN, and AlN.
  • the material of the isolation material layer 12 includes but is not limited to at least one of Si 3 N 4 and SiO 2 .
  • the transition layer material has lower thermal conductivity, which can improve the thermal efficiency of the phase change memory, thereby reducing the power consumption of the phase change memory unit.
  • the transition layer material has good thermal stability, and has good adhesion to the dielectric material, phase change material, OTS gate material and electrode material, and can prevent the electrode material from the phase change material and OTS gate material The role of mutual diffusion, improving adhesion and increasing cycle life.
  • the transition layer material has good electrical conductivity, which can avoid the introduction of large resistance. Since the phase change material and the OTS material are confined between the dielectric materials, this structure can avoid the diffusion and volatilization of the phase change material and the OTS material element during operation, which is beneficial to prolong the life of the device.
  • the existence of the transition layer avoids the diffusion of elements at the interface, and at the same time reduces the heat loss during device operation, which is beneficial to the reduction of device power consumption.
  • High density can be achieved by reducing the size of phase change materials and OTS materials. Therefore, the phase change memory of the present invention has the characteristics of high density, high speed, low power consumption and long life. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial value.

Abstract

本发明提供一种相变存储器及其制作方法，该相变存储器包括衬底、多个相变存储器单元及隔离材料层，其中，多个相变存储器单元分立设置于衬底上，自下而上依次包括第一电极材料层、第一过渡材料层、阈值选通管材料层、第二过渡材料层、第二电极材料层、第三过渡材料层、相变材料层、第四过渡材料层及第三电极材料层；隔离材料层位于衬底上，并包围相变存储器单元的侧面，各个相变存储器单元之间通过隔离材料层相互隔离。本发明的相变存储器中，相变材料与OTS材料被隔离材料限制在同一个空间中，过渡材料层位于相变材料与电极材料之间、相变材料与OTS材料之间、OTS材料与电极材料之间，使得相变存储器具有高密度、高速、低功耗和长寿命的特点。

Description

一种相变存储器及其制作方法 技术领域
本发明属于微电子技术领域，涉及一种相变存储器及其制作方法。
背景技术
在传统计算架构中，DRAM与NAND Flash显著的性能差异使得大型数据中心和计算机等设备内南北桥数据交换的响应效率低且能耗居高不下。近年来，工业界与科学界投入大量的人力、物力、财力研究新型存储技术，以IBM、英特尔、美光、三星为代表的大型企业，均在寻求新型高性能存储技术，称之为存储型内存(SCM-Storage Class Memory)，填补DRAM与Flash之间的性能鸿沟，或部分替代DRAM与Flash，以构建新型存储架构提升整体性能。在新型高性能存储技术中，相变存储器(PCM)、磁存储器(MRAM)、阻变存储器(RRAM)和铁电存储器(FeRAM)是最具有竞争力的四种主流新型存储技术。其中，PCM具有非易失、微缩性能好、与CMOS工艺兼容、循环寿命长、高速读取、可多级存储和抗辐照等优点，被认为是最具潜力的下一代非挥发存储技术，特别是在SCM应用方面有着广阔的市场前景。PCM的原理是利用材料相变前后电阻率的巨大差异来实现数据存储。在PCM中，一个状态(即晶态)电阻率较低，另一个状态(即非晶态)的电阻率较高。逻辑“1”或逻辑“0”取决于相变材料所处的电阻态。国际上已有Intel、Micron、Samsung、TSMC和STMicroelectronics等大公司在开展PCM存储器的研究与产业化工作。
PCM作为SCM应用时，要求PCM具有高密度、高速、低功耗和长寿命，目前国际上只有英特尔与美光研制出适用于SCM的相变存储器3D Xpoint，但是英特尔与美光并没有对外公布采用何种材料制备其相变存储单元和选通管单元，器件的单元性能也没有披露，研发自主知识产权的相变存储器材料与结构非常重要。
鉴于此，实有必要提出一种新的技术方案实现高密度、低功耗、高稳定性相变存储器以满足SCM的应用需求。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种相变存储器的制作方法，用于解决现有技术中相变存储器不能满足存储型内存的应用需求的问题。
为实现上述目的及其他相关目的，本发明提供一种相变存储器的制作方法，包括以下步骤：
提供一衬底，形成叠层结构于所述衬底上，所述叠层结构自下而上依次包括第一电极材料层、第一过渡材料层、阈值选通管材料层、第二过渡材料层、第二电极材料层、第三过渡材料层、相变材料层、第四过渡材料层及第三电极材料层；
形成隔离槽于所述叠层结构中，所述隔离槽自所述叠层结构顶面开口，并往下延伸至所述衬底表面，以将所述叠层结构分隔为多个柱状结构；
形成隔离材料层于所述隔离槽中，所述隔离材料层包围所述柱状结构的侧面。
可选地，所述第一过渡材料层、所述第二过渡材料层、所述第三过渡材料层及所述第四过渡材料层的材质分别包括C、Ta、TaC、TaN、Nb、NbN及SiC中的至少一种。
可选地，所述第一过渡材料层的厚度范围是2-10nm，所述第二过渡材料层的厚度范围是2-10nm，所述第三过渡材料层的厚度范围是2-10nm，所述第四过渡材料层的厚度范围是2-10nm。
可选地，形成所述第一电极材料层、所述第一过渡材料层、所述阈值选通管材料层、所述第二过渡材料层、所述第二电极材料层、所述第三过渡材料层、所述相变材料层、所述第四过渡材料层及所述第三电极材料层的方法分别包括溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。
可选地，形成所述隔离槽的方法包括反应离子刻蚀。
可选地，所述阈值选通管材料层选用具有开关特性的硫系化合物材料，包括Ge-Se系列材料、Ge-As-Se系列材料、Ge-As-Se-Si系列材料、Ge-As-Se-Si-Te系列材料及Ge-As-Se-Si-N系列材料中的一种，或其中一种通过掺杂N及C中一种或两种元素改性后得到的化合物。
可选地，所述相变材料层选用具有相变特性的硫系化合物材料，包括Sb 2Te 3、Sb 2Te及Ge 2Sb 2Te 5中的一种，或其中一种通过掺杂Ta、Hf及C中的一种或两种元素改性得到的化合物。
可选地，所述第一电极材料层、所述第二电极材料层及所述第三电极材料层的材质分别包括W、TiN、TiSiN及AlN中的至少一种。
本发明还提供一种相变存储器，包括：
衬底；
多个相变存储器单元，位于所述衬底上，所述相变存储器单元自下而上依次包括第一电极材料层、第一过渡材料层、阈值选通管材料层、第二过渡材料层、第二电极材料层、第三过渡材料层、相变材料层、第四过渡材料层及第三电极材料层；
隔离材料层，分立设置于所述衬底上，并包围所述相变存储器单元的侧面，各个所述相变存储器单元之间通过所述隔离材料层相互隔离。
可选地，所述相变存储器单元中，所述相变材料层与所述阈值选通管材料层的横截面积相同。
可选地，所述第一过渡材料层、所述第二过渡材料层、所述第三过渡材料层及所述第四过渡材料层的材质分别包括C、Ta、TaC、TaN、Nb、NbN及SiC中的至少一种。
可选地，所述第一过渡材料层的厚度范围是2-10nm，所述第二过渡材料层的厚度范围是2-10nm，所述第三过渡材料层的厚度范围是2-10nm，所述第四过渡材料层的厚度范围是2-10nm。
可选地，所述阈值选通管材料层选用具有开关特性的硫系化合物材料，包括Ge-Se系列材料、Ge-As-Se系列材料、Ge-As-Se-Si系列材料、Ge-As-Se-Si-Te系列材料及Ge-As-Se-Si-N系列材料中的一种，或其中一种通过掺杂N及C中一种或两种元素改性后得到的化合物。
可选地，所述相变材料层选用具有相变特性的硫系化合物材料，包括Sb 2Te 3、Sb 2Te及Ge 2Sb 2Te 5中的一种，或其中一种通过掺杂Ta、Hf及C中的一种或两种元素改性得到的化合物。
可选地，所述第一电极材料层、所述第二电极材料层及所述第三电极材料层的材质分别包括W、TiN、TiSiN及AlN中的至少一种。
如上所述，本发明的相变存储器中，过渡层材料具有较低的热导率，可以提高相变存储器工作的热效率，从而降低相变存储器单元功耗。过渡层材料具有良好的热稳定性，与介质材料、相变材料、OTS选通管材料和电极材料都有良好的粘附性，可以起到防止电极材料与相变材料、OTS选通管材料之间相互扩散、提高粘附性以及增加循环寿命的作用。过渡层材料具有较好的导电特性，可以避免引入较大的电阻。由于相变材料和OTS材料被限制在介质材料之间，这种结构可以避免操作中相变材料和OTS材料元素的扩散和挥发，有利于延长器件的寿命。过渡层的存在避免了界面处元素的扩散，同时还降低了器件操作中热量的散失，有利于器件功耗的降低。通过减小相变材料和OTS材料的尺寸可以实现高密度。因此，本发明的相变存储器具有高密度、高速、低功耗和长寿命的特点。
附图说明
图1显示为本发明的相变存储器的制作方法的工艺流程图。
图2显示为本发明的相变存储器的制作方法形成第一电极材料层于所述衬底上的示意图。
图3显示为本发明的相变存储器的制作方法形成第一过渡材料层于所述第一电极材料层上的示意图。
图4显示为本发明的相变存储器的制作方法形成阈值选通管材料层于所述第一过渡材料层上的示意图。
图5显示为本发明的相变存储器的制作方法形成第二过渡材料层于所述阈值选通管材料层上的示意图。
图6显示为本发明的相变存储器的制作方法形成第二电极材料层于所述第二过渡材料层上的示意图。
图7显示为本发明的相变存储器的制作方法形成第三过渡材料层于所述第二电极材料层上的示意图。
图8显示为本发明的相变存储器的制作方法形成相变材料层于所述第三过渡材料层上的示意图。
图9显示为本发明的相变存储器的制作方法形成第四过渡材料层于所述相变材料层上的示意图。
图10显示为本发明的相变存储器的制作方法形成第三电极材料层于所述第四过渡材料层上的示意图。
图11显示为本发明的相变存储器的制作方法形成隔离槽于所述叠层结构中的示意图。
图12显示为本发明的相变存储器的制作方法形成隔离材料层于所述隔离槽中的示意图。
元件标号说明
1                      衬底
2                      第一电极材料层
3                      第一过渡材料层
4                      阈值选通管材料层
5                      第二过渡材料层
6                      第二电极材料层
7                      第三过渡材料层
8                      相变材料层
9                      第四过渡材料层
10                     第三电极材料层
11                     隔离槽
12                     隔离材料层
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图12。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本发明提供一种相变存储器的制作方法，请参阅图1，显示为该方法的工艺流程图，包括以下步骤：
S1：提供一衬底，形成叠层结构于所述衬底上，所述叠层结构自下而上依次包括第一电极材料层、第一过渡材料层、阈值选通管材料层、第二过渡材料层、第二电极材料层、第三过渡材料层、相变材料层、第四过渡材料层及第三电极材料层；
S2：形成隔离槽于所述叠层结构中，所述隔离槽自所述叠层结构顶面开口，并往下延伸至所述衬底表面，以将所述叠层结构分隔为多个柱状结构；
S3：形成隔离材料层于所述隔离槽中，所述隔离材料层包围所述柱状结构的侧面。
请参阅图2至图10，执行步骤S1，以在所述衬底上1上形成所述叠层结构。
作为示例，所述衬底1包括但不限于Si、Ge、SiGe、III-V族化合物等半导体材料。本实施例中以Si衬底为例，使用丙酮与酒精溶液，在超声波作用下各清洗Si衬底3分钟，再在120℃下烘20分钟。该清洗步骤有助于提高后续膜层的沉积质量。对于不同的衬底，清洗方法可有所不同，只要能满足获得干净的衬底表面即可，此处不应过分限制本发明的保护范围。
作为示例，形成所述叠层结构包括以下步骤：
如图2所示，执行步骤S1-1：形成第一电极材料层2所述衬底1上。
具体的，形成所述第一电极材料层2的方法包括但不限于溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。所述第一电极材料层2的材质包括但不限于W、TiN、TiSiN及AlN中的至少一种。作为示例，本实施例中使用磁控溅射法沉积所述第一电极材料层2，厚度为50nm，溅射时本底真空为4×10 -6Torr，溅射时真空为0.18Pa，使用的电极材料为W。
如图3示，执行步骤S1-2：形成第一过渡材料层3于所述第一电极材料层2上。
具体的，形成所述第一过渡材料层3的方法包括但不限于溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。所述第一过渡材料层3的材质包括但不限于C、Ta、TaC、TaN、Nb、NbN及SiC中的至少一种，例如其中一种、两种、三种或者四种。所述第一过渡材料层3的厚度范围是2-10nm。作为示例，本实施例中使用磁控溅射法沉积所述第一过渡材料层3，厚度为5nm，溅射时本底真空为4×10 -6Torr，溅射时真空为0.2Pa，使用的第一过渡材料层材料为C。
如图4所示，执行步骤S1-3：形成阈值选通管(OTS)材料层4于所述第一过渡材料层3上。
具体的，所述阈值选通管材料层4选用具有开关特性的硫系化合物材料，包括但不限于Ge-Se系列材料、Ge-As-Se系列材料、Ge-As-Se-Si系列材料、Ge-As-Se-Si-Te系列材料及Ge-As-Se-Si-N系列材料中的一种，或其中一种通过掺杂N及C中一种或两种元素改性后得到的化合物。作为示例，本实施例中使用磁控溅射法沉积OTS材料，厚度为30nm，溅射时本底真空为4×10 -6Torr，溅射时真空为0.2Pa，使用的OTS材料为Ge-As-Se-Te系列材料。
如图5所示，执行步骤S1-4：形成第二过渡材料层5于所述阈值选通管材料层4上。
具体的，形成所述第二过渡材料层5的方法包括但不限于溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。所述第二过渡材料层5的材质包括但不限于C、Ta、TaC、TaN、Nb、NbN及SiC中的至少一种，例如其中一种、两种、三种或者四种。所述第二过渡材料层5的厚度范围是2-10nm。作为示例，本实施例中使用磁控溅射法沉积第二过渡材料层，厚度为5nm，溅射时本底真空为4×10 -6Torr，溅射时真空为0.2Pa，使用的第二过渡材料层材料为C。
如图6所示，执行步骤S1-5：形成第二电极材料层6于所述第二过渡材料层5上。
具体的，形成所述第二电极材料层6的方法包括但不限于溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。所述第二电极材料层6的材质包括但不限于W、TiN、TiSiN及AlN中的至少一种。作为示例，本实施例中使用磁控溅射法沉积所述第二电极材料层6，厚度为20nm，溅射时本底真空为4×10 -6Torr，溅射时真空为0.2Pa，使用的电极材料为TiN。
如图7所示，执行步骤S1-6：形成第三过渡材料层7于所述第二电极材料层6上。
具体的，形成所述第三过渡材料层7的方法包括但不限于溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。所述第三过渡材料层7的材质包括但不限于C、Ta、TaC、TaN、Nb、NbN及SiC中的至少一种，例如其 中一种、两种、三种或者四种。所述第三过渡材料层7的厚度范围是2-10nm。作为示例，本实施例中使用磁控溅射法沉积所述第三过渡材料层7，厚度为5nm，溅射时本底真空为4×10 -6Torr，溅射时真空为0.2Pa，使用的第三过渡材料层材料为TaC。
如图8所示，执行步骤S1-7：形成相变材料层8于所述第三过渡材料层7上。
具体的，形成所述相变材料层8的方法包括但不限于溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。所述相变材料层8选用具有相变特性的硫系化合物材料，包括但不限于Sb 2Te 3、Sb 2Te及Ge 2Sb 2Te 5中的一种，或其中一种通过掺杂Ta、Hf及C中的一种或两种元素改性得到的化合物。作为示例，本实施例中使用磁控溅射法沉积相变材料，厚度为50nm，溅射时本底真空为4×10 -6Torr，溅射时真空为0.2Pa，使用的相变材料为Ta-Sb-Te系列材料。
如图9所示，执行步骤S1-8：形成第四过渡材料层9于所述相变材料层8上。
具体的，形成所述第四过渡材料层9的方法包括但不限于溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。所述第四过渡材料层9的材质包括但不限于C、Ta、TaC、TaN、Nb、NbN及SiC中的至少一种，例如其中一种、两种、三种或者四种。所述第四过渡材料层9的厚度范围是2-10nm。作为示例，本实施例中使用磁控溅射法沉积所述第四过渡材料层9，厚度为5nm，溅射时本底真空为4×10 -6Torr，溅射时真空为0.2Pa，使用的第四过渡材料层材料为TaC。
如图10所示，执行步骤S1-9：形成第三电极材料层10于所述第四过渡材料层9上。
具体的，形成所述第三电极材料层10的方法包括但不限于溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。所述第三电极材料层10的材质包括但不限于W、TiN、TiSiN及AlN中的至少一种。作为示例，本实施例中使用磁控溅射法沉积所述第三电极材料层10，厚度为50nm，溅射时本底真空为4×10 -6Torr，溅射时真空为0.2Pa，使用的电极材料为TiN。
至此，得到所述叠层结构于所述衬底1上。
接着请参阅图11，执行步骤S2，形成隔离槽11于所述叠层结构中。
具体的，所述隔离槽11自所述叠层结构顶面开口，并往下延伸至所述衬底1表面，以将所述叠层结构分隔为多个柱状结构。
作为示例，采用微纳加工技术形成所述隔离槽11，所述微纳加工技术包括紫外曝光、显影、剥离法及反应离子刻蚀。本实施例中，使用极紫外曝光光刻出掩膜图形，使用反应离子刻蚀所述叠层结构，得到多个柱状结构，每一柱状结构对应一个存储器单元。
作为示例，所述存储器单元的横截面呈边长为100nm的正方形，相邻存储器单元的间距 为100nm。在其他实施例中，存储器单元的横截面形状及排布方式也可以根据需要进行调整，此处不应过分限制本发明的保护范围。
请参阅图12，执行步骤S3，形成隔离材料层12于所述隔离槽11中。
具体的，形成所述隔离材料层12的方法包括但不限于溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。所述隔离材料层12的材质包括但不限于Si 3N 4、SiO 2中的至少一种。作为示例，本实施例中使用化学气相沉积法沉积Si 3N 4隔离材料，并采用化学机械抛光法去除多余的Si 3N 4薄膜。
后续使用探针或导线引出电极，加载上电信号，便可以测试单元的各种性能了。
至此，制作得到一种高密度、高速、低功耗和长寿命的相变存储器，其中，相变材料与OTS材料被隔离材料限制在同一个空间中，可以避免操作中相变材料和OTS材料元素的扩散和挥发，有利于延长器件的寿命。过渡材料层位于相变材料与电极材料之间、相变材料与OTS材料之间、OTS材料与电极材料之间，由于过渡层材料具有较低的热导率，可以降低器件操作中热量的散失，提高相变存储器工作的热效率，从而降低相变存储器单元功耗。过渡层材料还具有良好的热稳定性，与介质材料、相变材料、OTS选通管材料和电极材料都有良好的粘附性，因此可以起到防止电极材料与相变材料、OTS选通管材料之间相互扩散、提高粘附性以及增加循环寿命的作用。此外，过渡层材料具有较好的导电特性，可以避免引入较大的电阻。通过减小相变材料和OTS材料的尺寸可以实现高密度。
实施例二
本发明还提供一种相变存储器，请参阅图12，显示为该相变存储器的剖面结构示意图，包括衬底1、隔离材料层12及多个相变存储器单元，其中，多个所述相变存储器单元分立设置于所述衬底1上，所述相变存储器单元呈柱状结构，自下而上依次包括第一电极材料层2、第一过渡材料层3、阈值选通管材料层4、第二过渡材料层5、第二电极材料层6、第三过渡材料层7、相变材料层8、第四过渡材料层9及第三电极材料层10；所述隔离材料层12位于所述衬底1上，并包围所述相变存储器单元的侧面，各个所述相变存储器单元之间通过所述隔离材料层12相互隔离。
作为示例，所述相变存储器单元中，所述相变材料层8与所述阈值选通管材料层4的横截面积相同。
作为示例，所述第一过渡材料层3、所述第二过渡材料层5、所述第三过渡材料层7及所述第四过渡材料层9的材质分别包括C、Ta、TaC、TaN、Nb、NbN及SiC中的至少一种。所述第一过渡材料层3的厚度范围是2-10nm，所述第二过渡材料层5的厚度范围是2-10nm， 所述第三过渡材料层7的厚度范围是2-10nm，所述第四过渡材料层9的厚度范围是2-10nm。
作为示例，所述阈值选通管材料层4选用具有开关特性的硫系化合物材料，包括但不限于Ge-Se系列材料、Ge-As-Se系列材料、Ge-As-Se-Si系列材料、Ge-As-Se-Si-Te系列材料及Ge-As-Se-Si-N系列材料中的一种，或其中一种通过掺杂N及C中一种或两种元素改性后得到的化合物。
作为示例，所述相变材料层8选用具有相变特性的硫系化合物材料，包括但不限于Sb 2Te 3、Sb 2Te及Ge 2Sb 2Te 5中的一种，或其中一种通过掺杂Ta、Hf及C中的一种或两种元素改性得到的化合物。
作为示例，所述第一电极材料层2、所述第二电极材料层6及所述第三电极材料层10的材质分别包括W、TiN、TiSiN及AlN中的至少一种。
作为示例，所述隔离材料层12的材质包括但不限于Si 3N 4、SiO 2中的至少一种。
综上所述，本发明的相变存储器中，过渡层材料具有较低的热导率，可以提高相变存储器工作的热效率，从而降低相变存储器单元功耗。过渡层材料具有良好的热稳定性，与介质材料、相变材料、OTS选通管材料和电极材料都有良好的粘附性，可以起到防止电极材料与相变材料、OTS选通管材料之间相互扩散、提高粘附性以及增加循环寿命的作用。过渡层材料具有较好的导电特性，可以避免引入较大的电阻。由于相变材料和OTS材料被限制在介质材料之间，这种结构可以避免操作中相变材料和OTS材料元素的扩散和挥发，有利于延长器件的寿命。过渡层的存在避免了界面处元素的扩散，同时还降低了器件操作中热量的散失，有利于器件功耗的降低。通过减小相变材料和OTS材料的尺寸可以实现高密度。因此，本发明的相变存储器具有高密度、高速、低功耗和长寿命的特点。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (15)

  1. 一种相变存储器的制作方法，其特征在于，包括以下步骤：
    提供一衬底，形成叠层结构于所述衬底上，所述叠层结构自下而上依次包括第一电极材料层、第一过渡材料层、阈值选通管材料层、第二过渡材料层、第二电极材料层、第三过渡材料层、相变材料层、第四过渡材料层及第三电极材料层；
    形成隔离槽于所述叠层结构中，所述隔离槽自所述叠层结构顶面开口，并往下延伸至所述衬底表面，以将所述叠层结构分隔为多个柱状结构；
    形成隔离材料层于所述隔离槽中，所述隔离材料层包围所述柱状结构的侧面。
  2. 根据权利要求1所述的相变存储器的制作方法，其特征在于：所述第一过渡材料层、所述第二过渡材料层、所述第三过渡材料层及所述第四过渡材料层的材质分别包括C、Ta、TaC、TaN、Nb、NbN及SiC中的至少一种。
  3. 根据权利要求1所述的相变存储器的制作方法，其特征在于：所述第一过渡材料层的厚度范围是2-10nm，所述第二过渡材料层的厚度范围是2-10nm，所述第三过渡材料层的厚度范围是2-10nm，所述第四过渡材料层的厚度范围是2-10nm。
  4. 根据权利要求1所述的相变存储器的制作方法，其特征在于：形成所述第一电极材料层、所述第一过渡材料层、所述阈值选通管材料层、所述第二过渡材料层、所述第二电极材料层、所述第三过渡材料层、所述相变材料层、所述第四过渡材料层及所述第三电极材料层的方法分别包括溅射法、蒸发法、原子层沉积法、化学气相沉积法、金属有机物热分解法及激光辅助沉积法中的至少一种。
  5. 根据权利要求1所述的相变存储器的制作方法，其特征在于：形成所述隔离槽的方法包括反应离子刻蚀。
  6. 根据权利要求1所述的相变存储器的制作方法，其特征在于：所述阈值选通管材料层选用具有开关特性的硫系化合物材料，包括Ge-Se系列材料、Ge-As-Se系列材料、Ge-As-Se-Si系列材料、Ge-As-Se-Si-Te系列材料及Ge-As-Se-Si-N系列材料中的一种，或其中一种通过掺杂N及C中一种或两种元素改性后得到的化合物。
  7. 根据权利要求1所述的相变存储器的制作方法，其特征在于：所述相变材料层选用具有相变特性的硫系化合物材料，包括Sb 2Te 3、Sb 2Te及Ge 2Sb 2Te 5中的一种，或其中一种通过 掺杂Ta、Hf及C中的一种或两种元素改性得到的化合物。
  8. 根据权利要求1所述的相变存储器的制作方法，其特征在于：所述第一电极材料层、所述第二电极材料层及所述第三电极材料层的材质分别包括W、TiN、TiSiN及AlN中的至少一种。
  9. 一种相变存储器，其特征在于，包括：
    衬底；
    多个相变存储器单元，分立设置于所述衬底上，所述相变存储器单元自下而上依次包括第一电极材料层、第一过渡材料层、阈值选通管材料层、第二过渡材料层、第二电极材料层、第三过渡材料层、相变材料层、第四过渡材料层及第三电极材料层；
    隔离材料层，位于所述衬底上，并包围所述相变存储器单元的侧面，各个所述相变存储器单元之间通过所述隔离材料层相互隔离。
  10. 根据权利要求9所述的相变存储器，其特征在于：所述相变存储器单元中，所述相变材料层与所述阈值选通管材料层的横截面积相同。
  11. 根据权利要求9所述的相变存储器，其特征在于：所述第一过渡材料层、所述第二过渡材料层、所述第三过渡材料层及所述第四过渡材料层的材质分别包括C、Ta、TaC、TaN、Nb、NbN及SiC中的至少一种。
  12. 根据权利要求9所述的相变存储器，其特征在于：所述第一过渡材料层的厚度范围是2-10nm，所述第二过渡材料层的厚度范围是2-10nm，所述第三过渡材料层的厚度范围是2-10nm，所述第四过渡材料层的厚度范围是2-10nm。
  13. 根据权利要求9所述的相变存储器，其特征在于：所述阈值选通管材料层选用具有开关特性的硫系化合物材料，包括Ge-Se系列材料、Ge-As-Se系列材料、Ge-As-Se-Si系列材料、Ge-As-Se-Si-Te系列材料及Ge-As-Se-Si-N系列材料中的一种，或其中一种通过掺杂N及C中一种或两种元素改性后得到的化合物。
  14. 根据权利要求9所述的相变存储器，其特征在于：所述相变材料层选用具有相变特性的硫系化合物材料，包括Sb 2Te 3、Sb 2Te及Ge 2Sb 2Te 5中的一种，或其中一种通过掺杂Ta、 Hf及C中的一种或两种元素改性得到的化合物。
  15. 根据权利要求9所述的相变存储器，其特征在于：所述第一电极材料层、所述第二电极材料层及所述第三电极材料层的材质分别包括W、TiN、TiSiN及AlN中的至少一种。
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