WO2017084237A1 - 一种三维存储器及其制备方法 - Google Patents

一种三维存储器及其制备方法 Download PDF

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WO2017084237A1
WO2017084237A1 PCT/CN2016/078643 CN2016078643W WO2017084237A1 WO 2017084237 A1 WO2017084237 A1 WO 2017084237A1 CN 2016078643 W CN2016078643 W CN 2016078643W WO 2017084237 A1 WO2017084237 A1 WO 2017084237A1
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insulating layer
type
electrode
plug column
semiconductor material
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PCT/CN2016/078643
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English (en)
French (fr)
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缪向水
颜柏寒
童浩
闫鹏
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华中科技大学
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies

Definitions

  • the invention belongs to the technical field of micro-nanoelectronics, and in particular relates to a three-dimensional memory.
  • 3D-NAND, 3D-RRAM, 3D X-point and other three-dimensional structure memories have been proposed in the world.
  • the three-dimensional memory has a vertical three-dimensional structure, which is formed by stacking multiple layers of memory, which can effectively utilize the space area and greatly increase the storage density. It is the inevitable direction of future memory development.
  • PCRAM Phase change memory
  • the storage medium of the PCRAM can realize the reversible transition between the amorphous state and the crystal state under the heat induction, and the storage medium exhibits different optical characteristics and resistance characteristics in the amorphous state and the crystal state, thus the amorphous state and the crystal.
  • the status can be used to represent "0" and "1" respectively to store data.
  • Each memory cell of the flash memory is composed of a source, a drain, a control gate and a floating gate.
  • the stored charge on the floating gate is different, the threshold voltage of the device is different, and the control gate is applied with a voltage to store 0 and 1.
  • NAND type Flash memory cells are connected in series, and all memory cells of NAND are divided into several blocks, each block is divided into several pages, each page is 512 bytes, which is 512 8-bit numbers, that is to say each The page has 512 bit lines, and there are 8 memory cells under each bit line.
  • 3D-NAND is a limitation to avoid the increase in the storage density of flash memory or memory chips, and stack them up to increase the storage density.
  • the three-dimensional vertical NAND string was first disclosed in 2001 ("Novel Ultra High Density Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36).
  • Resistive memory is a new type of non-volatile memory.
  • the memory cell is usually a MIM structure, ie a metal/resistive memory layer/metal sandwich structure, which facilitates 3D stacking.
  • the resistance of the device is reversibly transformed between a high-impedance state and a low-resistance state, thereby realizing the storage of “0” and “1”.
  • the resistance transition of a RRAM device can be classified into a unipolar (unipolar) and a bipolar (Bipolar) depending on the polarity of the voltage required to undergo a resistance transition.
  • unipolar means that the voltage polarity required for the Set and Reset processes of the device is the same, and the bipolar refers to the opposite polarity of the voltage required for the Set and Reset processes of the device.
  • Nonpolar a resistance transition characteristic
  • the present invention is directed to solving the above problems in view of the problem that the three-dimensional memory in the prior art requires additional gating switches and low space utilization.
  • the present invention provides a three-dimensional memory, characterized in that the three-dimensional memory comprises:
  • the lower electrode is disposed on the substrate, and the first direction refers to any direction in a plane;
  • the lower electric insulation layer being disposed on the substrate having the lower electrode
  • the lower electric heating layer has one or more small holes in the middle, and the bottom of the small holes is a lower electrode;
  • the lower n-type semiconductor material plug post is located in the small hole wrapped by the lower electric heat insulating layer, and the lower n-type semiconductor material plug column is formed at the bottom and the bottom Top of the electrode;
  • the lower p-type memory material plug column is located in the small hole wrapped by the lower electric heat insulating layer, and the bottom of the lower p-type memory material plug column is formed under the bottom N-type semiconductor material plug column top;
  • the intermediate electric heating insulating layer has one or more small holes in the middle, and the bottom of the small holes in the intermediate electric heating insulating layer is the lower adjacent electrode.
  • An intermediate p-type memory material plug column the intermediate p-type memory material plug column is located in a small hole wrapped by the intermediate electric heat insulating layer, and the bottom of the intermediate p-type memory material plug column is disposed at the bottom phase On top of the adjacent electrode,
  • An intermediate n-type semiconductor material plug post the intermediate n-type semiconductor material plug post is located in a small hole wrapped by the intermediate electric heating insulating layer, and the bottom of the intermediate n-type semiconductor material plug column is disposed in the middle p Type of storage material on the top of the plug column,
  • a strip-shaped intermediate electrode in a direction perpendicular to a direction of the adjacent strip-shaped electrode, the intermediate electrode being disposed on the intermediate electrothermal insulating layer, the intermediate electrode being disposed on a top of the intermediate n-type semiconductor material plug column;
  • An upper electrically insulating layer is disposed on the adjacent electrically insulating layer below the adjacent electrode;
  • the upper electric heat insulating layer has one or more small holes in the middle, and the bottom of the small holes in the upper electric heat insulating layer is the middle electrode;
  • the upper p-type memory material plug column is located in the small hole wrapped by the upper electric heat insulating layer, and the bottom of the upper p-type memory material plug column is disposed at the bottom phase Adjacent electrode top;
  • An upper n-type semiconductor material plug column the upper n-type semiconductor material plug column is located in the small hole wrapped by the upper electric heat insulating layer, and the bottom of the upper n-type semiconductor material plug column is disposed at the bottom Said the top of the p-type storage material plug column;
  • the upper electrode layer being disposed on the upper electric-thermal insulating layer, the upper electrode being disposed on the top of the upper n-type semiconductor material plug column .
  • a method of fabricating a multilayer three-dimensional memory comprising the steps of:
  • Step 1 performing photolithography on a substrate having a silicon dioxide insulating layer on the surface, and then preparing a lower electrode on the photolithographic substrate, and peeling off to obtain a first direction corresponding to the lithographic pattern.
  • Step 2 preparing a lower electric insulating layer
  • Step 3 preparing a small hole by using a micro-nano processing technique in the middle of the lower electric insulating layer
  • Step 4 filling a small-sized semiconductor material plug column in the small hole by chemical vapor deposition or sputtering
  • Step 5 filling a p-type memory material plug column in the small hole by chemical vapor deposition or sputtering, and filling the small hole;
  • Step 6 removing the n-type semiconductor material and the p-type memory material on the surface of the lower electric insulating layer by chemical mechanical polishing or reverse etching;
  • Step 7 performing photolithography on the surface of the lower electric insulating layer, and then preparing a sub-layer electrode, and after stripping, obtaining a strip-shaped layer electrode in a second direction perpendicular to the first direction corresponding to the lithographic pattern;
  • Step 8 preparing an intermediate layer on the lower electric insulating layer prepared with the inter-electrode, the number of the intermediate layers being zero or a positive integer; the preparation method of each intermediate layer is as follows:
  • Step 81 preparing an intermediate electrothermal insulating layer on the lower adjacent electrothermal insulating layer having the lower adjacent electrodes;
  • Step 82 preparing a small hole at the same position by using a micro-nano processing technique in the middle of the intermediate electric heating layer;
  • Step 83 filling a small p-type memory material plug column in the small hole of the intermediate electric heating insulation layer by chemical vapor deposition or sputtering;
  • Step 84 filling an n-type semiconductor material plug column in a small hole of the intermediate electrothermal insulating layer by chemical vapor deposition or sputtering, and filling the small hole;
  • Step 85 removing the n-type semiconductor material on the surface of the intermediate electrothermal insulating layer and the p-type storage material by chemical mechanical polishing or reverse etching;
  • Step 86 performing photolithography on the surface of the intermediate electrothermal insulating layer, and then preparing an intermediate electrode, and after stripping, obtaining a strip-shaped intermediate electrode in a vertical direction corresponding to the lithographic pattern;
  • Step 9 preparing an upper electric heat insulating layer on the intermediate electric heat insulating layer prepared with the intermediate electrode;
  • Step 10 preparing a small hole at the same position by using a micro-nano processing technique in the middle of the upper thermal insulating layer;
  • Step 11 filling a small hole of the upper insulating layer with a p-type memory material plug column by chemical vapor deposition or sputtering;
  • Step 12 filling a small hole of the upper insulating layer with a plug of n-type semiconductor material by chemical vapor deposition or sputtering, and filling the small hole;
  • Step 13 removing the n-type semiconductor material and the p-type memory material on the surface of the upper electric heat insulating layer by chemical mechanical polishing or reverse etching;
  • Step 14 performing photolithography on the surface of the upper electric insulating layer, then preparing an upper electrode, and after stripping, obtaining a strip-shaped upper electrode in a vertical direction corresponding to the lithographic pattern, thereby completing preparation of the three-dimensional memory.
  • the three-dimensional memory is formed by stacking a plurality of layers of memory, which can greatly increase the space utilization area, thereby greatly increasing the storage density;
  • the pn junction strobe switch of the invention can effectively reduce the area occupied by the transistors in the memory, reduce the leakage current and the thermal crosstalk, reduce the unit surface, and improve the storage density;
  • the p-type memory material in the invention is both a p-type material and a storage medium in the pn junction strobe tube, and has a dual function, which effectively simplifies the process steps and can reduce the cost of industrial production.
  • each picture includes two types of a perspective view and a cross-sectional view;
  • Figure 14 is a plan view of the three-dimensional memory after completion of preparation
  • Figure 17 is a 3D schematic diagram of a three dimensional memory of the present invention.
  • a multi-layer three-dimensional memory of the present invention is described by taking a dual-layer memory as an example, including:
  • the lower electrode is formed on the lithographic substrate 100, and after peeling, an electrode corresponding to the lithographic pattern is obtained, and the electrode material may be a metal or non-metal having good conductivity, such as silver. Copper, titanium tungsten alloy, graphene, etc., the thickness of the lower electrode 101 is 100-500 nm;
  • the electric insulating layer material 102 is formed on the substrate 100 on which the lower electrode 101 is prepared.
  • the material of the lower electric insulating layer 102 is: nitride, oxide, sulfide or two or more materials thereof. a mixture of the lower electric insulating layer 102 slightly smaller than the substrate 100, a portion of the lower electrode 101 is exposed, the thickness of the lower electric insulating layer 102 is 100-1000 nm;
  • the lower electric insulating layer has a small hole in the middle, the small hole depth is the same as the thickness of the lower electric insulating layer material 102, and the bottom of the small hole is the lower electrode 101;
  • the n-type semiconductor material plug post 103, the n-type semiconductor material plug post 103 is located in the small hole wrapped by the lower electric insulating layer 102, and the bottom of the lower n-type semiconductor material plug post 103 is connected to the top of the lower electrode post 102, the n
  • the semiconductor material plug post 103 has a thickness of 10-500 nm, and the sum of the thicknesses of the lower n-type semiconductor material plug post 103 and the lower p-type memory material plug post 104 is equal to the depth of the small hole, the n-type semiconductor material plug post 103.
  • the material may be any n-type semiconductor material capable of forming a pn junction with the p-type memory material in the memory, which may be: a doped n-type semiconductor such as n-type silicon, a metal oxide such as ZnO, Cu2O, n-type semiconductor. a compound material such as GaN or the like;
  • the p-type memory material plug column 104, the lower p-type memory material plug column 104 is located in the small hole wrapped by the lower electric heat insulating layer 102, the bottom of the lower p-type memory material plug column 104 and the lower n-type semiconductor material plug column 103 is connected at the top, the p-type memory material plug column 104 has a thickness of 10-500 nm, and the sum of the thickness of the lower n-type semiconductor material plug post 103 and the lower p-type memory material plug column 104 is equal to the depth of the small hole, the p-type The storage material may be a sulfur-based compound semiconductor material such as GeTe, SbTe, BiTe, SnTe, AsTe, GeSe, SbSe, BiSe, SnSe, AsSe, InSe, GeSbTe, AgInSbTe and a compound thereof, and the above compound is incorporated in S, N, O a mixture of elements such as Cu, Si, Au,
  • An intermediate electrode 105 in a horizontal direction the intermediate electrode 105 layer is prepared on the lithographic lower electric insulating layer 102, and after peeling off, the intermediate electrode 105 is obtained, and the intermediate electrode 105 and the lower electric insulating layer 102 are wrapped on the top of the small hole.
  • the lower p-type memory material plug column 104 is connected, the intermediate electrode 105 has a thickness of 100-500 nm, and the material of the intermediate electrode 105 is the same as that of the lower electrode 101;
  • An upper electric insulating layer 106 is prepared on the lower electric insulating layer 102 having the intermediate electrode 107.
  • the upper electric insulating layer 106 has the same thickness and material as the lower electric insulating layer 102.
  • the upper electric insulating layer is insulated.
  • the layer 106 area is slightly smaller than the lower electric insulating layer 102, so that the intermediate electricity
  • the pole 105 is partially exposed, and the upper thermal insulation layer is made of the same material as the lower thermal insulation layer, which can simplify the preparation and reduce the preparation cost;
  • the upper surface of the thermal insulation layer 106 has a small hole, the small hole is located at the same position as the small hole in the lower electric insulation layer 102, and the bottom of the small hole is the intermediate electrode 105;
  • An upper p-type memory material plug column 107 the upper p-type memory material plug column 107 is located in the small hole wrapped by the upper electric heat insulating layer 106, and the bottom of the upper p-type memory material plug column 107 is connected to the top of the middle electrode 105.
  • the upper p-type memory material plug column 107 has the same thickness and material as the lower p-type memory material plug column 104, which can simplify the preparation and reduce the manufacturing cost;
  • An n-type semiconductor material plug post 108, the n-type semiconductor material plug post 108 is located in the small hole wrapped by the upper electric heat insulating layer 106, the bottom of the upper n-type semiconductor material plug column 108 and the upper p-type memory material plug column 107 is connected at the top, and the upper n-type semiconductor material plug post 108 has the same thickness and material as the lower n-type semiconductor material plug post 103;
  • the upper electrode 109 layer is formed on the lithographic upper electric insulating layer 106, and after peeling off, the upper electrode 109 is obtained, and the upper electrode 109 and the upper electric insulating layer 106 are wrapped on the top of the small hole.
  • the upper n-type semiconductor material plug column 108 is connected, the upper electrode 109 has a thickness of 100-500 nm, and the material of the upper electrode 109 is the same as that of the lower electrode 101, which can simplify the preparation and reduce the preparation cost;
  • the present invention further provides a method for preparing a multi-layer three-dimensional memory, which is described by taking a dual-layer memory as an example.
  • the method includes:
  • Step 1 performing photolithography on the insulating or semiconductor substrate 100, and then preparing a lower electrode 101 in the vertical direction on the lithographic substrate 100, and peeling off to obtain a lower electrode 101 corresponding to the lithographic pattern.
  • the electrode material may be a metal or non-metal having good conductivity, such as silver, copper, titanium tungsten alloy, graphene, etc., the thickness of the lower electrode 101 is 100-500 nm, and the structure after step 1 is as shown in FIG. 1;
  • Step 2 further preparing a lower electric insulating layer 102, the material of the lower electric insulating layer 102 is: nitride, oxide, sulfide or a mixture of two or more materials, the lower electric insulating layer 102 is slightly smaller than the substrate 100, such that a portion of the lower electrode 101 is exposed.
  • the thickness of the lower electric insulating layer 102 is 100-1000 nm.
  • Step 3 Prepare a small hole in the middle of the lower electric insulating layer 102 by using a micro-nano processing technique.
  • the small hole depth is the same as the thickness of the lower electric insulating layer material 102, and the bottom of the small hole is the lower electrode 101.
  • Step 4 filling the n-type semiconductor material plug post 103 by chemical vapor deposition or sputtering.
  • the structure is as shown in FIG. 4, and the n-type semiconductor material plug post 103 is located on the lower electric insulating layer 102. In the hole, the bottom of the lower n-type semiconductor material plug post 103 is connected to the top of the lower electrode 101.
  • the n-type semiconductor material plug post 103 has a thickness of 10-500 nm, and the lower n-type semiconductor material plug post 103 and the lower p-type memory material.
  • the sum of the thicknesses of the plugs 104 is equal to the depth of the small holes, and the material of the n-type semiconductor material plugs 103 may be any n-type semiconductor material capable of forming a pn junction with the p-type memory material in the memory;
  • Step 5 filling the p-type memory material plug column 104 by chemical vapor deposition or sputtering, and filling the small holes, and the bottom of the lower p-type memory material plug column 104 and the bottom of the lower n-type semiconductor material plug column 103 Connected, the p-type memory material plug post 104 has a thickness of 10-500 nm, and the sum of the thickness of the lower n-type semiconductor material plug post 103 and the lower p-type memory material plug post 104 is equal to the depth of the small hole, the p-type memory material It may be, for example, GeTe, SbTe, BiTe, SnTe, AsTe, GeSe, SbSe, BiSe, SnSe, AsSe, InSe, GeSbTe, AgInSbTe and its compounds, and the above compounds are doped with elements such as S, N, O, Cu, Si, Au, etc.
  • the formed mixture, after the step 5, the structure is as shown in
  • Step 6 removing the n-type semiconductor material and the p-type memory material on the surface of the lower thermal insulating layer 102 by chemical mechanical polishing or reverse etching, and the structure is as shown in FIG. 6 after step 6;
  • Step 7 performing photolithography on the surface of the lower electric insulating layer 102, and then preparing the intermediate electrode 105 in the horizontal direction, and after peeling off, obtaining the intermediate electrode 105 corresponding to the lithographic pattern, and the small hole wrapped by the intermediate electrode 105 and the lower electric insulating layer 102
  • the top lower p-type memory material plug column 104 is connected, the intermediate electrode 105 has a thickness of 100-500 nm, and the material of the intermediate electrode 105 and the lower electrode 101
  • Figure 7 shows the same, after the step 7 structure is shown in Figure 7;
  • Step 8 Preparing an upper electric thermal insulation layer 106 on the lower electric thermal insulation layer 102 having the intermediate electrode 105.
  • the thickness and material of the upper electric thermal insulation layer 106 are the same as those of the lower electric thermal insulation layer 102.
  • the area ratio of the upper electric thermal insulation layer 106 is The lower thermal insulation layer 102 is slightly smaller, so that the intermediate electrode 105 is partially exposed.
  • Step 9 Prepare a small hole at the same position in the middle of the upper thermal insulating layer by using a micro-nano processing technique.
  • the small hole is located at the same position as the small hole in the lower electric insulating layer 102, and the bottom of the small hole is the intermediate electrode 105.
  • the structure is shown in Figure 9;
  • Step 10 filling the p-type memory material plug column 107 by chemical vapor deposition or sputtering, and connecting the bottom of the upper p-type memory material plug column 107 to the top of the intermediate electrode 105, the thickness of the upper p-type memory material plug column 107
  • the material is the same as the lower p-type memory material plug column 104, and after the step 10, the structure is as shown in FIG. 10;
  • Step 11 filling the upper n-type semiconductor material plug post 108 by chemical vapor deposition or sputtering, and filling the small holes, the bottom of the upper n-type semiconductor material plug column 108 and the top of the upper p-type memory material plug column 107 Connected, the upper n-type semiconductor material plug column 108 has the same thickness and material as the lower n-type semiconductor material plug post 103, and after step 11, the structure is as shown in FIG. 11;
  • Step 12 removing the n-type semiconductor material and the p-type memory material on the surface of the upper thermal insulating layer 106 by chemical mechanical polishing or reverse etching, and the structure is as shown in FIG. 12 after step 12;
  • Step 13 performing photolithography on the surface of the upper thermal insulating layer 106, and then preparing the upper electrode 109 in the vertical direction, and after peeling off, the upper electrode 109 corresponding to the lithographic pattern is obtained, and the upper electrode 109 and the upper electric insulating layer 106 are small.
  • the upper n-type semiconductor material plug column 108 is connected to the top of the hole.
  • the upper electrode 109 has a thickness of 100-500 nm.
  • the material of the upper electrode 109 is the same as that of the lower electrode 101, and the preparation of the three-dimensional memory is completed. 13 shows a completed top view of the three-dimensional memory as shown in FIG. 14;
  • Step 1 Photolithography is performed on a silicon substrate having a silicon dioxide insulating layer on the surface, and a lower electrode is prepared on the lithographic substrate, and after peeling, a strip-shaped lower electrode in a vertical direction is obtained.
  • the electrode thickness is 100 nm, and the lower electrode material is silver;
  • Step 2 further preparing a lower electric insulating layer, the lower insulating layer is slightly smaller than the lower electrode on the substrate, so that the lower electrode portion is exposed, the thickness is 500 nm, and the material is SiO 2 ;
  • Step 3 preparing a small hole in the middle of the lower electric insulating layer by using micro-nano processing technology, the hole diameter is 50 nm, and the depth is 500 nm;
  • Step 4 filling the n-type semiconductor material plug column by chemical vapor deposition, the n-type semiconductor material plug column has a thickness of 200 nm, and the material is n-type silicon;
  • Step 5 filling the p-type phase change memory material plug column by chemical vapor deposition or sputtering, and filling the small hole, the p-type memory material plug column thickness is 200 nm, p-type phase change memory material plug column
  • the material is a GeTe alloy
  • Step 6 removing n-type silicon and p-type GeTe alloy on the surface of the lower electric heat insulating layer by chemical mechanical polishing;
  • Step 7 performing photolithography on the surface of the lower electric insulating layer, and then preparing a horizontal electrode in the horizontal direction, and after peeling, obtaining an intermediate electrode in the horizontal direction, the electrode thickness is 100 nm, and the electrode material is silver;
  • Step 8 preparing an upper electric heat insulating layer on the lower electric heat insulating layer prepared with the intermediate electrode.
  • the size of the upper insulating layer is slightly smaller than that of the intermediate electrode, so that the intermediate electrode is partially exposed.
  • the thickness of the upper electric insulating layer is 500 nm, and the material is SiO 2 . ;
  • Step 9 preparing a small hole at the same position by using a micro-nano processing technique in the middle of the upper thermal insulating layer, the small hole is located at the same position as the small hole wrapped by the lower electrode, and the small hole depth is 500 nm;
  • Step 10 filling a p-type phase change memory material plug column by chemical vapor deposition, the p-type phase change memory material plug column has a thickness of 200 nm, and the material is a GeTe alloy;
  • Step 11 filling the n-type semiconductor material plug column by chemical vapor deposition, and filling the small holes, the n-type semiconductor material plug column has a thickness of 200 nm, and the n-type semiconductor material plug column material N-type silicon;
  • Step 12 removing n-type silicon and p-type GeTe alloy on the surface of the upper thermal insulating layer by chemical mechanical polishing or reverse etching;
  • Step 13 performing photolithography on the surface of the upper thermal insulating layer, and then preparing an upper electrode in a vertical direction, and peeling off to obtain an upper electrode in a vertical direction, the upper electrode having a thickness of 100 nm, and the material being silver, completing a three-dimensional phase change memory ( Preparation of 3D-PCRAM or 3D X-point).
  • Step 1 Photolithography is performed on a silicon substrate having a silicon dioxide insulating layer on the surface, and a lower electrode is prepared on the lithographic substrate, and after peeling, a strip-shaped lower electrode in a vertical direction is obtained.
  • the electrode thickness is 100 nm, and the lower electrode material is titanium;
  • Step 2 further preparing a lower electric insulating layer, the lower insulating layer is slightly smaller than the lower electrode on the substrate, so that the lower electrode portion is exposed, the thickness is 500 nm, and the material is SiO 2 ;
  • Step 3 preparing a small hole in the middle of the lower electric insulating layer by using micro-nano processing technology, the hole diameter is 50 nm, and the depth is 500 nm;
  • Step 4 filling the n-type semiconductor material plug column by chemical vapor deposition, the n-type semiconductor material plug column has a thickness of 200 nm, and the material is ZnO;
  • Step 5 filling the p-type resistive memory material plug column by chemical vapor deposition or sputtering, and filling the small holes, the p-type memory material plug column has a thickness of 200 nm, and the p-type resistive memory material plug column The material is Cu 2 O;
  • Step 6 removing ZnO and p-type Cu 2 O on the surface of the lower electric insulating layer by chemical mechanical polishing;
  • Step 7 performing photolithography on the surface of the lower electric insulating layer, and then preparing a horizontal electrode in the horizontal direction, and after peeling, obtaining an intermediate electrode in the horizontal direction, the electrode thickness is 100 nm, and the electrode material is titanium;
  • Step 8 preparing an electric heating insulating layer on the lower electric insulating layer prepared with the intermediate electrode.
  • the size of the upper insulating layer is slightly smaller than that of the intermediate electrode, so that the intermediate electrode is partially exposed.
  • the thickness of the upper electric insulating layer is 500 nm, and the material is SiO 2 . ;
  • Step 9 preparing a small hole at the same position by using a micro-nano processing technique in the middle of the upper thermal insulating layer, the small hole is located at the same position as the small hole wrapped by the lower electrode, and the small hole depth is 500 nm;
  • Step 10 filling the p-type resistive memory material plug column by chemical vapor deposition, the p-type resistive memory material plug column has a thickness of 200 nm, and the material is Cu 2 O;
  • Step 11 filling the n-type semiconductor material plug column by chemical vapor deposition, and filling the small holes, the n-type semiconductor material plug column thickness is 200 nm, the n-type semiconductor material plug column material is ZnO;
  • Step 12 removing ZnO and p-type Cu 2 O on the surface of the upper thermal insulating layer by chemical mechanical polishing or reverse etching;
  • Step 13 performing photolithography on the surface of the upper thermal insulating layer, and then preparing an upper electrode in a vertical direction, and peeling off to obtain an upper electrode in a vertical direction, the upper electrode having a thickness of 100 nm, and the material being titanium, completing a three-dimensional resistive memory ( Preparation of 3D-RRAM).
  • the present invention when the P-type phase change material is selected as the storage material, the present invention can be applied to a three-dimensional phase change memory (3D-PCRAM); when the P-type phase change material is selected as a storage material, the structure is a cross structure, The invention can be applied to a three-dimensional phase change memory (3D X-Point); when a P-type resistive material is selected as a storage material, the present invention can apply a three-dimensional resistive memory (3D-RRAM).
  • 3D-PCRAM three-dimensional phase change memory
  • 3D X-Point three-dimensional phase change memory
  • the present invention when a P-type resistive material is selected as a storage material, the present invention can apply a three-dimensional resistive memory (3D-RRAM).

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Abstract

一种三维存储器及其制备方法，该三维存储器由多层存储器垂直堆叠而成，每层包括：条状电极(101、105、109)；电热绝缘层(102、106)；电热绝缘层(102、106)中间的小孔；位于小孔中的n型半导体材料插塞柱(103、108)和p型存储材料插塞柱（104、107）；该存储器可独立对每个单元进行读写。该存储器选取p型存储介质与n型半导体材料形成pn结，所选取的p型存储材料具有双重功能，既是存储介质也是选通管一部分。存储器自带选通管，不要额外的晶体管作为选通开关，可以大大地减小单元面积提高存储密度，同时能有效减小漏电流和热串扰。

Description

一种三维存储器及其制备方法 【技术领域】
本发明属于微纳电子技术领域，具体涉及一种三维存储器。
【背景技术】
当前是一个3D存储器技术爆炸性发展的一个阶段。目前国际上先后提出了3D-NAND、3D-RRAM、3D X-point等三维结构存储器，三维存储器具有垂直立体结构，由多层存储器堆叠而成，能有效利用空间面积，大大提高存储密度。是未来存储器发展的必然方向。
相变存储器(PCRAM)是基于奥弗辛斯基效应的元件，其最为核心的是以硫属化合物为基础的相变材料。PCRAM的存储介质在热诱导作用下可实现非晶体状态和晶体状态之间的可逆转变，存储介质处于非晶体状态和晶体状态时会呈现出不同的光学特性和电阻特性，于是非晶体状态和晶体状态可以分别用来代表“0”和“1”来存储数据。
Flash存储器每个存储单元由源极、漏极,控制栅极和浮空栅极组成，浮空栅极上存储电荷不同，器件的阈值电压不同，控制栅加电压，即可存储0和1。NAND型Flash各存储单元之间是串联的，NAND的全部存储单元分为若干个块，每个块又分为若干个页，每个页是512byte，就是512个8位数，就是说每个页有512条位线，每条位线下有8个存储单元。3D-NAND是为回避闪存或内存芯片存储密度增加的局限性，将它们向上堆叠，从而增加存储密度。三维垂直NAND存储串在2001年被首次公开(“Novel Ultra High Density Memory with a Stacked-Surrounding Gate Transistor(S-SGT)Structured Cell”,IEDM Proc.(2001)33-36)。
阻变存储器(RRAM)是一种新型非易失存储器，存储单元通常为MIM结构，即金属/阻变存储层/金属三明治结构，便于进行3D堆叠。在适当的 电压(直流/脉冲)作用下，器件的电阻会在高阻态和低阻态之间可逆转变，从而实现实现“0”和“1”的存储。根据发生电阻转变所需电压极性的不同，RRAM器件的电阻转变可以分为单极性(Unipolar)和双极性(Bipolar)。所谓的单极性是指器件发生Set和Reset过程所需要的电压极性相同，而双极性是指器件发生Set和Reset过程所需要的电压极性相反。除了单极性和双极性转变外，还存在一种被称作无极性(Nonpolar)的电阻转变特性，是指器件在正负电压下均能够实现Set和Reset操作。为了防止电流过大将器件永久击穿，Set过程中通常需要加入一定的限流。
【发明内容】
针对现有技术中的三维存储器存在需要额外的选通开关以及空间利用率低等问题，本发明旨在解决以上问题。
为实现上述目的，本发明提供了一种三维存储器，其特征在于，所述三维存储器包括：
一衬底；
一第一方向上的条状下电极，所述下电极设置在衬底上，所述第一方向是指平面内任一方向；
一下电热绝缘层，该下电热绝缘层设置在有所述下电极的所述衬底上；
其中所述下电热绝缘层中间有一个或多个小孔，小孔底部为下电极；
一下n型半导体材料插塞柱，所述下n型半导体材料插塞柱位于所述下电热绝缘层包裹的所述小孔中，所述下n型半导体材料插塞柱底部形成与所述下电极顶部；
一下p型存储材料插塞柱，所述下p型存储材料插塞柱位于所述下电热绝缘层包裹的所述小孔中，所述下p型存储材料插塞柱底部形成于所述下n型半导体材料插塞柱顶部；
一与第一方向垂直并在同一所述平面内的第二方向上的条状次层电 极，该次层电极层设置在所述下电热绝缘层上，所述中间电极设置在所述下p型存储材料插塞柱的顶部；
设置在包括所述次层电极层的所述下热绝缘层上多个中间层，所述中间层的数量为包括零的正整数，所述中间层的结构如下：
一中间电热绝缘层，该中间电热绝缘层设置在有下方相邻电极的下方相邻电热绝缘层上，
其中所述中间电热绝缘层中间有一个或多个小孔，且该中间电热绝缘层中的小孔底部为所述下方相邻电极，
一中间p型存储材料插塞柱，所述中间p型存储材料插塞柱位于所述中间电热绝缘层包裹的小孔中，所述中间p型存储材料插塞柱底部设置在所述下方相邻电极顶部，
一中间n型半导体材料插塞柱，所述中间n型半导体材料插塞柱位于所述中间电热绝缘层包裹的小孔中，所述中间n型半导体材料插塞柱底部设置在所述中间p型存储材料插塞柱顶部，
一与下方相邻条状电极方向垂直方向上的条状中间电极，该中间电极设置在所述中间电热绝缘层上，所述中间电极设置在所述中间n型半导体材料插塞柱顶部；
一上电热绝缘层，该上电热绝缘层设置在有下方相邻电极的下方相邻电热绝缘层上；
其中所述上电热绝缘层中间有一个或多个小孔，且该上电热绝缘层中的小孔底部为所述中间电极；
一上p型存储材料插塞柱，所述上p型存储材料插塞柱位于所述上电热绝缘层包裹的小孔中，所述上p型存储材料插塞柱底部设置在所述下方相邻电极顶部；
一上n型半导体材料插塞柱，所述上n型半导体材料插塞柱位于所述上电热绝缘层包裹的小孔中，所述上n型半导体材料插塞柱底部设置在所 述上p型存储材料插塞柱顶部；
一与下方相邻条状电极方向垂直方向上的的条状上电极，该上电极层设置在所述上电热绝缘层上，所述上电极设置在所述上n型半导体材料插塞柱顶部。。
按照本发明的另一方面，本发明提供了一种多层三维存储器的制备方法，其特征在于，该方法包括以下步骤：
步骤1：在表面有一层二氧化硅绝缘层的衬底上进行光刻，再在光刻后的所述衬底上制备一层下电极，经过剥离，得到对应光刻图形的第一方向上的条状下电极；
步骤2：再制备一层下电热绝缘层；
步骤3：在所述下电热绝缘层的中间利用微纳加工技术制备小孔；
步骤4：利用化学气相沉积或者溅射法在所述小孔中填充下型半导体材料插塞柱；
步骤5：利用化学气相沉积或者溅射法在所述小孔中填充p型存储材料插塞柱，并将小孔填满；
步骤6：用化学机械抛光或者反刻蚀的方法，将所述下电热绝缘层表面的n型半导体材料与p型存储材料去除；
步骤7：在所述下电热绝缘层的表面进行光刻，然后制备次层电极，经过剥离后得到对应光刻图形的与第一方向垂直的第二方向上的条状此层电极；
步骤8：在制备有所述次间电极的所述下电热绝缘层上制备中间层，所述中间层的数量为零或正整数；每层中间层的制备方法如下：
步骤81：在制备有下方相邻电极的下方相邻电热绝缘层上制备中间电热绝缘层；
步骤82：在所述中间电热绝缘层的中间利用微纳加工技术在同一位置制备小孔；
步骤83：利用化学气相沉积或者溅射法在所述中间电热绝缘层的小孔中填充上p型存储材料插塞柱；
步骤84：利用化学气相沉积或者溅射法在所述中间电热绝缘层的小孔中填充上n型半导体材料插塞柱，并将小孔填满；
步骤85：用化学机械抛光或者反刻蚀的方法，将所述中间电热绝缘层的表面的所述n型半导体材料与所述p型存储材料去除；
步骤86：在所述中间电热绝缘层的表面进行光刻，然后制备中间电极，经过剥离后得到对应光刻图形的垂直方向上的条状中间电极；
步骤9：在制备有所述中间电极的所述中间电热绝缘层上制备上电热绝缘层；
步骤10：在上电热绝缘层的中间利用微纳加工技术在同一位置制备小孔；
步骤11：利用化学气相沉积或者溅射法在所述上绝缘层的小孔中填充上p型存储材料插塞柱；
步骤12：利用化学气相沉积或者溅射法在所述上绝缘层的小孔中填充上n型半导体材料插塞柱，并将小孔填满；
步骤13：用化学机械抛光或者反刻蚀的方法，将所述上电热绝缘层的表面的n型半导体材料与p型存储材料去除；
步骤14：在所述上电热绝缘层的表面进行光刻，然后制备上电极，经过剥离后得到对应光刻图形的垂直方向上的条状上电极，完成三维存储器的制备。
通过本发明所构思的以上技术方案，与现有技术相比，能够取得以下有益效果：
(1)该三维存储器由多层存储器堆叠而成，能大大增加空间利用面积，从而能极大地增加存储密度；
(2)利用该发明提供的制备方法可以推广到多层结构中去，具有极大 的发展潜力；
(3)本发明自带pn结选通开关，能有效减少存储器中晶体管所占的面积，在有效减少漏电流与热串扰的同时缩小了单元面，提高了存储密度；
(4)该发明中的p型存储材料既是pn结选通管中的p型材料，又是存储介质，具有双重功能，有效的简化了工艺步骤，能降低的工业生产的成本。
【附图说明】
图1-13是本发明三维存储器的制备方法的每一步骤的视图，为了更直观地描述器件结构与制备流程，每一图片包括了立体图和剖面图两种；
图14是完成制备后的三维存储器的俯视图；
图15为实施例1中，对一个存储器单元进行I-V特性测试的结果；
图16为实施例1中，对一个存储器单元进行读写测试的结果；
图17为本发明三维存储器的3D示意图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参阅图1所示，本发明一种多层三维存储器，以双层存储器为例进行说明，包括：
一衬底100；
一垂直方向上的下电极101，该下电极制作在光刻后的衬底100上，经过剥离后获得对应光刻图形的电极，电极材料可以是导电性良好的金属或非金属，如银，铜，钛钨合金，石墨烯等，该下电极101的厚度为100-500nm；
一下电热绝缘层材料102，该下电热绝缘材料层102制作在制备有下电极101的衬底100上，该下电热绝缘层102材料是：氮化物，氧化物，硫化物或其中两种以上材料的混合物，该下电热绝缘层102略小于衬底100， 使得下电极101有部分裸露出来，该下电热绝缘层102 的厚度为100-1000nm；
其中所述的下电热绝缘层中间有一小孔，小孔深度与下电热绝缘层材料102厚度相同，小孔的底部为下电极101；
一下n型半导体材料插塞柱103，n型半导体材料插塞柱103位于下电热绝缘层102包裹的小孔中，下n型半导体材料插塞柱103底部与下电极柱102顶部相连，该n型半导体材料插塞柱103厚度为10-500nm，下n型半导体材料插塞柱103与下p型存储材料插塞柱104厚度之和等于小孔的深度，该n型半导体材料插塞柱103的材料可以是任何能与本存储器中p型存储材料形成pn结的n型半导体材料，该材料可以是：掺杂的n型半导体如n型硅、金属氧化物如ZnO、Cu2O、n型半导体化合物材料如GaN等；
一下p型存储材料插塞柱104，下p型存储材料插塞柱104位于下电热绝缘层102包裹的小孔中，下p型存储材料插塞柱104底部与下n型半导体材料插塞柱103顶部相连，该p型存储材料插塞柱104厚度为10-500nm，下n型半导体材料插塞柱103与下p型存储材料插塞柱104厚度之和等于小孔的深度，该p型存储材料可以是硫系化合物半导体材料，如GeTe，SbTe，BiTe，SnTe,AsTe,GeSe,SbSe,BiSe,SnSe,AsSe,InSe,GeSbTe，AgInSbTe及其化合物，以及上述化合物掺入S、N、O、Cu、Si、Au等元素形成的混合物；
一水平方向上的中间电极105，该中间电极105层制备在光刻后的下电热绝缘层102上，经剥离后得到中间电极105，中间电极105与下电热绝缘层102包裹的小孔顶部的下p型存储材料插塞柱104相连，该中间电极105的厚度为100-500nm，该中间电极105的材料与下电极101相同；
一上电热绝缘层106，该上电热绝缘层106制备在有中间电极107的下电热绝缘层102上，该上电热绝缘层106的厚度与材料均与下电热绝缘层102相同，该上电热绝缘层106面积比下电热绝缘层102略小，使得中间电 极105有部分裸露出来，上热绝缘层采用与下热绝缘层相同的材料，这样可以使得简化制备，降低制备成本；
其中上电热绝缘层106中间有一小孔，该小孔与下电热绝缘层102中小孔位于同一位置，小孔底部为中间电极105；
一上p型存储材料插塞柱107，上p型存储材料插塞柱107位于上电热绝缘层106包裹的小孔中，上p型存储材料插塞柱107底部与中间电极105顶部相连，该上p型存储材料插塞柱107厚度与材料均与下p型存储材料插塞柱104相同，这样可以使得简化制备，降低制备成本；
一上n型半导体材料插塞柱108，n型半导体材料插塞柱108位于上电热绝缘层106包裹的小孔中，上n型半导体材料插塞柱108底部与上p型存储材料插塞柱107顶部相连，该上n型半导体材料插塞柱108的厚度与材料均与下n型半导体材料插塞柱103相同；
一垂直方向上的上电极109，该上电极109层制备在光刻后的上电热绝缘层106上，经剥离后得到上电极109，上电极109与上电热绝缘层106包裹的小孔顶部的上n型半导体材料插塞柱108相连，该上电极109的厚度为100-500nm，该上电极109的材料与下电极101相同，这样可以使得简化制备，降低制备成本；
请参照图1-15，本发明还提供一种多层三维存储器的制备方法，以双层存储器为例进行说明，该方法包括：
步骤1：在绝缘的或者半导体衬底100上进行光刻，再在光刻后的衬底100上制备一层垂直方向上的下电极101，经过剥离，得到对应光刻图形的下电极101，电极材料可以是导电性良好的金属或非金属，如银，铜，钛钨合金，石墨烯等，该下电极101的厚度为100-500nm，经过步骤1后结构如图1所示；
步骤2：再制备一层下电热绝缘层102，该下电热绝缘层102材料是：氮化物，氧化物，硫化物或其中两种以上材料的混合物，该下电热绝缘层 102略小于衬底100，使得下电极101有部分裸露出来，该下电热绝缘层102的厚度为100-1000nm，经过步骤2后结构如图2所示；
步骤3：在下电热绝缘层102的中间利用微纳加工技术制备小孔，小孔深度与下电热绝缘层材料102厚度相同，小孔的底部为下电极101，经过步骤3后结构如图3所示；
步骤4：利用化学气相沉积或者溅射法填充下n型半导体材料插塞柱103，经过步骤4后结构如图4所示，n型半导体材料插塞柱103位于下电热绝缘层102包裹的小孔中，下n型半导体材料插塞柱103底部与下电极101顶部相连，该n型半导体材料插塞柱103厚度为10-500nm，下n型半导体材料插塞柱103与下p型存储材料插塞柱104厚度之和等于小孔的深度，该n型半导体材料插塞柱103的材料可以是任何能与本存储器中p型存储材料形成pn结的n型半导体材料；
步骤5：利用化学气相沉积或者溅射法填充下p型存储材料插塞柱104，并将小孔填满，下p型存储材料插塞柱104底部与下n型半导体材料插塞柱103顶部相连，该p型存储材料插塞柱104厚度为10-500nm，下n型半导体材料插塞柱103与下p型存储材料插塞柱104厚度之和等于小孔的深度，该p型存储材料可以是如GeTe，SbTe，BiTe，SnTe,AsTe,GeSe,SbSe,BiSe,SnSe,AsSe,InSe,GeSbTe，AgInSbTe及其化合物，以及上述化合物掺入S、N、O、Cu、Si、Au等元素形成的混合物，经过步骤5后结构如图5所示；
步骤6：用化学机械抛光或者反刻蚀的方法，将下电热绝缘层102的表面的n型半导体材料与p型存储材料去除，经过步骤6后结构如图6所示；
步骤7：在下电热绝缘层102的表面进行光刻，然后制备水平方向上的中间电极105，经过剥离后得到对应光刻图形的中间电极105，中间电极105与下电热绝缘层102包裹的小孔顶部的下p型存储材料插塞柱104相连，该中间电极105的厚度为100-500nm，该中间电极105的材料与下电极101 相同，经过步骤7后结构如图7所示；
步骤8：在制备有中间电极105的下电热绝缘层102上制备上电热绝缘层106，该上电热绝缘层106的厚度与材料均与下电热绝缘层102相同，该上电热绝缘层106面积比下电热绝缘层102略小，使得中间电极105有部分裸露出来，经过步骤8后结构如图8所示；
步骤9：在上电热绝缘层的中间利用微纳加工技术在同一位置制备小孔，该小孔与下电热绝缘层102中小孔位于同一位置，小孔底部为中间电极105，经过步骤9后结构如图9所示；
步骤10：利用化学气相沉积或者溅射法填充上p型存储材料插塞柱107，上p型存储材料插塞柱107底部与中间电极105顶部相连，该上p型存储材料插塞柱107厚度与材料均与下p型存储材料插塞柱104相同，经过步骤10后结构如图10所示；
步骤11：利用化学气相沉积或者溅射法填充上n型半导体材料插塞柱108，并将小孔填满，上n型半导体材料插塞柱108底部与上p型存储材料插塞柱107顶部相连，该上n型半导体材料插塞柱108的厚度与材料均与下n型半导体材料插塞柱103相同，经过步骤11后结构如图11所示；
步骤12：用化学机械抛光或者反刻蚀的方法，将上电热绝缘层106的表面的n型半导体材料与p型存储材料去除，经过步骤12后结构如图12所示；
步骤13：在上电热绝缘层106的表面进行光刻，然后制备垂直方向上的上电极109，经过剥离后得到对应光刻图形的上电极109，上电极109与上电热绝缘层106包裹的小孔顶部的上n型半导体材料插塞柱108相连，该上电极109的厚度为100-500nm，该上电极109的材料与下电极101相同，完成三维存储器的制备，经过步骤13后结构如图13所示，完成的三维存储器俯视图如图14所示；
实施例1：
步骤1：在表面有一层二氧化硅绝缘层的硅衬底上进行光刻，再在光刻后的衬底上制备一层下电极，经过剥离，得到垂直方向上的条状下电极，下电极厚度为100nm，下电极材料为银；
步骤2：再制备一层下电热绝缘层，下绝缘层比衬底上的下电极尺寸略小，使得下电极部分裸露出来，厚度为500nm，材料为SiO2；
步骤3：在下电热绝缘层的中间利用微纳加工技术制备小孔，孔径为50nm，深度为500nm；
步骤4：利用化学气相沉积填充下n型半导体材料插塞柱，n型半导体材料插塞柱厚度为200nm，材料为n型硅；
步骤5：利用化学气相沉积或者溅射法填充下p型相变存储材料插塞柱，并将小孔填满，p型存储材料插塞柱厚度为200nm，p型相变存储材料插塞柱材料为GeTe合金；
步骤6：用化学机械抛光的方法，将下电热绝缘层的表面的n型硅与p型GeTe合金去除；
步骤7：在下电热绝缘层的表面进行光刻，然后制备水平方向的中间电极，经过剥离后得到水平方向上的中间电极，电极厚度为100nm，电极材料为银；
步骤8：在制备有中间电极的下电热绝缘层上制备上电热绝缘层，上绝缘层尺寸比中间电极略小，使得中间电极由部分裸露出来，上电热绝缘层厚度为500nm，材料为SiO2；
步骤9：在上电热绝缘层的中间利用微纳加工技术在同一位置制备小孔，该小孔与下电极包裹着的小孔位于同一位置，小孔深度为500nm；
步骤10：利用化学气相沉积法填充上p型相变存储材料插塞柱，p型相变存储材料插塞柱厚度为200nm，材料为GeTe合金；
步骤11：利用化学气相沉积法填充上n型半导体材料插塞柱，并将小孔填满，n型半导体材料插塞柱厚度为200nm，n型半导体材料插塞柱材料 为n型硅；
步骤12：用化学机械抛光或者反刻蚀的方法，将上电热绝缘层的表面的n型硅与p型GeTe合金去除；
步骤13：在上电热绝缘层的表面进行光刻，然后制备垂直方向上的上电极，经过剥离后得到垂直方向上的上电极，上电极厚度为100nm，材料为银，完成三维相变存储器(3D-PCRAM或者3D X-point)的制备。
实施例2：
步骤1：在表面有一层二氧化硅绝缘层的硅衬底上进行光刻，再在光刻后的衬底上制备一层下电极，经过剥离，得到垂直方向上的条状下电极，下电极厚度为100nm，下电极材料为钛；
步骤2：再制备一层下电热绝缘层，下绝缘层比衬底上的下电极尺寸略小，使得下电极部分裸露出来，厚度为500nm，材料为SiO2；
步骤3：在下电热绝缘层的中间利用微纳加工技术制备小孔，孔径为50nm，深度为500nm；
步骤4：利用化学气相沉积填充下n型半导体材料插塞柱，n型半导体材料插塞柱厚度为200nm，材料为ZnO；
步骤5：利用化学气相沉积或者溅射法填充下p型阻变存储材料插塞柱，并将小孔填满，p型存储材料插塞柱厚度为200nm，p型阻变存储材料插塞柱材料为Cu2O；
步骤6：用化学机械抛光的方法，将下电热绝缘层的表面的ZnO与p型Cu2O去除；
步骤7：在下电热绝缘层的表面进行光刻，然后制备水平方向的中间电极，经过剥离后得到水平方向上的中间电极，电极厚度为100nm，电极材料为钛；
步骤8：在制备有中间电极的下电热绝缘层上制备上电热绝缘层，上绝缘层尺寸比中间电极略小，使得中间电极由部分裸露出来，上电热绝缘层 厚度为500nm，材料为SiO2；
步骤9：在上电热绝缘层的中间利用微纳加工技术在同一位置制备小孔，该小孔与下电极包裹着的小孔位于同一位置，小孔深度为500nm；
步骤10：利用化学气相沉积法填充上p型阻变存储材料插塞柱，p型阻变存储材料插塞柱厚度为200nm，材料为Cu2O；
步骤11：利用化学气相沉积法填充上n型半导体材料插塞柱，并将小孔填满，n型半导体材料插塞柱厚度为200nm，n型半导体材料插塞柱材料为ZnO；
步骤12：用化学机械抛光或者反刻蚀的方法，将上电热绝缘层的表面的ZnO与p型Cu2O去除；
步骤13：在上电热绝缘层的表面进行光刻，然后制备垂直方向上的上电极，经过剥离后得到垂直方向上的上电极，上电极厚度为100nm，材料为钛，完成三维阻变存储器(3D-RRAM)的制备。
在本发明中，当选取P型相变材料为存储材料时，本发明可应用于三维相变存储器(3D-PCRAM)；当选取P型相变材料为存储材料时，结构为交叉结构，本发明可应用于三维相变存储器(3D X-Point)；当选取P型阻变材料为存储材料时，本发明可应用三维阻变存储器(3D-RRAM)。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (29)

  1. 一种三维存储器，其特征在于，所述三维存储器包括：
    一衬底；
    一第一方向上的条状下电极，所述下电极设置在衬底上，所述第一方向是指平面内任一方向；
    一下电热绝缘层，该下电热绝缘层设置在有所述下电极的所述衬底上；
    其中所述下电热绝缘层中间有一个或多个小孔，小孔底部为下电极；
    一下n型半导体材料插塞柱，所述下n型半导体材料插塞柱位于所述下电热绝缘层包裹的所述小孔中，所述下n型半导体材料插塞柱底部形成与所述下电极顶部；
    一下p型存储材料插塞柱，所述下p型存储材料插塞柱位于所述下电热绝缘层包裹的所述小孔中，所述下p型存储材料插塞柱底部形成于所述下n型半导体材料插塞柱顶部；
    一与第一方向垂直并在同一所述平面内的第二方向上的条状次层电极，该次层电极层设置在所述下电热绝缘层上，所述中间电极设置在所述下p型存储材料插塞柱的顶部；
    设置在包括所述次层电极层的所述下热绝缘层上多个中间层，所述中间层的数量为包括零的正整数，所述中间层的结构如下：
    一中间电热绝缘层，该中间电热绝缘层设置在有下方相邻电极的下方相邻电热绝缘层上，
    其中所述中间电热绝缘层中间有一个或多个小孔，且该中间电热绝缘层中的小孔底部为所述下方相邻电极，
    一中间p型存储材料插塞柱，所述中间p型存储材料插塞柱位于所述中间电热绝缘层包裹的小孔中，所述中间p型存储材料插塞柱底部设置在所述下方相邻电极顶部，
    一中间n型半导体材料插塞柱，所述中间n型半导体材料插塞柱位于所述中间电热绝缘层包裹的小孔中，所述中间n型半导体材料插塞柱底部设置在所述中间p型存储材料插塞柱顶部，
    一与下方相邻条状电极方向垂直方向上的条状中间电极，该中间电极设置在所述中间电热绝缘层上，所述中间电极设置在所述中间n型半导体材料插塞柱顶部；
    一上电热绝缘层，该上电热绝缘层设置在有下方相邻电极的下方相邻电热绝缘层上；
    其中所述上电热绝缘层中间有一个或多个小孔，且该上电热绝缘层中的小孔底部为所述中间电极；
    一上p型存储材料插塞柱，所述上p型存储材料插塞柱位于所述上电热绝缘层包裹的小孔中，所述上p型存储材料插塞柱底部设置在所述下方相邻电极顶部；
    一上n型半导体材料插塞柱，所述上n型半导体材料插塞柱位于所述上电热绝缘层包裹的小孔中，所述上n型半导体材料插塞柱底部设置在所述上p型存储材料插塞柱顶部；
    一与下方相邻条状电极方向垂直方向上的的条状上电极，该上电极层设置在所述上电热绝缘层上，所述上电极设置在所述上n型半导体材料插塞柱顶部。
  2. 按权利要求1所述的三维存储器，其特征在于，所述电热绝缘层为同一种材料，所述材料是：氮化物，氧化物，硫化物或其中两种以上材料的混合物，该下电热绝缘层的厚度为100-1000nm，该上电热绝缘层的厚度为100-1000nm。
  3. 按权利要求1所述的三维存储器，其特征在于，所述电热绝缘层在下方相邻条状电极长度方向上比所述下方相邻条状电极短，使所述下方相邻电极有裸露的部分。
  4. 按权利要求1所述的三维存储器，其特征在于，所述的电热绝缘层包裹的小孔的深度等于所述电热绝缘层的厚度；所述电热绝缘层包裹的小孔位于上下相邻两个电极的交叉点阵结构的交叉点上。
  5. 按权利要求1所述的三维存储器，其特征在于，上下相邻两电极构成交叉点阵结构；所述上下相邻两个交叉点阵结构的交叉点位于同一位置；所述电极厚度为10-500nm。
  6. 按权利要求1所述的三维存储器，其特征在于，所述的衬底表面有一层二氧化硅绝缘层，其厚度为0-1000nm。
  7. 按权利要求1所述的三维存储器，其特征在于，所述电热绝缘层包裹的小孔、所述p型存储材料插塞柱、所述n型半导体材料插塞柱、具有相同的直径，所述直径为1-500nm；在同一小孔中的所述p型存储材料插塞柱、n型半导体材料插塞柱的厚度之和等于小孔深度；该中间电热绝缘层中的小孔、该上绝缘层中的小孔与所述下电热绝缘层中小孔位于同一位置。
  8. 按权利要求1所述的三维存储器，其特征在于，其中所述的下电极厚度为10-500nm，中间电极厚度为10-500nm，上电极厚度为10-500nm；下n型半导体材料插塞柱厚度为10-500nm；上n型半导体材料插塞柱厚度为10-500nm；下p型存储材料插塞柱厚度为10-500nm；上p型存储材料插塞柱厚度为10-500nm。
  9. 按权利要求1所述的三维存储器，其特征在于，所述的p型存储材料可以为任何p型存储材料；述的n型存储材料可以为任何n型存储材料；在同一小孔中的n型半导体材料插塞柱与p型存储材料插塞柱构成pn结。
  10. 按权利要求1所述的三维存储器，其特征在于，该p型存储材料可以是硫系化合物半导体材料，所述硫系化合物半导体材料为GeTe，SbTe，BiTe，SnTe,AsTe,GeSe,SbSe,BiSe,SnSe,AsSe,InSe,GeSbTe，AgInSbTe及其化合物，以及上述化合物掺入S、N、O、Cu、Si、Au等元素形成的混合物。
  11. 按权利要求1所述的三维存储器，其特征在于，该n型半导体材料可以是掺杂的n型半导体材料、金属氧化物或n型半导体化合物材料，该n型半导体材料为n型硅，该金属氧化物为ZnO、Cu2O，该n型半导体化合物材料为GaN。
  12. 按权利要求1所述的三维存储器，其特征在于，选取一种p型存储材料与n型半导体材料组成pn结，其中所述p型存储材料既是存储介质也是选通管的一部分。
  13. 按权利要求1所述的三维存储器，其特征在于，其所述的p型存储材料是p型相变材料，所述三维存储器可应用为三维相变存储器。
  14. 按权利要求1所述的三维存储器，其特征在于，其所述的p型存储材料是p型相变材料，并且相邻两层电极构成点阵交叉结构，所述三维存储器可应用为3D X-Point。
  15. 按权利要求1所述的三维存储器，其特征在于，其所述的p型存储材料可以是p型阻变材料，所述三维存储器可应用为三维阻变存储器。
  16. 一种多层三维存储器的制备方法，其特征在于，该方法包括以下步骤：
    步骤1：在表面有一层二氧化硅绝缘层的衬底上进行光刻，再在光刻后的所述衬底上制备一层下电极，经过剥离，得到对应光刻图形的第一方向上的条状下电极；
    步骤2：再制备一层下电热绝缘层；
    步骤3：在所述下电热绝缘层的中间利用微纳加工技术制备小孔；
    步骤4：利用化学气相沉积或者溅射法在所述小孔中填充下型半导体材料插塞柱；
    步骤5：利用化学气相沉积或者溅射法在所述小孔中填充p型存储材料插塞柱，并将小孔填满；
    步骤6：用化学机械抛光或者反刻蚀的方法，将所述下电热绝缘层表面 的n型半导体材料与p型存储材料去除；
    步骤7：在所述下电热绝缘层的表面进行光刻，然后制备次层电极，经过剥离后得到对应光刻图形的与第一方向垂直的第二方向上的条状此层电极；
    步骤8：在制备有所述次间电极的所述下电热绝缘层上制备中间层，所述中间层的数量为零或正整数；每层中间层的制备方法如下：
    步骤81：在制备有下方相邻电极的下方相邻电热绝缘层上制备中间电热绝缘层；
    步骤82：在所述中间电热绝缘层的中间利用微纳加工技术在同一位置制备小孔；
    步骤83：利用化学气相沉积或者溅射法在所述中间电热绝缘层的小孔中填充上p型存储材料插塞柱；
    步骤84：利用化学气相沉积或者溅射法在所述中间电热绝缘层的小孔中填充上n型半导体材料插塞柱，并将小孔填满；
    步骤85：用化学机械抛光或者反刻蚀的方法，将所述中间电热绝缘层的表面的所述n型半导体材料与所述p型存储材料去除；
    步骤86：在所述中间电热绝缘层的表面进行光刻，然后制备中间电极，经过剥离后得到对应光刻图形的垂直方向上的条状中间电极；
    步骤9：在制备有所述中间电极的所述中间电热绝缘层上制备上电热绝缘层；
    步骤10：在上电热绝缘层的中间利用微纳加工技术在同一位置制备小孔；
    步骤11：利用化学气相沉积或者溅射法在所述上绝缘层的小孔中填充上p型存储材料插塞柱；
    步骤12：利用化学气相沉积或者溅射法在所述上绝缘层的小孔中填充上n型半导体材料插塞柱，并将小孔填满；
    步骤13：用化学机械抛光或者反刻蚀的方法，将所述上电热绝缘层的表面的n型半导体材料与p型存储材料去除；
    步骤14：在所述上电热绝缘层的表面进行光刻，然后制备上电极，经过剥离后得到对应光刻图形的垂直方向上的条状上电极，完成三维存储器的制备。
  17. 按权利要求16所述的三维存储器的制备方法，其特征在于，所述电热绝缘层在下方相邻条状电极长度方向上比所述下方相邻条状电极短，使所述下方相邻电极有裸露的部分；其中所述的通过光刻剥离制备的所述电极与上下相邻的电极分别构成交叉点阵结构；其中所述电极与上下相邻电极分别构成的交叉点阵结构的交叉点位于同一位置。
  18. 按权利要求16所述的三维存储器的制备方法，其特征在于，其中所述的电热绝缘层包裹的小孔的深度等于所述电热绝缘层的厚度；该中间电热绝缘层中的小孔、该上绝缘层中的小孔与所述下电热绝缘层中小孔位于同一位置。
  19. 按权利要求16所述的三维存储器的制备方法，其特征在于，所述电热绝缘层包裹的小孔位于与其上下相邻的两个电极构成的交叉点阵结构的交叉点；所述电极厚度为10-500nm。
  20. 按权利要求16所述的三维存储器的制备方法，其特征在于，所述电热绝缘层包裹的小孔、所述p型存储材料插塞柱、所述n型半导体材料插塞柱具有相同的直径，直径为1-500nm。
  21. 按权利要求16所述的三维存储器的制备方法，其特征在于，其中所述下电热绝缘层包裹的小孔由下向上依次为所述下电极、所述下n型半导体材料插塞柱、所述下p型存储材料插塞柱、所述次层电极，且所述下n型半导体材料插塞柱、所述下p型存储材料插塞柱厚度之和等于小孔深度。
  22. 按权利要求16所述的三维存储器的制备方法，其特征在于，其中所述n型半导体材料插塞柱厚度为10-500nm；所述p型存储材料插塞柱厚 度为10-500nm；所述n型半导体材料插塞柱与所述p型存储材料插塞柱构成pn结。
  23. 按权利要求16所述的三维存储器的制备方法，其特征在于，其中所述的p型存储材料可以为任何p型存储材料。
  24. 按权利要求16所述的三维存储器的制备方法，其特征在于，其中所述的n型半导体材料可以为任何与p型存储材料形成pn结的n型半导体材料。
  25. 按权利要求16所述的三维存储器的制备方法，其特征在于，其中所有所述电热绝缘层为同一种材料，该材料可以是：氮化物，氧化物，硫化物或其中两种以上材料的混合物，该电热绝缘层的厚度为100-1000nm。
  26. 按权利要求16所述的三维存储器的制备方法，其特征在于，选取一种p型存储材料与n型半导体材料组成pn结，其中所述p型存储材料既是存储介质也是选通管的一部分。
  27. 按权利要求16所述的三维存储器的制备方法，其特征在于，其所述的p型存储材料是p型相变材料，所述三维存储器可应用为三维相变存储器。
  28. 按权利要求16所述的三维存储器的制备方法，其特征在于，其所述的p型存储材料是p型相变材料，并且相邻两层电极构成点阵交叉结构，所述三维存储器可应用为3D X-Point。
  29. 按权利要求16所述的三维存储器的制备方法，其特征在于，其所述的p型存储材料可以是p型阻变材料，所述三维存储器可应用为三维阻变存储器。
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