WO2011160337A1 - 防止浮体及自加热效应的mos器件结构及其制造方法 - Google Patents

防止浮体及自加热效应的mos器件结构及其制造方法 Download PDF

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WO2011160337A1
WO2011160337A1 PCT/CN2010/076692 CN2010076692W WO2011160337A1 WO 2011160337 A1 WO2011160337 A1 WO 2011160337A1 CN 2010076692 W CN2010076692 W CN 2010076692W WO 2011160337 A1 WO2011160337 A1 WO 2011160337A1
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layer
region
sige
substrate
self
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French (fr)
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肖德元
王曦
黄晓橹
陈静
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中国科学院上海微系统与信息技术研究所
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Priority to US13/128,439 priority Critical patent/US8710549B2/en
Publication of WO2011160337A1 publication Critical patent/WO2011160337A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Definitions

  • M0S device structure for preventing floating body and self-heating effect and manufacturing method thereof
  • the present invention relates to a MOS device structure and a fabrication process thereof, and more particularly to a MOS device structure and a fabrication process thereof for preventing a floating body effect and a self-heating effect, and belonging to a semiconductor manufacturing technology. field.
  • SOI Silicon On Insulator
  • SOI Silicon On Insulator
  • the SOI technology reduces the parasitic capacitance of the source and drain
  • the speed of the S0I circuit is significantly improved compared to the speed of the conventional bulk silicon circuit, and the S0I also has a short channel effect.
  • S0I technology has gradually become the mainstream technology for manufacturing high-speed, low-power, high-integration and high-reliability ultra-large-scale silicon integrated circuits.
  • S0I devices have floating body effects and self-heating effects, which cause degradation of device performance and seriously affect the reliability of the device. When the device size is reduced, the negative effects are more prominent, which greatly limits the promotion of S0I technology.
  • the isolation of the buried oxide layer (BOX) in the SOI makes the body region in a floating state, and the charge generated by the impact ionization cannot be quickly removed, resulting in the floating body effect of the S0I device.
  • the thermal conductivity of the buried oxide layer is very low, so that the S0I device has a self-heating effect.
  • the buried oxide layer has a large thermal resistance and the device temperature is too high, thereby affecting device performance.
  • the present invention will propose another novel MOS device structure and a fabrication process thereof which can prevent the floating body effect and the self-heating effect, and the manufacturing process is simple and the device reliability is strong.
  • the technical problem to be solved by the present invention is to provide a MOS device structure and a manufacturing method thereof that prevent floating body and self-heating effect, and can reduce the parasitic capacitance of the source and drain regions while preventing the floating body effect and the self-heating effect.
  • the present invention uses the following technical solutions:
  • a MOS device structure for preventing floating body and self-heating effect comprising: a Si substrate, an insulating buried layer, a SiGe spacer, an active region, a gate region and a shallow trench isolation structure; wherein the active region is located on a Si substrate
  • the active region includes a channel and source and drain regions respectively located at both ends of the channel; the gate region is located above the channel; the insulating buried layer is disposed between the source region and the Si substrate And between the drain region and the Si substrate; the SiGe spacer is disposed between the channel and the Si substrate; for the Li OS device, the SiGe spacer is made of a P-type SiGe material; for the PMOS device, the SiGe spacer An N-type SiGe material is used; the shallow trench isolation structure is disposed around the active region.
  • a method of fabricating the above-described MOS device structure for preventing floating body and self-heating effect comprising the steps of:
  • Step 1 sequentially epitaxially growing the SiGe layer and the Si layer on the Si substrate;
  • Step 2 etching the SiGe layer and the Si layer, and doping so that they form a first conductive type SiGe layer and a first conductive type Si layer on the Si substrate, wherein the first conductive type Si layer is used Forming an active region;
  • Step 3 coating a photoresist on the first conductive type Si layer to cover the surface of the region for forming the channel, and extending outward from both sides to cover the portion of the first conductive type SiGe layer under the region a sidewall, and then a portion of the first conductive type SiGe layer under the first conductive type Si layer is removed by a selective etching technique to form a SiGe spacer, and the first conductive type Si layer is used to form a source region and a drain region. Hanging below the area;
  • Step 4 removing the photoresist, and filling the SiGe spacer above the Si substrate and the first conductive type Si layer with an insulating medium;
  • Step 5 forming a gate region on the first conductivity type Si layer, and forming a source region and a drain region of the second conductivity type in the first conductivity type Si layer by a doping process to complete the MOS device structure.
  • the MOS device structure and the manufacturing method thereof for preventing floating body and self-heating effect of the invention have the beneficial effects that: a SiGe spacer is disposed between the channel and the Si substrate, so that the channel can be lining through the SiGe spacer to the Si lining The bottom conduction and heat conduction prevent the floating body effect and self-heating effect of the device; the insulating buried layer is left between the source region and the drain region and the Si substrate, thereby reducing the parasitic capacitance of the source and drain regions; and the preparation process of the device structure Simple, easy to implement, and of great application value.
  • FIG. 1 is a schematic structural view of a MOS device for preventing floating body and self-heating effect according to the present invention
  • FIGS. 2a-2g are schematic diagrams showing the process flow for fabricating a CMOS device structure using the method of the present invention.
  • a MOS device structure for preventing floating body and self-heating effect includes a Si substrate 1 and an active region on the Si substrate 1.
  • the active region includes a channel 31 and a source region 32 and a drain region 33 respectively located at both ends of the channel 31, and a gate region is provided over the channel 31.
  • the gate region includes a gate dielectric layer 42 and a gate electrode 41 on the gate dielectric layer 42.
  • An insulating sidewall insulation structure 43 is also disposed around the gate region.
  • a shallow trench isolation structure (STI) 52 is disposed around the active region.
  • an insulating buried Layer 51 electrically isolates them, and a SiGe spacer 2 is provided between the channel 31 and the Si substrate 1 to separate them while being electrically conductive.
  • the source region 32 and the drain region 33 are heavily doped with an N-type semiconductor material, the channel 31 is made of a P-type semiconductor material, and the SiGe spacer 2 is made of a P-type SiGe material; and for the PM0S, The source region 32 and the drain region 33 are made of a heavily doped P-type semiconductor material, the channel 31 is made of an N-type semiconductor material, and the SiGe spacer 2 is made of an N-type SiGe material.
  • the insulating buried layer 51 is made of a material such as silicon oxide or silicon nitride.
  • the Si substrate may be a P-type Si substrate.
  • Step 1 The SiGe layer and the Si layer are epitaxially grown on the Si substrate 1, and the Si substrate may be a P-type Si substrate.
  • Step 2 etching the SiGe layer and the Si layer, and performing a doping process such as ion implantation to form a first conductive type SiGe layer and a first conductive type Si layer on the Si substrate, the first conductive type The Si layer is used to form an active region.
  • a doping process such as ion implantation
  • Step 3 coating a photoresist on the first conductive type Si layer to cover the surface of the region for forming the channel, and extending outward from both sides to cover the portion of the first conductive type SiGe layer under the region
  • the sidewall, the first conductive type SiGe layer under the two sides of the protection trench is not etched, and then uses a selective etching technique, for example, a mixture of H 2 and HC 1 at 600 to 800 ° C, using sub-atmospheric chemistry Selective etching by vapor phase etching, wherein a partial pressure of HC1 is greater than 300 Torr, and a portion of the first conductive type SiGe layer under the first conductive type Si layer is removed to form the SiGe spacer 2, and only the first conductive type Si layer is formed.
  • the area used to form the source and drain regions is suspended below.
  • Step 4 removing the photoresist, and filling an insulating medium around the SiGe spacer 2 and the first conductive type Si layer on the Si substrate to form a region under the region for forming the source region and the drain region in the first conductive type Si layer.
  • the buried layer 51 is insulated, and a shallow trench isolation structure 52 is formed around the first conductive type Si layer, and the filled insulating medium may be made of a material such as silicon oxide or silicon nitride.
  • Step 5 forming a gate region on the first conductive type Si layer, the gate region includes a gate dielectric layer 42 and a gate electrode 41 on the gate dielectric layer 42.
  • the gate dielectric material may be silicon dioxide or silicon oxynitride. a high dielectric constant material of a compound or a ruthenium, etc.
  • the gate electrode material may be one of titanium, nickel, tantalum, tungsten, tantalum nitride, tungsten nitride, titanium nitride, titanium silicide, tungsten silicide or nickel silicide. Or a combination thereof.
  • the source region 32 and the drain region 33 of the second conductivity type are formed in the first conductivity type Si layer by a doping process such as ion implantation.
  • the source region light doping (LDS) and the drain region can be first performed by ion implantation.
  • Light doping (LDD) and halo implantation, and finally performing second conductivity type ion implantation of source region 32 and drain region 33, and insulating sidewall spacer structure 43 may be formed around the gate region, and the material thereof may be It is silicon dioxide, silicon nitride, etc., and finally the fabrication of the MOS device is completed.
  • CMOS device based on the MOS device structure is shown in Figure 2g.
  • the following is a preferred embodiment of the fabrication of the CMOS device structure using the method of the present invention (see Figures 2a-2g):
  • Step 1 The SiGe layer 20 and the Si layer 30 are epitaxially grown on the Si substrate 10 in order, and the Si substrate 10 is a P-type Si substrate as shown in Fig. 2a.
  • Step 2 etching the SiGe layer 20 and the Si layer 30, and performing ion implantation so that they form a P-type SiGe layer 201, a P-type Si layer 301, and an N-type SiGe layer 202, N on the Si ⁇ " bottom 10, respectively.
  • the Si layer 302 is as shown in Fig. 2b, wherein the P-type Si layer 301 and the N-type Si layer 302 are used to form active regions of NMOS and PMOS, respectively.
  • Step 3 applying a photoresist 40 on the P-type Si layer 301 and the N-type Si layer 302, so that the photoresist 40 covers the surface of the region where the P-type Si layer 301 and the N-type Si layer 302 are respectively formed, And extending from both sides thereof to cover a part of the sidewalls of the P-type SiGe layer 201 and the N-type SiGe layer 202 under the region.
  • selective etching is performed by sub-atmospheric chemical vapor etching, wherein the partial pressure of HC1 is greater than 300 Torr, and the removal is at P
  • the partial pressure of HC1 is greater than 300 Torr
  • the removal is at P
  • a portion of the P-type SiGe layer 201 and the N-type SiGe layer 202 under the Si-type layer 301 and the N-type Si layer 302 form a P-type SiGe spacer 201, and an N-type SiGe spacer 202, and only the P-type Si layer 301 and
  • the region of the N-type Si layer 302 for forming the source and drain regions is suspended below.
  • FIG. 2c a schematic view of the photoresist after removing the photoresist is shown in FIG. 2d, where L is the length of the device structure along the channel direction, and W is Device structure width.
  • Step 4 removing the photoresist 40, and filling the P0 SiGe spacer 201, the P-type Si layer 301, the N-type SiGe spacer 202, and the N-type Si layer 302 over the Si substrate 10 with a Si0 2 insulating medium, so that P An insulating buried layer 501 is formed under the regions for forming the source and drain regions in the Si-type layer 301 and the N-type Si layer 302, and a shallow trench isolation structure 502 is formed around the P-type Si layer 301 and the N-type Si layer 302.
  • the CMP chemically polishes the surface.
  • Step 5 forming gate regions on the channels of the P-type Si layer 301 and the N-type Si layer 302, respectively, wherein the gate region of the NMOS layer includes a gate dielectric layer 602 and a gate electrode 601 on the gate dielectric layer 602, PM0S
  • the gate region includes a gate dielectric layer 604 and a gate electrode 603 on the gate dielectric layer 604.
  • source and drain regions are respectively formed in the P-type Si layer 301 and the N-type Si layer 302 by ion implantation.
  • source region light doping (LDS), drain region light doping (LDD), and halo can be performed first.
  • the ring is implanted (Halo), and finally the heavily doped ion implantation of the source region and the drain region is performed, and an insulating sidewall spacer structure 70 can be formed around the gate region.
  • CMOS device Based on the structure of the device, a complete CMOS device can be obtained through subsequent semiconductor fabrication processes.
  • the CMOS device prepared by the method can eliminate the floating body effect and the self-heating effect, and at the same time reduce the parasitic capacitance of the source and drain regions, and the preparation process is simple and easy to implement.

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Description

防止浮体及自加热效应的 M0S器件结构及其制造方法
技术领域 本发明涉及一种 M0S 器件结构及其制作工艺， 尤其涉及一种防止浮体效 应 (Floating Body Effect )及自力口热效应 ( Self-heating Effect ) 的 MOS 器件结构及其制作工艺， 属于半导体制造技术领域。
背景技术
SOI (Silicon On Insulator)是指绝缘体上硅技术， 由于 S0I技术减小了 源漏的寄生电容， S0I电路的速度相对传统体硅电路的速度有显著的提高， 同 时 S0I 还具有短沟道效应小， 很好的抗闭锁性， 工艺简单等一系列优点， 因 此 S0I 技术已逐渐成为制造高速、 低功耗、 高集成度和高可靠超大规模硅集 成电路的主流技术。 然而， S0I器件存在浮体效应及自加热效应， 它们会导致 器件性能的退化， 严重影响器件的可靠性， 当器件尺寸缩小时， 其负面影响 显得更为突出， 因此大大限制了 S0I技术的推广。 S0I中埋氧层（BOX) 的隔 离作用， 使得体区处于悬空状态， 碰撞电离产生的电荷无法迅速移走， 导致 了 S0I器件的浮体效应。 另外， 埋氧层的热导率很低， 因此使 S0I器件存在 自加热效应， 当 S0I 器件工作时， 埋氧层热阻大， 器件温度过高， 从而影响 了器件性能。
近年来， 为了克服上述问题， 新型的器件结构 SON (Silicon On Nothing) 和 DSOI (Drain/source On Insulator )等相继被提出。 美国专利号为 7361956 的发明专利 《 Semiconductor device having partially insulated field effect trans is tor (PIFET) and method of fabricating the same》 就公 开了一种部分绝缘隔离的场效应管及其制作方法。 该结构在沟道下方开设了 窗口， 使沟道区与衬底连通， 可消除浮体效应， 而器件工作时产生的热量也 可以通过沟道下的衬底传导出去， 从而有效抑制自加热效应， 其源漏区与半 导体衬底之间设有埋层空隙隔离区， 可减小源漏的寄生电容。 然而， 这种结 构的制造工艺较为复杂， 需要在沟道位置开设窗口再填充半导体材料与衬底 连通， 这种复杂的工艺， 在器件尺寸进一步缩小时， 将面临挑战。
在此，本发明将提出另一种新型的可以防止浮体效应及自加热效应的 M0S 器件结构及其制作工艺， 其制造工艺简单， 器件可靠性强。 发明内容 本发明要解决的技术问题在于提供一种防止浮体及自加热效应的 M0S 器 件结构及其制造方法， 可在防止浮体效应及自加热效应的同时减小源漏区的 寄生电容。
为了解决上述技术问题， 本发明釆用如下技术方案：
一种防止浮体及自加热效应的 M0S器件结构， 包括： Si衬底、 绝缘埋层、 SiGe隔层、 有源区、 栅区和浅沟槽隔离结构； 所述有源区位于 Si衬底之上， 所述有源区包括沟道以及分别位于沟道两端的源区和漏区； 所述栅区位于沟 道之上； 所述绝缘埋层设置在所述源区与 Si衬底之间， 以及漏区与 Si衬底 之间； 所述 SiGe隔层设置在沟道与 Si衬底之间； 对于丽 OS 器件， SiGe隔 层釆用 P型的 SiGe材料； 对于 PM0S器件， SiGe隔层釆用 N型的 SiGe材料； 所述浅沟槽隔离结构设置在有源区周围。
一种上述防止浮体及自加热效应的 M0S 器件结构的制造方法， 包括以下 步骤：
步骤一、 在 Si衬底上依次外延生长 SiGe层和 Si层；
步骤二、 刻蚀所述 SiGe层和 Si层， 并进行掺杂， 使它们在 Si衬底上形 成第一导电类型 SiGe层和第一导电类型 Si层， 所述第一导电类型 Si层用于 形成有源区；
步骤三、 在第一导电类型 Si层上涂覆光刻胶， 使其覆盖用于形成沟道的 区域表面， 并由两侧向外延伸覆盖该区域之下的第一导电类型 SiGe层的部分 侧壁， 然后利用选择性刻蚀技术去除位于第一导电类型 Si层之下的部分第一 导电类型 SiGe层以形成 SiGe隔层， 使第一导电类型 Si层中用于形成源区及 漏区的区域下方悬空；
步骤四、 去除光刻胶， 并在 Si衬底上方的 SiGe隔层和第一导电类型 Si 层周围填充绝缘介质；
步骤五、 在第一导电类型 Si层上制作栅区， 并通过掺杂工艺在第一导电 类型 Si层中形成第二导电类型的源区及漏区， 完成 M0S器件结构。
本发明公开的防止浮体及自加热效应的 M0S 器件结构及其制造方法， 其 有益效果在于： 在沟道与 Si衬底之间设有 SiGe隔层， 使沟道可以通过 SiGe 隔层向 Si衬底导电导热， 防止了器件的浮体效应及自加热效应； 在源区及漏 区与 Si衬底之间保留绝缘埋层， 从而可减小源漏区的寄生电容； 并且该器件 结构的制备工艺简单， 易于实施， 具有重要的应用价值。
附图说明 图 1为本发明防止浮体及自加热效应的 M0S器件结构示意图；
图 2a-2g为利用本发明方法制备 CMOS器件结构的工艺流程示意图。
具体实施方式 下面结合附图进一步说明本发明的器件结构， 为了示出的方便附图并未 按照比例绘制。
如图 1所示， 一种防止浮体及自加热效应的 M0S器件结构， 包括 Si衬底 1和位于 Si衬底 1之上的有源区。所述有源区包括沟道 31以及分别位于沟道 31两端的源区 32和漏区 33, 在沟道 31之上设有栅区。 所述栅区包括栅介质 层 42和位于所述栅介质层 42上的栅电极 41。 在所述栅区周围还设有绝缘侧 墙隔离结构 43。 所述有源区周围设有浅沟槽隔离结构（STI ) 52。 其中， 在所 述源区 32与 Si衬底 1之间， 以及漏区 33与 Si衬底 1之间分别设有绝缘埋 层 51将它们电隔离， 在沟道 31与 Si衬底 1之间设有 SiGe隔层 2将它们分 隔开但同时又能电热导通。
对于丽 OS而言， 源区 32和漏区 33釆用重掺杂的 N型半导体材料， 沟道 31釆用 P型半导体材料， SiGe隔层 2釆用 P型的 SiGe材料； 而对于 PM0S, 源区 32和漏区 33釆用重掺杂的 P型半导体材料， 沟道 31釆用 N型半导体材 料， SiGe隔层 2釆用 N型的 SiGe材料。 所述绝缘埋层 51釆用氧化硅或氮化 硅等材料。 所述 Si衬底可釆用 P型 Si衬底。
制备上述防止浮体及自加热效应的 M0S 器件结构的工艺方法， 包括以下 步骤：
步骤一、在 Si衬底 1上依次外延生长 SiGe层和 Si层， Si衬底可为 P型 Si衬底。
步骤二、 刻蚀所述 SiGe层和 Si层， 并进行离子注入等掺杂工艺， 使它 们在 Si衬底上形成第一导电类型 SiGe层和第一导电类型 Si层， 所述第一导 电类型 Si层用于形成有源区。
步骤三、 在第一导电类型 Si层上涂覆光刻胶， 使其覆盖用于形成沟道的 区域表面， 并由两侧向外延伸覆盖该区域之下的第一导电类型 SiGe层的部分 侧壁， 保护沟道两侧下方的第一导电类型 SiGe层不受刻蚀， 然后利用选择性 刻蚀技术、 例如釆用 600 ~ 800°C的 H2和 HC1混合气体， 利用次常压化学气相 刻蚀法进行选择性刻蚀， 其中 HC1的分压大于 300Torr, 去除位于第一导电类 型 Si层之下的部分第一导电类型 SiGe层形成 SiGe隔层 2, 仅使第一导电类 型 Si层中用于形成源区及漏区的区域下方悬空。
步骤四、 去除光刻胶， 并在 Si衬底上方 SiGe隔层 2和第一导电类型 Si 层周围填充绝缘介质， 使第一导电类型 Si层中用于形成源区及漏区的区域下 方形成绝缘埋层 51, 并在第一导电类型 Si层周围形成浅沟槽隔离结构 52, 填充的绝缘介质可釆用氧化硅或氮化硅等材料。
步骤五、 在第一导电类型 Si 层上制作栅区， 所述栅区包括栅介质层 42 和位于所述栅介质层 42上的栅电极 41,栅介质材料可以为二氧化硅、 氮氧硅 化合物、 或铪基的高介电常数材料等， 栅电极材料可以为钛、 镍、 钽、 钨、 氮化钽、 氮化钨、 氮化钛、 硅化钛、 硅化钨或硅化镍中的一种或其组合。 然 后通过离子注入等掺杂工艺在第一导电类型 Si层中形成第二导电类型的源区 32及漏区 33, 此时， 可通过离子注入先进行源区轻掺杂 （LDS) 、 漏区轻掺 杂 （LDD) 以及晕环注入 (Halo) , 最后进行源区 32、 漏区 33的第二导电类 型离子注入， 在所述栅区周围还可制作绝缘侧墙隔离结构 43, 其材料可以是 二氧化硅、 氮化硅等， 最终完成 M0S器件的制作。
以该 M0S器件结构为基础的 CMOS器件如图 2g所示。 以下是利用本发明 方法制备该 CMOS器件结构的优选实施例 （请参看图 2a-2g) ：
步骤一、 在 Si衬底 10上依次外延生长 SiGe层 20和 Si层 30, Si衬底 10为 P型 Si衬底， 如图 2a所示。
步骤二、 刻蚀所述 SiGe层 20和 Si层 30, 并进行离子注入， 使它们在 Si ^"底 10上分别形成 P型 SiGe层 201、 P型 Si层 301和 N型 SiGe层 202、 N型 Si层 302, 如图 2b所示。 其中 P型 Si层 301和 N型 Si层 302分别用于 形成 NM0S和 PM0S的有源区。
步骤三、 在 P型 Si层 301和 N型 Si层 302上涂覆光刻胶 40, 使光刻胶 40分别覆盖 P型 Si层 301和 N型 Si层 302用于形成沟道的区域表面， 并由 其两侧向外延伸覆盖该区域之下的 P型 SiGe层 201和 N型 SiGe层 202的部 分侧壁。 然后利用选择性刻蚀技术， 例如釆用 600 ~ 800°C的 H2和 HC1混合气 体， 利用次常压化学气相刻蚀法进行选择性刻蚀， 其中 HC1 的分压大于 300Torr, 去除位于 P型 Si层 301和 N型 Si层 302之下的部分 P型 SiGe层 201和 N型 SiGe层 202形成 P型 SiGe隔层 201， 和 N型 SiGe隔层 202， ，仅 使 P型 Si层 301和 N型 Si层 302中用于形成源区及漏区的区域下方悬空， 如图 2c所示， 去除光刻胶后的俯视示意图如图 2d, L为器件结构沿沟道方向 的长度， W为器件结构宽度。
步骤四、 去除光刻胶 40, 并在 Si衬底 10上方 P型 SiGe隔层 201、 P型 Si层 301和 N型 SiGe隔层 202、 N型 Si层 302周围填充 Si02绝缘介质， 使 P 型 Si层 301和 N型 Si层 302中用于形成源区及漏区的区域下方形成绝缘埋 层 501, 并在 P型 Si层 301和 N型 Si层 302周围形成浅沟槽隔离结构 502。 然后 CMP化学机械抛光表面。
步骤五、 分别在 P型 Si层 301和 N型 Si层 302的沟道上制作栅区， 其 中丽 OS的栅区包括栅介质层 602和位于所述栅介质层 602上的栅电极 601, PM0S的栅区包括栅介质层 604和位于所述栅介质层 604上的栅电极 603。 然 后通过离子注入分别在 P型 Si层 301和 N型 Si层 302中形成源区及漏区， 此时，可先进行源区轻掺杂（LDS)、漏区轻掺杂（LDD)以及晕环注入（Halo), 最后进行源区、 漏区的重掺杂离子注入， 在栅区周围还可制作绝缘侧墙隔离 结构 70。
在该器件结构的基础上， 经后续半导体制造工艺即可得到完整的 CMOS器 件。 该方法制备的 CMOS器件， 可消除浮体效应及自加热效应， 同时减小源漏 区的寄生电容， 并且其制备工艺简单， 易于实施。
本发明中涉及的其他技术属于本领域技术人员熟悉的范畴， 在此不再赘 精神和范围的技术方案均应涵盖在本发明的专利申请范围当中。

Claims

权利要 求书
1. 一种防止浮体及自加热效应的 MOS器件结构， 其特征在于， 包括： Si 衬底、 绝缘埋层、 SiGe隔层、 有源区、 栅区和浅沟槽隔离结构； 所述 有源区位于 Si衬底之上，所述有源区包括沟道以及分别位于沟道两端 的源区和漏区； 所述栅区位于沟道之上； 所述绝缘埋层设置在所述源 区与 Si衬底之间， 以及漏区与 Si衬底之间； 所述 SiGe隔层设置在沟 道与 Si衬底之间； 对于醒 OS 器件， SiGe隔层釆用 P型的 SiGe材料； 对于 PM0S器件， SiGe隔层釆用 N型的 SiGe材料； 所述浅沟槽隔离结 构设置在有源区周围。
2. 根据权利要求 1所述防止浮体及自加热效应的 M0S器件结构， 其特征 在于： 所述栅区周围设有绝缘侧墙隔离结构。
3. 根据权利要求 1所述防止浮体及自加热效应的 M0S器件结构， 其特征 在于： 所述绝缘埋层釆用氧化硅或氮化硅材料。
4. 一种防止浮体及自加热效应的 M0S器件结构的制造方法，其特征在于， 包括以下步骤：
步骤一、 在 Si衬底上依次外延生长 SiGe层和 Si层；
步骤二、 刻蚀所述 SiGe层和 Si层， 并进行掺杂， 使它们在 Si 衬底上形成第一导电类型 SiGe层和第一导电类型 Si层， 所述第一导 电类型 Si层用于形成有源区；
步骤三、在第一导电类型 Si层上涂覆光刻胶，使其覆盖用于形成 沟道的区域表面， 并由两侧向外延伸覆盖该区域之下的第一导电类型 SiGe层的部分侧壁， 然后利用选择性刻蚀技术去除位于第一导电类型 Si层之下的部分第一导电类型 SiGe层以形成 SiGe隔层，使第一导电 类型 Si层中用于形成源区及漏区的区域下方悬空；
步骤四、 去除光刻胶， 并在 Si衬底上方的 SiGe隔层和第一导电 类型 S i层周围填充绝缘介质；
步骤五、在第一导电类型 S i层上制作栅区，并通过掺杂工艺在第 一导电类型 S i层中形成第二导电类型的源区及漏区，完成 MOS器件结 构。
5. 根据权利要求 4所述防止浮体及自加热效应的 M0S器件结构的制造方 法， 其特征在于： 在所述栅区周围制备绝缘侧墙隔离结构。
6. 根据权利要求 4所述防止浮体及自加热效应的 M0S器件结构的制造方 法， 其特征在于： 在步骤五中形成第二导电类型的源区及漏区时， 通 过离子注入先进行源区轻掺杂、 漏区轻掺杂以及晕环注入， 最后进行 源区、 漏区的第二导电类型离子注入。
7. 根据权利要求 4所述防止浮体及自加热效应的 M0S器件结构的制造方 法， 其特征在于： 步骤四填充的绝缘介质釆用氧化硅或氮化硅材料。
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