WO2012100396A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
WO2012100396A1
WO2012100396A1 PCT/CN2011/001310 CN2011001310W WO2012100396A1 WO 2012100396 A1 WO2012100396 A1 WO 2012100396A1 CN 2011001310 W CN2011001310 W CN 2011001310W WO 2012100396 A1 WO2012100396 A1 WO 2012100396A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
source
stress
shallow trench
region
Prior art date
Application number
PCT/CN2011/001310
Other languages
English (en)
French (fr)
Inventor
王桂磊
尹海洲
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US13/320,581 priority Critical patent/US20130037821A1/en
Publication of WO2012100396A1 publication Critical patent/WO2012100396A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Definitions

  • the present invention relates to the field of semiconductor devices, and more particularly to a semiconductor device structure for improving epitaxial edges and a method of fabricating the same.
  • the method of reducing the cost by a single reduced feature size has encountered a bottleneck, especially when the feature size falls below 150 nm, the physical parameters cannot be scaled, such as the silicon forbidden band width Eg, the Fermi potential cp F , Interface state and oxide charge Qox, thermoelectric potential Vt, and pn junction self-construction potential, etc., will affect the performance of the scaled down device.
  • stress is introduced into the MOSFET channel region to improve carrier mobility.
  • the crystal orientation of the channel region is ⁇ 110>, and the stress in the PMOS along the longitudinal axis (in the source-drain direction) needs to be pressure, and the stress along the horizontal axis needs It is tension; in the NMOS, the stress along the longitudinal axis needs to be tension, and the stress along the horizontal axis is pressure. It is also to introduce the tension in the direction of the source (S)-drain (Drain) into the NMOS channel; and the pressure in the S-D direction is introduced into the PMOS channel.
  • a commonly used method of applying compressive stress to a PMOS channel is to epitaxially grow a SiGe stress layer along the S - D direction on the source and drain regions. Since the SiGe lattice constant is greater than Si, the S/D stress layer will be The compressive stress is applied to the inter-channel region, which increases the mobility of the holes and increases the driving current of the PMOS. Similarly, a Si:C stress layer with a lattice constant less than Si grown on the source and drain regions provides tension to the NMOS channel.
  • SiGe epitaxial growth is the slowest on the (111) plane, so epitaxial SiGe has a source-drain strain process integration. Larger edge effects.
  • FIG. 1A is a side cross-sectional view of the device
  • FIG. 1B is a top view of the device, and unless otherwise specified, a certain figure A represents a side cross-sectional view.
  • a picture B represents its corresponding top view.
  • the pad oxide layer or silicon nitride layer 2 is generally rectangular in shape and corresponds to the active region and is surrounded by shallow trenches.
  • the deposition forms shallow trench isolation.
  • the shallow trench formed by etching is filled with an oxide, such as CVD deposition or thermal oxidation to form silicon dioxide, and then the oxide layer is planarized by, for example, chemical mechanical polishing (CMP) until the substrate 1 is exposed, thereby forming a shallow
  • CMP chemical mechanical polishing
  • An STI liner layer (not shown) may also be deposited in the shallow trench prior to filling the oxide, the material shield being oxide or silicon nitride, used as a stress liner layer for subsequent selective epitaxial growth of SiGe or SiC. .
  • a gate stack structure is formed.
  • a gate dielectric layer 4 on the substrate 1 the material of which may be silicon oxide or germanium oxide of a high-k material, etc.
  • a gate electrode layer 5 on the gate dielectric layer 4 which is made of polysilicon or metal
  • the etch forms a gate stack structure; an insulating isolation layer, such as silicon nitride, is deposited over the entire structure and etched leaving the isolation spacers 6 only around the gate stack structure.
  • photolithography forms a source-drain recess, located inside the STI3 and on both sides of the isolation sidewall 6, corresponding to the source-drain regions of the PMOS to be formed later.
  • the SiGe stress layer 7 is epitaxially grown. Since the material of the STI liner layer is different or not similar to the epitaxial layer 7, it cannot be used as a seed layer of the epitaxial layer 7, that is, there is still a lattice mismatch between the epitaxially grown SiGe or SiC layer and the liner layer and STI3. Since SiGe grows the slowest on the (111) plane, the inclined side surface shown in Fig. 5A is formed at the edge of the STI 3, that is, at the interface with the epitaxially grown SiGe, and the side surface is the (111) plane.
  • Figure 5C is a cross-sectional view of the structure of Figure 5 taken along the BB' direction perpendicular to the source drain.
  • a graph C is a cross-sectional view of the corresponding structure along the BB' direction perpendicular to the source drain.
  • silicide is formed on the source and drain regions.
  • a metal of Ni, Ti or Co is deposited, annealed to form a corresponding metal silicide, and the unreacted metal is stripped, i.e., a contact layer 8 is left on the SiGe stress layer 7.
  • the thickness of SiGe is much thinner at the edge of the shallow trench isolation STI, so the stress in the source and drain regions along the longitudinal axis AA, the direction and the horizontal axis BB is reduced; and the silicidation in the edge region
  • the contact layer 8 of the object may contact the silicon region at the bottom, which is likely to increase Junction leakage current. Similar to PMOS, SiC will also be thinner at the STI edge of the NMOS, reducing drive capability.
  • the present invention provides a semiconductor device comprising: a substrate; shallow trench isolation, embedded in the substrate, and forming at least one open region; a channel region located in the open region; a gate dielectric layer and a gate electrode layer over the channel region; source and drain regions on both sides of the channel region, including a stress layer that provides strain to the channel region; There is a liner layer between the trench isolation and the stressed layer.
  • the stress layer comprises epitaxially grown Si 1-x Ge x
  • the stress layer comprises epitaxially grown Si 1-y C y , wherein xy is greater than 0 and less than 1.
  • the village mat layer includes Si 1-x Ge x , Sii -xy Ge x Cy or Si!-yCy, wherein xy is greater than 0 and less than 1, X is in the range of 0.15 to 0.7, and y is in the range of 0.002 to 0.02. .
  • the liner layer has a thickness of from 1 to 20 nm. The stress region is flush with the top of the shallow trench isolation.
  • the present invention also provides a method for fabricating a semiconductor device, comprising: forming a shallow trench in a substrate; selectively epitaxially growing a liner layer in the shallow trench; and in the shallow trench Forming an isolation material on the liner layer to form a shallow trench isolation, the shallow trench isolation surrounding at least one open region; forming a gate stack in the open region; forming source and drain regions on both sides of the gate stack, A source region is formed between the source and drain regions under the gate stack, and the source and drain regions include a stress layer that provides strain to the channel region.
  • the stress layer comprises epitaxially grown Si!-xGex
  • the stress layer comprises epitaxially grown Si! ⁇ Cy, wherein xy is greater than 0 and less than 1.
  • the village mat layer includes Si 1-x Ge x , SinyGexCy or Si!-yCy, wherein xy is greater than 0 and less than 1, X is in the range of 0.15 to 0.7, and y is in the range of 0.002 to 0.02.
  • the liner layer has a thickness of from 1 to 20 nm. Wherein the stress layer is flush with the top of the shallow trench isolation.
  • the insulating material is silicon dioxide.
  • the step of forming the source and drain regions includes etching a source/drain region trench in the substrate, and epitaxially growing the stress layer in the source and drain region trenches.
  • the invention inserts a liner layer which is the same or similar to the material of the source/drain region stress layer between the S TI and the source-drain region stress layer as an epitaxially grown seed layer or nucleation layer, thereby eliminating the
  • the STI edge effect which eliminates the gap between the STI and the stressor layer of the source and drain regions, prevents the stress from being reduced, improves the carrier mobility of the MOS device, and improves the driving capability of the device.
  • Figures 1 through 6 are cross-sectional views showing a step of forming a stress layer of a MOS source and drain region in the prior art; and Figs. 7 through 11 are step sectional views showing the formation of a stress layer of a MOS source and drain region with a pad layer in accordance with the present invention.
  • etching forms shallow trenches.
  • a pad oxide layer 20 is deposited on the substrate 10, and shallow trenches are formed by conventional mask exposure etching.
  • the substrate 10 may be bulk silicon or silicon-on-insulator (SOI), or may be a common semiconductor substrate material such as SiGe, S:, sapphire or the like.
  • the substrate crystal plane is (100), the channel region crystal orientation is ⁇ 110>, and the pad oxide layer 20 is generally rectangular, corresponding to the active region, surrounded by shallow trenches.
  • the pad layer 30 is made of S _ x Ge x , S -x-yGexCy or S -yCy.
  • xy is greater than 0 and less than 1
  • X is preferably in the range of from 0.15 to 0.7
  • y is preferably in the range of from 0.002 to 0.02.
  • the pad layer 30 is preferably Si 1-x Ge x of the same material as the PMOS source/drain region stress layer; for the NMOS, the pad layer 30 is preferably Si of the same material as the NMOS source and drain region stress layer.
  • 1-y C y is preferably Si of the same material as the NMOS source and drain region stress layer.
  • the function of the pad layer 30 is to use the pad layer 30 as a nucleation layer or a seed layer in the subsequent epitaxial growth of the source/drain region stress layer, and completely fill the STI 40 caused by the slow growth of SiGe on the (111) crystal plane.
  • the thickness of the liner layer 30 of the thin layer is, for example, 1 to 20 nm.
  • the deposition forms shallow trench isolation.
  • the pad oxide layer 20 is removed using a hydrofluoric acid wet etch or a fluorine-based gas plasma dry etch.
  • the insulating material is filled in the shallow trench formed by etching, and the insulating material may be an oxide, such as CVD deposition or thermal oxidation to form silicon dioxide, and then planarizing the oxide layer by, for example, chemical mechanical polishing (CMP) until exposed.
  • CMP chemical mechanical polishing
  • the substrate 10 is thereby formed with shallow trench isolation (STI) 40.
  • a gate stack structure is formed.
  • a gate dielectric layer 50 is deposited on the substrate 10, and the material thereof may be silicon oxide or high-k material yttrium oxide or the like;
  • a gate electrode layer 60 is deposited on the gate dielectric layer 50, and the material thereof is polysilicon or metal;
  • the etch forms a gate stack structure;
  • an insulating isolation layer, such as silicon nitride, is deposited over the entire structure and etched leaving only the isolation sidewalls 70 around the gate stack structure.
  • the mask is exposed and anisotropically etched to form source and drain recesses, located inside the STI 40 and on both sides of the isolation sidewall 6, corresponding to the source and drain regions of the PMOS to be formed later.
  • the stress layer 80 is epitaxially grown to serve as a source and drain region of the device, that is, the stress layer 80 also serves as the source and drain regions 80. Since the liner layer 30 shield is similar or identical to the stress layer 80, the potential gap is eliminated during epitaxial growth, that is, the STI edge effect is eliminated, the stress is prevented from being reduced, the carrier mobility is maintained or improved, and the carrier mobility is improved. MOS drive capability.
  • the top surface of the epitaxially grown stressor layer 80 is higher than the top surface of the STI 40 as shown in FIG. 11, preferably, the top surface of the stressor layer 80 is substantially flush with the top surface of the STI 40 to prevent stress.
  • stress layer 80 is preferably Si!_ x Ge x ; for NMOS, stress layer 80 is preferably Wherein xy is greater than 0 and less than 1, x is preferably in the range of from 0.15 to 0.7, and y is preferably in the range of from 0.002 to 0.02.
  • a silicide is formed on the source/drain region stress layer 80.
  • a metal of Ni, Ti or Co is deposited on the epitaxially grown SiGe stress layer 80, annealed to form a corresponding metal silicide, and the unreacted metal is stripped, ie, a contact layer is left on the SiGe stress layer 80 (FIG. 1) Not shown in 1).
  • the resulting device structure is shown in Figure 11: shallow trench isolation (STO 40 is located in substrate 10, STI 40 is surrounded by a semiconductor open region, the channel region of the device is located within the semiconductor open region; gate dielectric layer 50 is on the substrate Above the channel region of 10, the gate electrode layer 60 is on the gate dielectric layer 50, and the gate dielectric layer 50 and the gate electrode layer 60 form a gate stack structure, and the isolation sidewall 70 is located around the gate stack structure; the source and drain regions 80 are also The stress layer 80 is located on both sides of the gate stack structure, and is composed of a material capable of increasing stress.
  • STO 40 shallow trench isolation
  • STI 40 is surrounded by a semiconductor open region, the channel region of the device is located within the semiconductor open region
  • gate dielectric layer 50 is on the substrate Above the channel region of 10
  • the gate electrode layer 60 is on the gate dielectric layer 50, and the gate dielectric layer 50 and the gate electrode layer 60 form a gate stack structure, and the isolation sidewall 70 is located around the gate stack structure
  • the stress layer 80 is preferably Si!-xGex;
  • the stress layer 80 is preferably Si 1-y Cy, wherein xy is greater than 0 and less than 1; the source/drain region 80 or the stress layer 80 and the STI 40 have a liner layer 30, and the material and stress of the liner layer 30
  • the layers 80 are of the same or similar material, for example, Si 1-x Ge x , Si 1-x- yGe x C y or Sii-yC y , wherein xy is greater than 0 and less than 1, and X is preferably in the range of 0.15 to 0.7.
  • y is preferably in the range of 0.002 to 0.02; the top of the stressor layer 80 may also have a metal silicide (not shown). In particular, the top of the stressor layer 80 is flush with the top of the STI 40.
  • the formation process of the PMOS source/drain stress layer 80 is disclosed above, and for the NMOS, it becomes Sil-yCy.
  • the invention inserts a liner layer which is the same or similar to the material of the source/drain region stress layer between the STI and the source-drain region stress layer as an epitaxially grown seed layer or nucleation layer, thereby eliminating the STI edge effect, that is, The gap between the STI and the stressor layer of the source and drain regions is eliminated, the stress is reduced, the carrier mobility of the MOS device is improved, and the driving capability of the device is improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

半导体器件及其制造方法 优先权要求
本申请要求了 201 1年 1月 26日提交的、申请号为 2011 10029212.9、 发明名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体器件领域， 特别是涉及一种改进外延边缘的半 导体器件结构及其制造方法。
背景技术
当前通过单一缩减特征尺寸来降低成本的方法已经遇到了瓶颈， 特别是当特征尺寸降至 150nm以下时， ί艮多物理参数不能按比例变化， 例如硅禁带宽度 Eg、 费米势 cp F、 界面态及氧化层电荷 Qox、 热电势 Vt 以及 pn结自建势等等， 这些将影响按比例缩小的器件性能。
为了进一步改进器件性能，人们将应力引入 MOSFET沟道区， 用来 改善载流子的迁移率。 例如在晶面为 （ 100 ) 的晶片上， 沟道区晶向为 <110>, 在 PMOS中沿着纵轴方向 （沿源漏方向） 的应力需要为压力， 沿着横轴方向的应力需要为张力；而在 NMOS中沿着纵轴方向的应力需 要为张力， 而沿着横轴方向的应力为压力。 也即将沿着源 （Source, 简 称 S ) -漏 （Drain, 简称 D ) 方向的张力引入 NMOS沟道； 而将沿着 S - D方向的压力引入 PMOS沟道。 常用的对 PMOS沟道施加压应力的方 法， 是沿着 S - D方向在源漏区上外延生长出 SiGe应力层， 由于 SiGe晶 格常数大于 Si, 故 S/D的应力层会对于其之间的沟道区施加压应力， 增 大了空穴的迁移率从而增大了 PMOS的驱动电流。 同样， 在源漏区上外 延生长晶格常数小于 Si的 Si:C应力层可对 NMOS沟道提供张力。
但是， 由于 SiGe是在 Si上选择性外延生长的， 不同的晶面具有不同 的外延生长速度， 例如在 （ 111 ) 晶面上 SiGe外延生长最慢， 因此在源 漏应变工艺集成中外延 SiGe具有较大的边缘效应。 图。 、 、 ;'、' 、
首先，如图 1所示，刻蚀形成浅沟槽。附图 1A为器件的側视剖面图， 附图 1B为器件的顶视图， 以下若无特殊说明， 某图 A代表側视剖面图而 某图 B代表其相应的顶视图。 在衬底 1上沉积垫氧化层或氮化硅层 2， 通 过常规的掩模曝光刻蚀形成浅沟槽， 其中， 衬底晶面为 （ 100 ) ， 沟道 区晶向为<110>， 垫氧化层或氮化硅层 2通常为矩形， 与有源区相对应， 被浅沟槽包围。
其次， 如图 2所示， 沉积形成浅沟槽隔离。 在刻蚀形成的浅沟槽中 填充氧化物， 例如 CVD沉积或热氧化法生成二氧化硅， 随后通过例如 化学机械抛光（CMP ) 的方法平坦化氧化物层直至露出衬底 1， 从而形 成浅沟槽隔离 STI 3。 在填充氧化物之前， 还可以在浅沟槽中沉积 STI 衬垫层 （未示出） ， 其材盾为氧化物或氮化硅， 用作后续选择性外延 生长 SiGe或 SiC的应力衬垫层。
再次， 如图 3所示， 形成栅极堆叠结构。 在衬底 1上沉积栅介质层 4， 其材质可为氧化硅或高 k材料的氧化铪等等； 在栅介质层 4上沉积栅电 极层 5 , 其材质为多晶硅或金属； 掩模曝光刻蚀形成栅堆叠结构； 在整 个结构上沉积例如为氮化硅的绝缘隔离层并刻蚀， 只在栅堆叠结构周 围留下隔离侧墙 6。
接着， 如图 4所示， 光刻形成源漏凹槽， 位于 STI3内侧且位于隔离 侧墙 6两侧， 对应于后续要形成的 PMOS的源漏区域。
然后， 如图 5所示， 外延生长 SiGe应力层 7。 由于 STI衬垫层材质与 外延层 7不同或不相近， 不能作为外延层 7的晶种层， 也即外延生长的 SiGe或 SiC层与衬垫层以及 STI3之间仍然存在晶格不匹配。 而由于 SiGe 在 （ 111 ) 面上生长最慢， 因此在 STI3的边缘处也即与外延生长的 SiGe 的界面处会形成图 5A所示的倾斜的側面， 该側面为 （ 111 ) 面。 该侧面 形成的空隙会减小源漏区 S i G e中的压应力， 使得空穴迁移率降低， PMOS驱动能力变弱。 图 5C为图 5结构沿垂直于源漏的 BB'方向的剖面 图， 类似地， 以下若无特别说明， 某图 C即为相应结构沿垂直于源漏的 BB'方向的剖面图。
最后， 如图 6所示， 在源漏区上形成硅化物。 在外延生长的 SiGe应 力层 7上沉积材盾为 Ni、 Ti或 Co的金属，退火以形成相应的金属硅化物， 剥除未反应的金属， 即在 SiGe应力层 7上留下接触层 8。
由图 6可见， SiGe的厚度在浅沟槽隔离 STI边缘处要薄很多， 因此 源漏区中 SiGe沿纵轴 AA，方向以及横轴 BB，方向的应力均降低了； 而在 边缘区域的硅化物的接触层 8可能接触底部的硅区域， 这很可能将增大 结泄漏电流。 与 PMOS类似的， SiC在 NMOS的 STI边缘处也将变薄， 从 而降低了驱动能力。
有鉴于此，需要一种能有效提供应力以增强 CMOS驱动能力且减小 结泄漏电流的新型半导体器件及其制造方法。
发明内容
本发明的目的在于防止半导体器件应力层与浅沟槽隔离之间出现 空隙而使得应力减小。
为此， 本发明提供了一种半导体器件， 包括： 衬底； 浅沟槽隔离， 嵌于所述衬底中， 且形成至少一个开口区； 沟道区， 位于所述开口区 内； 栅堆叠， 包括栅介质层和栅电极层， 位于所述沟道区上方； 源漏 区， 位于所述沟道区的两侧， 包括为所述沟道区提供应变的应力层； 其 中， 所述浅沟槽隔离和所迷应力层之间具有衬垫层。
其中， 对于 pMOSFET, 所述应力层包括外延生长的 Si1-xGex, 对于 nMOSFET, 所述应力层包括外延生长的 Si1-yCy, 其中 xy均大于 0小于 1。 所述村垫层包括 Si1-xGex、 Sii-x-yGexCy或 Si!-yCy, 其中 xy均大于 0小于 1 , X介于 0.15至 0.7范围内， y介于 0.002至 0.02范围内。 所述衬垫层的厚度 为 l-20nm。 所述应力区与所述浅沟槽隔离的顶部齐平。
本发明还提供了一种用于制造半导体器件的方法， 包括： 在衬底 中形成浅沟槽； 在所述浅沟槽中选择性外延生长衬垫层； 在所述浅沟 槽中且在所述衬垫层上形成隔离材料， 构成浅沟槽隔离， 所述浅沟槽 隔离包围至少一个开口区； 在所述开口区内形成栅堆叠； 在所述栅堆 叠两侧形成源漏区， 所述栅堆叠下方的所述源漏区之间形成为沟道区， 所述源漏区包括为所述沟道区提供应变的应力层。
其中， 对于 pMOSFET, 所述应力层包括外延生长的 Si!-xGex, 对于 nMOSFET, 所述应力层包括外延生长的 Si!^Cy, 其中 xy均大于 0小于 1。 所述村垫层包括 Si1-xGex、 SinyGexCy或 Si!-yCy, 其中 xy均大于 0小于 1 , X介于 0.15至 0.7范围内， y介于 0.002至 0.02范围内。 所述衬垫层的厚度 为 l-20nm。 其中， 所述应力层与所述浅沟槽隔离的顶部齐平。 所述隔 离材料为二氧化硅。 形成所述源漏区的步骤包括， 在衬底中刻蚀形成 源漏区沟槽， 在源漏区沟槽中外延生长所述应力层。
本发明在 S TI和源漏区应力层中间插入一个与源漏区应力层材质 相同或相近的衬垫层作为外延生长的晶种层或成核层， 借此而消除了 STI边缘效应， 也即消除了 STI与源漏区应力层之间的空隙， 防止了应 力的减小， 提高了 MOS器件的载流子迁移率从而提高了器件的驱动能 力。
本发明所述目的， 以及在此未列出的其他目的， 在本申请独立权 利要求的范围内得以满足。 本发明的实施例限定在独立权利要求中， 具体特征限定在其从属权利要求中。
附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1至 6为现有技术的形成 MOS源漏区应力层的步骤剖面图； 以及 图 7至为 11依照本发明的形成带衬垫层的 MOS源漏区应力层的步 骤剖面图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果。 需要指出的是， 类似的附图标记表示类似的结 构， 本申请中所用的术语 "笫一"、 "第二" 、 "上" 、 "下" 、 "厚" 、 "薄" 等等可用于修饰各种器件结构。 这些修饰除非特别说明并非暗 示所修饰器件结构的空间、 次序或层级关系。 意图。 、 、 、
首先， 如图 7所示， 刻蚀形成浅沟槽。 在衬底 10上沉积垫氧化层 20, 通过常规的掩模曝光刻蚀形成浅沟槽。 其中， 衬底 10可为体硅或绝缘 体上硅（SOI ) , 也可为 SiGe、 S ：、 蓝宝石等常用的半导体衬底材料。 衬底晶面为 （ 100 ) , 沟道区晶向为 <110>， 垫氧化层 20通常为矩形， 与有源区相对应， 被浅沟槽包围。 以垫氧化层 20为掩模， 在浅沟槽中 选择性外延生长一薄层的衬垫层 30 , 衬垫层 30的材质为 S _xGex、 S -x-yGexCy或 S -yCy, 其中 xy均大于 0小于 1 , X优选为介于 0.15至 0.7范 围内， y优选地介于 0.002至 0.02范围内。 对于 PMOS而言， 衬垫层 30优 选为与 PMOS源漏区应力层同材质的 Si1-xGex; 对于 NMOS而言， 衬垫层 30优选为与 NMOS源漏区应力层同材质的 Si1-yCy。 衬垫层 30的作用是在 后续外延生长源漏区应力层时， 以衬垫层 30为成核层或晶种层， 完全 填充因 SiGe在 （ 111 ) 晶面上生长緩慢而引起的 STI 40与源漏区应力层 之间的空隙。 该薄层的衬垫层 30的厚度例如是 1至 20nm。 其次， 如图 8所示， 沉积形成浅沟槽隔离。 使用氢氟酸湿法刻蚀或 者氟基气体等离子干法刻蚀去除垫氧化层 20。 在刻蚀形成的浅沟槽中 填充隔离材料， 隔离材料可为氧化物， 例如 CVD沉积或热氧化法生成 二氧化硅， 随后通过例如化学机械抛光 （CMP ) 的方法平坦化氧化物 层直至露出衬底 10, 从而形成浅沟槽隔离 （STI ) 40。
再次， 如图 9所示， 形成栅极堆叠结构。 在衬底 10上沉积栅介质层 50, 其材质可为氧化硅或高 k材料的氧化铪等等； 在栅介质层 50上沉积 栅电极层 60, 其材质为多晶硅或金属； 掩模曝光刻蚀形成栅堆叠结构； 在整个结构上沉积例如为氮化硅的绝缘隔离层并刻蚀， 只在栅堆叠结 构周围留下隔离側墙 70。
接着， 如图 10所示， 掩模曝光并各向异性地刻蚀形成源漏凹槽， 位于 STI40内侧且位于隔离側墙 6两側，对应于后续要形成的 PMOS的源 漏区域。
然后， 如图 11所示， 外延生长应力层 80， 以作为器件的源漏区， 也即应力层 80也作为源漏区 80。 由于衬垫层 30材盾与应力层 80相近或 相同， 外延生长时消除了可能存在的空隙也即消除了 STI边缘效应， 防 止了应力减小， 保持或提高了载流子迁移率， 提高了 MOS驱动能力。 特别地， 外延生长的应力层 80的顶面虽然如图 1 1所示比 STI40的顶面要 高， 但是， 优选地， 应力层 80的顶面与 STI40的顶面大致齐平， 以防止 应力从应力层 80高于 STI40的地方泄漏而减小了实际施加的应力， 从而 防止了驱动能力降低。 对于 PMOS而言， 应力层 80优选为 Si!_xGex; 对 于 NMOS而言， 应力层 80优选为
Figure imgf000007_0001
其中 xy均大于 0小于 1 , x优选 为介于 0.15至 0.7范围内， y优选地介于 0.002至 0.02范围内。
最后， 在源漏区应力层 80上形成硅化物。 在外延生长的 SiGe应力 层 80上沉积材质为 Ni、 Ti或 Co的金属， 退火以形成相应的金属硅化物， 剥除未反应的金属，即在 SiGe应力层 80上留下接触层（图 1 1中未示出）。
最后形成的器件结构如图 11所示： 浅沟槽隔离 （STO 40位于衬底 10中， STI40包围有半导体开口区， 器件的沟道区位于该半导体开口区 内； 栅介质层 50位于衬底 10的沟道区上方， 栅电极层 60位于栅介质层 50上， 栅介质层 50与栅电极层 60构成栅极堆叠结构， 隔离侧墙 70位于 栅极堆叠结构周围； 源漏区 80也即应力层 80位于栅极堆叠结构两侧， 由能增加应力的材料构成， 对于 PMOS而言， 应力层 80优选为 Si!-xGex; 对于 NMOS而言， 应力层 80优选为 Si1-yCy， 其中 xy均大于 0小于 1 ; 源漏 区 80或应力层 80与 STI40之间具有衬垫层 30, 衬垫层 30的材质与应力层 80材质相同或相近， 例如为 Si1-xGex、 Si1-x-yGexCy或 Sii-yCy, 其中 xy均大 于 0小于 1 , X优选为介于 0.15至 0.7范围内， y优选地介于 0.002至 0.02范 围内； 应力层 80顶部还可具有金属硅化物 （未示出） 。 特别地， 应力 层 80顶部与 STI40的顶部齐平。
以上公开了 PMOS源漏区应力层 80的形成工艺， 对于 NMOS而言， 而变为 Sil-yCy。
本发明在 STI和源漏区应力层中间插入一个与源漏区应力层材质 相同或相近的衬垫层作为外延生长的晶种层或成核层， 借此而消除了 STI边缘效应， 也即消除了 STI与源漏区应力层之间的空隙， 防止了应 力的减小， 提高了 MOS器件的载流子迁移率从而提高了器件的驱动能 力。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员 可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适 的改变和等价方式。 此外， 由所公开的教导可做出许多可能适于特定 情形或材料的修改而不脱离本发明范围。 因此， 本发明的目的不在于 限定在作为用于实现本发明的最佳实施方式而公开的特定实施例， 而 所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施 例。

Claims

权 利 要 求
1. 一种半导体器件， 包括：
衬底；
浅沟槽隔离， 嵌于所述衬底中， 且形成至少一个开口区；
沟道区， 位于所述开口区内；
栅堆叠， 包括栅介质层和栅电极层， 位于所述沟道区上方； 源漏区，位于所述沟道区的两側， 包括为所述沟道区提供应变的应 力层；
其中， 所述浅沟槽隔离和所述应力层之间具有衬垫层， 作为所述 应力层的晶种层。
2. 如权利要求 1所述的半导体器件， 其中， 对于 pMOSFET, 所述 应力层包括外延生长的
Figure imgf000009_0001
对于 nMOSFET, 所述应力层包括外延 生长的 S^yCy, 其中 xy均大于 0小于 1。
3.如权利要求 1所述的半导体器件，其中，所述衬垫层包括 Si^Ge^ Si1-x-yGexCy或 S -yCy, 其中 xy均大于 0小于 1。
4. 如权利要求 3所述的半导体器件， 其中， X介于 0.15至 0.7范围内， y介于 0.002至 0.02范围内。
5.如权利要求 1所述的半导体器件， 其中， 所述衬垫层的厚度为 1-20亂
6. 如权利要求 1所述的半导体器件， 其中， 所述应力区与所述浅 沟槽隔离的顶部齐平。
7. 一种方法， 用于制造如权利要求 1所述的半导体器件， 包括： 在衬底中形成浅沟槽；
在所述浅沟槽中选择性外延生长衬垫层， 作为应力层的晶种层； 在所述浅沟槽中且在所述衬垫层上形成隔离材料， 构成浅沟槽隔 离， 所述浅沟槽隔离包围至少一个开口区；
在所述开口区内形成栅堆叠；
在所述栅堆叠两側形成源漏区， 所述栅堆叠下方的所述源漏区之 间形成为沟道区， 所述源漏区包括为所述沟道区提供应变的应力层。
8. 如权利要求 7所述的方法， 其中， 对于 pMOSFET, 所迷应力层 包括外延生长的 S -xGex, 对于 nMOSFET, 所述应力层包括外延生长的 Sii.yCy, 其中 xy均大于 0小于 1。
9.如权利要求 7所述的方法， 其中， 所述衬垫层包括 Si^Ge^ Si1-x_yGexCy或 Si1-yCy, 其中 xy均大于 0小于 1。
10. 如权利要求 9所述的方法， 其中， X介于 0.15至 0.7范围内， y介 于 0.002至 0.02范围内。
11.如权利要求 7所述的方法， 其中， 所述衬垫层的厚度为 l-20nm。
12. 如权利要求 7所述的方法， 其中， 所述应力层与所述浅沟槽隔 离的顶部齐平。
13. 如权利要求 7所述的方法， 其中， 所述隔离材料为二氧化硅。
14. 如权利要求 7所述的方法， 其中， 形成所迷源漏区的步骤包括， 在衬底中刻蚀形成源漏区沟槽， 在源漏区沟槽中外延生长所述应力层。
PCT/CN2011/001310 2011-01-26 2011-08-09 半导体器件及其制造方法 WO2012100396A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/320,581 US20130037821A1 (en) 2011-01-26 2011-08-09 Semiconductor Device and Manufacturing Method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110029212.9 2011-01-26
CN201110029212.9A CN102623487B (zh) 2011-01-26 2011-01-26 半导体器件及其制造方法

Publications (1)

Publication Number Publication Date
WO2012100396A1 true WO2012100396A1 (zh) 2012-08-02

Family

ID=46563293

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/001310 WO2012100396A1 (zh) 2011-01-26 2011-08-09 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US20130037821A1 (zh)
CN (1) CN102623487B (zh)
WO (1) WO2012100396A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594374B (zh) * 2012-08-17 2017-03-08 中国科学院微电子研究所 半导体器件制造方法
CN103779222A (zh) * 2012-10-23 2014-05-07 中国科学院微电子研究所 Mosfet的制造方法
CN103779223B (zh) * 2012-10-23 2016-07-06 中国科学院微电子研究所 Mosfet的制造方法
US10134895B2 (en) 2012-12-03 2018-11-20 Stmicroelectronics, Inc. Facet-free strained silicon transistor
CN104103570B (zh) * 2013-04-11 2018-11-06 中国科学院微电子研究所 增强浅沟槽隔离应力的方法
US9136330B2 (en) * 2013-07-22 2015-09-15 GlobalFoundries, Inc. Shallow trench isolation
CN104425379A (zh) * 2013-09-04 2015-03-18 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN105261567B (zh) * 2015-10-27 2018-11-09 上海华力微电子有限公司 嵌入式外延锗硅层的盖帽层的制作方法
CN107516635B (zh) * 2016-06-15 2021-05-04 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN109786337B (zh) * 2017-11-13 2020-09-08 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070235770A1 (en) * 2006-04-07 2007-10-11 Shyh-Fann Ting Semiconductor structure and fabricating method thereof
US20080157200A1 (en) * 2006-12-27 2008-07-03 International Business Machines Corporation Stress liner surrounded facetless embedded stressor mosfet
CN101425534A (zh) * 2007-10-31 2009-05-06 周星工程股份有限公司 晶体管及其制造方法
JP2010010403A (ja) * 2008-06-27 2010-01-14 Sony Corp 半導体装置およびその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6855963B1 (en) * 2003-08-29 2005-02-15 International Business Machines Corporation Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate
US7569434B2 (en) * 2006-01-19 2009-08-04 International Business Machines Corporation PFETs and methods of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070235770A1 (en) * 2006-04-07 2007-10-11 Shyh-Fann Ting Semiconductor structure and fabricating method thereof
US20080157200A1 (en) * 2006-12-27 2008-07-03 International Business Machines Corporation Stress liner surrounded facetless embedded stressor mosfet
CN101425534A (zh) * 2007-10-31 2009-05-06 周星工程股份有限公司 晶体管及其制造方法
JP2010010403A (ja) * 2008-06-27 2010-01-14 Sony Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
CN102623487B (zh) 2015-04-08
CN102623487A (zh) 2012-08-01
US20130037821A1 (en) 2013-02-14

Similar Documents

Publication Publication Date Title
US10693003B2 (en) Integrated circuit transistor structure with high germanium concentration SiGe stressor
US11393727B2 (en) Structure and formation method of fin-like field effect transistor
US9647118B2 (en) Device having EPI film in substrate trench
JP5291736B2 (ja) フィン型ｆｅｔを有する半導体装置およびその製造方法
WO2012100396A1 (zh) 半导体器件及其制造方法
US10037921B2 (en) Structure and formation method of fin-like field effect transistor
US8659091B2 (en) Embedded stressors for multigate transistor devices
TWI440097B (zh) 應力增強之ｍｏｓ電晶體及其製造方法
US7439110B2 (en) Strained HOT (hybrid orientation technology) MOSFETs
WO2012174694A1 (zh) 半导体器件及其制造方法
JP6786755B2 (ja) 異なる歪み状態を有するフィン構造を含む半導体構造を作製するための方法及び関連する半導体構造
US20080303062A1 (en) Semiconductor device with strain in channel region and its manufacture method
WO2013143035A1 (zh) 使源/漏区更接近沟道区的mos器件及其制作方法
WO2014015450A1 (zh) 半导体器件及其制造方法
US20130285118A1 (en) CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION
US20150364580A1 (en) Structure and formation method of fin-like field effect transistor
WO2013177725A1 (zh) 半导体器件及其制造方法
US20130313655A1 (en) Semiconductor device and a method for manufacturing the same
US8441045B2 (en) Semiconductor device and method for manufacturing the same
WO2012027864A1 (zh) 半导体结构及其制造方法
WO2013174070A1 (zh) 半导体器件及其制造方法
WO2012174696A1 (zh) 半导体器件及其制造方法
CN105702723B (zh) 晶体管及其形成方法
US10600890B2 (en) Contact to metal gate isolation structure

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13320581

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11857222

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11857222

Country of ref document: EP

Kind code of ref document: A1