US20070235770A1 - Semiconductor structure and fabricating method thereof - Google Patents
Semiconductor structure and fabricating method thereof Download PDFInfo
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- US20070235770A1 US20070235770A1 US11/399,827 US39982706A US2007235770A1 US 20070235770 A1 US20070235770 A1 US 20070235770A1 US 39982706 A US39982706 A US 39982706A US 2007235770 A1 US2007235770 A1 US 2007235770A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title description 36
- 239000000758 substrate Substances 0.000 claims abstract description 53
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 55
- 229910052710 silicon Inorganic materials 0.000 claims description 55
- 239000010703 silicon Substances 0.000 claims description 55
- 239000002184 metal Substances 0.000 claims description 25
- 229910021332 silicide Inorganic materials 0.000 claims description 25
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 25
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 9
- 238000009826 distribution Methods 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 description 16
- 238000005530 etching Methods 0.000 description 11
- 125000006850 spacer group Chemical group 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- 229910052799 carbon Inorganic materials 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000003247 decreasing effect Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 2
- 229910052986 germanium hydride Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 229910016006 MoSi Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 229910021140 PdSi Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910008812 WSi Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Definitions
- the present invention relates to a semiconductor structure and fabrication of the same. More particularly, the present invention relates to a semiconductor structure having a doped strained layer as a source/drain and a method for fabricating the same.
- MOS transistors are essential to VLSI and ULSI circuits, and are widely used in microprocessors, semiconductor memory devices and power devices, etc., as basic constituent units.
- the speed of a MOS transistor is increased by forming an opening in the substrate beside the gate structure and then filling the opening with a doped strained material as a source/drain (S/D) region to increase the carrier mobility of the S/D region.
- S/D source/drain
- FIGS. 1A-1B illustrate a process flow of fabricating a prior-art MOS transistor in a cross-sectional view.
- a substrate 100 with a well 101 therein is provided, and then a gate structure 102 including gate dielectric 104 and a gate 106 is formed on the well 101 .
- a spacer 108 is formed on the sidewall of the gate structure 102 , and then etching is conducted with the gate structure 102 and the spacer 108 as a mask to remove a portion of the exposed substrate 100 and form an opening 110 .
- a doped strained layer 112 is formed in the opening 110 to serve as an S/D region, wherein a portion 103 of the doped strained layer 112 is above the surface of the substrate 100 .
- a (self-aligned silicide) salicide layer 114 is then formed on the gate structure 102 and the doped strained layer 112 .
- the stress caused by the salicide layer 114 is decreased.
- the MOS transistor is PMOS, for example, to increase the compressive stress in the strained layer 112 , a SiGe layer with a Ge-content higher than 20% is formed as the strained layer 112 , or the thickness of the same is increased by increasing the depth of the opening 100 .
- the thickness of a strained SiGe layer decreases with increase in the Ge-content thereof. Moreover, when the Ge-content is higher, the cell parameter of the SiGe layer is larger making the difference between the cell parameter of the SiGe layer and that of the substrate larger, so that defects easily occur at the interface of the SiGe layer and the substrate lowering the device performance. Furthermore, in a subsequent salicide process, the Ge-atoms will enter the metal silicide layer degrading its quality.
- this invention provides a semiconductor structure that includes a doped strained layer with a non-uniform cell parameter distribution as an S/D region for decreasing the difference between the cell sizes of the S/D region and the substrate and thereby prevents defects from occurring at the interface of the two.
- the semiconductor structure includes a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type.
- the first MOS transistor is disposed on the second well, including a first gate structure on the second well and a first strained layer of the first conductivity type in a first opening in the second well beside the first gate structure.
- the difference between the cell parameter of a portion of the first strained layer near the bottom of the first opening and the cell parameter of the substrate is smaller than the difference between the cell parameter of a portion of the first strained layer apart from the bottom of the first opening and the cell parameter of the substrate.
- the second MOS transistor is on the first well.
- the cell parameter of the first strained layer has a gradient distribution.
- the cell parameter of a portion of the first strained layer near the bottom of the first opening is smaller than that of a portion of the first strained layer apart from the bottom of the first opening.
- the material of such a first strained layer may be SiGe.
- the cell parameter of a portion of the first strained layer near the bottom of the first opening is larger than that of a portion of the first strained layer apart from the bottom of the first opening.
- the material of such a first strained layer may be SiC.
- the above second MOS transistor includes a second gate structure on the first well and an S/D region of the second conductivity type in the first well beside the second gate structure.
- the above semiconductor structure may further include a silicon layer on the first strained layer and a metal silicide layer on the silicon layer, the S/D region and the first and the second gate structures.
- the above second MOS transistor includes a second gate structure on the first well and an S/D region of the second conductivity type around and under a second opening in the first well beside the second gate structure.
- the above semiconductor structure may also include a silicon layer on the first strained layer and a metal silicide layer on the silicon layer, the S/D region and the two gate structures.
- the above second MOS transistor includes a second gate structure on the first well and a second strained layer of the second conductivity type in a second opening in the first well beside the second gate structure.
- the difference between the cell parameter of a portion of the second strained layer near the bottom of the second opening and the cell parameter of the substrate is smaller than the difference between the cell parameter of a portion of the second strained layer apart from the bottom of the second opening and the cell parameter of the substrate.
- the cell parameter of a portion of the first strained layer near the bottom of the first opening is smaller than that of a portion of the first strained layer apart from the bottom of the first opening, but the cell parameter of a portion of the second strained layer near the bottom of the second opening is larger than that of a portion of the second strained layer apart from the bottom of the second opening.
- the cell parameter of a portion of the first strained layer near the bottom of the first opening is larger than that of a portion of the first strained layer apart from the bottom of the first opening, but the cell parameter of a portion of the second strained layer near the bottom of the second opening is smaller than that of a portion of the second strained layer apart from the bottom of the second opening.
- the cell parameter of the second strained layer may also have a gradient distribution.
- the semiconductor structure may further include a silicon layer on the first strained layer and the second strained layer, and a metal silicide layer on the silicon layer and the first and the second gate structures.
- the method for fabricating a semiconductor structure of this invention is described as follows.
- a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type is provided, and then a first gate structure is formed on the second well.
- a portion of the substrate beside the first gate structure is removed to form a first opening, and then a first epitaxy process is performed with a first mixed gas to form in the first opening a first strained layer containing silicon and a first IV-group element.
- the first mixed gas includes a first gas containing silicon and a second gas containing the first IV-group element, and the percentage of the second gas in the first mixed gas is increased with time during the first epitaxy process.
- a MOS transistor of the second conductivity type is formed on the first well.
- the atomic size of the first IV-group element is larger than that of silicon increasing the cell parameter, so that the first strained layer of P-type is subject to a compressive stress raising the hole mobility.
- the first IV-group element is carbon that has an atomic size smaller than that of silicon decreasing the cell parameter, so that the first strained layer of N-type is subject to a tensile stress raising the electron mobility.
- the first mixed gas further includes a first doping gas so that the first strained layer is formed having the first conductivity type.
- the MOS transistor of the second conductivity type may be formed by forming a second gate structure on the first well and then forming an S/D region of the second conductivity type in the first well beside the second gate structure.
- a silicon layer may be further formed on the first strained layer, and then a metal silicide layer may be formed on the silicon layer, the S/D region and the first and the second gate structures.
- the MOS transistor of the second conductivity type may be formed with the following steps.
- a second gate structure is formed on the first well, a portion of the substrate beside the second gate structure is removed to form a second opening, and then an S/D region of the second conductivity type is formed in the first well around and under the second opening.
- a silicon layer may be further formed on the first strained layer, and then a metal silicide layer may be formed on the silicon layer, the S/D region and the first and the second gate structures.
- the MOS transistor is formed with the following steps.
- a second gate structure is formed on the first well, a portion of the substrate beside the second gate structure is removed to form a second opening, and then a second epitaxy process is performed with a second mixed gas to form in the second opening a second strained layer containing silicon and a second IV-group element.
- the second mixed gas includes the first gas containing silicon and a third gas containing the second IV-group element, and the percentage of the third gas in the second mixed gas is increased with time during the second epitaxy process.
- the atomic size of the first IV-group element is larger than that of silicon but the second IV-group element is carbon that has an atomic size smaller than that of silicon.
- the first IV-group element is carbon that has an atomic size smaller than that of silicon but the atomic size of the second IV-group element is larger than that of silicon.
- the second mixed gas further includes a second doping gas so that the second strained layer is formed having the second conductivity type.
- a silicon layer may be further formed on the first strained layer and the second strained layer, and then a metal silicide layer may be formed on the silicon layer and the first and the second gate structures.
- the percentage of the gas containing the non-silicon IV-group element in the mixed gas is increased with time.
- the difference between the cell size of a portion of the strained layer near the bottom of the opening and the cell size of the substrate is smaller than the difference between the cell size of a portion of the strained layer apart from the bottom of the opening and the cell size of the substrate.
- the non-silicon IV-group element does not enter the metal silicide layer in the salicide process, so that the quality of the metal silicide layer is not degraded.
- FIGS. 1A-1B illustrate a process flow of fabricating a prior-art MOS transistor in a cross-sectional view.
- FIG. 2 illustrates a cross-sectional view of a semiconductor structure according to an embodiment of this invention.
- FIGS. 3A-3C illustrate, in a cross-sectional view, a process flow of fabricating the MOS transistor 202 in FIG. 2 according to an embodiment of this invention.
- FIG. 4 illustrates a cross-sectional view of a semiconductor structure according to another embodiment of this invention.
- FIG. 5 illustrates a cross-sectional view of a semiconductor structure according to still another embodiment of this invention.
- the semiconductor structure of this embodiment includes a substrate 200 , a MOS transistor 202 of a first conductivity type, a MOS transistor 204 of a second conductivity type and an isolation structure 206 .
- the substrate 200 has a well 208 of the first conductivity type and a well 210 of the second conductivity type therein.
- the MOS transistor 202 is disposed on the well 210 , including a gate structure 212 on the well 210 and a doped strained layer 216 of the first conductivity type.
- the gate structure 212 includes a gate 212 a on the substrate 200 , gate dielectric 212 b between the gate 212 a and the substrate 200 and a spacer 212 c on the sidewall of the gate 212 a , and an opening 214 is formed in the well 210 beside the gate structure 212 .
- the gate 212 a may include poly-Si or metal
- the gate dielectric 212 b may include SiO, SiN or SiON
- the spacer 212 c may include SiN.
- the strained layer 216 is disposed in the opening 214 serving as a part of the S/D region of the MOS transistor 202 , wherein the difference between the cell parameter of a portion of the strained layer 216 near the bottom of the opening 214 and the cell parameter of the substrate 200 is smaller than the difference between the cell parameter of a portion of the strained layer 216 apart from the bottom of the opening 214 and the cell parameter of the substrate 200 . It is more preferred that the cell parameter of the strained layer 216 has a gradient distribution.
- the strained layer 216 is a compressively strained layer, wherein a portion of the strained layer 216 near the bottom of the opening 214 has a cell parameter equal to or larger than that of the substrate 200 but smaller than that of a portion of the strained layer 216 apart from the bottom of the opening 214 .
- the strained layer 216 is a tensily strained layer, wherein a portion of the strained layer 216 near the bottom of the opening 214 has a cell parameter equal to or smaller than that of the substrate 200 but larger than that of a portion of the strained layer 216 apart from the bottom of the opening 214 .
- the MOS transistor 202 also includes a doped region 217 of the first conductivity type under and around the opening 214 as another part of its S/D region, and an S/D extension region 219 of the first conductivity type in the well 210 under the spacer 212 c.
- the MOS transistor 204 is disposed on the well 208 .
- the isolation structure 206 is disposed in the substrate 200 to define the active areas of the devices, and may be an STI structure or other type of isolation structure.
- the MOS transistor 204 includes a gate structure 218 and a doped strained layer 222 of the second conductivity type.
- the gate structure 218 is disposed on the well 208 , and an opening 220 is formed in the well 208 beside the gate structure 218 .
- the gate structure 218 includes gate dielectric 218 b , a gate 218 a on the gate dielectric 218 b and a spacer 218 c on the sidewall of the gate 218 a , wherein possible materials of 218 a , 218 b and 218 c are the same as above.
- the strained layer 222 is disposed in the opening 220 serving as a part of the S/D of the MOS transistor 204 .
- the difference between the cell parameter of a portion of the strained layer 222 near the bottom of the opening 220 and the cell parameter of the substrate 200 is smaller than the difference between the cell parameter of a portion of the strained layer 222 apart from the bottom of the opening 220 and the cell parameter of the substrate 200 .
- the cell parameter of the strained layer 222 changes reversely with respect to that of the strained layer 216 .
- the strained layer 216 is a compressively strained layer with the cell parameter increasing toward its top, while the strained layer 222 is a tensily strained layer with the cell parameter decreasing toward its top.
- the strained layer 216 is a tensily strained layer just mentioned, while the strained layer 222 is a compressively strained layer just mentioned.
- the MOS transistor 204 also includes a doped region 223 of the second conductivity type under and around the opening 220 as another part of the S/D region of the MOS transistor 204 , and an S/D extension region 225 of the second conductivity type in the well 208 under the spacer 218 c.
- the compressively strained layer 216 may include SiGe that is larger in cell parameter relative to pure silicon, while the tensily strained layer 222 may include SiC that is smaller in cell parameter relative to pure silicon.
- the first conductivity type is N-type and the second one P-type
- the tensily strained layer 216 may include SiC
- the compressively strained layer 222 may include SiGe.
- two silicon layers 224 a and 224 b with corresponding conductivity types may be disposed respectively, and a metal silicide layer 226 may further be disposed on the silicon layers 224 a and 224 b and the gate structures 212 and 218 .
- the thickness of the silicon layer 224 a or 224 b may range from 100 ⁇ to 500 ⁇ .
- the material of the metal silicide layer 226 may be WSi, TiSi, MoSi, NiSi, PdSi or PtSi.
- contact etching stop layers 228 a and 228 b may further be disposed over the substrate 200 covering the resulting structure.
- the material of the contact etching stop layer 228 a or 228 b may be SiN, and the contact etching stop layer 228 a / 228 b may be a compressive or tensile layer for increasing the carrier mobility in the channel layer of the MOS transistor 202 / 204 and thereby further improves the performance of the MOS transistor 202 / 204 .
- FIG. 2 An example of fabricating the semiconductor structure in FIG. 2 is described as follows. Since the left half and the right half of the semiconductor structure is similar in structure, the fabricating process of the left half is described firstly.
- FIGS. 3A-3C illustrate, in a cross-sectional view, a process flow of fabricating the MOS transistor 202 in FIG. 2 .
- a substrate 200 is provided, having therein a well of the first conductivity type (not shown), a well 210 of the second conductivity type and an isolation structure 206 defining the active areas of the devices.
- the wells can be formed through ion implantation, and the isolation structure 206 may be formed through an STI process.
- a gate 212 a and gate dielectric 212 b are formed on the well 210 , possibly by forming a layer of gate dielectric material and a gate material layer on the substrate 200 and then sequentially patterning the two layers.
- a doped region 211 of the first conductivity type is formed in the well 210 beside the gate 212 a , possibly through an ion implantation with the gate 212 a as a mask.
- a spacer 212 c is formed on the sidewall of the gate 212 a , constituting a gate structure 212 together with the gate 212 a and gate dielectric 212 b.
- a portion of the substrate 200 beside the gate structure 212 is removed to form an opening 214 , while a portion of the doped region 211 is removed to form an S/D extension region 219 .
- the opening 214 may be formed with the following steps.
- a patterned photoresist layer (not shown) is formed over the substrate 200 , exposing the gate structure 212 and the region for forming the opening 214 .
- An etching process is conducted with the gate structure 212 and the patterned photoresist layer as a mask to remove a portion of the substrate 200 , wherein the etching may be isotropic, anisotropic or tilted etching.
- the depth of the opening 214 is usually 100-1000 ⁇ , preferably 300-500 ⁇ .
- ion implantation is conducted with the gate structure 212 as a mask to implant a dopant of the first conductivity type into a portion of the substrate 200 under and around the opening 214 to form a doped region 217 as a part of the S/D region of the MOS transistor 202 .
- the above ion implantation can alternatively be conducted before the opening 214 is formed, wherein the depth of the opening 214 has to be controlled smaller than that of the implantation.
- a first epitaxy process is conducted with a first mixed gas to form a strained layer 216 in the opening 214 , wherein the first mixed gas includes a first gas containing silicon and a second gas containing a first IV-group element and the percentage of the second gas in the first mixed gas is increased with time during the first epitaxy process.
- the first gas is, for example, silane or disilane.
- the first mixed gas preferably further includes a first doping gas so that the strained layer 216 is formed having the first conductivity type.
- the first IV-group element is one having an atomic size larger than that of silicon, such as Ge, so that the cell parameter is increased and a compressively strained layer 216 is formed with improved hole mobility.
- the IV-group element is carbon that is smaller than silicon in atomic size, so that the cell parameter is decreased and a tensily strained layer 216 is formed with improved electron mobility.
- the fabricating process of the MOS transistor 204 is analogous to that of the MOS transistor 202 .
- the main differences are that the MOS transistor 204 has an opposite conductivity type and the strained layer 222 thereof is formed with a second epitaxy process that uses a second mixed gas that includes the first gas containing Si and a third gas containing a second IV-group element.
- the second mixed gas may further include a second doping gas, so that the strained layer 222 is formed having the second conductivity type.
- the atomic size of the first IV-group element is larger than that of silicon to result in a larger cell parameter, while the second IV-group element is carbon that has an atomic size smaller than that of silicon to result in a smaller cell parameter.
- the first conductivity type is N-type and the second one P-type
- the first IV-group element is carbon
- the atomic size of the second IV-group element is larger than that of silicon.
- the second gas when the first conductivity type is P-type and the second one N-type, the second gas may be GeH 4 , and the second gas in the first mixed gas may be increased from 0 to 40% with time during the first epitaxy process, while the first doping gas may be B 2 H 6 .
- the third gas may be CH 4 or C 2 H 6 , and the third gas in the second mixed gas may be increased from 0 to 20% with time during the second epitaxy process, while the second doping gas may be PH 3 .
- the second gas when the first conductivity type is N-type and the second one P-type, the second gas may be CH 4 or C 2 H 6 , and the second gas in the first mixed gas may be increased from 0 to 20% with time during the first epitaxy process, while the first doping gas may be PH 3 .
- the third gas may be GeH 4 , and the third gas in the second mixed gas may be increased from 0 to 40% with time during the second epitaxy process, while the second doping gas may be B 2 H 6 .
- MOS transistors 202 and 204 are not restricted to form in two separate processes.
- the fabricating process of the MOS transistor 202 is usually integrated more or less with that of the MOS transistor 204 for step simplification.
- a silicon layer 224 a (or 224 b ) of the same conductivity type may be further formed on the strained layer 216 (or 222 ), as shown in FIG. 2 .
- the silicon layer 224 a (or 224 b ) may be formed directly in the first (or second) epitaxy process by stopping supplying the second (or third) gas after the strained layer 216 (or 222 ) is formed but continuing to supply the Si-containing first gas and the First (or second) doping gas for epitaxy.
- a metal silicide layer 226 can be further formed, possibly through a salicide process, on the silicon layers 224 a and 224 b and the gate structures 212 and 218 , as shown in FIG. 2 .
- contact etching stop layers 228 a and 228 b may be formed over the substrate 200 covering the resulting structure, as shown in FIG. 2 , possibly through chemical vapor deposition (CVD).
- MOS transistor 202 of the first conductivity type having a strained S/D region of non-uniform cell parameter is not restricted to form together with a MOS transistor of the second conductivity type also having a strained S/D region of non-uniform cell parameter.
- the MOS transistor 202 may alternatively be formed together with a structurally different MOS transistor of the second conductivity type. Such examples are described in the following embodiments.
- FIG. 4 illustrates a cross-sectional view of a semiconductor structure according to another embodiment of this invention.
- the MOS transistor 204 ′ in replacement of the MOS transistor 204 includes a gate structure 218 as mentioned above and an S/D region 227 in the well 208 beside the gate structure 218 .
- the MOS transistor 204 ′ also includes an SID extension region 225 of the second conductivity type in the well 208 under the spacer 218 c .
- the strained layer 216 may also be formed with a silicon layer 224 thereon, and then a metal silicide layer 226 may be further formed on the silicon layer 224 , the S/D region 227 and the gate structures 212 and 218 .
- the thickness of the silicon layer 224 and the material of the metal silicide layer 226 may be the same as above.
- two contact etching stop layers 228 a and 228 b such as SiN layers formed with different recipes to have different stresses, can be formed over the substrate 200 covering the MOS transistors 202 and 204 ′.
- the MOS transistor 204 ′ may be formed by forming a gate structure 218 on the well 208 and then forming, possibly through an ion implantation process using the gate structure 218 as a mask, an S/D region 227 of the second conductivity type in the well 208 beside the gate structure 218 .
- FIG. 5 illustrates a cross-sectional view of a semiconductor structure according to yet another embodiment of this invention.
- the MOS transistor 204 ′′ in replacement of the MOS transistor 204 includes a gate structure 218 as mentioned above and an S/D region 229 in the well 208 under and around an opening 231 beside the gate structure 218 .
- the transistor 204 ′′ also includes an S/D extension region 225 of the second conductivity type in the well 208 under the spacer 218 c .
- the strained layer 216 may similarly be formed with a silicon layer 224 thereon, and then a metal silicide layer 226 may be further formed on the silicon layer 224 , the S/D region 229 and the gate structures 212 and 218 .
- the thickness of the silicon layer 224 and the material of the metal silicide layer 226 may be the same as above.
- contact etching stop layers 228 a and 228 b as mentioned above may be further formed over the substrate 200 covering the MOS transistors 202 and 204 ′′, respectively.
- the contact etching stop layer 228 b preferably has a thickness at least sufficient to fill up the opening 231 to apply a sufficient large stress to the channel layer of the MOS transistor 204 ′′ and effectively increase the carrier mobility in the channel layer thereby.
- the MOS transistor 204 ′′ may be formed with the following steps.
- a gate structure 218 is formed on the well 208 , a portion of the substrate 200 beside the gate structure 218 is removed to form an opening 231 , and then an S/D region 229 of the second conductivity type is formed in the well 208 under and around the opening 231 , possibly with an ion implantation process using the gate structure 218 as a mask.
- MOS transistors 202 and 204 ′ are either not restricted to form in two separate processes.
- the fabricating process of the MOS transistor 202 is usually integrated more or less with that of the MOS transistor 204 ′ (or 204 ′′) for step simplification.
- the MOS transistor 202 with a strained S/D region of non-uniform cell parameter can alternatively be formed together with a MOS transistor of opposite conductivity type that has a structure similar to that of the MOS transistor 204 in FIG. 2 but has a strained S/D region of uniform cell parameter.
- the percentage of the gas containing the non-silicon IV-group element in the mixed gas for epitaxy is increased with time.
- the difference between the cell size of a portion of the strained layer near the bottom of the opening and the cell size of the substrate is smaller than the difference between the cell size of a portion of the strained layer apart from the bottom of the opening and the cell size of the substrate.
- the non-silicon IV-group element does not enter the metal silicide layer in the salicide process, so that the quality of the metal silicide layer is not degraded.
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor structure and fabrication of the same. More particularly, the present invention relates to a semiconductor structure having a doped strained layer as a source/drain and a method for fabricating the same.
- 2. Description of the Related Art
- Metal-oxide-semiconductor (MOS) transistors are essential to VLSI and ULSI circuits, and are widely used in microprocessors, semiconductor memory devices and power devices, etc., as basic constituent units. In some nanometer processes, the speed of a MOS transistor is increased by forming an opening in the substrate beside the gate structure and then filling the opening with a doped strained material as a source/drain (S/D) region to increase the carrier mobility of the S/D region.
-
FIGS. 1A-1B illustrate a process flow of fabricating a prior-art MOS transistor in a cross-sectional view. Referring toFIG. 1A , asubstrate 100 with a well 101 therein is provided, and then agate structure 102 including gate dielectric 104 and agate 106 is formed on thewell 101. Aspacer 108 is formed on the sidewall of thegate structure 102, and then etching is conducted with thegate structure 102 and thespacer 108 as a mask to remove a portion of the exposedsubstrate 100 and form anopening 110. - Referring to
FIG. 1B , a dopedstrained layer 112 is formed in theopening 110 to serve as an S/D region, wherein a portion 103 of the dopedstrained layer 112 is above the surface of thesubstrate 100. A (self-aligned silicide)salicide layer 114 is then formed on thegate structure 102 and the dopedstrained layer 112. - Because the top surface of the doped
strained layer 112 is higher than that of thesubstrate 100, the stress caused by thesalicide layer 114 is decreased. When the MOS transistor is PMOS, for example, to increase the compressive stress in thestrained layer 112, a SiGe layer with a Ge-content higher than 20% is formed as thestrained layer 112, or the thickness of the same is increased by increasing the depth of theopening 100. - However, the thickness of a strained SiGe layer decreases with increase in the Ge-content thereof. Moreover, when the Ge-content is higher, the cell parameter of the SiGe layer is larger making the difference between the cell parameter of the SiGe layer and that of the substrate larger, so that defects easily occur at the interface of the SiGe layer and the substrate lowering the device performance. Furthermore, in a subsequent salicide process, the Ge-atoms will enter the metal silicide layer degrading its quality.
- Accordingly, this invention provides a semiconductor structure that includes a doped strained layer with a non-uniform cell parameter distribution as an S/D region for decreasing the difference between the cell sizes of the S/D region and the substrate and thereby prevents defects from occurring at the interface of the two.
- The semiconductor structure includes a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a first gate structure on the second well and a first strained layer of the first conductivity type in a first opening in the second well beside the first gate structure. The difference between the cell parameter of a portion of the first strained layer near the bottom of the first opening and the cell parameter of the substrate is smaller than the difference between the cell parameter of a portion of the first strained layer apart from the bottom of the first opening and the cell parameter of the substrate. The second MOS transistor is on the first well.
- In a preferred embodiment, the cell parameter of the first strained layer has a gradient distribution.
- In embodiments where the first conductivity type is P-type, the cell parameter of a portion of the first strained layer near the bottom of the first opening is smaller than that of a portion of the first strained layer apart from the bottom of the first opening. The material of such a first strained layer may be SiGe. In embodiments where the first conductivity type is N-type, the cell parameter of a portion of the first strained layer near the bottom of the first opening is larger than that of a portion of the first strained layer apart from the bottom of the first opening. The material of such a first strained layer may be SiC.
- In some embodiments, the above second MOS transistor includes a second gate structure on the first well and an S/D region of the second conductivity type in the first well beside the second gate structure. The above semiconductor structure may further include a silicon layer on the first strained layer and a metal silicide layer on the silicon layer, the S/D region and the first and the second gate structures.
- In some embodiments, the above second MOS transistor includes a second gate structure on the first well and an S/D region of the second conductivity type around and under a second opening in the first well beside the second gate structure. The above semiconductor structure may also include a silicon layer on the first strained layer and a metal silicide layer on the silicon layer, the S/D region and the two gate structures.
- In some embodiments, the above second MOS transistor includes a second gate structure on the first well and a second strained layer of the second conductivity type in a second opening in the first well beside the second gate structure. The difference between the cell parameter of a portion of the second strained layer near the bottom of the second opening and the cell parameter of the substrate is smaller than the difference between the cell parameter of a portion of the second strained layer apart from the bottom of the second opening and the cell parameter of the substrate. When the first conductivity type is P-type and the second one N-type, the cell parameter of a portion of the first strained layer near the bottom of the first opening is smaller than that of a portion of the first strained layer apart from the bottom of the first opening, but the cell parameter of a portion of the second strained layer near the bottom of the second opening is larger than that of a portion of the second strained layer apart from the bottom of the second opening. When the first conductivity type is N-type and the second one P-type, the cell parameter of a portion of the first strained layer near the bottom of the first opening is larger than that of a portion of the first strained layer apart from the bottom of the first opening, but the cell parameter of a portion of the second strained layer near the bottom of the second opening is smaller than that of a portion of the second strained layer apart from the bottom of the second opening. The cell parameter of the second strained layer may also have a gradient distribution. In addition, the semiconductor structure may further include a silicon layer on the first strained layer and the second strained layer, and a metal silicide layer on the silicon layer and the first and the second gate structures.
- The method for fabricating a semiconductor structure of this invention is described as follows. A substrate having therein a first well of a first conductivity type and a second well of a second conductivity type is provided, and then a first gate structure is formed on the second well. A portion of the substrate beside the first gate structure is removed to form a first opening, and then a first epitaxy process is performed with a first mixed gas to form in the first opening a first strained layer containing silicon and a first IV-group element. The first mixed gas includes a first gas containing silicon and a second gas containing the first IV-group element, and the percentage of the second gas in the first mixed gas is increased with time during the first epitaxy process. In addition, a MOS transistor of the second conductivity type is formed on the first well.
- In embodiments where the first conductivity type is P-type, the atomic size of the first IV-group element is larger than that of silicon increasing the cell parameter, so that the first strained layer of P-type is subject to a compressive stress raising the hole mobility. In embodiments where the first conductivity type is N-type, the first IV-group element is carbon that has an atomic size smaller than that of silicon decreasing the cell parameter, so that the first strained layer of N-type is subject to a tensile stress raising the electron mobility.
- In a preferred embodiment, the first mixed gas further includes a first doping gas so that the first strained layer is formed having the first conductivity type. The MOS transistor of the second conductivity type may be formed by forming a second gate structure on the first well and then forming an S/D region of the second conductivity type in the first well beside the second gate structure. In addition, a silicon layer may be further formed on the first strained layer, and then a metal silicide layer may be formed on the silicon layer, the S/D region and the first and the second gate structures.
- In some embodiments, the MOS transistor of the second conductivity type may be formed with the following steps. A second gate structure is formed on the first well, a portion of the substrate beside the second gate structure is removed to form a second opening, and then an S/D region of the second conductivity type is formed in the first well around and under the second opening. Similarly, a silicon layer may be further formed on the first strained layer, and then a metal silicide layer may be formed on the silicon layer, the S/D region and the first and the second gate structures.
- In still some embodiments, the MOS transistor is formed with the following steps. A second gate structure is formed on the first well, a portion of the substrate beside the second gate structure is removed to form a second opening, and then a second epitaxy process is performed with a second mixed gas to form in the second opening a second strained layer containing silicon and a second IV-group element. The second mixed gas includes the first gas containing silicon and a third gas containing the second IV-group element, and the percentage of the third gas in the second mixed gas is increased with time during the second epitaxy process. When the first conductivity type is P-type and the second one N-type, the atomic size of the first IV-group element is larger than that of silicon but the second IV-group element is carbon that has an atomic size smaller than that of silicon. When the first conductivity type is N-type and the second one P-type, the first IV-group element is carbon that has an atomic size smaller than that of silicon but the atomic size of the second IV-group element is larger than that of silicon.
- In a preferred embodiment, the second mixed gas further includes a second doping gas so that the second strained layer is formed having the second conductivity type. In addition, a silicon layer may be further formed on the first strained layer and the second strained layer, and then a metal silicide layer may be formed on the silicon layer and the first and the second gate structures.
- Accordingly, in the epitaxy process for forming a strained layer as an S/D region in this invention, the percentage of the gas containing the non-silicon IV-group element in the mixed gas is increased with time. Thereby, the difference between the cell size of a portion of the strained layer near the bottom of the opening and the cell size of the substrate is smaller than the difference between the cell size of a portion of the strained layer apart from the bottom of the opening and the cell size of the substrate. Thus, less defects occur at the interface of the strained layer and the substrate. Moreover, since a silicon layer is formed on the strained layer before the metal silicide layer is formed, the non-silicon IV-group element does not enter the metal silicide layer in the salicide process, so that the quality of the metal silicide layer is not degraded.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
-
FIGS. 1A-1B illustrate a process flow of fabricating a prior-art MOS transistor in a cross-sectional view. -
FIG. 2 illustrates a cross-sectional view of a semiconductor structure according to an embodiment of this invention. -
FIGS. 3A-3C illustrate, in a cross-sectional view, a process flow of fabricating theMOS transistor 202 inFIG. 2 according to an embodiment of this invention. -
FIG. 4 illustrates a cross-sectional view of a semiconductor structure according to another embodiment of this invention. -
FIG. 5 illustrates a cross-sectional view of a semiconductor structure according to still another embodiment of this invention. - Referring to
FIG. 2 , the semiconductor structure of this embodiment includes asubstrate 200, aMOS transistor 202 of a first conductivity type, aMOS transistor 204 of a second conductivity type and anisolation structure 206. Thesubstrate 200 has a well 208 of the first conductivity type and a well 210 of the second conductivity type therein. TheMOS transistor 202 is disposed on the well 210, including agate structure 212 on the well 210 and a dopedstrained layer 216 of the first conductivity type. Thegate structure 212 includes agate 212 a on thesubstrate 200,gate dielectric 212 b between thegate 212 a and thesubstrate 200 and aspacer 212 c on the sidewall of thegate 212 a, and anopening 214 is formed in the well 210 beside thegate structure 212. Thegate 212 a may include poly-Si or metal, thegate dielectric 212 b may include SiO, SiN or SiON, and thespacer 212 c may include SiN. - The
strained layer 216 is disposed in theopening 214 serving as a part of the S/D region of theMOS transistor 202, wherein the difference between the cell parameter of a portion of thestrained layer 216 near the bottom of theopening 214 and the cell parameter of thesubstrate 200 is smaller than the difference between the cell parameter of a portion of thestrained layer 216 apart from the bottom of theopening 214 and the cell parameter of thesubstrate 200. It is more preferred that the cell parameter of thestrained layer 216 has a gradient distribution. When the first conductivity type is P-type, thestrained layer 216 is a compressively strained layer, wherein a portion of thestrained layer 216 near the bottom of theopening 214 has a cell parameter equal to or larger than that of thesubstrate 200 but smaller than that of a portion of thestrained layer 216 apart from the bottom of theopening 214. When the first conductivity type is N-type, thestrained layer 216 is a tensily strained layer, wherein a portion of thestrained layer 216 near the bottom of theopening 214 has a cell parameter equal to or smaller than that of thesubstrate 200 but larger than that of a portion of thestrained layer 216 apart from the bottom of theopening 214. TheMOS transistor 202 also includes a dopedregion 217 of the first conductivity type under and around theopening 214 as another part of its S/D region, and an S/D extension region 219 of the first conductivity type in the well 210 under thespacer 212 c. - The
MOS transistor 204 is disposed on thewell 208. Theisolation structure 206 is disposed in thesubstrate 200 to define the active areas of the devices, and may be an STI structure or other type of isolation structure. TheMOS transistor 204 includes agate structure 218 and a dopedstrained layer 222 of the second conductivity type. Thegate structure 218 is disposed on the well 208, and anopening 220 is formed in the well 208 beside thegate structure 218. Thegate structure 218 includes gate dielectric 218 b, agate 218 a on thegate dielectric 218 b and aspacer 218 c on the sidewall of thegate 218 a, wherein possible materials of 218 a, 218 b and 218 c are the same as above. - The
strained layer 222 is disposed in theopening 220 serving as a part of the S/D of theMOS transistor 204. Similarly, the difference between the cell parameter of a portion of thestrained layer 222 near the bottom of theopening 220 and the cell parameter of thesubstrate 200 is smaller than the difference between the cell parameter of a portion of thestrained layer 222 apart from the bottom of theopening 220 and the cell parameter of thesubstrate 200. However, the cell parameter of thestrained layer 222 changes reversely with respect to that of thestrained layer 216. Specifically, when the First conductivity type is P-type and the second one N-type, thestrained layer 216 is a compressively strained layer with the cell parameter increasing toward its top, while thestrained layer 222 is a tensily strained layer with the cell parameter decreasing toward its top. When the first conductivity type is N-type and the second one P-type, thestrained layer 216 is a tensily strained layer just mentioned, while thestrained layer 222 is a compressively strained layer just mentioned. TheMOS transistor 204 also includes a dopedregion 223 of the second conductivity type under and around theopening 220 as another part of the S/D region of theMOS transistor 204, and an S/D extension region 225 of the second conductivity type in the well 208 under thespacer 218 c. - It is noted that in this embodiment, when the first conductivity type is P-type and the second one N-type, the compressively
strained layer 216 may include SiGe that is larger in cell parameter relative to pure silicon, while the tensilystrained layer 222 may include SiC that is smaller in cell parameter relative to pure silicon. When the first conductivity type is N-type and the second one P-type, the tensilystrained layer 216 may include SiC, while the compressivelystrained layer 222 may include SiGe. - Moreover, on the
strained layers silicon layers metal silicide layer 226 may further be disposed on the silicon layers 224 a and 224 b and thegate structures silicon layer metal silicide layer 226 may be WSi, TiSi, MoSi, NiSi, PdSi or PtSi. Moreover, contact etching stop layers 228 a and 228 b may further be disposed over thesubstrate 200 covering the resulting structure. The material of the contactetching stop layer etching stop layer 228 a/228 b may be a compressive or tensile layer for increasing the carrier mobility in the channel layer of theMOS transistor 202/204 and thereby further improves the performance of theMOS transistor 202/204. - An example of fabricating the semiconductor structure in
FIG. 2 is described as follows. Since the left half and the right half of the semiconductor structure is similar in structure, the fabricating process of the left half is described firstly. -
FIGS. 3A-3C illustrate, in a cross-sectional view, a process flow of fabricating theMOS transistor 202 inFIG. 2 . Referring toFIG. 3A , asubstrate 200 is provided, having therein a well of the first conductivity type (not shown), a well 210 of the second conductivity type and anisolation structure 206 defining the active areas of the devices. The wells can be formed through ion implantation, and theisolation structure 206 may be formed through an STI process. Agate 212 a and gate dielectric 212 b are formed on the well 210, possibly by forming a layer of gate dielectric material and a gate material layer on thesubstrate 200 and then sequentially patterning the two layers. - Referring to
FIG. 3A again, a dopedregion 211 of the first conductivity type is formed in the well 210 beside thegate 212 a, possibly through an ion implantation with thegate 212 a as a mask. Aspacer 212 c is formed on the sidewall of thegate 212 a, constituting agate structure 212 together with thegate 212 a and gate dielectric 212 b. - Referring to
FIG. 3B , a portion of thesubstrate 200 beside thegate structure 212 is removed to form anopening 214, while a portion of the dopedregion 211 is removed to form an S/D extension region 219. Theopening 214 may be formed with the following steps. A patterned photoresist layer (not shown) is formed over thesubstrate 200, exposing thegate structure 212 and the region for forming theopening 214. An etching process is conducted with thegate structure 212 and the patterned photoresist layer as a mask to remove a portion of thesubstrate 200, wherein the etching may be isotropic, anisotropic or tilted etching. The depth of theopening 214 is usually 100-1000 Å, preferably 300-500 Å. - Referring to
FIG. 3C , ion implantation is conducted with thegate structure 212 as a mask to implant a dopant of the first conductivity type into a portion of thesubstrate 200 under and around theopening 214 to form a dopedregion 217 as a part of the S/D region of theMOS transistor 202. It is particularly noted that the above ion implantation can alternatively be conducted before theopening 214 is formed, wherein the depth of theopening 214 has to be controlled smaller than that of the implantation. - Thereafter, a first epitaxy process is conducted with a first mixed gas to form a
strained layer 216 in theopening 214, wherein the first mixed gas includes a first gas containing silicon and a second gas containing a first IV-group element and the percentage of the second gas in the first mixed gas is increased with time during the first epitaxy process. The first gas is, for example, silane or disilane. The first mixed gas preferably further includes a first doping gas so that thestrained layer 216 is formed having the first conductivity type. When the first conductivity type is P-type, the first IV-group element is one having an atomic size larger than that of silicon, such as Ge, so that the cell parameter is increased and a compressivelystrained layer 216 is formed with improved hole mobility. When the first conductivity type is N-type, the IV-group element is carbon that is smaller than silicon in atomic size, so that the cell parameter is decreased and a tensilystrained layer 216 is formed with improved electron mobility. - The fabricating process of the
MOS transistor 204 is analogous to that of theMOS transistor 202. The main differences are that theMOS transistor 204 has an opposite conductivity type and thestrained layer 222 thereof is formed with a second epitaxy process that uses a second mixed gas that includes the first gas containing Si and a third gas containing a second IV-group element. Similarly, the second mixed gas may further include a second doping gas, so that thestrained layer 222 is formed having the second conductivity type. To respectively form a compressively strained layer required by PMOS and a tensily strained layer required by NMOS, when the first conductivity type is P-type and the second one N-type, the atomic size of the first IV-group element is larger than that of silicon to result in a larger cell parameter, while the second IV-group element is carbon that has an atomic size smaller than that of silicon to result in a smaller cell parameter. On the contrary, when the first conductivity type is N-type and the second one P-type, the first IV-group element is carbon, and the atomic size of the second IV-group element is larger than that of silicon. - Moreover, when the first conductivity type is P-type and the second one N-type, the second gas may be GeH4, and the second gas in the first mixed gas may be increased from 0 to 40% with time during the first epitaxy process, while the first doping gas may be B2H6. The third gas may be CH4 or C2H6, and the third gas in the second mixed gas may be increased from 0 to 20% with time during the second epitaxy process, while the second doping gas may be PH3.
- On the contrary, when the first conductivity type is N-type and the second one P-type, the second gas may be CH4 or C2H6, and the second gas in the first mixed gas may be increased from 0 to 20% with time during the first epitaxy process, while the first doping gas may be PH3. The third gas may be GeH4, and the third gas in the second mixed gas may be increased from 0 to 40% with time during the second epitaxy process, while the second doping gas may be B2H6.
- It is also noted that the
MOS transistors MOS transistor 202 is usually integrated more or less with that of theMOS transistor 204 for step simplification. - After the MOS transistor 202 (or 204) is formed, a
silicon layer 224 a (or 224 b) of the same conductivity type may be further formed on the strained layer 216 (or 222), as shown inFIG. 2 . Thesilicon layer 224 a (or 224 b) may be formed directly in the first (or second) epitaxy process by stopping supplying the second (or third) gas after the strained layer 216 (or 222) is formed but continuing to supply the Si-containing first gas and the First (or second) doping gas for epitaxy. After the silicon layers 224 a and 224 b are formed, ametal silicide layer 226 can be further formed, possibly through a salicide process, on the silicon layers 224 a and 224 b and thegate structures FIG. 2 . After themetal silicide layer 226 is formed, contact etching stop layers 228 a and 228 b may be formed over thesubstrate 200 covering the resulting structure, as shown inFIG. 2 , possibly through chemical vapor deposition (CVD). - It is also noted that the
MOS transistor 202 of the first conductivity type having a strained S/D region of non-uniform cell parameter is not restricted to form together with a MOS transistor of the second conductivity type also having a strained S/D region of non-uniform cell parameter. TheMOS transistor 202 may alternatively be formed together with a structurally different MOS transistor of the second conductivity type. Such examples are described in the following embodiments. -
FIG. 4 illustrates a cross-sectional view of a semiconductor structure according to another embodiment of this invention. TheMOS transistor 204′ in replacement of theMOS transistor 204 includes agate structure 218 as mentioned above and an S/D region 227 in the well 208 beside thegate structure 218. TheMOS transistor 204′ also includes anSID extension region 225 of the second conductivity type in the well 208 under thespacer 218 c. Similarly, in this embodiment, thestrained layer 216 may also be formed with asilicon layer 224 thereon, and then ametal silicide layer 226 may be further formed on thesilicon layer 224, the S/D region 227 and thegate structures silicon layer 224 and the material of themetal silicide layer 226 may be the same as above. Moreover, two contact etching stop layers 228 a and 228 b, such as SiN layers formed with different recipes to have different stresses, can be formed over thesubstrate 200 covering theMOS transistors - The
MOS transistor 204′ may be formed by forming agate structure 218 on the well 208 and then forming, possibly through an ion implantation process using thegate structure 218 as a mask, an S/D region 227 of the second conductivity type in the well 208 beside thegate structure 218. -
FIG. 5 illustrates a cross-sectional view of a semiconductor structure according to yet another embodiment of this invention. TheMOS transistor 204″ in replacement of theMOS transistor 204 includes agate structure 218 as mentioned above and an S/D region 229 in the well 208 under and around anopening 231 beside thegate structure 218. Thetransistor 204″ also includes an S/D extension region 225 of the second conductivity type in the well 208 under thespacer 218 c. In the present embodiment, thestrained layer 216 may similarly be formed with asilicon layer 224 thereon, and then ametal silicide layer 226 may be further formed on thesilicon layer 224, the S/D region 229 and thegate structures silicon layer 224 and the material of themetal silicide layer 226 may be the same as above. Moreover, contact etching stop layers 228 a and 228 b as mentioned above may be further formed over thesubstrate 200 covering theMOS transistors etching stop layer 228 b preferably has a thickness at least sufficient to fill up theopening 231 to apply a sufficient large stress to the channel layer of theMOS transistor 204″ and effectively increase the carrier mobility in the channel layer thereby. - In addition, the
MOS transistor 204″ may be formed with the following steps. Agate structure 218 is formed on the well 208, a portion of thesubstrate 200 beside thegate structure 218 is removed to form anopening 231, and then an S/D region 229 of the second conductivity type is formed in the well 208 under and around theopening 231, possibly with an ion implantation process using thegate structure 218 as a mask. - It is also noted that the
MOS transistors MOS transistor 202 is usually integrated more or less with that of theMOS transistor 204′ (or 204″) for step simplification. - Nevertheless, it is particularly noted that the
MOS transistor 202 with a strained S/D region of non-uniform cell parameter can alternatively be formed together with a MOS transistor of opposite conductivity type that has a structure similar to that of theMOS transistor 204 inFIG. 2 but has a strained S/D region of uniform cell parameter. - Accordingly, in the epitaxy process for forming a strained layer as an S/D region in this invention, the percentage of the gas containing the non-silicon IV-group element in the mixed gas for epitaxy is increased with time. Thereby, the difference between the cell size of a portion of the strained layer near the bottom of the opening and the cell size of the substrate is smaller than the difference between the cell size of a portion of the strained layer apart from the bottom of the opening and the cell size of the substrate. Thus, less defects occur at the interface of the strained layer and the substrate.
- Moreover, since a silicon layer is formed on the strained layer before the metal silicide layer is formed, the non-silicon IV-group element does not enter the metal silicide layer in the salicide process, so that the quality of the metal silicide layer is not degraded.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (15)
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009108365A1 (en) * | 2008-02-29 | 2009-09-03 | Advanced Micro Devices, Inc | A cmos device comprising an nmos transistor with recessed drain and source areas and a pmos transistor having a silicon/germanium material in the drain and source areas |
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5977592A (en) * | 1997-01-31 | 1999-11-02 | Oki Electric Industry Co., Ltd. | Semiconductor device having an improved structure and capable of greatly reducing its occupied area |
US20030122199A1 (en) * | 2001-12-18 | 2003-07-03 | Kabushiki Kaisha Toshiba | Semiconductor device and fabricating method for the same |
US6914307B2 (en) * | 2000-11-21 | 2005-07-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US20050266631A1 (en) * | 2004-05-26 | 2005-12-01 | Fujitsu Limited | Semiconductor device fabricating method |
US20060202278A1 (en) * | 2005-03-09 | 2006-09-14 | Fujitsu Limited | Semiconductor integrated circuit and cmos transistor |
US20070018328A1 (en) * | 2005-07-07 | 2007-01-25 | Matthias Hierlemann | Piezoelectric stress liner for bulk and SOI |
US7226820B2 (en) * | 2005-04-07 | 2007-06-05 | Freescale Semiconductor, Inc. | Transistor fabrication using double etch/refill process |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7101742B2 (en) * | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
US7883979B2 (en) * | 2004-10-26 | 2011-02-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing a semiconductor device with reduced floating body effect |
US7238580B2 (en) * | 2005-01-26 | 2007-07-03 | Freescale Semiconductor, Inc. | Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration |
-
2006
- 2006-04-07 US US11/399,827 patent/US7288822B1/en active Active
-
2007
- 2007-05-30 US US11/755,669 patent/US7524716B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5977592A (en) * | 1997-01-31 | 1999-11-02 | Oki Electric Industry Co., Ltd. | Semiconductor device having an improved structure and capable of greatly reducing its occupied area |
US6914307B2 (en) * | 2000-11-21 | 2005-07-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US20030122199A1 (en) * | 2001-12-18 | 2003-07-03 | Kabushiki Kaisha Toshiba | Semiconductor device and fabricating method for the same |
US20050266631A1 (en) * | 2004-05-26 | 2005-12-01 | Fujitsu Limited | Semiconductor device fabricating method |
US20060202278A1 (en) * | 2005-03-09 | 2006-09-14 | Fujitsu Limited | Semiconductor integrated circuit and cmos transistor |
US7226820B2 (en) * | 2005-04-07 | 2007-06-05 | Freescale Semiconductor, Inc. | Transistor fabrication using double etch/refill process |
US20070018328A1 (en) * | 2005-07-07 | 2007-01-25 | Matthias Hierlemann | Piezoelectric stress liner for bulk and SOI |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009108365A1 (en) * | 2008-02-29 | 2009-09-03 | Advanced Micro Devices, Inc | A cmos device comprising an nmos transistor with recessed drain and source areas and a pmos transistor having a silicon/germanium material in the drain and source areas |
US20090218633A1 (en) * | 2008-02-29 | 2009-09-03 | Jan Hoentschel | Cmos device comprising an nmos transistor with recessed drain and source areas and a pmos transistor having a silicon/germanium material in the drain and source areas |
GB2470523A (en) * | 2008-02-29 | 2010-11-24 | Advanced Micro Devices Inc | A cmos device comprising an nmos transistor with recessed drain and source areas and a pmos transistor having a silcon/gernanium material in the drain and sou |
CN101971325A (en) * | 2008-02-29 | 2011-02-09 | 先进微装置公司 | CMOS device comprising an nmos transistor with recessed drain and source areas and a pmos transistor having a silicon/germanium material in the drain and source areas |
GB2470523B (en) * | 2008-02-29 | 2012-03-21 | Advanced Micro Devices Inc | Cmos device with an nmos transistor with recessed drain and source areas and a pmos transistor with a silicon/germanium alloy in the drain and source areas |
KR101148138B1 (en) | 2008-02-29 | 2012-05-23 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | A cmos device comprising an nmos transistor with recessed drain and source areas and a pmos transistor having a silicon/germanium material in the drain and source areas |
JP2013534052A (en) * | 2010-06-25 | 2013-08-29 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Semiconductor structure including embedded stressor element and method of manufacturing the same |
CN102623487A (en) * | 2011-01-26 | 2012-08-01 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
WO2012100396A1 (en) * | 2011-01-26 | 2012-08-02 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing same |
US20150021702A1 (en) * | 2013-07-22 | 2015-01-22 | Globalfoundries Inc. | Shallow trench isolation |
US9136330B2 (en) * | 2013-07-22 | 2015-09-15 | GlobalFoundries, Inc. | Shallow trench isolation |
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