WO2012022109A1 - 一种半导体器件结构及其制造方法 - Google Patents

一种半导体器件结构及其制造方法 Download PDF

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Publication number
WO2012022109A1
WO2012022109A1 PCT/CN2011/000306 CN2011000306W WO2012022109A1 WO 2012022109 A1 WO2012022109 A1 WO 2012022109A1 CN 2011000306 W CN2011000306 W CN 2011000306W WO 2012022109 A1 WO2012022109 A1 WO 2012022109A1
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Prior art keywords
gate
forming
channel region
insulating layer
semiconductor substrate
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PCT/CN2011/000306
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English (en)
French (fr)
Inventor
钟汇才
梁擎擎
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中国科学院微电子研究所
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Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US13/133,061 priority Critical patent/US9653358B2/en
Priority to GB1202162.2A priority patent/GB2488401B/en
Publication of WO2012022109A1 publication Critical patent/WO2012022109A1/zh

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Definitions

  • the present invention relates to the field of semiconductor device design and manufacturing technology thereof, and more particularly to a method of fabricating a CMOS device in which a source/drain region is formed by self-alignment before gate formation and a structure thereof. Background technique
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS Complementary Metal Oxide Semiconductor
  • . 1 is a schematic diagram of a typical back gate process in the prior art, including forming a sacrificial gate 100 first, then forming a source/drain region 200, a sidewall spacer 300, and a source/drain silicide cap layer 400, and then removing the sacrificial gate 100 to The inner wall of the side wall 300 forms an opening 500, and finally a replacement gate stack is formed in the opening.
  • An advantage of this process is that the replacement gate stack is formed after the source/drain regions are formed, thereby avoiding the adverse effects of high temperature annealing and other source/drain processes on the dielectric and conductors in the gate stack.
  • An object of the present invention is to at least solve one of the above problems, in particular, to achieve the effect of a replacement gate process without resorting to a sacrificial gate, thereby avoiding many drawbacks of the replacement gate process.
  • the present invention provides a method of fabricating a semiconductor device structure, including: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; embedding the first insulating layer and the semiconductor liner Forming a shallow trench isolation; embedding the semiconductor substrate to form a channel region; forming a gate stack line on the channel region; wherein, before forming the channel region, the method further comprises: The semiconductor substrate is subjected to source/drain implantation.
  • the first insulating layer comprises Si 3 N 4 , Si0 2 , SiOx:F, SiCOH, SiO x , Si0 2 : a combination of any one or more of C, SiCON, and SiONx.
  • the method further includes: re-etching the first insulating layer; Forming a second insulating layer on the first insulating layer, the second insulating layer is the same material as the first insulating layer; and when forming the channel region, further comprising a second insulating layer above the channel region Etching is also performed.
  • the method further includes: removing the first insulation overlying the active region a source/drain region implantation on the semiconductor substrate; forming a second insulating layer on the semiconductor substrate, the second insulating layer being the same material as the first insulating layer; forming the channel region And etching the second insulating layer above the channel region.
  • forming the channel region comprises: embedding the first insulating layer and the semiconductor substrate to form a strip-shaped groove, a bottom of the groove being higher than a bottom of the shallow trench isolation; Forming a third insulating layer at the bottom; forming a channel region on the third insulating layer in the recess.
  • the third insulating layer comprises a combination of any one or more of Si 3 N 4 , SiO 2 , SiO x : F, SiC OH, SiO x , SiO 2 :.C, SiCON, and SiONx.
  • the method of forming the channel region comprises: epitaxially growing a channel region with the exposed sidewalls in the recess as a source.
  • the material of the channel region comprises Si, Si: C, GaN, AlGaN, InP, and
  • a combination of any one or more of SiGe This makes it possible to select the constituent materials of the channel region as needed.
  • the method further comprises: forming a gate inner wall along the sidewall of the trench over the channel region to reduce a feature size of the gate channel, thereby reducing the short gate The difficulty of the process.
  • performing source/drain implantation on the semiconductor substrate comprises: performing source/drain implantation on the entire semiconductor substrate or the active region on the semiconductor substrate, and annealing to activate the implanted impurities.
  • forming a gate stack line on the channel region comprising: forming a gate dielectric layer on the channel region; forming a gate electrode line on the gate dielectric layer; removing the first insulating layer; Forming an outer wall outside the gate electrode line; wherein, after forming the outer wall, cutting the gate electrode line before completing the front process of the semiconductor device To form an electrically isolated gate electrode.
  • cutting the gate electrode line comprises: using reactive ion etching or laser cutting etching.
  • the gate electrode line is diced to form an electrically isolated gate electrode; the method further comprising: forming an interlayer dielectric layer on the semiconductor substrate, wherein the layer An intervening dielectric layer fills the isolated gate electrodes; and etches the interlayer dielectric layer to form contact holes on the gate electrodes or source/drain regions.
  • the method further comprises: forming a first interlayer dielectric layer; etching the first interlayer dielectric layer to form a lower contact hole on the source/drain region; Forming a lower contact portion in the lower contact hole; cutting the gate electrode line; forming a second interlayer dielectric layer; etching the second interlayer dielectric layer to be on the gate electrode line or source/drain
  • An upper contact hole is formed on the region; an upper contact portion is formed in the upper contact hole; wherein, on the source/drain region, the lower contact portion is aligned with the upper contact portion.
  • the present invention also provides a semiconductor device structure fabricated according to the above method, comprising: a semiconductor substrate; a channel region embedded in the semiconductor substrate; a gate stack located on the channel region, a gate dielectric layer on the channel region and a gate electrode on the gate dielectric layer; source/drain regions on both sides of the channel region in the semiconductor substrate before the channel region and the gate stack are formed
  • the source/drain region is implanted by the semiconductor substrate, so that the impurity concentration at the same depth in the source/drain regions is uniform.
  • the material of the channel region comprises a combination of one or more of Si, Si: C, GaN, AlGaN, InP, and SiGe.
  • the channel region is formed by epitaxial growth. Insulation.
  • shallow trench isolation is formed in the semiconductor substrate, and a bottom of the insulating layer is higher than a bottom of the shallow trench isolation.
  • the insulating layer comprises a combination of any one or more of Si 3 N 4 , SiO 2 , SiO x : F, SiC OH, SiO x , SiO 2 : C, SiCON, and SiONx.
  • the semiconductor device structure further includes a gate inner wall formed on the channel region, on both sides of the gate stack, and in an direction along the gate width, an end portion of the inner wall The ends of the gate electrodes are aligned.
  • the semiconductor device structure further includes an outer wall formed on both sides of the gate stack, and an end of the outer wall is aligned with an end of the gate electrode in a direction of a gate width.
  • the semiconductor device structure is characterized in that, in the direction of the gate width, adjacent gate electrodes are filled with a dielectric material to form electrical isolation between the gate stacks.
  • the distance between adjacent gate electrodes is 1-10 nm in the direction of the gate width.
  • the semiconductor device structure further includes a lower contact portion and an upper contact portion, the lower contact portion is in contact with the source/drain region and is at the same height as the top of the gate stack, and the upper contact portion and the top portion of the gate stack
  • the lower contact portions are respectively in contact; wherein, on the source/drain regions, the lower contact portion is aligned with the upper contact portion.
  • the present invention provides a method for forming a source/drain region in a self-aligned manner by implanting a semiconductor substrate before the channel region and the gate stack are formed, thereby realizing the advantageous effect of achieving a replacement gate process without using a sacrificial gate. This simplifies the process and reduces costs.
  • the source/drain implantation is performed before the formation of the channel region, thereby avoiding the impurity diffusion phenomenon which is easily caused by the formation of the source/drain regions in the prior art.
  • the feature size of the gate trench can be effectively adjusted.
  • the device performance of the MOSFET is greatly enhanced by applying an epitaxial channel that effectively increases the carrier mobility.
  • embodiments of the present invention are also combined with a unique process of gate electrode line dicing, which can effectively improve the insulation effect between the gate electrodes and simplify gate electrode etching, lithography, and reduction of OPC (Optical Proximity Correction).
  • the difficulty of this process is also compatible with high-k dielectric/metal gate processes.
  • FIG. 1 is a schematic view of a replacement gate process of the prior art
  • Figure 2-16a is a cross-sectional view showing the structure of an intermediate step of a method of fabricating a semiconductor device structure according to an embodiment of the present invention
  • the subscript a in the figure number is a cross-sectional view along the direction AA in the top view
  • the subscript b is shown as a cross-sectional view along the direction of BB in the top view
  • the subscript c in the figure number is a cross-sectional view along the CC in the plan view.
  • Example 5 surface description by reference to the accompanying drawings is a diagram ⁇ born, in the explanation of the present invention and should not be construed as limiting the present invention.
  • the following disclosure provides many different embodiments or examples for implementing the different structures of the present invention.
  • the components and settings of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
  • the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of brevity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • FIGS. 2-16a are cross-sectional views showing the structure of an intermediate step of fabricating a semiconductor device structure in accordance with an embodiment of the present invention.
  • a method of fabricating a semiconductor device structure and a device structure obtained thereby according to an embodiment of the present invention will be described in detail below with reference to Figs. 2-16a.
  • a semiconductor substrate 1000 is provided.
  • the substrate 1000 is exemplified by bulk silicon.
  • the substrate may include any suitable semiconductor substrate material, specifically but not limited to silicon, germanium, silicon germanium, SOI (on insulator). Silicon), silicon carbide, gallium arsenide or any III/V compound semiconductor.
  • the substrate 1000 can include various doping configurations in accordance with design requirements well known in the art (e.g., a p-type substrate or an n-type substrate). Additionally, substrate 1000 can optionally include an epitaxial layer that can be stressed to enhance performance.
  • source/drain implantation is performed before the formation of the first insulating layer 1003.
  • the specific method is as follows: First, ion implantation is performed on all regions of the semiconductor substrate 1000, for example, n-type or p-type weight may be performed. Doping and activation annealing to semiconductor The same depth in all regions of the substrate forms a doped region with a uniform ion concentration. It should be noted that the doped region remaining after subsequent processes is equivalent to a source/drain formed in a self-aligned manner.
  • a first insulating layer 1003 is formed on the surface of the semiconductor substrate 1000, and the first insulating layer 1003 may be composed of Si 3 N 4 , Si0 2 , SiOx:F, SiCOH, SiO x , Si0 2 :C, SiCON, and SiONx.
  • the embodiment of the present invention preferably adopts Si 3 N 4 ; then the first insulating layer 1003 and the semiconductor substrate 1000 are etched to form a groove according to the shape of the STI 1001 to be formed, in the concave
  • the trench is filled with an oxide, such as Si0 2 , to form a shallow trench isolation STI 1001, as shown in Figures 2 and 2c, and Figure 2c is a cross-sectional view taken along line CC of Figure 1.
  • a planarization process is performed, such as chemical mechanical polishing (CMP).
  • an oxide layer may be formed on the semiconductor substrate 1000 before the formation of the first insulating layer 1003, which may be formed by conventional thermal oxidation or other deposition methods.
  • the oxide layer is not shown in the drawing.
  • the first insulating layer 1003 may be selected to be etched back to the ratio.
  • the top of the STI is at a low position, and then a second insulating layer (not shown) is newly deposited.
  • the material of the second insulating layer can be the same as that of the first insulating layer, forming a brand new second insulating layer to facilitate formation. A better surface.
  • source/drain region implantation is performed after forming the STI, and as shown in FIGS. 2 and 2c, the STI 1001 and the active region 1002 are included on the semiconductor substrate 1000.
  • the first insulating layer 1003 is first formed on the surface of the semiconductor substrate 1000; then the first insulating layer 1003 and the semiconductor substrate 1000 are etched to form a recess according to the shape of the STI 1001 to be formed, and the recess is filled with oxidation.
  • STI 1001 a material such as SiO 2 to form STI 1001; then removing first insulating layer 1003 overlying surface of active region 1002 to expose the active region; then ion implantation of all active regions 1002 or the entire semiconductor substrate
  • n-type or p-type heavily doped and activated annealing may be performed to form a doped region having a uniform ion concentration at the same depth in all of the active regions, and similarly, the doping remaining after subsequent processes
  • the impurity region corresponds to a source/drain region formed in a self-aligned manner; and a second insulating layer is formed on the semiconductor substrate 1000, and the material of the second insulating layer and the first insulating layer may be the same.
  • the first insulating layer 1003 is still used in the subsequent drawings.
  • first insulating layer 1003 Before the formation of the first insulating layer 1003, it is also possible to An oxide layer is first formed on 1000, which is not shown.
  • the substrate on which the STI and the source/drain regions are formed can be obtained, and the following steps are the same for the two embodiments, so the description will be collectively made.
  • the source/drain regions are formed in advance and the annealing is activated, so that the gate formed in the subsequent process will not undergo annealing high temperature, which is advantageous for maintaining good characteristics of the gate.
  • a photoresist is coated on the semiconductor structure on which the STI 1001 is formed, and the photoresist is patterned according to the shape of the gate electrode line to be formed, so that the portion where the gate electrode line needs to be formed is an exposed region. Other areas are covered with photoresist.
  • the first insulating layer 1003 and the semiconductor substrate 1000 are selectively etched using the formed photoresist pattern as a mask.
  • the first insulating layer 1003 is Si 3 N 4
  • the STI is filled with Si0 2 , then this etching selectively etches Si 3 N 4 and Si with respect to SiO 2 , and finally forms.
  • a recess 1005 is embedded in the first insulating layer 1003 and the semiconductor substrate 1000. The bottom of the recess 1005 is higher than the bottom of the STI 1001 so that the STI can also provide isolation.
  • the etching is performed downward from the second insulating layer.
  • Figures 3a and 3b are cross-sectional views taken along line BB, and CC, respectively, in Fig. 2, clearly showing the results of this selective etching.
  • the size of the groove 1005 shown by the arrow in FIG. 3a is larger than the final gate channel size, which is advantageous for lithography processing, and further reduces the feature size of the gate channel through the inner wall; as can be seen from FIG. 3b Out, this etching has little effect on the STI, forming a very shallow groove 1005.
  • a third insulating layer 1007 is formed on the recess 1005, and the third insulating layer 1007 may be composed of Si 3 N 4 , Si0 2 , SiOx:F, SiCOH, A combination of any one or more of SiO x , Si0 2 : C, SiCON, and SiONx is formed.
  • the method of formation may be thermal oxidation, atomic layer chemical vapor deposition (ALCVD) or other deposition methods, which are not limited in the present invention.
  • the third insulating layer 1007 is capable of adjusting the thickness of the channel region to be formed later, and can also increase the switching speed of the device.
  • a selective selective atomic layer chemical vapor phase (ALCVD) method can be used to form a thick insulating layer at the bottom of the recess, and a thin or almost no sidewall is formed on the sidewall of the recess.
  • ACVD selective selective atomic layer chemical vapor phase
  • the structure of the insulating layer After forming the third insulating layer in the recess, selective wet chemical or dry chemical etching may be used to expose the sidewall of the recess leaving an insulating layer (thickness) 5-50nm) at the bottom of the groove.
  • the sidewall exposed by the recess 1005 is a crystal source, and the channel region 1008 is epitaxially grown.
  • the channel region 1008 is epitaxially grown.
  • a combination of any one or more of Si, Si:C, GaN, AlGaN, InP, and SiGe may be epitaxially grown to form the channel region 1008.
  • the Ge content in SiGe or Si:C or the percentage of C content is selected to adjust the stress in the channel region.
  • the thickness of the channel region thus formed can be adjusted, and the concentration of impurities in the channel region can be selected to generate stress, so that the mobility of carriers can be effectively improved and the device performance can be improved.
  • the doped region ie, active region 1002 in the semiconductor substrate 1000 except the channel region
  • the sidewalls of the recess 1005 above the channel region 1008 form the inner wall 1004.
  • the specific method may be as follows: atomic layer deposition (ALD) is performed over the channel region 1008 to form a filling layer, and then the filling layer is selectively etched to form a gate inner wall 1004, and the width of the gate inner wall 1004 is 1 to 5 nm.
  • ALD atomic layer deposition
  • the shape thereof is not limited in the present invention, and the shapes shown in Figs. 6a and 6b are merely illustrative.
  • the material of the filling layer may be an oxide, a nitride or a low-k material such as silicon oxide (Si0 2 ) or silicon nitride (Si 3 N 4 ), and the low-k material may be, for example, SiOx:F, SiCOH, SiO. x , Si0 2 : C, SiCON, etc.
  • the gate length can be further reduced, thereby making it possible to reduce the difficulty of the short gate process.
  • the width of the channel region 1008 is 30 nm
  • the width of the gate inner wall 1004 is 5 nm.
  • a gate length of 20 nm is obtained by an etching process of 30 nm, thereby reducing the difficulty of the short gate process.
  • the gate stack line can then be formed by conventional methods or methods of embodiments of the present invention. It is to be noted that since the source/drain regions have been formed before the channel formation and are subjected to high temperature annealing, the gate stack can be formed directly without using a replacement gate process for the purpose of thermal budgeting, thereby simplifying the process and reducing the cost.
  • a gate dielectric layer 1009 is formed over the channel region.
  • the gate dielectric layer 1009 may be a conventional dielectric material or a high-k dielectric material, and may be, for example, Hf0 2 , HfSiO, HfSiONx, HfTaO, Hf iO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO. Any one or more of them.
  • the method of forming the gate dielectric layer may be thermal oxidation, sputtering, deposition, or the like or other methods. High-k gate dielectric layer can suppress short channel of device Effect.
  • a gate electrode line 1010 is formed on the gate dielectric layer 1009.
  • a conductive material may be deposited on the entire semiconductor device structure, such as p 0 ly-Si, Ti, Co, Ni, Al, W, metal alloy, or the like, followed by CMP (Chemical Mechanical Polishing). Processing the entire semiconductor device structure and stopping on the first insulating layer 1003.
  • the gate electrode line 1010 on the STI 1001 is very thin.
  • the first insulating layer 1003 is removed, and may be performed by dry etching or wet etching.
  • Si 3 N 4 may be etched using a hot phosphoric acid. Thereby, a structure as shown in Figs. 8a and 8b is formed.
  • the STI 1001 of the substrate 1000 in Fig. 8a is removed, for example, HF etching may be employed.
  • an embodiment of the present invention may further employ a photolithographic mask to diced a gate electrode line into a gate electrode.
  • the gate electrode line 1010 is cut by a conventional process to form an electrically isolated gate electrode 1015.
  • a slit 1017 etched using a mask is schematically illustrated in Fig. 9, and the formation of the slit can be completely made according to the needs of the device.
  • the outer wall 101 1 is formed on the outer side of the gate electrode 1015.
  • the embodiment of the present invention does not limit the shape and material of the side wall, and therefore the shape of the side wall shown in Figs. 10 and 10a is merely illustrative. If the gate inner wall in the alternative is implemented, the outer wall 101 1 is formed on the outer side of the grid inner wall 1004.
  • a metal silicide contact can be formed on the source/drain region 1012 and the gate electrode 1015 as needed.
  • a layer of metal such as Ni, Co, W or the like is deposited over the entire semiconductor device structure, and then rapidly annealed to form a metal silicide contact, and the unreacted metal is removed.
  • a metal silicide 1013 as shown in Fig. 10a is formed. While the metal is being removed, the metal of the very thin gate electrode line 1010 on the STI may be removed, as shown in Fig. 10b.
  • the semiconductor device structure includes: a semiconductor substrate 1000; a channel region 1008 embedded in the semiconductor substrate 1000; and a gate stack formed on the channel region 1008.
  • the gate dielectric layer 1009 on the channel region and the gate electrode 10 ⁇ 5 on the gate dielectric layer are included; the source/drain regions 1012 are located on both sides of the channel region 1008, and the impurity concentration at the same depth is uniform.
  • the material of the channel region comprises a combination of one or more of Si, Si:C, GaN AlGaN, InP and SiGe.
  • the insulating layer 1007 may include a combination of any one or more of Si 3 N 4 , SiO 2 , SiO x : F, SiCOH, SiO x , SiO 2 : C:, SiCON, and SiONx, and may have a thickness of 5 to 50 nm.
  • the bottom of the insulating layer 1007 is higher than the bottom of the STI 1001 shown in the figure for better isolation. '
  • the outer wall 101 1 is formed on the outer side of the gate electrode line 1010 or on the outer side of the inner side spacer 1004 (the latter case is shown).
  • the shape of the outer wall shown in Fig. 1 1 , Fig. 1 1a and Fig. 1 ib is only illustrative.
  • a metal silicide contact is formed on the source/drain region 1012 and the gate electrode line 1010.
  • the specific formation method can also refer to the above embodiment, and the result is a structure as shown in Fig. 12a.
  • the gate electrode line 1010 and the outer wall 101 1 are cut by a laser dicing etching or reactive ion etching (RIE) over the STI 1001 to form a slit 1014, and a gate electrically isolated from each other.
  • the electrode 1015 can also be cut and cut at the same time. For the sake of convenience, only two slits are shown in the figure, which can be completely Select to cut as needed.
  • the gate electrode line is cut after the gate electrode line is formed, but in other subsequent processes, such as in the formation of the outer wall, the insulating material of the outer wall is not easily filled due to the small incision. Going in, it is likely to cause a short circuit between the gate electrodes in other subsequent processes. For example, when a metal silicide is formed, it is likely to cause a short circuit between the gate electrodes.
  • the gate line is cut after the formation of the metal silicide, and the insulating medium is filled in the subsequent process, so that the short circuit between the adjacent gate electrodes can be effectively prevented. Even if the slit is cut small, the electrical isolation between the gate electrodes can be effectively achieved. This method simplifies the process by avoiding the need for high-precision masks and OPCs.
  • the dielectric material 1016 fills the slits 1014, further determining the electrical isolation between the gate electrodes 1015.
  • the contact holes and contacts can then be formed in a conventional manner to complete the device structure.
  • the conventional method will not be described here.
  • the semiconductor device structure includes: a semiconductor substrate 1000; a channel region 1008 embedded in the semiconductor substrate 1000; and a gate stack formed on the channel region 1008.
  • the gate dielectric layer 1009 and the gate electrode 1015 are included; the source/drain regions 1012 are located on both sides of the channel region 1008, and the impurity concentration at the same depth is uniform.
  • the material of the channel region 1008 comprises a combination of one or more of Si, Si: C, GaN, AlGaN, InP or SiGe.
  • an insulating layer 1007 is included between the bottom of the channel region 1008 and the semiconductor substrate 1000.
  • the insulating layer 1007 may include a combination of any one or more of Si 3 N 4 , Si ⁇ 2 , SiO x : F, SiC OH, SiO x , SiO 2 : C, SiCON, and SiONx.
  • the bottom of the insulating layer 1007 is higher than the bottom of the STI 1001 shown in the figure to achieve the effect of isolation.
  • the semiconductor device structure includes a gate inner wall 1004 formed only on both sides of the gate electrode 1015; the outer wall 101 1 is formed outside the gate inner wall 1004; and in the direction of the gate width, the inside of the gate The ends of the wall 1004 and the outer wall 101 1 are aligned with the ends of the gate electrode 1015.
  • dielectric material 1016 is filled between adjacent gate electrodes in the direction of the gate width to form electrical isolation between the gate electrodes.
  • the distance between adjacent gate electrodes is preferably from 1 to 10 nm.
  • the gate electrodes are parallel slits, and the dielectric material is filled between the slits, thereby effectively isolating the gate electrodes to achieve better Device performance.
  • the method of gate electrode line cutting employed in the embodiment of the present invention can greatly reduce the proximity effect which causes lithography, etching or OPC to become complicated, making the gate electrode easier to etch, and the width of the gate electrode can be more easily controlled.
  • the method employed by embodiments of the present invention simplifies design standards and further reduces chip size.
  • Embodiments of the present invention are also advantageous for high k dielectric metal gate processes of 45 nm and below.
  • the method of gate electrode line cutting in the embodiment of the present invention can also be effectively applied to patterning of an active region.
  • 15a-16a are cross-sectional views showing structures corresponding to respective steps in a method of fabricating a semiconductor device structure in accordance with another embodiment of the present invention. After forming the structure as shown in FIG. 7, the contact portion is formed as the lower contact portion and the upper contact portion, respectively, and the gate electrode line is cut after the lower contact portion is formed. The implementation according to the present invention will be described in detail below with reference to Figures 15a-16a. A specific step of fabricating a semiconductor device structure.
  • an interlayer dielectric layer 1018 is deposited over the entire semiconductor device structure.
  • the interlayer dielectric layer 1018 may be ground to the top of the gate electrode line 1010, for example, CMP (Chemical Mechanical Polishing) may be employed.
  • CMP Chemical Mechanical Polishing
  • a lower contact hole is formed on the interlayer dielectric layer 1018, and a conductive material such as metal such as W is filled therein to form the lower contact portion 1019.
  • the entire semiconductor device structure is then grounded to the top of the gate electrode line 1010, thus forming a lower contact portion 1019 which is the same height as the top of the gate conductor layer.
  • the gate electrode line 1010 is cut, and the gate electrode 1015 and the parallel slit 1014 for electrically isolating between the gate electrodes 1015 are formed.
  • an interlayer dielectric layer 1020 is deposited over the entire semiconductor device structure, at which point the dielectric material of the interlayer dielectric layer can fill the parallel slits 1014.
  • the interlayer dielectric layer 1020 is then etched to form an upper contact portion on the gate electrode 1015 and the lower contact portion 1019, and similarly, a conductive material such as a metal such as W is filled therein.
  • the entire semiconductor device structure is then grounded to form an upper contact portion 1021 on the gate stack and/or source/drain regions 1012, wherein the source/drain regions 1012, the lower contacts 1019 and The contact portions 1021 are aligned.
  • embodiments of the present invention are compatible with the double contact hole forming method.
  • the short circuit between the gate electrodes can be effectively prevented, and the quality and performance of the semiconductor device can be improved.
  • Figure 16a is a cross-sectional view showing the structure of a semiconductor device obtained in accordance with still another embodiment of the present invention.
  • the structure is based on FIGS. 13, 13a and 13b, further comprising a lower contact portion 1019 and an upper contact portion 1021, wherein the top of the lower contact portion 1019 is at the same height as the top of the gate stack, in the gate stack, source/ The upper contact portion 1021 on the drain region is also high.
  • This device structure simplifies the difficulty of the contact formation process.

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Description

•种半导体器件结构及其制造方法
技术领域
本发明涉及半导体器件设计及其制造技术领域， 特别涉及一种在 栅极形成之前自对准形成源 /漏区的 CMOS器件的制造方法及其结构。 背景技术
随着半导体技术的发展， 对 CMOS (互补金属氧化物半导体） 器 件的性能和特征尺寸的要求越来越高， 尤其是在 45纳米及以下工艺集 成中， 替代栅（ replacement gate )工艺有广泛应用。 图 1为现有技术中 典型的后栅工艺示意图，包括先形成牺牲栅 100，接着形成源 /漏区 200、 侧墙 300和源 /漏区硅化物覆盖层 400， 然后去除牺牲栅 100以在侧墙 300的内壁形成开口 500， 最后在开口中形成替代栅堆叠。 这种工艺的 优点在于， 替代栅堆叠形成在源 /漏区生成之后， 从而避免了高温退火 以及其他的源 /漏工艺对栅堆叠中的介质和导体的不良影响。
但是此工艺存在以下缺陷： 替代栅工艺复杂成本高； 在 CMOSFET (互补金属氧化物半导体场效应晶体管） 中集成接触孔变得越来越困 难； 在 CMOS器件中实现高 k介质 /金属栅工艺更加困难。 因而开发既 具备替代栅工艺的有益效果， 又能够改进其工艺缺陷的新型制造技术 势在必行。 发明内容
本发明的目的旨在至少解决上述技术问题之一， 特别是不必借助 牺牲栅而达到替代栅工艺的效果， 从而避免了替代栅工艺的诸多缺陷。
为达到上述目的， 一方面， 本发明提出一种半导体器件结构的制 造方法， 包括： 提供半导体衬底; 在所述半导体衬底上形成第一绝缘 层； 嵌入所述第一绝缘层和半导体衬底形成浅沟槽隔离； 嵌入所述半 导体衬底形成沟道区； 形成所述沟道区上的栅堆叠线； 其中， 在形成 所述沟道区之前， 所述方法进一步包括： 对所述半导体衬底进行源 /漏 区注入。
优选地， 其中第一绝缘层包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx中的任一种或多种的组合。
可选地， 如果在形成所述第一绝缘层之前进行源 /漏区注入， 则形 成所述浅沟槽隔离之后， 所述方法进一步包括： 回刻所述笫一绝缘层； 在回刻后的第一绝缘层上形成第二绝缘层， 所述第二绝缘层与第一绝 缘层的材料相同； 则形成所述沟道区时， 进一步包括将所述沟道区上 方的第二绝缘层也进行刻蚀。
可选地， 如果在形成所述浅沟槽隔离之后进行源 /漏区注入， 则形 成所述浅沟槽隔离之后， 所述方法进一步包括： 去除覆盖在有源区上 的所述第一绝缘层； 对所述半导体衬底进行源 /漏区注入； 在所述半导 体衬底上形成第二绝缘层， 所述第二绝缘层与第一绝缘层的材料相同； 则形成所述沟道区时， 包括将所述沟道区上方的第二绝缘层进行刻蚀。
优选地， 形成所述沟道区包括： 嵌入所述第一绝缘层和半导体衬 底形成条状凹槽， 所述凹槽的底部高于所述浅沟槽隔离的底部； 在所 述凹槽底部形成第三绝缘层； 在所述凹槽内、 所述第三绝缘层上形成 沟道区。
优选地， 所述第三绝缘层包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:.C、 SiCON和 SiONx中的任一种或多种的组合。
优选地， 形成所述沟道区的方法包括： 以所述凹槽内暴露的侧壁 为源外延生长沟道区。
优选地， 所述沟道区的材料包括 Si、 Si:C、 GaN、 AlGaN、 InP和
SiGe 中任一种或多种的组合。 这样能够根据需要选择沟道区的组成材 料。
优选地， 形成所述沟道区之后还包括： 在所述沟道区之上、 沿所 述沟槽侧壁形成栅内侧墙， 用以减小栅沟道的特征尺寸， 从而能够降 低短栅工艺的难度。
优选地， 对所述半导体衬底进行源 /漏区注入包括： 对整个半导体 衬底或所述半导体衬底上的有源区进行源 /漏区注入， 并进行退火以激 活注入的杂质。
优选地， 在所述沟道区上形成栅堆叠线， 包括： 在所述沟道区上 形成栅介质层； 在所述栅介质层上形成栅电极线； 去除所述第一绝缘 层； 环绕所述栅电极线外侧形成外侧墙； 其中， 在形成所述外侧墙之 后、 完成所述半导体器件的前道工艺之前， 将所述栅电极线进行切割 以形成电隔离的栅电极。
优选地， 将所述栅电极线进行切割包括： 采用反应离子刻蚀或激 光切割刻蚀。
优选地， 在形成所述栅堆叠线之后， 进行栅电极线的切割以形成 电隔离的栅电极； 所述方法进一步包括： 在所述半导体衬底上形成层 间介质层， 其中， 所述层间介质层将所述隔离的栅电极之间进行填充； 以及刻蚀所述层间介质层以在所述栅电极或源 /漏区上形成接触孔。
优选地， 在形成所述栅堆叠线之后， 所述方法进一步包括： 形成 第一层间介质层； 刻蚀所述第一层间介质层以在所述源 /漏区上形成下 接触孔； 在所述下接触孔中形成下接触部； 将所述栅电极线进行切割； 形成第二层间介质层； 刻蚀所述第二层间介质层以在所述栅电极线或 源 /漏区上形成上接触孔； 在所述上接触孔中形成上接触部； 其中， 在 所述源 /漏区上， 所述下接触部与上接触部对齐。 可见， 本发明的实施 例还可以兼容双接触孔工艺。
另一方面， 本发明还提出一种根据上述方法制造的半导体器件结 构， 包括： 半导体衬底； 沟道区， 内嵌于所述半导体衬底中； 栅堆叠， 位于所述沟道区上， 包括位于沟道区上的栅介质层和位于栅介质层上 的栅电极； 源 /漏区， 位于所述半导体衬底中沟道区的两侧， 在所述沟 道区和栅堆叠形成之前通过对所述半导体衬底进行源 /漏区注入形成， 从而所述源 /漏区中位于同一深度的杂质浓度均匀。
优选地， 所述沟道区的材料包括 Si、 Si:C、 GaN、 AlGaN、 InP和 SiGe中一种或多种的组合。
优选地， 所述沟道区通过外延生长形成。 绝缘层。
优选地， 在所述半导体衬底中形成有浅沟槽隔离， 且所述绝缘层 的底部高于所述浅沟槽隔离的底部。
优选地， 所述绝缘层包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx中任一种或多种的组合。
优选地， 所述半导体器件结构， 进一步包括栅内侧墙， 形成在所 述沟道区之上、 所述栅堆叠的两侧， 且沿栅宽的方向上， 所述内侧墙 的端部与所述栅电极的端部相齐。 优选地， 所述半导体器件结构， 进一步包括外侧墙， 形成在所述 栅堆叠的两侧， 且沿栅宽的方向上， 所述外侧墙的端部与所述栅电极 的端部相齐。
优选地， 所述半导体器件结构， 其中， 沿栅宽的方向上， 相邻的 栅电极之间填充有介质材料以形成栅堆叠之间的电隔离。
优选地， 所述半导体器件结构， 沿栅宽的方向上， 相邻的栅电极 之间的距离为 1-10 nm。
优选地， 所述半导体器件结构， 进一步包括下接触部和上接触部， 所述下接触部与源 /漏区接触并与栅堆叠的顶部同高， 所述上接触部与 栅堆叠的顶部和下接触部分别接触； 其中， 在所述源 /漏区上， 所述下 接触部与上接触部对齐。
本发明提出一种在沟道区和栅堆叠形成之前通过对半导体衬底进 行注入， 以自对准的方式形成源 /漏区的方法， 实现不必借助牺牲栅而 达到替代栅工艺的有益效果， 从而简化工艺、 降低成本。 另外， 在形 成沟道区之前进行源 /漏区注入， 则避免了现有技术中形成源 /漏区容易 造成的杂质扩散现象。 并且， 通过增加栅内侧墙， 能够有效调节栅沟 道的特征尺寸。 另外， 通过应用有效增大载流子迁移率的外延沟道， 大大增强 MOSFET的器件性能。 此外， 本发明的实施例还结合栅电极 线切割的一种独特工艺， 能够有效提高栅电极之间的绝缘效果以及简 化栅电极刻蚀、 光刻以及降低 OPC ( Optical Proximity Correction, 光 学临近效应校正） 的难度， 本工艺还兼容于高 k介质 /金属栅工艺。
本发明附加的方面和优点将在下面的描述中部分给出， 部分将从 下面的描述中变得明显， 或通过本发明的实践了解到。 附图说明
本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的 描述中将变得明显和容易理解， 本发明的附图是示意性的， 因此并没 有按比例绘制。 其中：
图 1为现有技术的替代栅工艺示意图；
图 2-16a 为本发明实施例的半导体器件结构的制造方法的中间步 骤的结构剖面图；
其中， 图号中带有下标 a表示为沿俯视图中 AA，方向的剖面图， 图号中带有下标 b表示为沿俯视图中 BB，方向的剖面图；图号中带有下 标 c的表示沿俯视图中 CC，方向的剖面图。 具体实施方式
下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 类似功能的元件。5 面通过参 附图描 实施例是示^ 生的， 于解释本发明， 而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不 同结构。 为了简化本发明的公开， 下文中对特定例子的部件和设置进 行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了简 化和清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关 系。 此外， 本发明提供了各种特定的工艺和材料的例子， 但是本领域 普通技术人员可以意识到其他工艺的可应用性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上" 的结构可以包括第一 和第二特征形成为直接接触的实施例， 也可以包括另外的特征形成在 第一和第二特征之间的实施例，. 这样第一和第二特征可能不是直接接 触。
图 2-16a 示出了根据本发明的实施例制造半导体器件结构的中间 步骤的结构剖面图。以下将结合图 2- 16a详细说明根据本发明实施例制 造半导体器件结构的方法以及由此得到的器件结构。
如图 2和图 2c所示， 提供半导体衬底 1000。 在本实施例中， 衬底 1000 以体硅为例， 但实际应用中， 衬底可以包括任何适合的半导体衬 底材料， 具体可以是但不限于硅、 锗、 锗化硅、 SOI (绝缘体上硅） 、 碳化硅、 砷化镓或者任何 III/V族化合物半导体等。 根据现有技术公知 的设计要求 （例如 p型衬底或者 n型衬底） ， 衬底 1000可以包括各种 掺杂配置。 此外， 衬底 1000可以可选地包括外延层， 可以被应力改变 以增强性能。
根据本发明一个优选的实施例， 在形成第一绝缘层 1003之前进行 源 /漏区注入， 具体方法如下： 首先对半导体衬底 1000的全部区域进行 离子注入， 例如可以进行 n型或 p型重掺杂并活化退火， 以在半导体 衬底的全部区域中的同一深度形成离子浓度均勾的掺杂区， 需指出地 是， 经过后续各道工艺后仍保留的掺杂区即相当于以自对准的方式形 成的源 /漏区； 然后在半导体衬底 1000表面形成第一绝缘层 1003， 第 一绝缘层 1003可以是包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON 和 SiONx 中任一种或多种的组合， 本发明的实施例优选采用 Si3N4; 然后根据需要形成的 STI 1001 的形状对该第一绝缘层 1003和 半导体村底 1000刻蚀形成凹槽， 在凹槽中填充氧化物， 例如 Si02， 以 形成浅沟槽隔离 STI 1001 , 如图 2、 图 2c所示， 图 2c即为沿图 1 中 CC，方向的剖面图。 为了方便起见， 在图 2c中仅示出了一个 STI结构 1001。 形成 STI之后， 会进行一次平坦化处理， 例如采用化学机械抛 光 ( CMP ) 。
可选地， 在形成第一绝缘层 1003之前， 还可以在半导体衬底 1000 上先形成一氧化物层， 可以通过常规的热氧化或其他淀积方法形成。 为了方便起见， 该氧化物层在图中未示出。
在形成 STI区之后， 可以选择先对第一绝缘层 1003进行回刻至比
STI的顶部低的位置， 然后再重新淀积一层第二绝缘层（图中未示出）， 第二绝缘层的材料与第一绝缘层可以相同， 形成全新的第二绝缘层有 利于形成一个更好的表面。
根据本发明另一个优选的实施例， 在形成 STI之后进行源 /漏区注 入， 如图 2、 图 2c所示， 在半导体衬底 1000上包括 STI 1001和有源 区 1002。 具体地， 首先在半导体村底 1000表面形成第一绝缘层 1003; 然后根据需要形成的 STI 1001的形状对该第一绝缘层 1003和半导体衬 底 1000刻蚀形成凹槽， 在凹槽中填充氧化物， 例如 Si02, 以形成 STI 1001 ; 然后去除覆盖在有源区 1002表面的第一绝缘层 1003， 以使有源 区暴露；接着对全部有源区 1002或者对整个半导体衬底进行离子注入， 例如可以进行 n型或 p型重掺杂并活化退火， 以在所述全部有源区中 的同一深度形成离子浓度均匀的掺杂区， 同样地， 经过后续各道工艺 后仍保留的掺杂区即相当于以自对准的方式形成的源 /漏区； 再在半导 体衬底 1000上形成第二绝缘层， 所述第二绝缘层与第一绝缘层的材料 可以相同。 为了方便起见， 后续的附图中仍然使用第一绝缘层 1003表 示。
同样可选地， 在形成第一绝缘层 1003之前， 还可以在半导体衬底 1000上先形成一氧化物层， 图中未示出。
至此根据以上两个实施例的方法， 均可以得到形成有 STI和源 /漏 区的衬底， 以下的步骤对该两个实施例而言是相同的， 故合并描述。 通过本发明实施例的方法， 预先形成源 /漏区并激活退火， 因此在后续 工艺中形成的栅极将不会经历退火高温， 有利于保持栅极的良好特性。
然后， 在形成了 STI 1001的半导体结构上涂覆一层光刻胶， 并根 据将要形成的栅电极线的形状图案化这一层光刻胶， 使得需要形成栅 电极线的部位为暴露区域， 而其他区域覆盖有光刻胶。 以形成的光刻 胶图案为掩模， 对第一绝缘层 1003和半导体衬底 1000进行选择性刻 蚀。 例如在本发明的一个实施例中， 第一绝缘层 1003 为 Si3N4, STI 中填充的是 Si02， 则这次刻蚀相对于 Si02选择刻蚀 Si3N4和 Si, 最终 形成嵌入于第一绝缘层 1003和半导体衬底 1000的凹槽 1005。凹槽 1005 的底部高于 STI 1001的底部， 这样 STI还能够起到隔离作用。
可选地， 如果在前述步骤中形成了第二绝缘层， 则刻蚀形成条状 凹槽 1005时， 从第二绝缘层开始向下刻蚀。
图 3a和图 3b分别为沿图 2中的 BB，和 CC，方向的剖面图，清楚地 显示了经过这一次选择性刻蚀的结果。 其中， 图 3a中箭头所示的凹槽 1005 的尺寸比最终的栅沟道尺寸大， 有利于光刻加工， 后续将通过内 侧墙进一步减小栅沟道的特征尺寸； 从图 3b中可以看出， 这一次刻蚀 对 STI的影响很小， 形成了很浅的凹槽 1005。
为了方便起见， 在后面的示意图中， 如果不加其它说明， 图号中 的下标 a和 b分别表示沿 AA'和 BB'方向的剖面图。
可选地， 如图 4、 图 4a和图 4b所示， 在凹槽 1005上形成第三绝 缘层 1007, 第三绝缘层 1007可以由包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx中任一种或多种的组合形成。 形成的 方法可以是热氧化、 原子层化学气相淀积（ ALCVD )或其他淀积方法， 本发明对此不做限制。 第三绝缘层 1007能够调整后面将要形成的沟道 区的厚度， 并且也能够提高器件的开关速度。 例如， 在凹槽内形成第 三绝缘层时， 可采用选择性选择性原子层化学气相 （ALCVD ) 方法在 凹槽底部形成较厚的绝缘层， 而在凹槽侧壁形成很薄或几乎没有绝缘 层的结构。 在凹槽内形成第三绝缘层时后， 可以采用选择性湿化学方 法或干化学方法刻蚀以使凹槽的侧壁暴露， 而留下一层绝缘层 （厚度 为 5-50nm ) 在凹槽底部。
接着， 如图 5、 图 5a和图 5b所示， 以凹槽 1005暴露出的侧壁为 晶源， 外延生长沟道区 1008。 例如， 可以外延生长 Si、 Si:C、 GaN、 AlGaN、 InP和 SiGe中的任一种或多种的组合， 从而形成沟道区 1008。 择 SiGe或 Si:C中的 Ge含量或者是 C含量的百分比， 从而调节沟道区 的应力。 这样形成的沟道区的厚度可调节， 并且能够选择沟道区中杂 质的浓度， 能够产生应力， 因此能够有效提高载流子的迁移率， 改善 器件性能。
至此， 半导体衬底 1000中的掺杂区域（即有源区 1002 )除沟道区
1008之外的区域即自对准地形成为源 /漏区 1012,分别位于沟道区的两 侧， 如图 5a所示。
可选地， 形成沟道区之后， 在沟道区 1008之上的凹槽 1005侧壁 形成内侧墙 1004。 具体方法可以如下： 在沟道区 1008的上方进行原子 层沉积 （ALD ) 以形成填^层， 然后选择性刻蚀该填充层以形成栅内 侧墙 1004， 栅内侧墙 1004的宽度为 l ~ 5nm， 其形状本发明不作限定， 如图 6a和图 6b所示形状仅为示意。 其中， 填充层的材料可以为氧化 物、 氮化物或低 k材料， 如氧化硅 （Si02 ) 或氮化硅 （Si3N4 ) ， 低 k 材料例如可以是： SiOx:F、 SiCOH、 SiOx、 Si02:C, SiCON等。 通过形 成栅内侧墙， 能够进一步减小栅长， 从而能够降低短栅工艺的难度。 例如， 沟道区 1008的宽度为 30nm, 栅内侧墙 1004的宽度为 5nm, 通 过 30nm的刻蚀工艺就得到了 20nm的栅长， 因此降低了短栅工艺的难 度。
接着可以通过常规方法或本发明实施例的方法形成栅堆叠线。 需 注意地是， 由于源 /漏区在沟道形成之前已经形成并且经过高温退火， 因此栅堆叠可以直接形成， 而不需要为了热预算的目的而采用替代栅 工艺， 从而简化工艺， 降低成本。
如图 7、 图 7a和图 7b所示， 在沟道区上形成栅介质层 1009。 栅 介质层 1009可以是常规介质材料， 也可以是高 k介质材料， 例如可以 是 Hf02、 HfSiO、 HfSiONx, HfTaO, Hf iO、 HfZrO、 A1203、 La203、 Zr02、 LaAlO中的任一种或多种。 形成栅介质层的方法可以是热氧化、 溅射、 淀积等方法或其他方法。 高 k栅介质层能够抑制器件的短沟道 效应。 接着， 在栅介质层 1009上形成栅电极线 1010。 具体地， 可以整 个半导体器件结构上淀积一层导电材料， 例如可以是 p0ly-Si、 Ti、 Co、 Ni、 Al、 W、 金属合金等材料或其他材料， 接着用 CMP (化学机械抛 光） 处理整个半导体器件结构， 并停止于第一绝缘层 1003上。
从图 7b可以看出， STI 1001上的栅电极线 1010很薄。
接着将第一绝缘层 1003去除， 可以采用干刻或湿刻等方法进行， 例如对于 Si3N4可以采用热磷酸（ Hot phosphoric acid )进行刻蚀。 从而 形成如图 8a、 图 8b所示的结构。
接着， 可选地， 将图 8a中高出衬底 1000的 STI 1001去除， 例如 可以采用 HF腐蚀。
在常规的工艺中， 本发明的实施例可以再采用一次光刻掩模， 将 栅电极线切割为栅电极。 如图 9所示， 采用常规工艺将栅电极线 1010 进行切割， 从而形成电隔离的栅电极 1015。 图 9中示意性地示出了采 用掩模板刻蚀出的切口 1017， 切口的形成完全可以根据器件的需要。
接着， 在栅电极 1015的外侧形成外侧墙 101 1， 本发明的实施例对 形成侧墙的形状以及材料不做限制， 因此图 10、 图 10a所示侧墙形状 仅为示意。 如果实施了可选方案中的栅内侧墙， 则外侧墙 101 1形成在 栅内侧墙 1004的外侧。
可以根据需要在源 /漏区 1012和栅电极 1015上形成金属硅化物接 触。 首先， 在整个半导体器件结构上淀积一层金属， 如 Ni、 Co、 W等 金属， 然后进行快速退火形成金属硅化物接触， 再将未反应的金属去 除。 最终形成了如图 10a所示的金属硅化物 1013。 在将金属去除的同 时， 可能将 STI上很薄的栅电极线 1010的金属去除， 如图 10b所示。
至此就形成了根据本发明的一个实施例得到的半导体器件结构。 如图 10、 图 10a和图 10b所示， 该半导体器件结构包括： 半导体衬底 1000; 沟道区 1008 , 内嵌形成于所述半导体衬底 1000中； 栅堆叠， 形 成于沟道区 1008上， 包括位于沟道区上的栅介质层 1009和位于栅介 质层上的栅电极 10Γ5; 源 /漏区 1012， 位于沟道区 1008的两侧， 且位 于同一深度的杂质浓度均匀。
优选地， 沟道区的材料包括 Si、 Si:C、 GaN AlGaN、 InP和 SiGe 中一种或多种的组合。
并且， 在沟道区 1008的底部与半导体衬底 1000之间包括绝缘层 1007ο 该绝缘层 1007可以包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C：、 SiCON和 SiONx中任一种或多种的组合，厚度可以为 5-50nm。
绝缘层 1007的底部高于图中所示的 STI 1001的底部，以达到更好 的隔离效果。 '
以下描述根据本发明的另一实施例制造半导体器件结构的方法。 在图图 8、 图 8a和图 8b的基础上， 此时不直接进行栅电极线的切割， 而按照以下的步骤进行。
如图 1 1、 图 1 1a和图 l ib所示， 在栅电极线 1010的外侧或者栅内 侧墙 1004的外侧（图中所示为后者情形）形成外侧墙 101 1。 具体的方 法可以参照上述实施例所述的方法， 这里不再赘述。 因此图 1 1、 图 1 1a 和图 l ib所示的外侧墙形状仅为示意。
接着， 在源 /漏区 1012和栅电极线 1010上形成金属硅化物接触。 具体的形成方法同样可以参照以上的实施例， 结果形成了如图 12a 所 示的结构。
可以选择在这个时候进行栅电极线 1010的切割。 如图 13所示， 采用激光切割刻蚀或反应离子刻蚀（RIE )在 STI 1001的上方对栅电极 线 1010和外侧墙 101 1进^"切割， 从而形成切口 1014, 以及相互电隔 离的栅电极 1015。 可选地对于图 10b所示的位于 STI上方的栅电极线 1010也可同时被切割断开。 为了方便起见， 图中只示出了两个切口， 对于本发明来说， 完全可以根据需要选择进行切割。
在常规的工艺中， 是在栅电极线形成之后进行栅电极线的切割， 但是在后续其他的工艺中， 例如在外侧墙的形成中， 由于切口较小， 外侧墙的绝缘材料很不容易填充进去， 很可能在后续的其他工艺中造 成栅电极之间的短路。 例如， 在形成金属硅化物时， 很可能导致栅电 极之间短路。 但是在本发明中， 在金属硅化物形成之后进行栅极线的 切割， 在后续的工艺中将填充绝缘介质， 能够有效防止相邻的栅电极 之间短路。 即使将切口切得很小， 也能够有效达到栅电极之间的电隔 离要求。 本方法避免了高精度的掩模和 OPC的要求， 简化了工艺。
接着， 可以进行层间介质层的淀积。 如图 14、 图 14a和图 14b所 示， 淀积了层间介质层后， 介质材料 1016将切口 1014填满， 进一步 确定了栅电极 1015之间的电隔离。
然后可以按照常规的方法形成接触孔和接触部， 以完成器件结构， 常规方法这里不再赘述。
至此就形成了根据本发明的另一实施例得到的一个半导体器件结 构。 如图 14、 图 14a和图 14b所示， 该半导体器件结构包括： 半导体 衬底 1000; 沟道区 1008 , 内嵌形成于所述半导体衬底 1000 中； 栅堆 叠， 形成于沟道区 1008上， 包括栅介质层 1009和栅电极 1015; 源 /漏 区 1012， 位于沟道区 1008的两侧， 且位于同一深度的杂质浓度均匀。
优选地， 沟道区 1008的材料包括 Si、 Si:C、 GaN、 AlGaN、 InP或 SiGe中一种或多种的组合。 并且， 在沟道区 1008的底部与半导体衬底 1000之间包括绝缘层 1007。 该绝缘层 1007 可以包括 Si3N4、 Si〇2、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx 中任一种或多种的 组合。 绝缘层 1007的底部高于图中所示的 STI 1001的底部， 以达到隔 离的效果。
在上述方案的基础上， 该半导体器件结构包括栅内侧墙 1004, 仅 形成在栅电极 1015的两侧； 外侧墙 101 1 , 形成在栅内侧墙 1004外侧； 并且沿栅宽的方向上， 栅内侧墙 1004和外侧墙 101 1 的端部与栅电极 1015的端部相齐。
优选地，沿栅宽的方向上，相邻的栅电极之间填充有介质材料 1016 以形成栅电极之间的电隔离。相邻的栅电极之间的距离优选为 l-10nm。
在本发明的实施例半导体器件结构中， 平行于栅宽的方向上， 栅 电极之间为平行切口， 切口之间填充有介质材料， 能够有效地将栅电 极之间进行隔离， 实现更好的器件性能。
本发明实施例采用的栅电极线切割的方法能够大大减小导致光 刻、 刻蚀或 OPC变得复杂的临近效应， 使得栅电极更容易刻蚀， 栅电 极的宽度更容易控制。 对于半导体工艺流程标准来说 本发明实施例 采用的方法使得设计标准简化， 能够进一步减小芯片尺寸。
本发明的实施例还有利于 45nm及以下的高 k介质金属栅工艺。本 发明实施例中栅电极线切割的方法也可以有效应用于有源区的图案 化。
图 15a-16a 为根据本发明的另一实施例制造半导体器件结构的方 法中各步骤对应的结构剖面图。 在形成如图 7 所示的结构之后， 将接 触部分为下接触部和上接触部分别形成， 并且在形成下接触部之后进 行栅电极线的切割。以下将结合图 15a-16a详细说明根据本发明的实施 例制造半导体器件结构的具体的步骤。
如图 15a所示， 在整个半导体器件结构上淀积层间介质层 1018， 可选地可将层间介质层 1018磨平至栅电极线 1010的顶部露出， 例如 可以采用 CMP (化学机械抛光）。 然后在层间介质层 1018上形成下接 触孔，并在其中填充导电材料，例如 W等金属，从而形成下接触部 1019。 再将整个半导体器件结构进行磨平处理，至栅电极线 1010的顶部露出， 这样就形成了与栅极导体层顶部同高的下接触部 1019。
这时， 可如图 13所示， 进行栅电极线 1010的切割， 形成栅电极 1015以及将栅电极 1015之间进行电隔离的平行切口 1014。
如图 16a所示，在整个半导体器件结构上再淀积层间介质层 1020, 则此时层间介质层的介质材料能够将平行切口 1014进行填充。 然后刻 蚀层间介质层 1020 , 以在栅电极 1015上以及下接触部 1019上形成上 接触部， 同样地， 在其中填充导电材料， 例如 W等金属。 再将整个半 导体器件结构进行磨平处理， 就形成了位于栅堆叠和 /或源 /漏区 1012 上的上接触部 1021 , 其中， 在源 /漏区 1012上， 所述下接触部 1019与 上接触部 1021对齐。
可见， 本发明的实施例， 能够兼容双接触孔形成方法。 在形成双 接触孔的过程中， 能够有效地防止栅电极之间短路， 提高半导体器件 的质量和性能。
如图 16a 所示， 为根据本发明再一实施例得到的半导体器件结构 的剖面图。 其中， 该结构在图 13、 13a和图 13b的基础之上， 进一步 包括下接触部 1019和上接触部 1021 , 其中下接触部 1019的顶部与栅 堆叠的顶部同高， 在栅堆叠、 源 /漏区上的上接触部 1021则也同高。 这 种器件结构能够简化接触形成工艺的难度。
尽管已经示出和描述了本发明的实施例， 对于本领域的普通技术 人员而言， 应该知道本发明的应用范围不局限于说明书中描述的特定 实施例的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发 明的公开内容， 作为本领域的普通技术人员将容易地理解， 对于目前 已存在或者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明描述的对应实施例大体相同的功 能或者获得大体相同的结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利要求旨在将这些工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内

Claims

权 利 要 求
1. 一种半导体器件结构的制造方法， 包括：
提供半导体衬底；
在所述半导体衬底上形成第一绝缘层；
嵌入所述第一绝缘层和半导体衬底形成浅沟槽隔离；
嵌入所述半导体衬底形成沟道区；
形成所述沟道区上的栅堆叠线；
其中， 在形成所述沟道区之前， 所述方法进一步包括： 对所述半 导体村底进行源 /漏区注入。
2. 根据权利要求 1所述的方法， 其中所述第一绝缘层包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx中的任一种或 多种的组合。
3. 根据权利要求 1 所述的方法， 其中， 在形成所述第一绝缘层之 前进 4亍源 /漏区注入；
在形成所述浅沟槽隔离之后， 所述方法进一步包括： 回刻所述第 一绝缘层； 在回刻后的第一绝缘层上形成第二绝缘层， 所述第二绝缘 层与第一绝缘层的材料相同；
在形成所述沟道区时， 进一步包括将所述沟道区上方的第二绝缘 层也进行刻蚀。
4. 根据权利要求 1所述的方法， 其中， 在形成所述浅沟槽隔离之 后进行源 /漏区注入；
在形成所述浅沟槽隔离之后， 所述方法进一步包括： 去除覆盖在 有源区上的所述第一绝缘层； 对所述半导体衬底进行源 /漏区注入； 在 所述半导体衬底上形成第二绝缘层， 所述第二绝缘层与第一绝缘层的 材料相同；
在形成所述沟道区时， 包括将所述沟道区上方的第二绝缘层进行 刻蚀。
5. 根据权利要求 1所述的方法， 其中， 形成所述沟道区包括： 嵌入所述第一绝缘层和半导体衬底形成条状凹槽， 所述凹槽的底 部高于所述浅沟槽隔离的底部；
在所述凹槽底部形成第三绝缘层； 在所述凹槽内、 所述第三绝缘层上形成沟道区。
6. 根据权利要求 5所述的方法， 其中所述第三绝缘层包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx中的任一种或 多种的组合。
7. 根据权利要求 5所述的方法，其中形成所述沟道区的方法包括： 以所述凹槽内暴露的侧壁为源外延生长沟道区。
8. 根据权利要求 1所述的方法， 所述沟道区的材料包括 Si、 Si:C、 GaN、 AlGaN、 InP和 SiGe中任一种或多种的组合。
9. 根据权利要求 1所述的方法，其中形成所述沟道区之后还包括： 在所述沟道区之上、 沿所述沟槽侧壁形成栅内侧墙。
10. 根据权利要求 1所述的方法， 其中， 对所述半导体衬底进行源 /漏区注入包括： 对整个半导体衬底或所述半导体衬底上的有源区进行 源 /漏区注入， 并进行退火以激活注入的杂质。
11. 根据权利要求 1至 10中任一项所述的方法， 其中在所述沟道 区上形成栅堆叠线， 包括：
在所述沟道区上形成栅介质层；
在所述栅介盾层上形成栅电极线；
去除所述第一绝缘层；
环绕所述栅电极线外侧形成外侧墙；
其中， 在形成所述外侧墙之后、 完成所述半导体器件的前道工艺 之前， 将所述栅电极线进行切割以形成电隔离的栅电极。
12. 根据权利要求 1 1所述的方法，将所述栅电极线进行切割包括： 采用反应离子刻蚀或激光切割刻蚀。
13. 根据权利要求 1 1所述的方法， 其中， 在形成所述栅堆叠线之 后， 进行栅电极线的切割以形成电隔离的栅电极； 所述方法进一步包 括：
在所述半导体衬底上形成层间介质层， 其中， 所述层间介质层将 所述隔离的栅电极之间进行填充； 以及
14. 根据权利要求 1 1所述的方法， 其中， 在形成所述栅堆叠线之 后， 所述方法进一步包括：
形成第一层间介质层； 刻蚀所述第一层间介质层以在所述源 /漏区上形成下接触孔； 在所述下接触孔中形成下接触部；
将所述栅电极线进行切割；
形成第二层间介质层；
刻蚀所述第二层间介盾层以在所述栅电极线或源 /漏区上形成上接 触孔；
在所述上接触孔中形成上接触部；
其中， 在所述源 /漏区上， 所述下接触部与上接触部对齐。
15. 一种半导体器件结构， 包括：
半导体衬底；
沟道区， 内嵌于所述半导体衬底中；
栅堆叠， 位于所述沟道区上， 包括位于沟道区上的栅介质层和位 于栅介质层上的栅电极；
源 /漏区， 位于所述半导体衬底中沟道区的两侧， 在所述沟道区和 栅堆叠形成之前通过对所述半导体衬底进行源 /漏区注入形成， 从而所 述源 /漏区中位于同一深度的杂质浓度均匀。
16. 根据权利要求 15所述的半导体器件结构， 所述沟道区的材料 包括 Si、 Si:C、 GaN、 AlGaN、 InP和 SiGe中一种或多种的组合。
17. 根据权利要求 15所述的半导体器件结构， 所述沟道区通过外 延生长形成。
18. 根据权利要求 15所述的半导体器件结构， 在所述沟道区的底 部与所述半导体衬底之间进一步包括绝缘层。
19. 根据权利要求 18所述的半导体器件结构， 在所述半导体村底 中形成有浅沟槽隔离， 且所述绝缘层的底部高于所述浅沟槽隔离的底 部。
20. 根据权利要求 18 所述的半导体器件结构， 所述绝缘层包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C；、 SiCON和 SiONx 中任 一种或多种的组合。
21. 根据权利要求 15至 20中任一项所述的半导体器件结构，进一 步包括栅内侧墙， 形成在所述沟道区之上、 所述栅堆叠的两侧， 且沿 栅宽的方向上， 所述内侧墙的端部与所述栅电极的端部相齐。
22. 根据权利要求 21所述的半导体器件结构，进一步包括外侧墙， 形成在所述栅堆叠的两侧， 且沿栅宽的方向上， 所述外侧墙的端部与 所述栅电极的端部相齐。
23. 根据权利要求 22所述的半导体器件结构， 其中， 沿栅宽的方 向上， 相邻的栅电极之间填充有介质材料以形成栅堆叠之间的电隔离。
24. 根据权利要求 22所述的半导体器件结构， 沿栅宽的方向上， 相邻的栅电极之间的距离为 1 -10 nm。
25. 根据权利要求 22所述的半导体器件结构， 进一步包括下接触 部和上接触部， 所述下接触部与源 /漏区接触并与栅堆叠的顶部同高， 所述上接触部与栅堆叠的顶部和下接触部分别接触；
其中， 在所述源 /漏区上， 所述下接触部与上接触部对齐。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120306000A1 (en) * 2011-05-31 2012-12-06 International Business Machines Corporation Formation of Field Effect Transistor Devices
US8828834B2 (en) * 2012-06-12 2014-09-09 Globalfoundries Inc. Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process
CN103633029B (zh) * 2012-08-28 2016-11-23 中国科学院微电子研究所 半导体结构及其制造方法
CN103681461B (zh) * 2012-09-10 2016-06-01 中国科学院微电子研究所 半导体器件结构及其制作方法
KR101878754B1 (ko) 2012-09-13 2018-07-17 삼성전자주식회사 대면적 갈륨 나이트라이드 기판 제조방법
US8835237B2 (en) 2012-11-07 2014-09-16 International Business Machines Corporation Robust replacement gate integration
US8921188B2 (en) * 2013-02-07 2014-12-30 Globalfoundries Inc. Methods of forming a transistor device on a bulk substrate and the resulting device
US9263270B2 (en) 2013-06-06 2016-02-16 Globalfoundries Inc. Method of forming a semiconductor device structure employing fluorine doping and according semiconductor device structure
CN104952725B (zh) * 2014-03-24 2018-02-06 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
WO2015171873A1 (en) * 2014-05-07 2015-11-12 Cambridge Electronics, Inc. Transistor structure having buried island regions
US20160079167A1 (en) * 2014-09-12 2016-03-17 Qualcomm Incorporated Tie-off structures for middle-of-line (mol) manufactured integrated circuits, and related methods
KR102504165B1 (ko) * 2014-09-26 2023-02-28 인텔 코포레이션 반도체 디바이스들에 대한 선택적 게이트 스페이서들
CN106601674B (zh) * 2015-10-14 2019-08-06 中国科学院微电子研究所 半导体晶体管金属栅的集成工艺方法
US9679965B1 (en) * 2015-12-07 2017-06-13 Samsung Electronics Co., Ltd. Semiconductor device having a gate all around structure and a method for fabricating the same
CN108538848B (zh) * 2018-06-21 2024-01-16 长江存储科技有限责任公司 半导体结构及其形成方法
CN111128895A (zh) * 2018-10-30 2020-05-08 长鑫存储技术有限公司 半导体器件及其制作方法
KR20210027678A (ko) * 2019-08-30 2021-03-11 삼성디스플레이 주식회사 표시 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
US20050104055A1 (en) * 2002-12-06 2005-05-19 Hynix Semiconductor Inc. Transistor of semiconductor device, and method for manufacturing the same
JP2005209980A (ja) * 2004-01-26 2005-08-04 Sony Corp 半導体装置の製造方法および半導体装置
CN101006569A (zh) * 2004-08-25 2007-07-25 英特尔公司 形成突变的源漏金属栅晶体管

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180465B1 (en) * 1998-11-20 2001-01-30 Advanced Micro Devices Method of making high performance MOSFET with channel scaling mask feature
JP2005072084A (ja) * 2003-08-28 2005-03-17 Toshiba Corp 半導体装置及びその製造方法
US6943087B1 (en) * 2003-12-17 2005-09-13 Advanced Micro Devices, Inc. Semiconductor on insulator MOSFET having strained silicon channel
KR100602113B1 (ko) * 2003-12-31 2006-07-19 동부일렉트로닉스 주식회사 트랜지스터 및 그의 제조 방법
KR100539269B1 (ko) * 2004-06-25 2005-12-27 삼성전자주식회사 자기정렬 부분적 ｓｏｉ 구조의 반도체 소자 및 그 제조방법
JP2006332243A (ja) * 2005-05-25 2006-12-07 Toshiba Corp 半導体装置及びその製造方法
US20080286698A1 (en) * 2007-05-18 2008-11-20 Haoren Zhuang Semiconductor device manufacturing methods
US7939384B2 (en) * 2008-12-19 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminating poly uni-direction line-end shortening using second cut
CN102347234B (zh) * 2010-07-29 2013-09-18 中国科学院微电子研究所 半导体器件结构及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
US20050104055A1 (en) * 2002-12-06 2005-05-19 Hynix Semiconductor Inc. Transistor of semiconductor device, and method for manufacturing the same
JP2005209980A (ja) * 2004-01-26 2005-08-04 Sony Corp 半導体装置の製造方法および半導体装置
CN101006569A (zh) * 2004-08-25 2007-07-25 英特尔公司 形成突变的源漏金属栅晶体管

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