WO2012013009A1 - 半导体器件结构及其制造方法 - Google Patents

半导体器件结构及其制造方法 Download PDF

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Publication number
WO2012013009A1
WO2012013009A1 PCT/CN2011/000308 CN2011000308W WO2012013009A1 WO 2012013009 A1 WO2012013009 A1 WO 2012013009A1 CN 2011000308 W CN2011000308 W CN 2011000308W WO 2012013009 A1 WO2012013009 A1 WO 2012013009A1
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Prior art keywords
insulating layer
forming
gate electrode
channel region
gate
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PCT/CN2011/000308
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English (en)
French (fr)
Inventor
钟汇才
梁擎擎
Original Assignee
中国科学院微电子研究所
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Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to GB1202338.8A priority Critical patent/GB2488634B/en
Priority to US13/131,745 priority patent/US8759923B2/en
Publication of WO2012013009A1 publication Critical patent/WO2012013009A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation

Definitions

  • the present invention relates to the field of semiconductor device design and its manufacturing technology, and more particularly to a semiconductor device structure and a method of fabricating the same that improve device performance through channel engineering. Background technique
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • the shortening of the channel length is mainly achieved by improving the semiconductor process technology and improving the processing level.
  • the channel length can now be shortened to deep submicron or even nanometer size, continuing to shorten the channel length is limited by many factors.
  • the improvement of semiconductor processing technology is difficult to adapt to the needs of semiconductor manufacturing.
  • the physical properties of the device also cause many problems, such as short channel effect, DIBL (drain induced barrier reduction) effect, device threshold voltage is too high, etc. .
  • a technical measure that is now fully recognized to effectively improve the physical properties of the device is to increase the mobility of the carriers.
  • the mobility of carriers is an important physical quantity that marks the movement of carriers under the action of an electric field. Its size directly affects the operating frequency and speed of semiconductor devices and circuits.
  • the concave height is mainly etched in the bottom of the substrate on both sides of the channel region.
  • source/drain regions with tensile stress are usually formed on both sides of the channel region, and Si:C can be formed by epitaxial growth C content to a specific ratio, thereby generating tensile stress on both sides of the channel;
  • Si:C can be formed by epitaxial growth C content to a specific ratio, thereby generating tensile stress on both sides of the channel;
  • pMOSFET It is possible to form SiGe by epitaxially growing Ge content to a specific ratio, thereby generating compressive stress on both sides of the channel.
  • This method of forming the source/drain regions does not sufficiently improve the performance of the channel region and improve the mobility of carriers. Therefore, it is necessary to propose a novel semiconductor device structure and its manufacturer. The method is to achieve an improvement in device performance. Summary of the invention
  • a - method of manufacturing a semiconductor device structure comprising: providing a semiconductor substrate; a semiconductor substrate Forming a first insulating layer on the surface; embedding the first insulating layer and the semiconductor substrate to form a shallow trench isolation STI; embedding the first insulating layer and the semiconductor substrate to form a strip-shaped recess; forming a channel region in the recess; forming a channel A gate stack line on the region and source/drain regions on both sides of the channel region.
  • the bottom of the recess is higher than the bottom of the shallow trench isolation.
  • the first insulating layer comprises a combination of any one or more of Si 3 N 4 , SiO 2 , SiO x : F, SiC OH, SiO x , SiO 2 : C, SiCON, and SiONx.
  • the first insulating layer may be etched back to a position lower than the top of the STI, and then a second insulating layer may be newly deposited, and the material of the second insulating layer and the first insulating layer may be the same.
  • forming the channel region in the recess includes: forming a third insulating layer at a bottom of the recess; and forming a channel region on the third insulating layer.
  • the third insulating layer includes a combination of any one or more of Si 3 N 4 , SiO 2 , SiO x : F, SiC OH, SiO x , SiO 2 : C, SiCON, and SiONx.
  • the step of forming the third insulating layer may include: forming a third insulating layer in the recess, the thickness of the third insulating layer on the sidewall of the recess is smaller than the thickness at the bottom of the recess; selectively etching the third insulating layer in the recess A portion of the sidewall of the trench such that the third insulating layer remains only at the bottom of the recess.
  • the step of forming the channel region may be: growing the channel region by using the exposed sidewalls in the recess as a source.
  • the material forming the channel region may include a combination of one or more of the following: Si, SiC, GaN, AlGaN, InP, and SiGe.
  • the semiconductor substrate in the embodiment of the invention may be bulk silicon.
  • the step of forming a gate stack line on the channel region may include: forming a gate dielectric layer on the channel region; forming a gate electrode line on the gate dielectric layer; and then forming the first insulating layer Removing; then forming a sidewall spacer around the outside of the gate electrode line; wherein, after forming the sidewall spacer, cutting the gate electrode line before completing the front process of the semiconductor device To form an electrically isolated gate electrode.
  • a method of cutting a gate electrode line includes reactive ion etching (RIE) or laser cutting etching.
  • the method may further include: removing the gate electrode lines to form openings in the sidewalls; forming a replacement gate electrode line within the openings.
  • the method may further include: removing the gate electrode lines to form openings in the sidewalls; forming a replacement gate electrode line within the openings.
  • the method may further include: forming an interlayer dielectric layer on the semiconductor substrate, wherein the interlayer dielectric a layer fills the isolated gate electrodes; and etching the interlayer dielectric layer to form contact holes on the gate electrode or source/drain regions.
  • the method may further include: forming a first interlayer dielectric layer; etching the first interlayer dielectric layer to form a lower contact hole on the source/drain regions; Forming a lower contact portion in the lower contact hole; forming a second interlayer dielectric layer; etching the second interlayer dielectric layer to form an upper contact hole on the gate electrode line or source/drain region; An upper contact portion is formed in the contact hole; wherein, on the source/drain region, the lower contact portion is aligned with the upper contact portion. And the cutting of the gate electrode line is performed after the lower contact portion is formed. It can be seen that embodiments of the present invention are also compatible with dual contact hole processes.
  • a semiconductor device structure comprising: a semiconductor substrate; a channel region embedded on the semiconductor substrate and formed by epitaxial growth; a gate stack formed on the channel region; Source/drain regions are formed on both sides of the channel region.
  • the material of the channel region comprises a combination of one or more of Si, SiC, GaN, AlGaN, InP and SiGe.
  • an insulating layer is included between the bottom of the channel region and the semiconductor substrate.
  • the insulating layer may include a combination of any one or more of Si 3 N 4 , SiO 2 , SiO x : F, SiC OH, SiO x , SiO 2 : C, SiCON, and SiONx, and may have a thickness of 5 to 50 nm.
  • the semiconductor device structure further includes sidewall spacers formed only on both sides of the gate electrode, and the ends of the sidewall spacers are aligned with the ends of the gate electrodes in the direction of the gate width.
  • dielectric materials are filled between adjacent gate electrodes in the direction of the gate width to form electrical isolation between the gate electrodes, and the distance between adjacent gate electrodes is l-10 nm.
  • the semiconductor device may further include a lower contact portion and an upper contact portion, the lower contact portion is in contact with the source/drain region and is at the same height as the top of the gate stack, and the upper contact portion is at the top of the top and bottom contact portions of the gate stack Contact; wherein, on the source/drain regions, the lower contact portion is aligned with the upper contact portion.
  • the invention provides a semiconductor device structure having a buried channel and a forming method thereof, and can greatly enhance the performance of the MOSFET device by forming an epitaxial channel capable of effectively increasing carrier mobility in the semiconductor substrate. .
  • embodiments of the present invention are also combined with a unique process of gate electrode line dicing, which can effectively improve the insulation effect between the gate electrodes and simplify gate electrode etching, lithography, and reduction of OPC (Optical Proximity Correction).
  • the difficulty of this process is also compatible with high-k dielectric/metal gate processes and replacement gate technology.
  • Figure 14-14a is a cross-sectional view showing the structure of an intermediate step of a method of fabricating a semiconductor device structure according to an embodiment of the present invention
  • the subscript a in the figure number indicates a cross-sectional view along the direction AA in the top view
  • the subscript b in the figure number indicates a cross-sectional view along the BB in the top view
  • the subscript c in the figure number A cross-sectional view taken along the CC' direction in the top view.
  • the following disclosure provides many different embodiments or examples for implementing different structures of the present invention.
  • the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
  • the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of brevity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • FIGS. 1-14a are cross-sectional views showing the structure of an intermediate step of fabricating a semiconductor device structure in accordance with an embodiment of the present invention.
  • a method of fabricating a semiconductor device structure and a device structure obtained thereby according to an embodiment of the present invention will be described in detail below with reference to Figs.
  • a semiconductor substrate 1000 is provided.
  • the substrate 1000 is exemplified by bulk silicon, but in practical applications, the substrate may include any suitable semiconductor substrate material, specifically but not limited to silicon, germanium, silicon germanium, and SOK insulator. Silicon), silicon carbide, gallium arsenide or any III/V compound semiconductor.
  • the substrate 1000 can include various doping configurations in accordance with design requirements well known in the art (e.g., p-type substrate or n-type substrate). Additionally, substrate 1000 can optionally include an epitaxial layer that can be stressed to enhance performance.
  • STI shallow trench isolation
  • FIG. 1c is a cross-sectional view taken along line CC in FIG.
  • the first insulating layer 1003 may be a combination including any one or more of Si 3 N 4 , SiO 2 , SiO x : F, SiCOH, SiO x , SiO 2 : C, SiCON, and SiONx, and an embodiment of the present invention is preferably employed.
  • Si 3 N 4 a combination including any one or more of Si 3 N 4 , SiO 2 , SiO x : F, SiCOH, SiO x , SiO 2 : C, SiCON, and SiONx, and an embodiment of the present invention is preferably employed.
  • Si 3 N 4 The first insulating layer 1003 and the semiconductor substrate 1000 are then etched to form a recess according to the shape of the STI 1001 to be formed, and an oxide such as SiO 2 is filled in the recess to form the STI 1001.
  • an oxide layer may be formed on the semiconductor substrate 1000 before the formation of the first insulating layer 1003, which may be formed by conventional thermal oxidation or other deposition methods. For ease of viewing, the oxide layer is not shown in the figure.
  • the first insulating layer 1003 may be etched back to a position lower than the top of the STI, and then a second insulating layer is deposited, the material of the second insulating layer and the first insulating layer. Can be the same. Forming a brand new second insulating layer facilitates the formation of a better surface.
  • the first insulating layer 1003 The semiconductor substrate 1000 is selectively etched.
  • the first insulating layer 1003 is Si 3 N 4
  • the STI is filled with Si0 2 , then this etching selectively etches Si 3 N 4 and Si with respect to SiO 2 , and finally forms.
  • a recess 1005 is embedded in the first insulating layer 1003 and the semiconductor substrate 1000. The bottom of the recess 1005 is higher than the bottom of the STI 1001 so that the STI can also provide isolation.
  • the etching is performed downward from the second insulating layer.
  • FIG. 2a and 2b are cross-sectional views taken along line BB, and CC, respectively, in Fig. 2, clearly showing the results of this selective etching. As can be seen in Figure 2b, this time the etching has little effect on the STI, forming a very shallow groove 1005.
  • a third insulating layer 1007 is formed on the recess 1005, and the third insulating layer 1007 may be composed of Si 3 N 4 , Si ⁇ 2 , SiO x : F, SiCOH. A combination of any one or more of SiO x , Si0 2 : C, SiCON, and SiONx is formed.
  • the method of formation may be thermal oxidation, atomic layer chemical vapor deposition (ALCVD) or other deposition methods, which are not limited in the present invention.
  • the third insulating layer 1007 is capable of adjusting the thickness of the channel region to be formed later, and can also increase the switching speed of the device.
  • a thicker insulating layer may be formed at the bottom of the recess by a selective atomic layer chemical vapor phase (ALCVD) method, and a thin or almost no insulating layer may be formed on the sidewall of the recess. Structure.
  • ACVD selective atomic layer chemical vapor phase
  • a thin or almost no insulating layer may be formed on the sidewall of the recess.
  • selective wet chemical or dry chemical etching may be used to expose the sidewall of the recess, leaving an insulating layer (thickness 5-50 nm) in the recess. bottom.
  • the third insulating layer 1007 is capable of adjusting the thickness of the channel region to be formed later, and can also increase the switching speed of the device.
  • the sidewall exposed by the recess 1005 is a crystal source, and the channel region 1008 is epitaxially grown.
  • the channel region 1008 is epitaxially grown.
  • a combination of any one or more of Si, SiC, GaN, AlGaN, InP, and SiGe may be epitaxially grown to form the channel region 1008.
  • the Ge content in SiGe or SiC or the percentage of the C content may be selected as needed to adjust the stress in the channel region.
  • Si:C can be epitaxially grown
  • SiGe can be epitaxially grown.
  • the thickness of the channel region thus formed can be adjusted, and the concentration of impurities in the channel region can be selected to generate stress, so that the mobility of carriers can be effectively improved and the device performance can be improved.
  • the gate stack line and the source/drain regions can then be formed by a conventional method or a method of an embodiment of the present invention.
  • a gate dielectric layer 1009 is formed over the channel region.
  • the gate dielectric layer 1009 may be a conventional dielectric material or a high-k dielectric material, and may be, for example, Hf0 2 , HfSiO x , HfSiNOx, HfTaOx, HiTiOx, HfZrOx, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO. Any one or more of them.
  • the method of forming the gate dielectric layer may be thermal oxidation, sputtering, deposition, or the like or other methods.
  • the high-k gate dielectric layer is capable of suppressing the short channel effect of the device.
  • a gate electrode line 1010 is formed on the gate dielectric layer 1009.
  • a conductive material may be deposited on the entire semiconductor device structure, for example, a material such as Poly-Si, Ti, Co, Ni, Al, W, metal alloy or the like, and then processed by CMP (Chemical Mechanical Polishing). The entire semiconductor device structure is stopped on the first insulating layer 1003.
  • the gate electrode line 1010 on the STI 1001 is very thin.
  • the first insulating layer 1003 is removed, and may be performed by dry etching or wet etching.
  • Si 3 N 4 may be etched using hot phosphoric acid. Thereby, a structure as shown in Figs. 6a and 6b is formed.
  • the STI 1001 of the substrate 1000 in Fig. 6a is removed, for example, HF etching may be employed.
  • an embodiment of the present invention may further employ a photolithographic mask to diced a gate electrode line into a gate electrode.
  • the gate electrode line 1010 is cut by a conventional process to form an electrically isolated gate electrode 1015.
  • the slit 1017 etched using the mask is schematically illustrated in Fig. 7, and the formation of the slit can be completely made according to the needs of the device.
  • sidewalls 101 are formed around the outside of the gate electrode 1015, and source/drain regions 1012 are formed on both sides of the channel region 1008.
  • the substrate regions on both sides of the channel region 1008 may be subjected to oblique ion implantation to form source/drain extension regions; alternatively, halo (Halo) ion implantation may be used to form source/drain halos.
  • the sidewall 1011 is formed on the outer side of the gate electrode 1015.
  • the embodiment of the present invention does not limit the shape and material of the sidewall. Therefore, the shape of the sidewall shown in FIG. 8 and FIG. 8a is only schematic; Heavy doping ion implantation is performed on both sides of the channel region 1008 to form source/drain regions 1012. Similarly, the shape of source/drain regions 1012 shown in Figure 8a is merely illustrative.
  • a metal silicide contact can be formed on the source/drain regions 1012 and the gate electrode 1015 as needed. First, deposit a layer of metal on the entire semiconductor device structure, such as Ni, Co, W, etc. The metal is then rapidly annealed to form a metal silicide contact, and the unreacted metal is removed. Finally, a metal silicide 1013 as shown in Fig. 9a is formed. While the metal is being removed, the metal of the very thin gate electrode line 1010 on the STI may be removed, as shown in Figure 8b.
  • the semiconductor device structure includes: a semiconductor substrate 1000; a channel region 1008 embedded in the semiconductor substrate 1000 and formed by epitaxial growth; a gate stack formed on On the channel region 1008; source/drain regions 1012 are formed on both sides of the channel region 1008.
  • the material of the channel region comprises a combination of one or more of Si, SiC, GaN, AlGaN, InP, and SiGe.
  • an insulating layer 1007 is included between the bottom of the channel region 1008 and the semiconductor substrate 1000.
  • the insulating layer 1007 may include a combination of any one or more of Si 3 N 4 , SiO 2 , SiO x : F, SiC OH, SiO x , SiO 2 : C, SiCON, and SiONx, and may have a thickness of 5 to 50 nm.
  • the lower surface of the insulating layer 1007 is higher than the bottom of the STI 1001 shown in the figure for better isolation.
  • the thickness of the channel region is adjustable, and the concentration of impurities in the channel region can be selected, and the stress can be effectively adjusted.
  • the Ge content in the SiGe or the C content in the SiC can be selected as needed. The percentage is therefore effective to improve carrier mobility and improve device performance.
  • a replacement gate process may also be selected. After the source/drain regions are formed, the gate electrode can be removed, and then the replacement gate electrode is reformed.
  • side walls 101 1 are formed on the outer side of the gate electrode line 1010, and source/drain regions 1012 are formed on both sides of the channel region 1008.
  • source/drain regions 1012 are formed on both sides of the channel region 1008.
  • the shape of the side wall and the shape of the source/drain regions shown in Figs. 9, 9a and 9b are merely illustrative.
  • a metal silicide contact is formed on the source/drain region 1012 and the gate electrode line 1010.
  • the specific formation method can also refer to the above embodiment, and the result is a structure as shown in Fig. 10a.
  • the cutting of the gate electrode line 1010 can be selected at this time. As shown in Figure 11.
  • the gate electrode line 1010 and the sidewall spacer 101 1 are cut over the STI 1001 by laser dicing etching or reactive ion etching (RIE) to form a slit 1014, and a gate electrode 1015 electrically isolated from each other.
  • the gate electrode line 1010 located above the STI shown in FIG. 9b can also be cut and disconnected at the same time. For the sake of convenience, only two slits are shown in the drawing, and for the present invention, it is entirely possible to perform cutting as needed.
  • the gate electrode line is cut after the gate electrode line of FIG. 6 is formed, but in other subsequent processes, for example, in the formation of the sidewall spacer, since the slit is small, the insulating material of the sidewall spacer is very It is not easy to fill in, and it is likely to cause a short circuit between the gate electrodes in other subsequent processes. For example, when ion implantation of a source/drain region or formation of a metal silicide is performed, it is likely to cause a short circuit between the gate electrodes.
  • the gate electrode line is cut after the formation of the metal silicide, and the insulating dielectric is filled in the subsequent process, so that the short circuit between the adjacent gate electrodes can be effectively prevented. Even if the slit is cut small, the electrical isolation requirement between the gate electrodes can be effectively achieved. This method simplifies the process by avoiding the need for high-precision masks and OPCs.
  • the dielectric material 1016 fills the slits 1014, further determining the electrical isolation between the gate electrodes 1015.
  • the contact holes and contacts can then be formed in a conventional manner to complete the device structure, which will not be described in detail herein.
  • the semiconductor device structure includes: a semiconductor substrate 1000; a channel region 1008 embedded in the semiconductor substrate 1000 and formed by epitaxial growth; a gate stack formed on On the channel region 1008; source/drain regions 1012 are formed on both sides of the channel region 1008.
  • the material of the channel region 1008 comprises Si, SiC, GaN, AlGaN, InP or
  • an insulating layer 1007 is included between the bottom of the channel region 1008 and the semiconductor substrate 1000.
  • the insulating layer 1007 may include a combination of any one or more of Si 3 N 4 , SiO 2 , SiO x : F, SiCOH, SiO x , SiO 2 : C, SiCON, and SiONx.
  • the lower surface of the insulating layer 1007 is higher than the bottom of the STI 1001 shown in the drawing to achieve the effect of isolation.
  • the semiconductor device structure includes sidewall spacers 1011 formed only on both sides of the gate electrode 1015 ⁇ and in the direction of the gate width, the end portion and the gate of the sidewall spacer 101 1 The ends of the electrodes 1015 are aligned.
  • dielectric material 1016 is filled between adjacent gate electrodes in the direction of the gate width to form electrical isolation between the gate electrodes.
  • the distance between adjacent gate electrodes is preferably from 1 to 10 nm.
  • the gate electrodes are parallel slits, and the dielectric material is filled between the slits, thereby effectively isolating the gate electrodes to achieve better Device performance.
  • an alternative gate process may also be selected. After the source/drain regions are formed, the gate electrode lines can be removed, and then the replacement gate electrode lines are reformed.
  • the method of gate electrode line cutting employed in the embodiment of the present invention can greatly reduce the proximity effect which causes lithography, etching or OPC to become complicated, making the gate electrode easier to etch, and the width of the gate electrode can be more easily controlled.
  • the method employed by embodiments of the present invention simplifies design standards and further reduces chip size.
  • Embodiments of the present invention are also advantageous for high k metal gate processes of 45 nm and below.
  • the method of gate electrode line dicing in the embodiment of the present invention can also be effectively applied to patterning of an active region.
  • FIG. 13a-14a are cross-sectional views showing structures corresponding to respective steps in a method of fabricating a semiconductor device structure in accordance with another embodiment of the present invention.
  • the contact hole is divided into a lower contact hole portion and an upper contact hole portion, respectively, and the gate electrode is formed after the lower contact hole portion is formed. Cutting of the line.
  • an interlayer dielectric layer 1018 is deposited over the entire semiconductor device structure.
  • the interlayer dielectric layer 1018 may be ground to the top of the gate electrode line 1010, for example, CMP (Chemical Mechanical Polishing) may be employed.
  • CMP Chemical Mechanical Polishing
  • a lower contact hole 1019 is formed on the interlayer dielectric layer 1018, and a conductive material such as a metal such as W is filled therein.
  • the entire semiconductor device structure is then grounded to the top of the gate electrode line 1010, thus forming a lower contact portion (shown also as 1019 in the figure) that is the same height as the top of the gate conductor layer.
  • the gate electrode line 1004 is cut, and the gate electrode 1015 and the gate 1014 which electrically isolates the gate electrode 1015 are formed.
  • an interlayer dielectric layer 1020 is deposited over the entire semiconductor device structure, at which point the dielectric material of the interlayer dielectric layer can fill the parallel slits 1014.
  • the interlayer dielectric layer 1020 is then etched to form an upper contact hole 1021 on the gate electrode 1015 and the lower contact hole 1019, and similarly, a conductive material such as a metal such as W is filled therein. Then
  • the semiconductor device structure is grounded to form a gate stack and/or source/drain regions.
  • the upper contact portion (shown also as 1021 in the figure) on the 1012, wherein the lower contact portion 1019 is aligned with the upper contact portion 1021 on the source/drain region 1012.
  • embodiments of the present invention are compatible with alternative gate technologies and are also compatible with dual contact hole formation methods.
  • double contact hole forming method short-circuiting between the gate electrodes can be effectively prevented, and the quality and performance of the semiconductor device can be improved.
  • Figure 14a is a cross-sectional view showing the structure of a semiconductor device obtained in accordance with still another embodiment of the present invention.
  • the structure is based on FIGS. 12, 12a and 12b, further comprising a lower contact portion 1019 and an upper contact portion 1021, wherein the top of the lower contact portion 1019 is at the same height as the top of the gate stack, in the gate stack, source/ The upper contact portion 1021 on the drain region is also high.
  • This device structure simplifies the process of forming a contact hole.

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Description

半导体器件结构及其制造方法 技术领域
本发明涉及半导体器件设计及其制造技术领域， 特别涉及一种通 过沟道工程改善器件性能的半导体器件结构及其制造方法。 背景技术
随着半导体制造技术的发展， 半导体器件的尺寸不断减小， 而对 半导体器件结构的制造工艺要求也越来越高。
目前半导体制造技术的进步， 在很大程度上是通过不断缩短 MOSFET (金属氧化物半导体场效应晶体管）的沟道长度实现的。 而沟 道长度的缩短主要通过改善半导体工艺技术和提高加工水平来实现。 尽管现在沟道长度已经可以缩短到深亚微米乃至纳米尺寸， 但继续缩 短沟道长度受到很多因素的限制。 一方面半导体加工工艺能力的提高 还难以适应半导体制造的需要， 另一方面器件物理性能也产生了很多 问题， 例如短沟道效应、 DIBL (漏极感应势垒降低） 效应、 器件阈值 电压过高等。
因此在进一步发展半导体制造技术过程中， 采用新的材料、 开发 新的工艺和构建新的器件结构成为半导体界共同努力的方向。 现在已 充分认识到的一种有效改善器件物理性能的技术措施就是提高载流子 的迁移率。 载流子的迁移率是标志载流子在电场作用下运动快慢的一 个重要物理量， 它的大小直接影响到半导体器件和电路的工作频率与 速度。
在现在的主流技术中， 主要通过在沟道区两侧的村底中刻蚀出凹 高。 例如， 对于 nMOSFET, 通常在沟道区两侧形成具有拉应力的源 / 漏区， 可以采用外延生长 C含量为特定比例的 Si:C形成， 从而对沟道 两侧产生拉应力； 对于 pMOSFET, 可以采用外延生长 Ge含量为特定 比例的 SiGe形成， 从而对沟道两侧产生压应力。
这种形成源 /漏区的方法还不能充分改善沟道区的性能， 提高载流 子的迁移率。 因此有必要提出一种新颖的半导体器件结构及其制造方 法以实现对器件性能的提高。 发明内容
本发明的目的旨在至少解决上述技术问题之一， -特别是提出†一 根据本 明的一个方面， 提供了 A—种半导体器件结构的制造方法， 包括： 提供半导体衬底； 在半导体衬底表面形成第一绝缘层； 嵌入第 一绝缘层和半导体衬底形成浅沟槽隔离 STI;嵌入第一绝缘层和半导体 衬底形成条状凹槽； 在凹槽内形成沟道区； 形成沟道区上的栅堆叠线 以及沟道区两侧的源 /漏区。
如果半导体衬底中形成有浅沟槽隔离， 则凹槽的底部高于浅沟槽 隔离的底部。
优选地， 其中第一绝缘层包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C, SiCON和 SiONx中的任一种或多种的组合。
在形成 STI 区之后， 可以选择先对第一绝缘层进行回刻至比 STI 的顶部低的位置， 然后再重新淀积一层第二绝缘层， 第二绝缘层的材 料与第一绝缘层可以相同。
根据本发明的一个实施例， 在凹槽内形成沟道区包括： 在凹槽的 底部形成第三绝缘层； 在第三绝缘层上形成沟道区。 优选地， 第三绝 缘层包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx 中的任一种或多种的组合。 形成第三绝缘层的步骤可以包括： 在凹槽 内形成第三绝缘层， 第三绝缘层在凹槽的侧壁的厚度小于在凹槽底部 的厚度； 选择性刻蚀第三绝缘层在凹槽侧壁上的部分， 以使第三绝缘 层仅保留在凹槽的底部。
优选地， 形成沟道区的步骤可以为： 以凹槽内暴露的侧壁为源外 延生长沟道区。 形成沟道区的材料可以包括以下一种或多种的组合： Si、 SiC、 GaN、 AlGaN、 InP和 SiGe。
可选地， 本发明实施例中半导体衬底可以为体硅。
根据本发明的另一实施例， 形成沟道区上的栅堆叠线的步骤， 可 以包括： 在沟道区上形成栅介质层； 在栅介质层上形成栅电极线； 接 着将第一绝缘层去除； 然后环绕栅电极线外侧形成侧墙； 其中， 在形 成侧墙之后、 完成半导体器件的前道工艺之前， 将栅电极线进行切割 以形成电隔离的栅电极。 将栅电极线进行切割的方法包括反应离子刻 蚀 （RIE)或激光切割刻蚀。
可选地， 在形成源 /漏区后， 该方法可以进一步包括： 将栅电极线 去除以在侧墙内形成开口； 在开口内形成替代栅电极线。 因而本发明 的实施例可以兼容替代栅工艺。
可选地， 在形成源 /漏区之后， 进行栅电极线的切割以形成电隔离 的栅电极； 该方法可以进一步包括： 在所述半导体衬底上形成层间介 质层， 其中， 层间介质层将所述隔离的栅电极之间进行填充； 以及刻 蚀所述层间介质层以在所述栅电极或源 /漏区上形成接触孔。
可选地， 在形成源 /漏区之后， 该方法可以进一步包括： 形成第一 层间介质层； 刻蚀所述第一层间介质层以在所述源 /漏区上形成下接触 孔； 在所述下接触孔中形成下接触部； 形成第二层间介质层； 刻蚀所 述第二层间介质层以在所述栅电极线或源 /漏区上形成上接触孔； 在所 述上接触孔中形成上接触部； 其中， 在所述源 /漏区上， 所述下接触部 与上接触部对齐。 并且在形成下接触部之后进行栅电极线的切割。 可 见， 本发明的实施例还可以兼容双接触孔工艺。
根据本发明的另一方面， 提供了一种半导体器件结构， 包括： 半 导体衬底； 沟道区， 内嵌形成于半导体衬底上且通过外延生长形成； 栅堆叠， 形成于沟道区上； 源 /漏区， 形成于沟道区的两侧。
其中， 沟道区的材料包括 Si、 SiC、 GaN、 AlGaN、 InP和 SiGe中 一种或多种的组合。 并且可选地， 在沟道区的底部与半导体衬底之间 包括绝缘层。 绝缘层可以包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx中任一种或多种的组合，厚度可以为 5-50nm。
在本发明的实施例中， 该半导体器件结构进一步包括侧墙， 仅形 成在栅电极的两侧， 且沿栅宽的方向上， 侧墙的端部与栅电极的端部 相齐。
优选地， 沿栅宽的方向上， 相邻的栅电极之间填充有介质材料以 形成栅电极之间的电隔离， 并且相邻的栅电极之间的距离为 l-10nm。
可选地， 该半导体器件可以进一步包括下接触部与上接触部， 下 接触部与源 /漏区接触并与栅堆叠的顶部同高， 上接触部与栅堆叠的顶 部和下接触部的顶部接触； 其中， 在源 /漏区上, 下接触部与上接触部 对齐。 本发明提出一种具有嵌入式沟道 （buried channel ) 的半导体器件 结构及其形成方法， 通过在半导体衬底中形成能够有效增大载流子迁 移率的外延沟道, 能够大大增强 MOSFET器件性能。 此外， 本发明的 实施例还结合栅电极线切割的一种独特工艺， 能够有效提高栅电极之 间的绝缘效果以及简化栅电极刻蚀、 光刻以及降低 OPC ( Optical Proximity Correction, 光学临近效应校正） 的难度， 本工艺还兼容于高 k介质 /金属栅工艺以及替代栅技术。
本发明附加的方面和优点将在下面的描述中部分给出， 部分将从 下面的描述中变得明显， 或通过本发明的实践了解到。 附图说明
本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的 描述中将变得明显和容易理解， 本发明的附图是示意性的， 因此并没 有按比例绘制。 其中：
图 l-14a 为本发明实施例的半导体器件结构的制造方法的中间步 骤的结构剖面图；
其中， 图号中带有下标 a表示为沿俯视图中 AA，方向的剖面图， 图号中带有下标 b表示为沿俯视图中 BB，方向的剖面图；图号中带有下 标 c的表示沿俯视图中 CC'方向的剖视图。 具体实施方式
下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或 类似功能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用 于解释本发明， 而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不 同结构。 为了简化本发明的公开， 下文中对特定例子的部件和设置进 行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了简 化和清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关 系。 此外， 本发明提供了各种特定的工艺和材料的例子， 但是本领域 普通技术人员可以意识到其他工艺的可应用性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上" 的结构可以包括第一 和第二特征形成为直接接触的实施例， 也可以包括另外的特征形成在 第一和第二特征之间的实施例， 这样第一和第二特征可能不是直接接 触。
图 l-14a 示出了根据本发明的实施例制造半导体器件结构的中间 步骤的结构剖面图。以下将结合图 l-14a详细说明根据本发明实施例制 造半导体器件结构的方法以及由此得到的器件结构。
首先如图 1所示， 提供半导体衬底 1000。 在本发明的实施例中， 衬底 1000以体硅为例， 但实际应用中， 衬底可以包括任何适合的半导 体衬底材料，具体可以是但不限于硅、锗、锗化硅、 SOK绝缘体上硅）、 碳化硅、 砷化镓或者任何 III/V族化合物半导体等。 根据现有技术公知 的设计要求 （例如 p型村底或者 n型衬底） ， 衬底 1000可以包括各种 掺杂配置。 此外， 衬底 1000可选地可以包括外延层， 可以被应力改变 以增强性能。
如图 1、 图 lc所示， 在半导体衬底 1000上形成 STI (浅沟槽隔离）
1001 以及有源区 1002。 首先在半导体衬底 1000表面形成第一绝缘层 1003 , 图 lc即为沿图 1 中 CC，方向的剖视图。 第一绝缘层 1003可以是 包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx 中任一种或多种的组合， 本发明的实施例优选采用 Si3N4。 然后根据需 要形成的 STI 1001的形状对该第一绝缘层 1003和半导体衬底 1000刻 蚀形成凹槽， 在凹槽中填充氧化物， 例如 Si02, 以形成 STI 1001。
为了方便起见， 在图 lc中仅示出了一个 STI结构 1001。
可选地， 在形成第一绝缘层 1003之前， 还可以在半导体衬底 1000 上先形成一氧化物层， 可以通过常规的热氧化或其他淀积方法形成。 为了方便查看， 该氧化物层在图中未示出。
在形成 STI区之后， 可以选择先对第一绝缘层 1003进行回刻至比 STI的顶部低的位置， 然后再重新淀积一层第二绝缘层， 第二绝缘层的 材料与第一绝缘层可以相同。 形成全新的第二绝缘层有利于形成一个 更好的表面。
然后， 在形成了 STI 1001的半导体结构上涂覆一层光刻胶， 并以 将要形成的栅电极线的形状图案化这一层光刻胶。 最后形成如图 2 所 示的光刻胶图案 1004。以图 2所示的光刻胶为掩模，对第一绝缘层 1003 和半导体衬底 1000进行选择性刻蚀。 例如在本发明的一个实施例中， 第一绝缘层 1003为 Si3N4， STI 中填充的是 Si02, 则这次刻蚀相对于 Si02选择刻蚀 Si3N4和 Si， 最终形成嵌入于第一绝缘层 1003和半导体 衬底 1000的凹槽 1005。 凹槽 1005的底部高于 STI 1001的底部， 这样 STI还能够起到隔离作用。
可选地， 如果形成了第二绝缘层， 则刻蚀形成条状凹槽 1005时， 从第二绝缘层开始向下刻蚀。 ·
图 2a和图 2b分别为沿图 2中的 BB，和 CC，方向的剖视图，清楚地 显示了经过这一次选择性刻蚀的结果。 图 2b中可以看出， 这一次刻蚀 对 STI的影响很小， 形成了很浅的凹槽 1005。
为了方便起见， 在后面的示意图中， 如果不加其他说明， 图号中 的下标 a和 b分别表示沿 AA'和 BB'方向的剖面图。
可选地， 如图 3、 图 3a和图 3b所示， 在凹槽 1005上形成第三绝 缘层 1007, 第三绝缘层 1007可以由包括 Si3N4、 Si〇2、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx中的任一种或多种的组合形成。 形成 的方法可以是热氧化、 原子层化学气相淀积 （ALCVD ) 或其他淀积方 法， 本发明对此不做限制。 第三绝缘层 1007能够调整后面将要形成的 沟道区的厚度， 并且也能够提高器件的开关速度。 例如， 在凹槽内形 成第三绝缘层时， 可采用选择性原子层化学气相 （ALCVD ) 方法在凹 槽底部形成较厚的绝缘层， 而在凹槽侧壁形成很薄或几乎没有绝缘层 的结构。 在凹槽内形成第三绝缘层后， 可以采用选择性湿化学方法或 干化学方法刻蚀以使凹槽的侧壁暴露， 而留下一层绝缘层 （厚度为 5-50nm )在凹槽底部。 第三绝缘层 1007能够调整后面将要形成的沟道 区的厚度， 并且也能够提高器件的开关速度。
接着， 如图 4、 图 4a和图 4b所示， 以凹槽 1005暴露出的侧壁为 晶源， 外延生长沟道区 1008。 例如， 可以外延生长 Si、 SiC、 GaN、 AlGaN、 InP和 SiGe中的任一种或多种的组合， 从而形成沟道区 1008。 例如， 可以根据需要选择 SiGe或 SiC中的 Ge含量或者是 C含量的百 分比， 从而调节沟道区中的应力。 例如对于 pMOSFET, 可以外延生长 Si:C, 对于 nMOSFET可以外延生长 SiGe。这样形成的沟道区的厚度可 调节， 并且能够选择沟道区中杂质的浓度， 能够产生应力， 因此能够 有效提高载流子的迁移率， 改善器件性能。 形成沟道区之后， 接着可以通过常规方法或本发明实施例的方法 形成栅堆叠线和源 /漏区。
如图 5、 图 5a和图 5b所示， 在沟道区上形成栅介质层 1009。 栅 介质层 1009可以是常规介质材料， 也可以是高 k介质材料， 例如可以 是 Hf02、 HfSiOx、 HfSiNOx, HfTaOx, HiTiOx, HfZrOx、 A1203、 La203、 Zr02、 LaAlO中的任一种或多种。 形成栅介质层的方法可以是热氧化、 溅射、 淀积等方法或其他方法。 高 k栅介质层能够抑制器件的短沟道 效应。 接着， 在栅介质层 1009上形成栅电极线 1010。 具体地， 可以整 个半导体器件结构上淀积一层导电材料， 例如可以是 Poly-Si、 Ti、 Co、 Ni、 Al、 W、 金属合金等材料或其他材料， 接着用 CMP (化学机械抛光) 处理整个半导体器件结构， 并停止于第一绝缘层 1003上。
从图 5b可以看出， STI 1001上的栅电极线 1010很薄。
接着将第一绝缘层 1003去除， 可以采用干刻或湿刻等方法进行， 例如对于 Si3N4可以采用热磷酸（Hot phosphoric acid )进行刻蚀。 从而 形成如图 6a、 图 6b所示的结构。
接着， 可选地， 将图 6a中高出衬底 1000的 STI 1001去除， 例如 可以采用 HF腐蚀。
在常规的工艺中， 本发明的实施例可以再采用一次光刻掩模， 将 栅电极线切割为栅电极。 如图 7、 图 8、 图 8a、 图 8b所示， 采用常规 工艺将栅电极线 1010进行切割， 从而形成电隔离的栅电极 1015。 图 7 中示意性地示出了采用掩模板刻蚀出的切口 1017， 切口的形成完全可 以根据器件的需要。
如图 8a所示， 环绕栅电极 1015的外侧形成侧墙 101 1， 在沟道区 1008的两侧形成源 /漏区 1012。
具体地， 可以先对沟道区 1008两侧的衬底区进行倾角离子注入， 形成源 /漏延伸区； 可选地， 还可以采用晕环 （ Halo ) 离子注入， 以形 成源 /漏晕环注入区； 接着， 在栅电极 1015 的外侧形成侧墙 1011， 本 发明的实施例对形成侧墙的形状以及材料不做限制， 因此图 8、 图 8a 所示侧墙形状仅为示意；然后在沟道区 1008两侧进行重掺杂离子注入， 以形成源 /漏区 1012。 同样地， 图 8a所示源 /漏区 1012形状仅为示意。
可以根据需要在源 /漏区 1012和栅电极 1015上形成金属硅化物接 触。 首先， 在整个半导体器件结构上淀积一层金属， 如 Ni、 Co、 W等 金属， 然后进行快速退火形成金属硅化物接触， 再将未反应的金属去 除。最终形成了如图 9a所示的金属硅化物 1013。在将金属去除的同时， 可能将 STI上很薄的栅电极线 1010的金属去除， 如图 8b所示。
至此就形成了根据本发明的一个实施例得到的半导体器件结构。 如图 8、图 8a和图 8b所示，该半导体器件结构包括：半导体衬底 1000; 沟道区 1008 ,内嵌形成于所述半导体衬底 1000中且通过外延生长形成； 栅堆叠， 形成于沟道区 1008上； 源 /漏区 1012， 形成于沟道区 1008的 两侧。
优选地， 沟道区的材料包括 Si、 SiC、 GaN、 AlGaN、 InP和 SiGe 中一种或多种的组合。
并且， 在沟道区 1008 的底部与半导体衬底 1000之间包括绝缘层 1007。 该绝缘层 1007可以包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx中任一种或多种的组合，厚度可以为 5-50nm。
绝缘层 1007的下表面高于图中所示的 STI 1001的底部，以达到更 好的隔离效果。
本发明的实施例得到的半导体器件结构， 沟道区的厚度可调， 并 且能够选择沟道区中杂质的浓度， 能够有效调节应力， 例如可以根据 需要选择 SiGe中的 Ge含量或者 SiC中 C含量的百分比， 因此能够有 效提高载流子的迁移率， 改善器件性能。
对于本发明的实施例， 还可以选择釆用替代栅工艺。 在源 /漏区形 成之后， 可以将栅电极去除， 接着重新形成替代栅电极。
以下描述根据本发明的另一实施例制造半导体器件结构的方法。 在图图 6、 图 6a和图 6b的基础上， 此时不直接进行栅电极线的切割， 而按照以下的步骤进行。
如图 9、图 9a和图 9b所示，在栅电极线 1010的外侧形成侧墙 101 1 , 在沟道区 1008 的两侧形成源 /漏区 1012。 具体的方法可以参照上述实 施例所述的方法， 这里不再赘述。 因此图 9、 图 9a和图 9b所示的侧墙 形状和源 /漏区形状仅为示意。
接着， 在源 /漏区 1012和栅电极线 1010上形成金属硅化物接触。 具体的形成方法同样可以参照以上的实施例， 结果形成了如图 10a 所 示的结构。
可以选择在这个时候进行栅电极线 1010的切割。 如图 1 1 所示， 采用激光切割刻蚀或反应离子刻蚀（RIE )在 STI 1001的上方对栅电极 线 1010和侧墙 101 1进行切割， 从而形成切口 1014, 以及相互电隔离 的栅电极 1015。可 地对于图 9b所示的位于 STI上方的栅电极线 1010 也可同时被切割断开。 为了方便起见， 图中只示出了两个切口， 对于 本发明来说， 完全可以根据需要选择进行切割。
在常规的工艺中， 是在图 6 的栅电极线形成之后进行栅电极线的 切割， 但是在后续其他的工艺中， 例如在侧墙的形成中， 由于切口较 小， 侧墙的绝缘材料很不容易填充进去， 很可能在后续的其他工艺中 造成栅电极之间的短路。 例如， 在进行源 /漏区的离子注入或者形成金 属硅化物时， 很可能导致栅电极之间短路。 但是在本发明中， 在金属 硅化物形成之后进行栅电极线的切割， 在后续的工艺中将填充绝缘介 质， 能够有效防止相邻的栅电极之间短路。 即使将切口切得很小， 也 能够有效达到栅电极之间的电隔离要求。 本方法避免了高精度的掩模 和 OPC的要求， 简化了工艺。
接着， 可以进行层间介质层的淀积。 如图 12、 图 12a和图 12b所 示， 淀积了层间介质层后， 介质材料 1016将切口 1014填满， 进一步 确定了栅电极 1015之间的电隔离。
然后可以按照常规的方法形成接触孔和接触部， 以完成器件结构， 常规方法这里不再赘述。
至此就形成了根据本发明的另一实施例得到的一个半导体器件结 构。 如图 12、 图 12a和图 12b所示， 该半导体器件结构包括： 半导体 衬底 1000; 沟道区 1008 , 内嵌形成于所述半导体衬底 1000 中且通过 外延生长形成； 栅堆叠， 形成于沟道区 1008上； 源 /漏区 1012, 形成 于沟道区 1008的两侧。
优选地， 沟道区 1008的材料包括 Si、 SiC、 GaN、 AlGaN、 InP或
SiGe中一种或多种的组合。 并且， 在沟道区 1008的底部与半导体衬底 1000之间包括绝缘层 1007。 该绝缘层 1007 可以包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx 中任一种或多种的 组合。 绝缘层 1007的下表面高于图中所示的 STI 1001的底部， 以达到 隔离的效果。
在上述方案的基础上， 该半导体器件结构包括侧墙 1011 , 仅形成 在栅电极 1015 ·的两侧， 并且沿栅宽的方向上， 侧墙 101 1 的端部与栅 电极 1015的端部相齐。
优选地，沿栅宽的方向上，相邻的栅电极之间填充有介质材料 1016 以形成栅电极之间的电隔离。相邻的栅电极之间的距离优选为 l-10nm。
在本发明的实施例半导体器件结构中， 平行于栅宽的方向上， 栅 电极之间为平行切口， 切口之间填充有介质材料， 能够有效地将栅电 极之间进行隔离， 实现更好的器件性能。
对于本发明的实施例， 还可以选择采用替代栅工艺。 在源 /漏区形 成之后， 可以将栅电极线去除， 接着重新形成替代栅电极线。
本发明实施例采用的栅电极线切割的方法能够大大减小导致光 刻、 刻蚀或 OPC变得复杂的临近效应， 使得栅电极更容易刻蚀， 栅电 极的宽度更容易控制。 对于半导体工艺流程标准来说， 本发明实施例 采用的方法使得设计标准简化， 能够进一步减小芯片尺寸。
本发明的实施例还有利于 45nm及以下的高 k金属栅工艺。本发明 实施例中栅电极线切割的方法也可以有效应用于有源区的图案化。
图 13a- 14a 为根据本发明的另一实施例制造半导体器件结构的方 法中各步骤对应的结构剖面图。 在形成如图 6 所示的结构之后， 或者 也可以在进行替代栅工艺之后， 将接触部孔分为下接触孔部和上接触 孔部分别形成， 并且在形成下接触孔部之后进行栅电极线的切割。 以 下将结合图 13a-14 a详细说明根据本发明的实施例制造半导体器件结 构的具体的步骤。
如图 13a所示， 在整个半导体器件结构上淀积层间介质层 1018 , 可选地可将层间介质层 1018磨平至栅电极线 1010的顶部露出， 例如 可以采用 CMP (化学机械抛光）。 然后在层间介质层 1018上形成下接 触孔 1019， 并在其中填充导电材料， 例如 W等金属。 再将整个半导体 器件结构进行磨平处理， 至栅电极线 1010的顶部露出， 这样就形成了 与栅极导体层顶部同高的下接触部 （图中同样标示为 1019 ) 。
这时， 可如图 1 1 所示， 进行栅电极线 1004的切割， 形成栅电极 1015以及将栅电极 1015之间进行电隔离的平^"切口 1014。
如图 14a所示，在整个半导体器件结构上再淀积层间介质层 1020， 则此时层间介质层的介质材料能够将平行切口 1014进行填充。 然后刻 蚀层间介质层 1020以在栅电极 1015上、 以及下接触孔 1019上形成上 接触孔 1021， 同样地， 在其中填充导电材料， 例如 W等金属。 再将整 个半导体器件结构进行磨平处理， 就形成了位于栅堆叠和 /或源 /漏区
1012上的上接触部 （图中同样标示为 1021 ) , 其中， 在源 /漏区 1012 上, 所述下接触部 1019与上接触部 1021对齐。
可见， 本发明的实施例， 能够兼容替代栅技术， 也能够兼容双接 触孔形成方法。 在双接触孔形成方法中， 能够有效地防止栅电极之间 短路， 提高半导体器件的质量和性能。
如图 14a 所示， 为根据本发明再一实施例得到的半导体器件结构 的剖面图。 其中， 该结构在图 12、 12a和图 12b的基础之上， 进一步 包括下接触部 1019和上接触部 1021 , 其中下接触部 1019的顶部与栅 堆叠的顶部同高， 在栅堆叠、 源 /漏区上的上接触部 1021则也同高。 这 种器件结构能够简化接触孔形成工艺的难度。
尽管已经示出和描述了本发明的实施例， 对于本领域的普通技术 人员而言， 应该知道本发明的应用范围不局限于说明书中描述的特定 实施例的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发 明的公开内容， 作为本领域的普通技术人员将容易地理解， 对于目前 已存在或者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明描述的对应实施例大体相同的功 能或者获得大体相同的结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利要求旨在将这些工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1. 一种半导体器件结构的制造方法， 包括：
提供半导体衬底；
在所述半导体衬底表面形成第一绝缘层；
嵌入所述第一绝缘层和半导体衬底形成浅沟槽隔离；
嵌入所述第一绝缘层和所述半导体衬底形成条状凹槽；
在所述凹槽内形成沟道区；
形成所述沟道区上的栅堆叠线以及所述沟道区两侧的源 /漏区。
2. 根据权利要求 1 所述的方法， 所述凹槽的底部高于所述浅沟槽 隔离区的底部。
3. 根据权利要求 1所述的方法， 其中所述第一绝缘层包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx中的任一种或 多种的组合。
4. 根据权利要求 1所述的方法， 其中， 在形成浅沟槽隔离后， 所 述方法进一步包括： 回刻所述第一绝缘层； 在回刻后的第一绝缘层上 形成第二绝缘层， 所述第二绝缘层与第一绝缘层的材料相同；
在形成所述凹槽时， 包括将所述第二绝缘层也进行刻蚀。
5. 根据权利要求 1所述的方法， 其中在所述凹槽内形成沟道区包 括：
在所述凹槽的底部形成第三绝缘层；
在所述第三绝缘层上形成所述沟道区。
6. 根据权利要求 5所述的方法， 其中所述第三绝缘层包括 Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si〇2:C、 SiCON和 SiONx中的任一种或 多种的组合。
7. 根据权利要求 5所述的方法， 其中， 形成第三绝缘层的方法包 括：
在所述凹槽内形成第三绝缘层， 所述第三绝缘层在凹槽的侧壁的 厚度小于在凹槽底部的厚度；
选择性刻蚀所述第三绝缘层在所述凹槽侧壁上的部分， 以使所述 第三绝缘层仅保留在所述凹槽的底部。
8. 根据权利要求 1所述的方法，其中形成所述沟道区的方法包括： 以所述凹槽内暴露的侧壁为晶源外延生长沟道区。
9. 根据权利要求 1所述的方法， 形成所述沟道区的材料包括以下 任一种或多种的组合： Si、 SiC、 GaN、 AlGaN、 InP和 SiG^
10. 根据权利要求 1所述的方法， 所述半导体衬底为体硅。
11. 根据权利要求 1至 10中任一项所述的方法， 形成所述沟道区 上的栅堆叠线包括：
在所述沟道区上形成栅介质层；
在所述栅介质层上形成栅电极线；
将所述第一绝缘层去除；
环绕所述栅电极线外侧形成侧墙；
其中， 在形成所述侧墙之后、 完成所述半导体器件的前道工艺之 前， 将所述栅电极线进行切割以形成电隔离的栅电极。
12. 根据权利要求 11所述的方法，将所述栅电极线进行切割包括： 采用反应离子刻蚀或激光切割刻蚀对所述栅电极线进行切割。
13. 根据权利要求 11所述的方法， 其中， 在形成源 /漏区后， 进一 步包括：
将所述栅电极线去除以在所述侧墙内形成开口；
在所述开口内形成替代栅电极线。
14. 根据权利要求 11所述的方法， 其中， 在形成源 /漏区之后， 进 行栅电极线的切割以形成电隔离的栅电极； 所述方法进一步包括：
在所述半导体衬底上形成层间介质层， 其中， 层间介质层将所述 隔离的栅电极之间进行填充； 以及
15. 根据权利要求 11所述的方法， 其中， 在形成源 /漏区之后， 所 述方法进一步包括：
形成第一层间介质层；
刻蚀所述第一层间介质层以在所述源 /漏区上形成下接触孔； 在所述下接触孔中形成下接触部;
形成第二层间介质层；
刻蚀所述第二层间介质层以在所述栅电极线或源 /漏区上形成上接 触孔；
在所述上接触孔中形成上接触部； 其中， 在所述源 /漏区上， 所述下接触部与上接触部对齐。
16. 根据权利要求 15所述的方法， 其中， 在形成下接触部之后进 行栅电极线的切割。
17. 一种半导体器件结构， 包括：
半导体衬底；
沟道区， 内嵌于所述半导体衬底上且通过外延生长形成； 栅堆叠， 形成于所述沟道区上；
源 /漏区， 形成于所述沟道区的两侧。
18. 根据权利要求 17所述的半导体器件结构， 所述沟道区的材料 包括 Si、 SiC、 GaN、 AlGaN、 InP和 SiGe中一种或多种的组合。
19. 根据权利要求 17所述的半导体器件结构， 在所述沟道区的底 部与所述半导体衬底之间包括绝缘层。
20. 根据权利要求 19所述的方法， 如果所述半导体衬底中形成有 浅沟槽隔离， 则所述绝缘层的底部高于所述浅沟槽隔离的底部。
21. 根据权利要求 19 所述的半导体器件结构， 所述绝缘层包括
Si3N4、 Si02、 SiOx:F、 SiCOH、 SiOx、 Si02:C、 SiCON和 SiONx 中任 一种或多种的组合。
22. 根据权利要求 19所述的半导体器件结构， 所述绝缘层的厚度 为 5-50nm 。
23. 根据权利要求 17至 22中任一项所述的半导体器件结构，进一 步包括侧墙， 仅形成在所述栅电极的两侧， 且沿栅宽的方向上， 所述 侧墙的端部与所述栅电极的端部相齐。
24. 根据权利要求 23所述的半导体器件结构， 其中， 沿栅宽的方 °
25. 根据权利要求 23所述的半导体器件结构， 沿栅宽的方向 jT, 相邻的栅电极之间的距离为 l-10nm。
26. 根据权利要求 23所述的半导体器件结构， 进一步包括下接触 部与上接触部， 所述下接触部与源 /漏区接触并与栅堆叠的顶部同高， 所述上接触部与栅堆叠的顶部和下接触部分别接触；
其中， 在所述源 /漏区上， 所述下接触部与上接触部对齐。
PCT/CN2011/000308 2010-07-29 2011-02-25 半导体器件结构及其制造方法 WO2012013009A1 (zh)

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CN103367154B (zh) * 2012-03-31 2016-03-16 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
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