WO2011135900A1 - Carte imprimée multi-couches assemblée et son procédé de fabrication - Google Patents

Carte imprimée multi-couches assemblée et son procédé de fabrication Download PDF

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Publication number
WO2011135900A1
WO2011135900A1 PCT/JP2011/053459 JP2011053459W WO2011135900A1 WO 2011135900 A1 WO2011135900 A1 WO 2011135900A1 JP 2011053459 W JP2011053459 W JP 2011053459W WO 2011135900 A1 WO2011135900 A1 WO 2011135900A1
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Prior art keywords
layer
build
double
sided
plating
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PCT/JP2011/053459
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English (en)
Japanese (ja)
Inventor
文彦 松田
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日本メクトロン株式会社
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Priority to CN201180001889XA priority Critical patent/CN102415228B/zh
Publication of WO2011135900A1 publication Critical patent/WO2011135900A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density

Definitions

  • the present invention relates to a build-up type multilayer printed wiring board having a stacked via structure and a method for manufacturing the same.
  • a build-up type multilayer printed wiring board generally has a double-sided printed wiring board having a through hole or a multilayer printed wiring board as a core substrate, and has about one or two build-up layers on both sides or one side of the core substrate. It is provided.
  • This build-up type multilayer printed wiring board is a bottomed type that electrically connects a circuit (inner layer circuit pattern) provided on a core substrate and a circuit (outer layer circuit pattern) provided on a build-up layer. Interlayer conduction part (blind via) is provided.
  • This blind via is composed of a plating layer formed on the inner wall of a bottomed via hole (blind via hole) that penetrates the build-up layer and exposes the receiving land portion provided as a part of the inner circuit pattern on the bottom surface.
  • This is an interlayer conductive path.
  • each of the members constituting the printed wiring board is thermally expanded, so that the blind via is easily broken. Furthermore, when a plating layer is formed on the inner wall of a bottomed via hole to obtain interlayer conduction, the plating solution tends to stay at the bottom of the via hole, so that a desired plating thickness cannot be obtained. For this reason, as the depth of the blind via increases, it becomes more difficult to ensure the reliability as the interlayer conductive path.
  • the thickness of the plating layer formed on the inner wall of the bottomed via hole increases, the thickness of the conductor layer formed on the buildup layer inevitably increases accordingly.
  • the outer layer circuit pattern is formed by wet etching the conductor layer on the build-up layer according to a desired pattern. For this reason, it becomes difficult to miniaturize the outer layer circuit pattern as the thickness of the conductor layer on the buildup layer increases. As a result, there is a problem that it becomes difficult to satisfy the demand for high-density mounting.
  • the stack via structure is a structure that electrically connects the outer layer circuit pattern and the inner layer circuit pattern on the interlayer connection portion that electrically connects the inner layer circuit patterns formed on the front surface and the back surface of the core substrate.
  • This is a structure in which the interlayer connection parts are stacked.
  • a method described in Patent Document 2 is known as one of methods for manufacturing a build-up type multilayer printed wiring board having a stacked via structure.
  • FIG. 4 is a process cross-sectional view illustrating a method for manufacturing a conventional build-up type multilayer printed wiring board.
  • a flexible double-sided copper-clad laminate 104 having a copper foil 102 and a copper foil 103 (each 12 ⁇ m thick) on both sides of a flexible insulating base material 101 (25 ⁇ m thick) made of a polyimide film is prepared. Then, as can be seen from FIG. 4A, through holes 105 ( ⁇ 100 ⁇ m) penetrating through the double-sided copper-clad laminate 104 in the thickness direction are formed using laser processing or NC drills.
  • a conductive paste is filled into the through hole 105 by screen printing or the like, and then the filled conductive paste is cured to form the embedded via 106. Form.
  • a lid plating layer 107 made of a copper plating film is formed on the exposed via 105 and the surrounding copper foils 102, 103 by performing an electrolytic copper plating process. ( ⁇ 200 ⁇ m, 10 ⁇ m thickness) is formed.
  • the lid plating layer 107 reduces the contact resistance between the embedded via 106 and the copper foils 102 and 103, ensures the reliability of interlayer connection by the embedded via 106, and at the time of laser processing the blind via hole later. Formed to protect 106.
  • the thickness of the lid plating layer 107 is determined in consideration of the resistance to the laser beam irradiated when forming the subsequent blind via hole. That is, the lid plating layer 107 needs to have a thickness that does not penetrate during laser processing.
  • the copper foils 102 and 103 are processed by the photofabrication technique, and the inner layer circuit pattern having the receiving land portion 108 ( ⁇ 300 ⁇ m) having a larger diameter than the lid plating layer 107.
  • the photofabrication method is a processing method for patterning a processing layer (copper foil or the like) into a predetermined pattern.
  • the formation of a resist layer on the processing layer, exposure, development, It consists of a series of processes such as etching and stripping of the resist layer.
  • the surface of the inner layer circuit pattern is roughened. This roughening treatment increases the absorption rate of carbon dioxide (CO 2 ) laser light (wavelength: about 9.8 ⁇ m) on the copper surface, so that the lid plating layer 107 is less resistant to laser processing.
  • CO 2 carbon dioxide
  • the polyimide film 109 (12 ⁇ m thickness) is adhered onto the inner layer circuit pattern via the adhesive layer 110 (25 ⁇ m thickness), and the coverlay 111 is formed.
  • a cover lay 111 having a polyimide film 109 and an adhesive layer 110 formed on one side of the polyimide film 109 may be laminated on a substrate on which an inner layer circuit pattern is formed using a vacuum laminator or the like.
  • the thickness of the adhesive layer 110 is determined so that the adhesive layer 110 can completely fill the lid plating layer 107 and the inner layer circuit pattern. For this reason, the greater the thickness of the lid plating layer 107, the greater the thickness of the adhesive layer 110.
  • the double-sided core substrate 112 shown in FIG. 4A is obtained.
  • a flexible single-sided copper-clad laminate 113 is prepared. As can be seen from FIG. 4B, an opening serving as a conformal mask is formed on the copper foil 113b of the single-sided copper-clad laminate 113 using a photofabrication technique.
  • the single-sided copper clad laminate 113 has a copper foil 113b (12 ⁇ m thickness) on one side of a polyimide film 113a (thickness 25 ⁇ m).
  • the single-sided copper-clad laminate 113 in which the copper foil 113 b has been processed in the previous step is laminated on both sides of the double-sided core substrate 112 via the adhesive layer 114. Glue.
  • an electrolytic copper plating film is formed on the copper foil 113 b and the inner walls of the blind via holes 115 A and 115 B by conducting a conductive treatment and subsequent electrolytic copper plating treatment. To do.
  • the thickness of the electrolytic copper plating film needs to be about 25 to 30 ⁇ m in order to ensure interlayer conduction.
  • blind vias 116A and 116B that function as interlayer conductive paths are formed.
  • the blind via 116A is stacked on the embedded via 106 of the core substrate via the lid plating layer 107, and a stacked via structure is formed.
  • the blind via 116B does not constitute a stacked via structure.
  • the electrolytic copper plating film formed in the previous step is processed using a photofabrication technique to form an outer layer circuit pattern 117.
  • the build-up type multilayer printed wiring board 118 includes a component mounting portion 118a in which a build-up layer is laminated on the double-sided core substrate 112, and a flexible cable extending from the component mounting portion 118a. Part 118b.
  • the flexible cable portion 118b is a part of the double-sided core substrate 112 that is not provided with a build-up layer.
  • the lid plating layer 107 is used. It must be thickened. As the lid plating layer 107 becomes thicker, the thickness of the adhesive layer 110 that embeds the inner layer circuit pattern increases, so that the blind via holes 115A and 115B become deeper.
  • the thickness of the electrolytic copper plating film formed on the blind via holes 115A and 115B and the copper foil 113b needs to be about 25 to 30 ⁇ m as described above in order to ensure the connection reliability of the blind vias 116A and 116B. .
  • the total thickness of the conductor layer (copper foil 113b and electrolytic copper plating film) on the buildup layer is 37 to 42 ⁇ m, a fine outer layer circuit pattern with a pitch of about 100 ⁇ m, for example, should be formed with a high yield. Is extremely difficult in practice.
  • the conventional build-up type multilayer printed wiring board having the step via structure has a problem that it cannot satisfy the demand for high-density mounting.
  • the present invention has been made based on the above technical recognition, and provides a build-up type multilayer printed wiring board having a stack via structure capable of high-density mounting, and such a printed wiring board. It aims at providing the method of manufacturing cheaply and stably.
  • a flexible insulating base material, an inner layer circuit pattern provided on both surfaces of the insulating base material and having receiving land portions, and the insulating base material are penetrated in the thickness direction.
  • the inner layer circuit pattern and the outer layer are formed of a plating film formed on the inner wall of the blind via hole that penetrates the up layer in the thickness direction and the lid plating layer is exposed on the bottom surface.
  • a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof is prepared.
  • a through hole penetrating in the thickness direction is formed, and after filling the through hole with a conductive paste, the conductive paste is cured to form a buried via, and at least the surface layer is the first metal foil
  • a lid plating layer made of a material resistant to the etchant is formed in a predetermined region, a resist layer having a predetermined pattern is formed on the first metal foil, and the resist layer and the lid plating layer are formed By etching the first metal foil as an etching resist, an inner layer circuit pattern having a receiving land portion covered with the lid plating layer is formed, thereby obtaining a double-sided circuit substrate.
  • Method for manufacturing a preparative wiring board is provided.
  • a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof is prepared, and the double-sided metal-clad laminate is After forming a through hole penetrating in the thickness direction and filling the through hole with a conductive paste, the conductive paste is cured to form a buried via, and the first metal foil and the exposed portion are exposed.
  • first plating film Forming a first plating film on the embedded via, forming a resist layer having a predetermined pattern on the first plating film, and using the resist layer as an etching resist, By etching the first metal foil, an inner layer circuit pattern having a receiving land portion is formed, and at least the surface layer is made of a material having resistance to the etchant of the first metal foil.
  • a plating layer is formed so as to cover the receiving land portion, thereby obtaining a double-sided circuit base material, and after roughening the surface of the inner layer circuit pattern, an insulating film and one side of the insulating film
  • a layer is laminated on the double-sided core substrate via a second adhesive layer, and an infrared laser beam is irradiated to a predetermined position of the buildup layer to penetrate the buildup layer in the thickness direction.
  • a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof is prepared, and the double-sided metal-clad laminate is After forming a through hole penetrating in the thickness direction and filling the through hole with a conductive paste, the conductive paste is cured to form a buried via, and the first metal foil and the exposed portion are exposed.
  • a lid plating layer made of a material resistant to an etchant so as to cover the receiving land portion
  • a double-sided core substrate is obtained, and the surface of the inner layer circuit pattern is subjected to a roughening treatment
  • a build-up layer having a second metal foil on the surface is laminated on the double-sided core substrate in the component mounting portion via a second adhesive layer having a thickness equal to or greater than the thickness of the coverlay, and the build By irradiating infrared laser light at a predetermined position of the up layer, the build-up layer penetrates in the thickness direction, and a blind via hole in which the lid plating layer is exposed on the bottom surface is formed, A build that forms a blind via that electrically connects the second metal foil and the inner layer circuit pattern by forming a
  • the present invention has the following effects.
  • the build-up type multilayer printed wiring board according to the present invention has a lid plating layer made of a material having resistance to a metal etchant whose surface layer constitutes an inner layer circuit pattern at a receiving land portion of a blind via hole. Since this lid plating layer has high resistance to infrared lasers, the thickness of the lid plating layer can be greatly reduced. Thereby, the thickness of the adhesive layer filling the inner layer circuit pattern and the lid plating layer can be reduced, and the blind via hole penetrating the buildup layer can be shallowed. As a result, the thickness of the plating layer necessary to ensure interlayer conduction can be reduced, and the outer circuit pattern can be miniaturized. Therefore, the build-up type multilayer printed wiring board having the stacked via structure according to the present invention can satisfy the demand for high-density mounting.
  • a cover plating layer made of a material having resistance to a metal etchant whose surface layer constitutes an inner layer circuit pattern is formed on the receiving land portion of the build-up via hole.
  • this lid plating layer has high resistance to infrared lasers, it can be formed significantly thinner. Thereby, the thickness of the adhesive layer filling the inner layer circuit pattern and the lid plating layer can be reduced, and the blind via hole penetrating the build-up layer can be formed shallow. As a result, the thickness of the plating layer necessary to ensure interlayer conduction can be reduced, and a fine outer layer circuit pattern can be formed. Furthermore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same, so that productivity can be improved.
  • FIGS. 1A to 1D are process cross-sectional views illustrating a method for manufacturing a build-up type multilayer printed wiring board according to the present embodiment.
  • a direct laser processing method in which the resin (flexible insulating base material 1) is directly processed with a laser beam can be selected.
  • a direct laser processing method that does not require a copper foil etching step by a photofabrication method was selected.
  • the through-hole 5 is filled with the conductive paste 6A by screen printing or the like, and then the filled conductive paste 6A is cured.
  • the conductive paste 6A preferably has a low volume resistivity and does not require a conductive treatment when a lid plating layer 9 described later is formed.
  • AE1244 volume resistivity: 5 ⁇ 10 ⁇ 5 ⁇ ⁇ cm
  • Tatsuta Electronics Co., Ltd. was used. In this step, as shown in FIG.
  • the upper and lower portions of the through-hole 5 are filled until the conductive paste 6A overflows so that voids or the like do not occur in the through-hole 5 due to the lack of the conductive paste. It is preferable to do.
  • the conductive paste is filled in the through hole instead of the blind via hole, the printing machine used in this process does not need to be a vacuum type and has a differential pressure enough to adsorb the double-sided copper clad laminate 4. As long as it has a mechanism capable of generating
  • both surfaces of the double-sided copper clad laminate 4 in which the conductive paste 6A is filled in the through-hole 5 shown in FIG. 1A (2) are mechanically polished by a belt sander or a roll buff, or chemical mechanically polished (CMP : Polishing by Chemical Mechanical Polishing).
  • CMP chemical mechanically polished by Chemical Mechanical Polishing
  • the excess conductive paste 6A protruding from the through hole 5 is scraped, and the buried via 6 is formed.
  • the copper foil 2 and the copper foil 3 are also shaved by polishing in this step, and the copper foil 2 and the copper foil 3 become a copper foil 2a and a copper foil 3a having a thickness of about 5 ⁇ m, respectively.
  • the double-sided copper-clad laminate 4 is bonded to a hard substrate (several mm thick) via an adhesive sheet before polishing. ) Etc. and then polishing. By doing in this way, the polisher for hard substrates can be used.
  • the double-sided copper-clad laminate 4 is adsorbed and held on a flat plate, the surface opposite to the adsorption surface is polished, and then the double-sided copper-clad laminate 4 is turned over and polished. This surface may be adsorbed on a flat plate, and the unpolished surface may be polished.
  • a plating resist layer 7 is formed on each of the copper foil 2a and the copper foil 3a.
  • This plating resist layer 7 has an opening 8a in a region where the embedded via 6 is exposed, and further has an opening 8b in a region which becomes a receiving land portion of a blind via hole without the embedded via 6.
  • the diameters of the openings 8a and 8b are preferably determined in consideration of the diameter of the blind via hole and the alignment accuracy when forming the blind via hole. Here, it is set to ⁇ 200 ⁇ m.
  • the lid plating layer 9 is formed in the openings 8a and 8b of the plating resist layer 7.
  • the lid plating layer 9 is formed as follows. First, electrolytic copper plating is performed to form a copper plating layer 9a having a thickness of 2 ⁇ m on the bottom surfaces of the openings 8a and 8b. Thereafter, electroless silver plating is performed to form a silver plating layer 9b having a thickness of 0.5 ⁇ m on the copper plating layer 9a. This series of plating processes is performed with the plating resist layer 7 left.
  • the lid plating layer 9 is not limited to the above configuration.
  • a nickel plating layer by electroless nickel plating may be formed instead of the copper plating layer 9a.
  • the plating layer constituting the surface layer of the lid plating layer 9 needs to have resistance to copper etchant (may be selective etching to copper).
  • a gold plating layer by electroless gold plating or a nickel plating layer by electroless nickel plating may be formed instead of the silver plating layer 9b.
  • a nickel plating layer and a gold plating layer may be sequentially formed on the copper plating layer 9a.
  • the cover plating layer 9 is made of silver, gold, under the condition that at least the surface layer is made of a material resistant to a copper etchant such as silver (Ag), gold (Au), nickel (Ni).
  • a plating layer made of nickel, copper, or the like can be configured singly or in combination. In any of these cases, it is not necessary to change the subsequent steps, and the same effect as when the lid plating layer 9 composed of the copper plating layer 9a and the silver plating layer 9b is formed can be obtained.
  • the configuration of the lid plating layer 9 is selected in consideration of productivity and cost.
  • FIGS. 1B (5) and (6) Next, after the plating resist layer 7 is peeled off, as shown in FIGS. 1B (5) and (6), an etching resist having a predetermined pattern for forming inner layer circuit patterns 11A and 11B described later.
  • the layer 10 is formed on the copper foils 2a and 2b.
  • FIG. 1B (5) is a cross-sectional view taken along the line A-A 'of FIG. 1B (6). That is, FIG. 1B (6) is a view of the base material shown in FIG. 1B (5) as viewed from above.
  • a dry film resist about 10 ⁇ m thick
  • the lid plating layer 9 can be filled.
  • the lid plating layer 9 functions as an etching resist during circuit pattern etching, it is not necessary to provide an etching resist layer for protecting the lid plating layer 9 as shown in FIGS. 1B (5) and (6). . Therefore, the shape of the lid plating layer 9 can be used as it is as the shape of the receiving land portion of the blind via hole without using an exposure machine capable of highly accurate alignment. This improves productivity and contributes to the manufacture of an inexpensive printed wiring board.
  • the copper foil 2a and the copper foil 3a are etched using the etching resist layer 10 and the lid plating layer 9 as an etching resist, thereby providing flexible insulation.
  • the inner layer circuit pattern 11A and the inner layer circuit pattern 11B are formed on the front surface and the back surface of the base material 1, respectively. Thereafter, the etching resist layer 10 is peeled off.
  • the inner layer circuit patterns 11 ⁇ / b> A and 11 ⁇ / b> B have blind via hole receiving land portions covered with the cover plating layer 9.
  • the etchant used in this step is one that etches the copper foils 2a and 3a but does not damage the lid plating layer 9 (silver plating layer 9b).
  • an etchant using cupric chloride or ferric chloride can be used as such an etchant.
  • the etching in this step is performed as selective etching using, for example, an ammonia-based alkali etchant.
  • the double-sided circuit substrate 12 shown in FIG. 1B (7) is obtained.
  • Inner layer circuit patterns 11A and 11B having receiving land portions are formed on the double-sided circuit substrate 12, and the embedded via 6 electrically connects the inner layer circuit pattern 11A and the inner layer circuit pattern 11B.
  • the lid plating layer 9 also has a function of reducing the contact resistance between the embedded via 6 and the copper foils 2 and 3 and ensuring the reliability of the embedded via 6 as an interlayer connection path.
  • the surface of the inner layer circuit patterns 11A and 11B is subjected to a roughening process.
  • the roughening process was performed using the multi bond 150 of Nippon Macder Mid Co., Ltd.
  • the roughening treatment improves the adhesion between the copper foils 2a and 3a and the adhesive, but increases the absorption rate of the carbon dioxide laser light in the copper foils 2a and 3a.
  • a silver plating layer 9b having copper etchant resistance is formed on the surface layer of the lid plating layer 9 covering the receiving land portion of the blind via hole. For this reason, the lid plating layer 9 is not roughened by the roughening treatment in this step, and the absorption rate of the carbon dioxide laser light in the receiving land portion does not increase.
  • the absorption rate of the carbon dioxide laser beam was measured before and after the roughening treatment, the absorption rate increased from about 20% to about 30% on the surfaces of the copper foils 2a and 3a, but on the surface of the silver plating layer 9b. There was no increase in absorption.
  • the thickness of the copper plating layer 9a and the copper foil 2a (3a) under the silver plating layer 9b is not reduced by the irradiation of the carbon dioxide laser beam, the resistance to thermal damage caused by laser processing is sufficiently ensured. Yes. Since the silver plating layer 9b hardly absorbs infrared laser light before this step (roughening treatment), the resistance of the lid plating layer 9 to the infrared laser light is maintained sufficiently high after the roughening treatment in this step. .
  • a coverlay 15 having an insulating film 13 (for example, 12 ⁇ m thick) made of polyimide or the like and an adhesive layer 14 formed on one surface of the insulating film 13 is prepared.
  • the adhesive layer 14 is made of an adhesive such as acrylic or epoxy.
  • the lamination process which affixes the coverlay 15 to the double-sided circuit base material 12 using a vacuum laminator etc. is performed.
  • the inner layer circuit patterns 11 A and 11 B and the cover plating layer 9 are filled with the adhesive layer 14.
  • the insulating layer 13 may be formed on the adhesive layer 14 after forming the adhesive layer 14 filling the inner layer circuit pattern with the structures 11A and 11B and the lid plating layer 9.
  • the thickness of the adhesive layer 14 is determined so that the inner layer circuit pattern 11A (11B) and the lid plating layer 9 can be completely filled.
  • the thickest portion of the inner layer circuit pattern 11A (11B) is a receiving land portion of the blind via hole.
  • the thickness of the receiving land portion is 7.5 ⁇ m (copper foil 2a (3a): 5 ⁇ m, lid plating layer 9: 2.5 ⁇ m), which is smaller than the conventional one due to the thinning of the lid plating layer 9. Therefore, the thickness of the adhesive layer 14 can be set to a value (8 ⁇ m) that is significantly smaller than the conventional one.
  • the single-sided copper-clad laminate 17 on which the conformal mask 18 is formed is bonded to the double-sided core via an adhesive layer 19 made of an adhesive for building up.
  • the substrate 16 is laminated and adhered.
  • the adhesive used here is a flow-out such as a low-flow type prepreg or a bonding sheet so that the adhesive does not flow out to the flexible cable portion (double-sided core substrate 16 not covered with the single-sided copper-clad laminate 17). Those with less are preferred. Even if the single-sided copper clad laminate 17 having the unprocessed copper foil 17b is bonded to the double-sided core substrate 16 through the adhesive layer 19, the copper foil 17b is processed to form the conformal mask 18. Good.
  • the diameter of the conformal mask 18 was set to 120 ⁇ m, which is 80 ⁇ m smaller than the diameter 200 ⁇ m of the receiving land portion of the blind via hole (the cover plating layer 9). Therefore, the conformal mask 18 may be formed by a technique that can obtain an alignment accuracy of ⁇ 40 ⁇ m.
  • this alignment method for example, there are the following two methods.
  • the first method is a method in which the single-sided copper-clad laminate 17 is laminated on the double-sided core substrate 16 after the conformal mask 18 is formed.
  • target marks are formed in advance on the double-sided core substrate 16. Then, after aligning the single-sided copper-clad laminate 17 using this target mark, the single-sided copper-clad laminate 17 is laminated on the double-sided core substrate 16.
  • the second method is a method in which the conformal mask 18 is formed after the single-sided copper-clad laminate 17 is laminated and bonded to the double-sided core substrate 16.
  • target marks are formed in advance on the double-sided core substrate 16.
  • the single-sided copper-clad laminate 17 is laminated and bonded to the double-sided core substrate 16 to form a resist layer on the copper foil 17b.
  • the double-sided core substrate 16 and the photomask are aligned using the mark indicating the reference position provided on the photomask for exposure and the target mark of the double-sided core substrate 16.
  • the resist layer is exposed and developed to form a conformal mask 18 at a predetermined position on the copper foil 17b.
  • the details of the laser processing in this step will be described.
  • the carbon dioxide laser processing machine ML605GTXIII-5100U2 manufactured by Mitsubishi Electric Corporation was used.
  • the laser beam diameter was adjusted to 200 ⁇ m with a predetermined aperture or the like, the laser irradiation position was adjusted, and then 5 shots of laser pulses with a pulse width of 10 ⁇ Sec and a pulse energy of 5 mJ were irradiated to form blind via holes 20A and 20B.
  • the thickness of the lid plating layer 9 is as thin as 2.5 ⁇ m, the absorption of the carbon dioxide laser beam of the silver plating layer 9 b is small, so that the laser beam penetrates the lid plating layer 9 or the lid plating layer 9 extends from the embedded via 6.
  • Laser processing can be performed without peeling.
  • a conductive layer on the flexible insulating base material 17a (copper foil 17b and the electrolytic copper plating film 21 thereon) is formed in a predetermined manner by a photofabrication technique.
  • the outer layer circuit pattern 23 is formed by processing into a pattern.
  • a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.
  • the double-sided core substrate 16 of the build-up type multilayer printed wiring board 24 includes a flexible insulating base material 1 and inner layer circuit patterns 11A and 11B provided on both surfaces of the flexible insulating base material 1 and having receiving land portions, An embedded via 6 that penetrates the flexible insulating base material 1 and the receiving land portion and electrically connects the inner layer circuit pattern 11A and the inner layer circuit pattern 11B is provided. Further, a cover plating layer 9 made of a material that covers the receiving land portion where the embedded via 6 is exposed and whose surface layer is resistant to the metal etchant constituting the inner layer circuit patterns 11A and 11B is provided.
  • a buildup layer having an outer layer circuit pattern 23 provided on the surface is laminated via an adhesive layer 19.
  • the blind vias 22A and 22B are made of a plating film formed on the inner walls of the blind via holes 20A and 20B that penetrate the build-up layer in the thickness direction and the cover plating layer 9 is exposed on the bottom surface.
  • the circuit patterns 11A and 11B and the outer layer circuit pattern 23 are electrically connected.
  • the blind via 22A is arranged so as to overlap the embedded via 6 with the lid plating layer 9 interposed therebetween.
  • the build-up type multilayer printed wiring board 24 according to the present embodiment has a stacked via structure including the embedded via 6 and the blind via 22A.
  • the build-up type multilayer printed wiring board 24 includes a component mounting portion 24a in which a build-up layer is laminated on the double-sided core substrate 16, and a flexible cable extending from the component mounting portion 24a. Part 24b.
  • the flexible cable portion 24b is a part of the double-sided core substrate 16 where the buildup layer is not provided.
  • the flexible cable portion 24b is not an essential component and may not be provided.
  • the buildup layers are provided on the front and back surfaces of the double-sided core substrate 16, but the buildup layers may be provided only on one side.
  • the lid plating layer 9 is formed in the region that becomes the receiving land portion of the blind via holes 20A and 20B that penetrate the build-up layer.
  • the surface layer of the lid plating layer 9 is composed of a plating layer (silver plating layer 9b or the like) resistant to a copper etchant.
  • the adhesive layer 14 of the coverlay 15 can be thinned.
  • the blind via holes 20A and 20B can be formed shallowly. For example, it is about 10 ⁇ m smaller than the conventional one.
  • membrane 21 with respect to the inner wall of blind via-hole 20A, 20B improves.
  • the influence on the blind vias 22A and 22B due to the thermal expansion of the constituent members of the multilayer printed wiring board is reduced.
  • the adhesive constituting the adhesive layer 14 has a particularly large coefficient of thermal expansion, so that the effect of making the adhesive layer 14 thinner is great.
  • the lid plating layer 9 has copper etchant resistance, it is not necessary to provide a resist layer for protecting the lid plating layer 9.
  • covered with the lid plating layer 9 can be made the same as the lid plating layer 9, and densification of an inner-layer circuit pattern can be carried out. Can be planned.
  • productivity can be improved and a printed wiring board can be manufactured at low cost.
  • a lid plating layer 9 is provided on the receiving land portion of the blind via hole 20B that does not constitute a stacked via structure. Therefore, the structure of the blind via hole 20B (via depth and the like) is substantially the same as the blind via hole 20A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to the present embodiment, a large processing margin can be ensured and productivity can be improved.
  • the build-up type multilayer printed wiring board according to the second embodiment has an inner layer terminal on the flexible insulating base material in the flexible cable portion.
  • the plating layer that protects the surface of the inner layer terminal is formed in the same plating step as the lid plating layer formed on the embedded via and the receiving land portion.
  • FIGS. 2A to 2D are process cross-sectional views illustrating a method for manufacturing a build-up type multilayer printed wiring board according to the present embodiment.
  • electrolytic copper plating treatment is performed on both surfaces of the base material, and electrolytic copper plating films 31 and 32 (respectively on the copper foils 2a and 3a and the exposed embedded via 6) 2 ⁇ m thick).
  • an etching resist layer 33 having a predetermined pattern is formed on the electrolytic copper plating films 31 and 32 to form inner layer circuit patterns 34A and 34B described later. To form.
  • a plating resist layer 35 is formed on both surfaces of the base material obtained in the previous step.
  • the plating resist layer 35 has an opening 36b in the receiving land portion of the blind via hole, and further has an opening 36c in a region where the inner layer terminal is formed.
  • the plating resist layer 35 may have an opening 36a in a region where the embedded via 6 is exposed. Whether or not the opening 36a is provided is arbitrary.
  • the plating layer constituting the surface layer of the lid plating layer 37 needs to have resistance to the copper etchant used in the subsequent roughening treatment.
  • the silver plating layer satisfies this condition.
  • a nickel plating layer by electroless nickel plating or a gold plating layer by electroless gold plating may be formed instead of the copper plating layer.
  • a nickel plating layer by electroless nickel plating and a gold plating layer by electroless gold plating may be sequentially formed.
  • the lid plating layer 37 is made of silver, gold, under the condition that at least the surface layer is made of a material resistant to a copper etchant such as silver (Ag), gold (Au), nickel (Ni).
  • the plating layer which consists of nickel etc. can be comprised individually or in combination. In any of these cases, it is not necessary to change the subsequent steps, and the same effect as when the silver plating layer is formed can be obtained.
  • the configuration of the lid plating layer 37 is selected in consideration of productivity, cost, and the connection method to the inner layer terminal.
  • the surface of the inner layer circuit patterns 34A and 34B is roughened. This roughening process can be performed in the same manner as the method described in the first embodiment.
  • the lid plating layer 37 that covers the receiving land portion to be irradiated with laser light later is composed of a silver plating layer having copper etchant resistance. For this reason, the lid plating layer 37 is not roughened by the roughening treatment in this step. Therefore, the absorption rate of the carbon dioxide laser beam in the receiving land portion does not increase, and a low absorption rate is maintained.
  • a cover lay 41 having an insulating film 39 (for example, 12 ⁇ m thick) made of polyimide or the like and an adhesive layer 40 formed on one surface of the insulating film 39 is prepared.
  • the adhesive layer 40 is made of an adhesive such as acrylic or epoxy.
  • the lamination process which affixes the coverlay 41 to the double-sided circuit base material 38 is performed using a vacuum laminator etc.
  • the inner layer circuit patterns 34 A and 34 B and the lid plating layer 37 in the component mounting portion are filled with the adhesive layer 40.
  • the insulating layer 39 may be formed on the adhesive layer 40 after forming the adhesive layer 40 filling the inner layer circuit pattern with the structures 34 ⁇ / b> A and 34 ⁇ / b> B and the lid plating layer 37.
  • the thickness of the adhesive layer 40 is determined so that the inner layer circuit pattern 34A (34B) and the lid plating layer 37 can be completely filled.
  • the thickness of the thickest receiving land portion is 7.5 ⁇ m (copper foil 2a (3a): 5 ⁇ m, electrolytic copper plating film 31 (32): 2 ⁇ m, lid plating layer 37: 0. 5 ⁇ m). Therefore, the thickness of the adhesive layer 40 can be set to a value (8 ⁇ m) that is significantly smaller than the conventional one.
  • a conformal mask 44 (opening) for forming blind via holes is formed in the copper foil 43b of the single-sided copper-clad laminate 43 using a photofabrication technique. .
  • the single-sided copper-clad laminate 43 on which the conformal mask 44 is formed is made of an adhesive for build-up.
  • the adhesive layer 45 is laminated and adhered to the front and back surfaces of the double-sided core substrate 42.
  • the blind via holes 46A and 46B are formed by performing laser processing using the conformal mask 44 in the same manner as in the first embodiment. To do. (11) Next, a desmear process is performed in order to remove the resin residue generated when the blind via holes 46A and 46B are formed.
  • the conductive layer on the build-up layer (copper foil 43b and electrolytic copper plating film 47 thereon) is processed into a predetermined pattern by a photofabrication technique.
  • the outer layer circuit pattern 49 is formed.
  • a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.
  • the build-up type multilayer printed wiring board 51 according to the second embodiment is obtained.
  • the build-up type multilayer printed wiring board 51 according to the present embodiment has a stacked via structure including embedded vias 6 and blind vias 48A.
  • the build-up type multilayer printed wiring board 51 includes a component mounting part 51a in which a build-up layer is laminated on a double-sided core substrate 42, and a flexible film extending from the component mounting part 51a. Cable portion 51b.
  • the flexible cable portion 51b is a part of the double-sided core substrate 42 that is not provided with a buildup layer.
  • the flexible cable portion 51 b is provided with an inner layer terminal 50 exposed on the flexible insulating base material 1.
  • a protective plating film made of the same material as the lid plating layer 37 is formed on the surface of the inner layer terminal 50.
  • a plurality of inner layer terminals 50 may be formed on the flexible insulating base material 1 to constitute a flexible connector region.
  • the buildup layers are provided on the front and back surfaces of the double-sided core substrate 42, but the buildup layers may be provided only on one side.
  • the surface plating layer of the inner layer terminal 50 can be formed simultaneously with the formation of the lid plating layer 37. Thereby, it becomes possible to reduce the number of processes and improve productivity.
  • the adhesive layer 40 of the cover lay 41 can be made much thinner than before.
  • the blind via holes 46A and 46B can be formed shallowly. For example, it is about 10 ⁇ m smaller than the conventional one.
  • the ease of electrodeposition of the electrolytic copper plating film 47 to the inner walls of the blind via holes 46A and 46B is improved.
  • the influence on the blind vias 48A and 48B due to the thermal expansion of the constituent members of the multilayer printed wiring board is reduced. For this reason, it is possible to reduce the thickness of the electrolytic copper plating film 47 necessary for improving yield and ensuring connection reliability.
  • a lid plating layer 37 is provided on the receiving land portion of the blind via hole 46B that does not constitute a stacked via structure.
  • the structure of the blind via hole 48B (via depth and the like) is substantially the same as the blind via hole 48A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to this embodiment, a large processing margin can be ensured and productivity can be improved.
  • FIGS. 3A to 3C are process cross-sectional views illustrating the method for manufacturing the build-up type multilayer printed wiring board according to the present embodiment.
  • a coverlay 63 having an insulating film 61 (for example, 12 ⁇ m thick) made of polyimide or the like and an adhesive layer 62 (for example, 8 ⁇ m thick) formed on one surface of the insulating film 61 is prepared.
  • the adhesive layer 62 is made of an adhesive such as acrylic or epoxy.
  • the double-sided circuit base material inner circuit pattern 34A, 34B was formed in the boundary area
  • the insulating film 61 may be formed on the adhesive layer 62.
  • a plating resist layer 64 is formed in the regions to be the component mounting portions 76a on both sides of the base material obtained in the previous step.
  • the plating resist layer 64 has an opening 65b in the receiving land portion of the blind via hole.
  • the coverlay 63 becomes a plating resist layer so that FIG. 3A (2) may show.
  • the plating resist layer 64 may have an opening 65a in a region where the embedded via 6 is exposed. Whether or not the opening 65a is provided is arbitrary.
  • a silver plating layer (lid plating layer 66) serving as a terminal protective film is also formed on the surface of the copper plating layer serving as the inner layer terminal by the plating treatment in this step, and the inner layer terminal 67 is formed. Is completed.
  • the plating layer constituting the surface layer of the lid plating layer 66 needs to have resistance to the copper etchant used in the subsequent roughening treatment.
  • the silver plating layer satisfies this condition.
  • the lid plating layer 66 can adopt the same material and configuration as the lid plating layer 37 in the second embodiment.
  • the surface of the inner layer circuit patterns 34A and 34B is subjected to a roughening treatment.
  • This roughening process can be performed in the same manner as the method described in the first embodiment.
  • the lid plating layer 66 which is a portion to be irradiated with laser light later, is composed of a silver plating layer having copper etchant resistance, as in the first embodiment. For this reason, the lid plating layer 66 is not roughened by the roughening treatment in this step. Therefore, the absorption rate of the carbon dioxide laser beam in the receiving land portion does not increase, and a low absorption rate is maintained.
  • the adhesive layer 71 filling the inner layer circuit patterns 34A and 34B and the lid plating layer 66 in the component mounting portion is formed.
  • the cover lay 63 functions like a dam that prevents the adhesive from flowing out from the component mounting region 76a to the flexible cable portion 76b. Therefore, in this step, an adhesive with a high flow-out can be used in addition to an adhesive with a low flow-out such as a low-flow type prepreg or a bonding sheet.
  • a conformal mask 70 opening for forming blind via holes is formed in the copper foil 69b of the single-sided copper-clad laminate 69 using the photofabrication technique. .
  • the substrate 68 is laminated and adhered to the front and back surfaces.
  • blind via holes 72A and 72B conduction holes.
  • a desmear process is performed in order to remove the resin residue generated when the blind via holes 72A and 72B are formed.
  • the conductive layer (copper foil 69b and the electrolytic copper plating film 73 thereon) is processed into a predetermined pattern by a photofabrication technique.
  • the outer layer circuit pattern 75 is formed.
  • a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.
  • the build-up type multilayer printed wiring board 76 according to the third embodiment is obtained.
  • the build-up type multilayer printed wiring board 76 according to the present embodiment has a stacked via structure including the embedded via 6 and the blind via 74A.
  • the build-up type multilayer printed wiring board 76 includes a component mounting portion 76a in which a build-up layer is laminated on a double-sided core substrate 68, and a flexible cable extending from the component mounting portion 76a. Part 76b.
  • the flexible cable portion 24b is a part of the double-sided core board 68 that is not provided with a buildup layer.
  • the flexible cable portion 76 b is provided with an inner layer terminal 67 exposed on the flexible insulating base material 1.
  • a plurality of inner layer terminals 67 may be formed on the flexible insulating base material 1 to constitute a flexible connector region.
  • the cover lay 63 configured by sequentially laminating the adhesive layer 62 and the insulating film 61 is formed in the boundary region between the component mounting portion 76a and the flexible cable portion 76b. It is provided on the flexible insulating base material 1.
  • the adhesive layer 71 is filled with the inner layer circuit patterns 34A and 34B and the lid plating layer 66 in the component mounting portion 76a.
  • the thickness of the adhesive layer 71 needs to be equal to or greater than the thickness of the cover lay 63 and is preferably the same as the thickness of the cover lay 63.
  • the buildup layers are provided on the front and back surfaces of the double-sided core substrate 68, but the buildup layers may be provided only on one side.
  • the coverlay 63 is provided in the boundary region between the component mounting portion 76a and the flexible cable portion 76b, and is not provided inside the component mounting portion 76a. For this reason, it is not necessary to consider the flow of the adhesive filling the inner layer circuit patterns 34A and 34B of the component mounting portion 76a to the flexible cable portion 76b. Therefore, the choice of the adhesive used for forming the adhesive layer 71 is eliminated. Spread. Furthermore, since the thickness of the printed wiring board in the component mounting portion 76a can be reduced, the blind via holes 72A and 72B can be further shallowed. As a result, according to the present embodiment, the outer layer circuit pattern 75 can be further finely formed.
  • the lid plating layer 66 is provided on the receiving land portion of the blind via hole 72B that does not constitute the stacked via structure. Therefore, the structure of the blind via hole 72B (via depth, etc.) is substantially the same as the blind via hole 72A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to this embodiment, a large processing margin can be ensured and productivity can be improved.
  • the surface plating layer of the inner layer terminal 67 can be formed simultaneously with the formation of the lid plating layer 66. Therefore, it becomes possible to reduce the number of processes and improve productivity.
  • the wiring pattern and the plating film are made of copper.
  • the present invention is not limited to this, and other metals such as aluminum and silver may be used.
  • a coverlay is laminated on a substrate on which an inner layer circuit pattern is formed to produce a double-sided core substrate, and then a build-up layer is laminated and adhered to the double-sided core substrate,
  • the build-up layer may be laminated directly on the substrate via an adhesive layer filling the inner layer circuit pattern and the lid plating layer.
  • a coverlay having a copper foil on the surface can be used.
  • FIG. 5A shows a cover having the double-sided circuit substrate 12 described in the first embodiment (see FIG.
  • FIG. 5B shows a cover having the double-sided circuit substrate 38 described in the second embodiment (see FIG. 2B (5)) having a copper foil 41a and an adhesive layer 40 on the front and back surfaces of the insulating film 39, respectively. It is sectional drawing which shows the state which laminated

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

Dans le but d'obtenir un procédé de production peu onéreux et stable de cartes imprimées multi-couches assemblées comprenant une structure de trous de contact empilés permettant un montage à haute densité, une carte imprimée multi-couches assemblée comprend : un matériau de base isolant et souple (1), des configurations de circuit des couches intérieures (11A, 11B) formés sur les deux côtés du matériau de base isolant (1), et un substrat intérieur à double face (16). Ledit substrat intérieur à double face (16) comprend : un trou d'interconnexion noyé (6) traversant le matériau de base isolant (1) et connecté électriquement aux configurations de circuit des couches intérieures (11A, 11B), et une couche électro-déposée de couverture (9) recouvrant les sections de réception des configurations de circuit des couches intérieures (11A, 11B) exposées par le trou d'interconnexion noyé (6), dont la couche superficielle comprend de l'or, de l'argent ou du nickel. La carte imprimée multi-couches assemblée comprend en outre une couche d'assemblage stratifiée sur le substrat intérieur à double face (16). La couche d'assemblage comprend une configuration de circuit de couche extérieure (23) sur la couche superficielle et un trou d'interconnexion borgne (22A) connecté à la configuration de circuit de couche extérieure (23) et à la configuration de circuit de couche intérieure (11A). Le trou d'interconnexion borgne (22A) constitue le trou d'interconnexion noyé (6) et une structure de trous de contact empilés.
PCT/JP2011/053459 2010-04-30 2011-02-18 Carte imprimée multi-couches assemblée et son procédé de fabrication WO2011135900A1 (fr)

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JP2017208524A (ja) * 2016-05-18 2017-11-24 モテク インダストリーズ インコーポレイテッド． 太陽電池の透明な導電膜に電気めっきを実施し、太陽電池の電極を形成する方法
CN114501805A (zh) * 2021-12-08 2022-05-13 江苏普诺威电子股份有限公司 整体金属化封边麦克风载板的制作工艺
CN114501805B (zh) * 2021-12-08 2024-02-02 江苏普诺威电子股份有限公司 整体金属化封边麦克风载板的制作工艺

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