Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
  • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
  • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
  • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
  • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
  • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
  • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate

Definitions

• an object of one embodiment of the invention disclosed in this specification is to provide a semiconductor device by which the above problems are solved.
• One embodiment of the invention disclosed in this specification relates to a semiconductor device in which a transistor including an oxide semiconductor is employed as a transistor used in a memory circuit and a configuration of the memory cell is determined depending on data stored in the memory circuit so that the power consumption of the semiconductor device can be reduced.
• a transistor including an oxide semiconductor is used in a memory circuit, whereby noise of a bit line can be prevented.
• the memory circuit includes a memory cell that does not include the semiconductor element, so that power consumption of the semiconductor device can be reduced.
• the semiconductor device illustrated in FIG 3 includes a CPU 151, a main memory 152, an input/output interface 153, an address bus 156, a data bus 157, and a controller bus 158.
• the CPU 151 controls operation of an apparatus. Data required for the CPU 151 to execute a program is stored in the ROM 154 included in the main memory 152.
• Data used in the semiconductor device illustrated in FIG 3, such as data stored in the main memory 152, is described in binary scale: that is, the data is described as “1” or "0".
• the "1" and “0” which constitute the data are described as “high” and “low”, respectively, depending on the potential of a signal.
• FIG 1 is a circuit diagram illustrating a configuration example where "high” is a majority in the data stored in the ROM 154.
• FIG 4 is a circuit diagram illustrating a configuration example where "low” is a majority in the data stored in the ROM 154.
• a transistor 114 preferably has low off-state current characteristics in order to prevent unnecessary leakage of charges which causes noise of the first bit line.
• a transistor including a silicon semiconductor can be used as the transistor 114, it is preferable to use a transistor including an oxide semiconductor so as to have extremely low off-state current characteristics. The same can be said for a first pre-charging transistor 118 used in the first pre-charge circuit 110 and a second pre-charging transistor 119 used in the second pre-charge circuit 111.
• the first pre-charge circuit 110 and the second pre-charge circuit 111 have the same configuration, and each of them has a transistor.
• the first pre-charge circuit 110 includes a first pre-charging transistor 118
• the second pre-charge circuit 111 includes a second pre-charging transistor 119.
• Gate electrodes of the first pre-charging transistor 118 and the second pre-charging transistor 119 are connected in common to the pre-charge line 105, and source electrodes thereof are connected in common to a power supply line 130.
• a drain electrode of the first pre-charging transistor 118 is connected to the first bit line 103, and a source electrode of the second pre-charging transistor 119 is connected to the second bit line 104.
• the potential of the power supply line 130 is fixed at a constant potential.
• the memory circuit illustrated in FIG 1 is an example of a circuit including the two bit lines and the two word lines; accordingly, the period of time for one data readout operation includes a first pre-charge signal period 208, a first word signal period 209, a first data holding period 210, a second pre-charge signal period 211, a second word signal period 212, and a second data holding period 213, as is shown in the timing chart of FIG 2.
• the off-state current of a transistor connected to each bit line is extremely low; thus, the potential 203 of the first bit line and the potential 204 of the second bit line are hardly changed and are kept. Accordingly, the potential 206 of the first memory output line is kept at "low” and the potential 207 of the second memory output line is kept at "high".
• the potential 203 of the first bit line and the potential 204 of the second bit line are not changed and kept at "high", since no memory cell is electrically connected to the second word line 102.
• the potential 203 of the first bit line is output as a signal "high” to the first memory output line 126 via the first buffer 124.
• the potential 204 of the second bit line is output as a signal "high” to the second memory output line 127 via the second buffer 125. That is, the data "high” and “high” can be read out from the third memory cell 108 and the fourth memory cell 109, respectively.
• the potential 505 of the pre-charge line is set at "high” in the first pre-charge signal period 508.
• the potentials of the gate electrodes of the first pre-charging transistor 118 and the second pre-charging transistor 119 become "high".
• the potential 505 of the pre-charge line is set at "low” and the potential 501 of the first word line is set at "high” in the first word signal period 509, so that "high” is applied to the gate electrode of the transistor 114 in the first memory cell 106 .
• the potential 504 of the second bit line is not changed and is kept at "high", since the second memory cell 107 is a vacant cell. That is, the potential 503 of the first bit line becomes "low” and the potential 204 of the second bit line becomes "high".
• a transistor 616 preferably has low off-state current characteristics in order to prevent unnecessary leakage of charges which causes noise of the first bit line.
• a transistor including a silicon semiconductor can be used as the transistor 616, it is preferable to use a transistor including an oxide semiconductor so as to have extremely low off-state current characteristics. The same can be said for a first pre-charging transistor 118 used in the first pre-charge circuit 110 and a second pre-charging transistor 119 used in the second pre-charge circuit 111.
• M represents one or more metal elements selected from Ga, Al, Mn, and Co.
• M can be Ga,
• the second memory cell 607, the third memory cell 608, and the fourth memory cell 609 are open cells.
• the potential 205 of the pre-charge line is set at "high”. At this time, the potential of the gate electrode of the first pre-charging transistor 118 becomes "high".
• the potential 203 of the first bit line and the potential 204 of the second bit line are input to the first buffer 124 and the second buffer 125, respectively.
• the potentials of the input signals (“low” and “high”) are not changed in the first buffer 124 and the second buffer 125, and are output to the first memory output line 126 and the second memory output line 127, respectively.
• the off-state current of the transistor connected to the bit line is low; thus, the potential 203 of the first bit line and the potential 204 of the second bit line are kept. Accordingly, the potential of the first memory output line 126 is kept at "low", and the potential of the second memory output line 127 is kept at "high".
• the configuration described above can provide a semiconductor device equipped with a memory circuit with reduced power consumption.
• all the memory cells formed corresponding to the first word line 101 store fixed non-rewritable data.
• a first memory cell 706 and a second memory cell 707 are vacant cells.
• the vacant cell indicates a cell which does not include a semiconductor element (in this embodiment, a memory element).
• a semiconductor element in this embodiment, a memory element.
• FIG 7 an example is shown in which data "high" is stored in vacant cells.
• a memory transistor 719 is formed; a gate electrode thereof is connected to the second word line 102; a drain electrode thereof is connected to the second bit line 104; and a source electrode thereof is connected to the reference potential line.
• Data writing operation is not executed via the first word line 101 since it is not necessary for the memory cells formed corresponding to the first word line 101.
• the second bit line 104 is set at the ground potential, hot carriers are not generated around the drain electrode of the memory transistor 719, and charges are not accumulated in the floating gate electrode. Accordingly, the threshold voltage of the memory transistor 719 does not change and the data "low" is stored.
• the memory transistor stores the data "high” or “low” depending on a potential state of the floating gate electrode.
• the data written in the memory transistors is erased by opening a drain electrode, connecting a control gate electrode to the ground, and applying a high voltage to a source electrode. Electrons in the floating gate electrode get a high-energy state by the application of the high voltage to the source electrode, and the electrons can be extracted from the floating gate electrode by tunnel effect. Note that the data stored in all the memory cells including the memory elements is erased since a high voltage is applied to the source electrodes of all the memory cells.
• the potential of the pre-charge line 105 is set at "high”, and then the potentials of the gate electrodes of the first pre-charging transistor 118 and the second pre-charging transistor 119 become "high".
• the data “high”, “high”, “high”, and “low” can be acquired from the first to fourth memory cells 706 to 709, respectively. That is, the data “high” can be read out from the vacant cells, and the data “high” and “low” can be read out from the memory cells including memory transistors.
• the memory cells storing the fixed data are composed of vacant cells only.
• data composed of both "high” and “low” can be stored as non-rewritable fixed data when grounded cells including a transistor like the first memory cell 106 illustrated in FIG 1 and FIG. 4 are used in addition to the vacant cells.
• the main memory 801 and the dedicated circuit 802 are connected to each other via the address bus 804. Further, the main memory 801, the dedicated circuit 802, and the input/output interface 803 are connected to each other via the data bus 805 and the controller bus 806.
• the power consumption of the whole semiconductor device can be reduced and heat generation can be suppressed by applying any of the memory circuits described in Embodiments 1 to 4 to the main memory 801.
• Any of the memory circuits described in Embodiments 1 to 3 is applied to a non-rewritable memory circuit which is incapable of rewriting data of the main memory 801.
• a main memory including a data non-rewritable region and a data rewritable region can be formed by applying the memory circuit described in Embodiment 4.
• the CPU 811 controls operation of an apparatus. Data required for the CPU
• the ROM 814 is a memory circuit only for reading out data. Data stored in the ROM 814 is fixed in a manufacturing stage.
• the address bus 817 is a wiring (route) for transmitting commands or data necessary for the CPU 811 to the main memory 813.
• the data bus 818 is a wiring (route) for reading and writing from/to the main memory 813 and for acquiring and providing data from/for external devices via the input/output interface 816.
• the controller bus 819 is a wiring (route) for providing controlling information to the main memory 813 and the input/output interface 816.
• any of the memory circuits described in Embodiments 1 to 3 can be applied to the ROM 814.
• the memory circuit described in Embodiment 4 can be applied to the main memory 813 including the ROM 814 and the RAM 815.
• a transistor 3410 illustrated in FIG 10A is one of bottom-gate transistors and is also called an inverted staggered transistor.
• a transistor 3420 illustrated in FIG 10B is one of bottom-gate transistors called channel protective transistors and is also referred to as an inverted staggered transistor.
• an inorganic insulating film typified by a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film can be used.
• FIGS. 11A to HE are cross-sectional views illustrating an example of a manufacturing process of a transistor 2510.
• the transistor 2510 is an inverted staggered transistor having a bottom-gate structure, which is similar to the transistor 3410 illustrated in FIG 10A. [0229]
• an oxide semiconductor which is made to be an i-type semiconductor or a substantially i-type semiconductor by removal of an impurity is used.
• Such a highly-purified oxide semiconductor is highly sensitive to an interface state or interface charge; thus, an interface between the oxide semiconductor layer and the gate insulating layer is important. For that reason, the gate insulating layer that is to be in contact with a highly-purified oxide semiconductor needs to have high quality.
• a film formation method such as a sputtering method or a plasma CVD method can be employed as long as the method enables formation of a high-quality insulating layer as a gate insulating layer.
• an insulating layer whose film quality and characteristic of the interface between the insulating layer and an oxide semiconductor are improved by heat treatment performed after formation of the insulating layer may be formed as the gate insulating layer.
• any insulating layer may be used as long as the insulating layer can reduce the interface state density of the interface between the insulating layer and an oxide semiconductor and form a favorable interface as well as having favorable film quality as a gate insulating layer.
• a sputtering method will be described.
• the oxide semiconductor film 2530 is formed by a sputtering method
• powder substances also referred to as particles or dust
• the reverse sputtering refers to a method in which voltage is not applied to a target side and voltage is applied to a substrate side with the use of an RF power source under an argon atmosphere and ionized argon collides with the substrate so that a substrate surface is modified.
• a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used instead of an argon atmosphere.
• an oxide semiconductor used for the oxide semiconductor film 2530 an oxide semiconductor described in Embodiment 6, such as a four-component metal oxide, a three-component metal oxide, a two-component metal oxide, an In-O-based metal oxide, a Sn-O-based metal oxide, or a Zn-O-based metal oxide can be used. Further, Si may be contained in the above oxide semiconductor.
• the oxide semiconductor film 2530 is formed by a sputtering method with the use of an In-Ga-Zn-O-based metal oxide target. A cross-sectional view at this stage corresponds to FIG. 11 A.
• the oxide semiconductor film 2530 can be formed by a sputtering method under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas and oxygen.
• the filling rate of the target is higher than or equal to 90 % and lower than or equal to 100 %, preferably, higher than or equal to 95 % and lower than or equal to 99.9 %. With the use of the metal oxide target with high filling rate, the deposited oxide semiconductor film has high density.
• the substrate is held in a deposition chamber under reduced pressure, and the substrate temperature is set to higher than or equal to 100 °C and lower than or equal to 600 °C, preferably higher than or equal to 200 °C and lower than or equal to 400 °C.
• Deposition is performed while the substrate is heated, whereby the impurity concentration in the oxide semiconductor film formed can be reduced. Moreover, damage to the oxide semiconductor film due to sputtering is reduced.
• the oxide semiconductor film 2530 is formed over the substrate 2505 in such a manner that residual moisture in the deposition chamber is removed, a sputtering gas from which hydrogen and moisture have been removed is introduced into the deposition chamber, and the above-described target is used.
• an entrapment vacuum pump for example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
• an evacuation unit may be a turbo molecular pump provided with a cold trap.
• a hydrogen atom, a compound containing a hydrogen atom such as water (H 2 0), (more preferably, also a compound containing a carbon atom), and the like are removed, whereby the impurity concentration in the oxide semiconductor film formed in the deposition chamber can be reduced.
• the oxide semiconductor film 2530 is processed into an island-shaped oxide semiconductor layer by a second photolithography step and an etching step.
• a resist mask for forming the island-shaped oxide semiconductor layer may be formed by an inkjet method. Formation of the resist mask by an inkjet method needs no photomask; thus, manufacturing cost can be reduced.
• a step of forming the contact hole can be performed at the same time as processing of the oxide semiconductor film 2530.
• oxide semiconductor film 2530 when the oxide semiconductor film 2530 is etched, dry etching, wet etching, or both dry etching and wet etching may be employed.
• a mixed solution of phosphoric acid, acetic acid, and nitric acid such as ⁇ -07 ⁇ (produced by KANTO CHEMICAL CO., INC.), or the like can be used.
• the heat treatment apparatus is not limited to an electrical furnace, and may be provided with a device for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element.
• a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be used.
• RTA rapid thermal annealing
• GRTA gas rapid thermal annealing
• LRTA lamp rapid thermal annealing
• An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp.
• a GRTA apparatus is an apparatus for heat treatment using a high-temperature gas.
• the high temperature gas an inert gas which does not react with an object to
• the inert gas which is introduced into the heat treatment apparatus. It is preferable that the purity of the inert gas be 6N (99.9999 %) or higher, preferably 7N (99.99999 %) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).
• the first heat treatment may be performed at any of the following timings other than the above timing as long as it is performed after deposition of the oxide semiconductor layer: after the source electrode layer and the drain electrode layer are formed over the oxide semiconductor layer; and after the insulating layer is formed over the source electrode layer and the drain electrode layer.
• the formation of the contact hole may be performed either before or after the first heat treatment is performed on the oxide semiconductor film 2530.
• a first oxide semiconductor film with a thickness greater than or equal to 3 nm and less than or equal to 15 nm is deposited, and first heat treatment is performed at a temperature higher than or equal to 450 °C and lower than or equal to 850 °C, preferably higher than or equal to 550 °C and lower than or equal to 750 °C, under a nitrogen atmosphere, an oxygen atmosphere, a rare gas atmosphere, or a dry air atmosphere, so that a first oxide semiconductor film having a crystal region in a region including a surface is formed.
• crystal growth can proceed from the lower part to the upper part using the first oxide semiconductor film as a seed crystal, whereby an oxide semiconductor layer having a thick crystal region is formed.
• the etching step may be performed using a resist mask formed with a multi-tone mask. Since a multi-tone mask through which light is transmitted to have a plurality of intensities, a resist mask having a plurality of thicknesses can be formed with use of the multi-tone mask.
• the resist mask can be changed in shape by ashing, so that different patterns can be provided without a photolithography process.
• the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can also be reduced, whereby simplification of a process can be realized.
• a Ti film is used as the conductive film and an In-Ga-Zn-O-based oxide is used as the oxide semiconductor layer 2531; thus, an ammonia hydrogen peroxide solution (a mixed solution of ammonia, water, and a hydrogen peroxide solution) is preferably be used as an etchant of the conductive film.
• an ammonia hydrogen peroxide solution a mixed solution of ammonia, water, and a hydrogen peroxide solution
• a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed be used as the sputtering gas for the deposition of the insulating layer 2516.
• the transistor 2510 is formed (see FIG 11D).
• the silicon nitride film used as the protective insulating layer 2506 is formed in such a manner that the substrate 2505 over which layers up to the insulating layer 2516 are formed is heated to higher than or equal to 100 °C and lower than or equal to 400 °C, a sputtering gas containing high-purity nitrogen from which hydrogen and moisture are removed is introduced, and a silicon target is used. Also in that case, the protective insulating layer 2506 is preferably formed while moisture remaining in the treatment chamber is removed, in a manner similar to that of the insulating layer 2516.
• heat treatment may be further performed at higher than or equal to 100 °C and lower than or equal to 200 °C for longer than or equal to one hour and shorter than or equal to 30 hours under the atmosphere.
• This heat treatment may be performed at a fixed temperature.
• the following change in temperature is set as one cycle and may be repeated plural times: the temperature is increased from room temperature to a heating temperature and then decreased to room temperature.
• the current value in an off state (off-state current value) can be further reduced.
• the transistor including a highly-purified oxide semiconductor layer has high field-effect mobility, high-speed operation is possible.
• a driver circuit portion and a pixel portion can be formed over one substrate, and thus the number of components can be reduced.
• a wireless chip can be applied for managing goods in the distribution industry.
• goods are managed with the use of bar codes in general, bar codes are scanned optically and thus data cannot be scanned if there is an optical obstacle.
• a wireless chip is required to be equipped with a high-capacity memory circuit. According to one embodiment of the present invention, an increase in power consumption due to an increase in a capacity of a memory circuit can be prevented.
• a wireless chip 2601 includes an arithmetic circuit 2606 and an analog unit 2615.
• the arithmetic circuit 2606 includes a CPU 2602, a ROM 2603, a RAM 2604, and a controller 2605.
• the analog unit 2615 includes an antenna 2607, a resonance circuit 2608, a power supply circuit 2609, a reset circuit 2610, a clock generation circuit 2611, a demodulation circuit 2612, a modulation circuit 2613, and a power supply management circuit 2614.
• Power consumption of a whole wireless chip can be efficiently reduced by applying any of the memory circuits described in Embodiments 1 to 3 to the ROM 2603. Power consumption of a whole wireless chip can be efficiently reduced by applying the memory circuit described in Embodiment 4 to the RAM 2604. In addition, the reduction in power consumption can suppress heat generation of the wireless chip.
• the controller 2605 includes a CPU interface (CPUIF) 2616, a control register
• An induced electromotive force is generated by the antenna 2607 and the resonance circuit 2608 when the wireless chip 2601 is put in a magnetic field formed by a communication signal.
• the induced electromotive force is held and stabilized by electrical capacitance in the power supply circuit 2609, and supplied to each circuit in the wireless chip 2601 as a power supply voltage.
• a frequency and duty ratio of a clock signal is changed depending on a control signal generated in the power supply management circuit 2614.
• the power supply management circuit 2614 monitors a power supply voltage which is supplied from the power supply circuit 2609 to the arithmetic circuit 2606 or the current consumption in the arithmetic circuit 2606, and generates a signal for controlling the clock generation circuit 2611.
• the reception signal 2620 is demodulated in the demodulation circuit 2612, and then divided in the code extraction circuit 2618 into a control command, ciphertext data, and the like, which are subsequently stored in the control register 2617.
• control command is data specifying a response of the wireless chip
• the CPU 2602 breaks (decodes) the ciphertext in accordance with a code breaking program stored in the ROM 2603 by using a secret key 2624 stored in advance in the ROM 2603.
• the decoded ciphertext (decoded text) is stored in the control register 2617.
• the RAM 2604 is used as a data storing region.
• the CPU 2602 accesses the ROM 2603, the RAM 2604, and the control register 2617 through the CPUIF 2616.
• the CPUIF 2616 has a function of generating an access signal for any of the ROM 2603, the RAM 2604, and the control register 2617 based on an address required by the CPU 2602.
• the encoding circuit 2619 generates the transmission data 2623 from the decoded text, which is then modulated in the modulation circuit 2613. Next, the transmission signal 2621 is transmitted from the antenna 2607 to the reader/writer.
• this example is described, as an arithmetic method, a processing method using software, that is, a method in which the arithmetic circuit is configured with the CPU and the high-capacity memory, and a program is executed with the CPU; however, it is also possible to select an optimum arithmetic method according to the purpose and form the arithmetic circuit based on the selected method.
• an arithmetic circuit may be a dedicated circuit.
• an arithmetic circuit may include a dedicated circuit, a CPU, and a memory circuit so that the dedicated circuit performs part of arithmetic operation and that the CPU may execute programs of the other part of arithmetic operation using software.
• the semiconductor device 3000 which is one embodiment of the present invention includes a memory element, and is mounted on a printed wiring board, attached to a surface of an object, or incorporated in an object, so that the semiconductor device 3000 is fixed in the object.
• the semiconductor device may be incorporated in paper of a book or an organic resin of a package.
• an identification function can be obtained and forgery thereof can be prevented by utilizing the identification function. Further, by providing the semiconductor device which is one embodiment of the present invention in containers for wrapping devices, recording media, personal belongings, foods, clothes, daily necessities, electronic devices, and the like, a system such as an inspection system can be used efficiently.

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