WO2011070855A1 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
- Publication number
- WO2011070855A1 WO2011070855A1 PCT/JP2010/068291 JP2010068291W WO2011070855A1 WO 2011070855 A1 WO2011070855 A1 WO 2011070855A1 JP 2010068291 W JP2010068291 W JP 2010068291W WO 2011070855 A1 WO2011070855 A1 WO 2011070855A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- semiconductor device
- laser
- manufacturing
- thin film
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
- H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
Definitions
- the present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for separating and transferring a single crystal thin film or a semiconductor device made of a single crystal on an insulating substrate.
- TFT Thin Film Transistor
- a-Si amorphous silicon
- poly-Si polycrystalline silicon
- FIG. 13A shows a case where circuit elements such as pixels are formed on a glass substrate having a large area by an existing large liquid crystal TFT process (a-Si process or poly-Si process).
- a-Si process or poly-Si process it is necessary to form an a-Si film or the like on the entire surface of the glass substrate, or to crystallize the entire surface of the substrate with a laser.
- enormous apparatus and enormous investment are required along with the enlargement of the mother glass (10th generation size: 3.1 m ⁇ 2.9 m), and it is difficult to reduce the manufacturing cost.
- the TFT performance can be obtained only with large variations and large power consumption.
- FIG. 13B shows a large area glass substrate obtained by dividing a silicon device or a circuit element created on a silicon substrate (hereinafter referred to as “Si substrate”) by an existing IC (Integrated Circuit) process into chips.
- Si substrate silicon substrate
- An example of a method of transferring (or pasting) to the above is shown.
- a smart cut method hydrogen ion separation method
- affixing using die bonding may be used.
- Patent Document 1 The transfer using the smart cut method of the element is shown in Patent Document 1 and Patent Document 2 invented by the inventors of the present invention.
- This method is an effective method in the case of dividing and bonding to several tens to several hundreds of chips (several mm size) such as a panel driver.
- chips hundreds of chips
- it is impractical in terms of throughput and handling to divide and bond to several million elements (several tens of ⁇ m size) like pixel TFTs.
- the smart device is used to attach a silicon device as an element formed on a Si substrate or Si substrate (Si wafer) to a large-area glass substrate or the like without dividing it into chips.
- a silicon device as an element formed on a Si substrate or Si substrate (Si wafer) to a large-area glass substrate or the like without dividing it into chips.
- FIG. 13B it is not necessary to divide the Si substrate into a plurality of chips.
- the silicon device is separated by heat treatment after being bonded to the glass substrate, the entire element on the Si substrate is transferred onto the glass substrate. Therefore, it cannot be transferred at a wide interval such as a pixel pitch.
- FIG. 13 (d) it is necessary to form the elements formed on the silicon substrate at intervals, but in this case, the utilization efficiency of the silicon substrate is very high. It gets worse.
- a release layer 12 is formed on a first substrate (base substrate) 11, and a plurality of elements 13 are arranged on the first substrate.
- the first substrate 11 and the intermediate substrate 15 are separated by a release layer, and the entire device is transferred (first time).
- a lift-off method using wet etching and an etch stopper layer, or laser ablation in which laser irradiation is performed on the peeling layer from the back surface of the first substrate 11 is used.
- the first substrate 11 When laser irradiation is performed from the back surface of the first substrate 11, the first substrate 11 needs to be a transparent substrate. Then, as shown in FIG. 14D, a transparent intermediate substrate 15 holding the element 13 shown in FIG. 14C is pasted on the final substrate (transfer destination substrate) 17 to which the adhesive 16 is adhered. Match. Thereafter, as shown in FIGS. 14E and 14F, UV light is selectively irradiated (with a certain pixel pitch interval) from the back surface of the intermediate substrate 15 to UV-releasable adhesive 14. After weakening the adhesive property, the intermediate substrate 15 and the final substrate 17 are separated and only the element 13 to be transferred is transferred to the final substrate 17 (second time). Even when the second transfer is performed by irradiating UV light from the back surface of the intermediate substrate 15, the intermediate substrate 15 needs to be a transparent substrate.
- an element that can be actually transferred is not a single crystal silicon device, but a low-performance element made of a-Si or poly-Si that can be formed on a transparent base substrate by CVD (Chemical Vapor Deposition) or the like. It is limited to elements that can be formed on a transparent base substrate, such as a TFT or an LED formed of GaN whose interface with the sapphire substrate is easily peeled off by a laser. That is, the above method cannot transfer a single crystal silicon element or the like formed on an opaque silicon substrate that does not transmit light.
- the elements formed on the base substrate 11 cannot be directly transferred by being dispersed on the transfer destination substrate 17. That is, in order to disperse and transfer the element, the element is once bonded to the transparent intermediate substrate 15 coated with UV peeling adhesive or the like, and lift-off or laser irradiation is performed from the back surface of the first substrate 11. The element must be separated from the first substrate 11 and transferred onto the intermediate substrate 15. Furthermore, it is necessary to selectively irradiate the element formed on the intermediate substrate 15 with UV light or the like from the back surface of the intermediate substrate 15 and to disperse and transfer it onto the transfer destination substrate 17.
- the present invention has been made in view of such conventional problems, and a transfer target such as a semiconductor thin film or a semiconductor element can be transferred from a base substrate to a transfer destination substrate in a single transfer process with high accuracy. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can realize cost reduction by transferring and shortening the manufacturing process, and a semiconductor device manufactured by this manufacturing method.
- a method for manufacturing a semiconductor device includes a step of forming an island pattern in which a plurality of elements are arranged on a base substrate to form a first substrate, the first substrate, A step of bonding a second substrate different from the first substrate through a part of the plurality of elements, and forming a part of the plurality of elements formed on the first substrate. Irradiating a certain position with a laser having a wavelength that causes multiphoton absorption, thereby separating the part of the element from the first substrate and selectively transferring the element onto the second substrate. It is characterized by that.
- the multi-photon absorption phenomenon can be caused by being transmitted through the surface of the base substrate and condensing inside thereof.
- a modified region (modified layer) in which the crystal structure or the like is modified can be formed inside the base substrate by the multiphoton absorption phenomenon. In this modified region, since the crystal structure and the like are changed, cracks and cracks are generated. Therefore, the part of the element is easily peeled off from the base substrate and bonded through the part of the first element. The substrate and the second substrate can be easily separated.
- the part of the elements to be transferred can be directly transferred to the second substrate as a transfer destination without using an intermediate substrate. Further, since the laser irradiation can be selectively performed on a predetermined position of the base substrate, only the element to be transferred can be directly transferred to the transfer destination substrate. For this reason, transfer of a semiconductor device or the like can be performed once.
- the element to be transferred can be directly transferred from the base substrate (first substrate) to the transfer destination substrate (second substrate) in one transfer step, high-precision transfer with little positional deviation is realized, Costs can be reduced by improving yield and shortening the manufacturing process. Thereby, the processing capability (tact time) of the manufacturing process can be improved.
- a semiconductor device of the present invention is a semiconductor device formed by transferring elements on an insulating substrate, and the insulating substrate has raised portions arranged at a predetermined interval.
- the element is formed directly on the raised portion so that its upper surface is in contact with the raised portion and its lower surface is separated from the raised portion.
- the upper surface of the element means a surface facing upward without contacting the base substrate on the base substrate before the element is transferred to the insulating substrate.
- the lower surface of the surface means a surface in contact with the base substrate on the base substrate before the element is transferred to the insulating substrate.
- the semiconductor device having the above-described configuration is manufactured by the above-described manufacturing method of the present invention, high performance can be maintained even with a small element configuration.
- an intermediate substrate is not required in the manufacturing process as described above, there is an advantage that the throughput is high and the manufacturing cost is reduced.
- the raised portions are also called islands or island patterns.
- the present invention forms a modified region by multiphoton absorption in the base substrate by using a laser having a multiphoton absorption wavelength that transmits through the silicon surface and condenses inside the silicon substrate.
- An element such as a single crystal thin film or a device made of a single crystal can be selectively separated and transferred onto a large transfer destination substrate directly from the opaque base substrate.
- direct transfer from the base substrate to be transferred to the transfer destination substrate can be realized in one transfer step, high-accuracy transfer with little positional deviation can be realized, and cost can be reduced by shortening the manufacturing process. .
- FIG. 3 is a flowchart showing main steps of a method for manufacturing a semiconductor device according to the present invention. It is sectional drawing which shows the manufacture flow of the base substrate which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacture flow of the transfer destination board
- FIG. 9 is a cross-sectional view showing a manufacturing flow of a base substrate including a semiconductor element according to the fifth embodiment of the present invention, following the manufacturing flow shown in FIG. 8. It is sectional drawing which shows the flow for transferring the thin film to the transcription
- stealth dicing using a laser having a wavelength that causes multiphoton absorption that is transmitted through the surface of the base substrate and condensed inside the base substrate is used as an element bonding technique by the smart cut method.
- Lasers used in stealth dicing technology (stealth dicing lasers) pass through the surface of an opaque substrate such as a Si substrate and condense inside to form a modified layer inside the substrate, so originally this stealth dicing laser is used. It is used to divide the Si substrate into small elements by scanning the Si substrate in a mesh line shape and separating it in the cross-sectional direction.
- a predetermined element to be transferred from the back surface of the substrate is selectively irradiated with the laser in a planar manner, whereby the element is planarly separated from the Si substrate, and the element can be selectively separated.
- the base substrate is a substrate on which a semiconductor element is first formed
- the transfer destination substrate is a substrate onto which the semiconductor element formed on the base substrate is transferred.
- a substrate in which a semiconductor element is formed over a base substrate is also called a first substrate
- a transfer destination substrate is also called a second substrate.
- the transfer destination substrate is a substrate constituting a final product, it is also called a final substrate.
- examples of the base substrate include a Si substrate, an SOI (Silicon On Insulator) substrate, a sapphire substrate, a GaN substrate, and a GaAs substrate.
- examples of the transfer destination substrate include a glass substrate, a plastic substrate, and an insulating substrate such as a film bonded to a support substrate.
- the elements on the base substrate include a semiconductor thin film (single film) or a semiconductor device.
- the semiconductor device include a light emitting element, a liquid crystal control element, a photoelectric exchange element, a piezoelectric element, a thin film transistor element, a thin film diode element, a resistance element, a switching element, a minute magnetic element, and a minute optical element.
- an opaque Si substrate is used as a base substrate
- a glass substrate is used as a transfer destination substrate
- the element is a semiconductor device made of a single crystal Si thin film or single crystal Si.
- FIG. 1 is a flowchart showing main steps of a method of manufacturing a semiconductor device according to the present invention
- FIG. 2 is a cross-sectional view showing main steps of a method of forming a base substrate
- FIG. FIG. 4 is a cross-sectional view showing main steps of a method for forming a substrate
- FIG. 4 is a cross-sectional view showing main steps of a method for transferring a thin film to be transferred from a base substrate to a transfer destination substrate.
- the planar Si substrate 100 ' is thermally oxidized to form a thermal oxide film 101 of about 50 to 100 nm on the surface (S11 in FIG. 1, thermal oxidation step).
- the thermal oxidation here is to perform thermal oxidation at a temperature of 900 to 1000 ° C. for about 1 to 3 hours using a general vertical furnace or horizontal furnace.
- an oxide film may be formed by a CVD method or the like.
- a resist pattern 102 is formed by photolithography so that a single-film island of a predetermined size can adhere to the substrate.
- the thermal oxide film 101 and the Si substrate 100 having a predetermined thickness are etched to form an island (bump) 100 ′′ on the Si substrate 100.
- the Si substrate 100 ′ is formed into an island in a matrix shape, and the etching method employs dry etching using a general fluorine-based or chlorine-based gas, for example, for dry etching of Si, CF 4 , SF 6 , fluorine-based gas such as NF 3 or,, Cl 2, HCl, a chlorine-based gas such as BCl 3, and Ar, the dry etching .SiO 2 used in combination a gas such as O 2 may, CF 4, CHF 3, C 2 F 6, H 2, O 2, may be used in combination a gas such as Ar. Further, instead of dry etching, HF, BHF, Tsu nitrate, KOH, may be employed wet etching using SLA etchant.
- a general fluorine-based or chlorine-based gas for example, for dry etching of Si, CF 4 , SF 6 , fluorine-based gas such as NF 3 or,, Cl 2, HCl, a chlorine-based gas such as
- the island 100 ′′ made of the Si substrate material formed here becomes a single-crystal Si thin film (semiconductor element) 100a on the transfer destination substrate 200 obtained in a later process (S12 in FIG. 1, element formation process).
- the element formation process and the element separation of the thin film can be realized at the same time by forming the Si substrate 100 'into an island (S13 in FIG. 1, element separation process). Then, as shown in FIG. 2D, when the resist pattern 102 is peeled off by performing ashing and peeling cleaning, the Si substrate 100 as the base substrate can be obtained.
- the Si substrate 100 in order to distinguish the first flat Si substrate 100 ′ from the Si substrate obtained by performing the steps S11 to S13 in FIG.
- the Si substrate after formation is denoted by Si substrate 100.
- the back surface of the Si substrate 100 is polished in advance by CMP before the thermal oxide film forming step so that laser light is not scattered by unevenness on the back surface of the Si substrate 100 during a laser irradiation process described later.
- the back surface of the Si substrate 100 after the resist pattern peeling process may be polished by CMP to make a mirror surface.
- the back surface of the Si substrate 100 indicates a surface opposite to the surface on which the thermal oxide film 101 is formed.
- a resist pattern 201 is formed on a flat glass substrate 200 ′ by photolithography so that islands (protrusions) are formed at predetermined intervals (resist pattern forming step).
- the island 200 ′′ on the glass substrate 200 ′ is preferably a pattern that is slightly larger than the island 100 ′′ on the Si substrate 100 side as shown in FIG.
- the interval between the islands 200 ′′ is previously set so as to correspond to the pixel pitch, and is desirably a pitch that is an integral multiple of the island 100 ′′ on the Si substrate 100 side. That is, it is desirable to form the resist pattern 201 so as to satisfy this condition.
- the glass substrate 200 ′ is etched using the resist pattern 201 as a mask to form a matrix-like island 200 ′′ (S21 in FIG. 1, an island formation step).
- etching method dry etching in which gases such as CF 4 , CHF 3 , C 2 F 6 , H 2 , O 2 , and Ar are combined may be employed, and wet etching using HF, BHF, or the like may be employed.
- HF a step of about 1 to 2 ⁇ m can be formed by etching for about 10 to 20 minutes.
- a glass substrate 200 serving as a transfer destination substrate is obtained on which the semiconductor element on the Si substrate 100 can be transferred as shown in FIG. 3C.
- the glass substrate after the element separation is used. It describes with the glass substrate 200.
- a surface treatment process and a bonding process are performed on the Si substrate 100 and the glass tip substrate 200 that have been performed through the steps as described above (S31 in FIG. 1).
- a general smart cut treatment method can be used. That is, the surfaces of both substrates are subjected to plasma treatment or chemical treatment to make the surfaces hydrophilic.
- plasma treatment Ar plasma, atmospheric pressure plasma, or the like can be used.
- hydrophilic treatment may be performed by performing chemical treatment such as ozone water cleaning and SC-1 cleaning (mixed solution of hydrogen peroxide water and ammonia water) for several minutes.
- the two substrates are bonded face-to-face in a surface-treated state, they are joined by intermolecular force (Van der Worth force). Thereafter, by performing pre-annealing at a temperature of 200 ° C. for about 2 hours, a dehydration reaction proceeds, a covalent bond is formed, and the bonding becomes stronger.
- FIGS. 4A and 4B among the plurality of thermal oxide films 101 that are element-isolated on the Si substrate 100, there is a receiving island 200 ′′ on the glass substrate 200. Only the parts are joined.
- a laser with a wavelength that causes multiphoton absorption is applied to the Si substrate 100 bonded to the glass substrate 200 from the back surface side of the Si substrate 100. 1 is selectively irradiated (S32 in FIG. 1, laser irradiation step), and the laser beam is condensed inside the Si substrate 100 to form a modified layer (modified region) 103.
- a crack region formed by cracks formed in the substrate due to thermal strain induced by optical damage due to multiphoton absorption 2) a phase change caused by local heating by multiphoton absorption Or a melt-processed region formed by the formation of a region with a changed crystal structure (for example, in the case of single crystal silicon, a region that has changed to amorphous silicon with disordered crystal structure periodicity due to local heating is melted. 3), or 3) a refractive index change region formed by inducing a permanent structural change such as ionic valence change, crystallization or polarization orientation in the substrate. Whether to form the region can be determined depending on the type of the substrate.
- a semiconductor substrate such as a Si substrate
- a transparent substrate such as a glass substrate or a sapphire substrate
- a refractive index changing region can be formed as the modified region.
- a crack or a region in which the crystal structure is weakly changed in the Si substrate 100, or a structural change such as an ionic valence or a polarization orientation is induced. Since the region and the like are formed, when the Si substrate 100 and the glass substrate 200 are separated in the opposite directions, the Si substrate 100 is easily separated at a position inside the Si substrate 100 where the modified layer 103 is formed. (S33 in FIG. 1, separation step).
- the portion on the side bonded to the glass substrate 200 through the thermal oxide film 101 is transferred onto the glass substrate 200 as shown in FIG.
- the glass substrate 200 to which the thin film (single crystal Si thin film, part of the base substrate) 100a is transferred can be obtained and used as a final substrate for a semiconductor device.
- the thickness can be appropriately controlled by adjusting the laser condensing position, and if necessary, such as when exceeding the laser adjustment range, after transfer onto the glass substrate 200, the dry etching apparatus is
- the single crystal Si thin film 100a thin film may be etched back to reduce the film thickness of the single crystal Si thin film 100a.
- the laser irradiated from the back side of the Si substrate 100 has a wavelength of 1064 nm, and a semiconductor laser pumped Nd: YAG laser of a stealth dicing laser is used.
- a laser that can be used as a laser light source there is an Nd: YVO4 laser, an Nd: YLF laser, or a titanium sapphire laser in addition to an Nd: YAG laser.
- Laser irradiation is performed under the condition that the peak power density is 1 ⁇ 10 8 W / cm 2 or more and the pulse width is 1 ⁇ s or less.
- the peak power density is 1 ⁇ 10 11 W / cm 2 to 1 ⁇ 10 12 W / cm 2 and the pulse width is 1 ns to 200 ns.
- what kind of laser is used can be determined by the type of the modified region to be formed.
- a laser having a peak power density of 1 ⁇ 10 8 W / cm 2 or more and a pulse width of 1 ⁇ s or less is used. It is preferable to use a YAG laser, an Nd: YVO4 laser, or an Nd: YLF laser.
- a laser having a peak power density of 1 ⁇ 10 8 W / cm 2 or more and a pulse width of 1 ns or less (more preferably 1 ps or less) is used.
- a titanium sapphire laser Since such a laser has a long wavelength, even a substrate that is not transparent to UV light is transmitted through the surface of the substrate and condensed inside the substrate due to the multiphoton absorption phenomenon. It is possible to form a modified layer such as a region in which the change is weak or a region in which a structural change such as ionic valence or polarization orientation is induced.
- the laser irradiation is preferably performed at a predetermined position where an element to be transferred is formed while scanning the laser light source along the substrate surface.
- the position of the laser light source may be fixed and the stage on which the substrate is placed may be scanned.
- the entire surface can be irradiated with a laser at a predetermined position having a peeling area larger than the spot diameter of the laser, and a modified layer for peeling is formed on the entire surface, and separation at the modified layer is more reliably performed. It can be carried out.
- a method for irradiating these lasers a conventional method can be used.
- laser irradiation may be performed with the temperature of the Si substrate 100 raised from room temperature.
- the Si band gap room temperature: 1.12 eV
- the Si band gap decreases to 1.1 eV or less
- a YAG laser wavelength inside the substrate
- the band gap can be reduced to 1.1 eV or less by raising the substrate temperature to 700 ° C. or higher.
- the element to be transferred is irradiated with the stealth dicing laser, whereby the element The element can be selectively transferred onto a large-area glass 200 to be a planar transfer substrate (second substrate) by peeling the substrate from the base substrate.
- second substrate planar transfer substrate
- ⁇ Second Embodiment> As described in the first embodiment, an example will be described in which a single crystal Si thin film (element) of a Si substrate is directly distributed and transferred onto a glass substrate. Compared with the first embodiment, in this embodiment, in order to make separation with the modified layer formed on the glass substrate easier, the base substrate is stronger than the other portions in the substrate in advance. An example of adding a step of forming a weak weak layer will be described.
- FIG. 5 is a cross-sectional view showing the steps of forming the Si substrate 100 in the present embodiment.
- the formation of the Si substrate 100 according to the present embodiment further includes a step of forming the fragile layer 104 in advance inside the Si substrate 100. Since the other steps are as described in the first embodiment, they will be described briefly.
- a thermal oxide film 101 is formed on a flat Si substrate 100 ′, and then in FIG. As shown, a fragile layer 104 is formed inside the Si substrate 100 ′.
- hydrogen ions are implanted into the Si substrate 100 ′ to a predetermined depth inside the Si substrate 100 ′ by hydrogen ion implantation or hydrogen ion doping.
- hydrogen ion implantation or doping conditions for example, when H + ions are implanted, the implantation energy is about 20 to 60 keV, and the implantation amount is 5 ⁇ 10 14 / cm 2 to 5 ⁇ 10 15 / cm 2 . Perform under certain conditions.
- ion doping including ions such as H 3+ is performed, the implantation energy is approximately 20 to 60 keV, and the implantation amount is 1 ⁇ 10 16 / cm 2 to 5 ⁇ 10 16 / cm 2 .
- the Si substrate 100 ′ Since hydrogen ions are light, they can penetrate deep into the Si substrate by ion implantation or ion doping. At this time, the Si crystal lattice is disturbed and stays inside. Subsequently, when annealing is performed at a low temperature of about 200 ° C. to 400 ° C., the internal pressure rises in a region where hydrogen ions remain, and microbubbles (platelets) are generated to induce microcracks. Therefore, the layer into which hydrogen ions are implanted or doped forms a fragile layer 104 inside the Si substrate 100 ′ by applying a subsequent thermal annealing.
- the predetermined depth can be appropriately adjusted by changing the implantation energy in consideration of the film thickness of the thin film 100a formed in a later step.
- a resist pattern 102 forming step and an etching step are performed on the Si substrate 100 '. Thereafter, a Si substrate 100 having a fragile layer 104 therein is obtained as shown in FIG.
- the glass substrate 200 may be formed according to the steps described in the first embodiment, as shown in FIG.
- the surface treatment process, the bonding process, and the laser irradiation process for the Si substrate 100 and the glass substrate 200 are also as described in the first embodiment.
- a modified layer 103 including a melt-processed region (amorphous silicon with disordered crystal structure periodicity) is formed inside the Si substrate 100 after the laser irradiation process. From this, cracks and cracks occur.
- the fragile layer 104 is formed in advance by hydrogen ion implantation and annealing, cracks and cracks caused by laser irradiation can run along the fragile layer 104. Therefore, the single crystal Si thin film 100a can be more easily separated from the Si substrate 100 as the base substrate.
- the base is formed in the place of the modified layer 103 that is easily peeled along the fragile layer 104.
- the substrate (Si substrate 100) and the transfer destination substrate (glass substrate 200) are easily separated. Thereby, the glass substrate 200 to which the thin film (single crystal Si thin film) 100a is transferred can be obtained.
- the base body of the base substrate is preliminarily placed inside the other portions of the substrate.
- a light absorption layer that absorbs more light is formed will be described. Processes other than the light absorption layer forming step are as described in the first and second embodiments, and will be briefly described. The description will be made with reference to the same drawings as those in the second embodiment.
- a thermal oxide film 101 is formed on a flat Si substrate 100 ′, and then in FIG. As shown, a light absorption layer 105 is formed inside the Si substrate 100 ′.
- ions are implanted into the Si substrate 100 'to a predetermined depth inside the Si substrate 100' by ion implantation or ion doping.
- the implanted ions form donor or acceptor levels in the band gap and form the light absorption layer 105 on the Si substrate 100 ′.
- the predetermined depth can be appropriately adjusted in consideration of the film thickness of the thin film 100a formed in a later step.
- ions boron, phosphorus, arsenic, gallium, indium, titanium, palladium, carbon, silicon, antimony, zinc, tellurium, cadmium, and the like can be used.
- ion implantation or ion doping conditions for example, when boron is ion-implanted, the implantation energy is about 40 to 150 keV, and the implantation amount is 1 ⁇ 10 15 / cm 2 or more.
- phosphorus is ion-implanted, the implantation energy is about 100 to 250 keV, and the implantation amount is 1 ⁇ 10 15 / cm 2 or more.
- a resist pattern 102 forming step and an etching step are performed on the Si substrate 100 '. Then, through the resist pattern 102 peeling step, as shown in FIG. 5E, the Si substrate 100 having the light absorption layer 105 therein is obtained.
- the glass substrate 200 may be formed according to the steps described in the first embodiment, as shown in FIG.
- a modified layer 103 including a melt-processed region (amorphous silicon with disordered crystal structure periodicity) is formed inside the Si substrate 100 after the laser irradiation process. From this, cracks and cracks occur.
- the light absorption layer 105 is formed inside the Si substrate 100, multi-photon absorption through the acceptor level here easily occurs in the light absorption layer 105 when laser irradiation is performed. Amorphous silicon having a more disturbed crystal structure periodicity is formed, and the modified layer 103 that is easy to peel off can be formed.
- Patent Document 6 irradiation is performed using a YAG laser having a wavelength of 1064 nm as a laser light source, and a Si substrate (thickness of 500 ⁇ m or less) having a band gap of 1.12 eV is used as a base substrate.
- a YAG laser having a wavelength of 1064 nm as a laser light source
- Si substrate having a band gap of 1.12 eV
- most of the light is transmitted (internal transmittance of about 80% or more).
- the acceptor level is formed only 0.045 eV from the bottom of the valence band, and therefore, via this acceptor level.
- the light absorption layer 105 is formed in advance by ion implantation of boron or the like, when a laser beam having a multiphoton absorption wavelength is irradiated from the back surface of the substrate body of the base substrate 100, more of the light absorption layer 105 is formed in the substrate. Laser light can be absorbed. Therefore, it is possible to form a modified layer having amorphous silicon (melting treatment region) whose crystal structure periodicity is more disturbed by laser light irradiation.
- the Si substrate 100 and the glass substrate 200 are separated from each other in the opposite directions, the Si substrate 100 and the glass substrate 200 are easily removed from the modified layer 103. Is easily separated, and the glass substrate 200 to which the thin film (single crystal Si thin film) 100a is transferred can be obtained.
- the Si substrate 100 and the glass substrate 200 are formed by any of the methods according to the first to third embodiments, and the surface treatment, the bonding process, and the laser irradiation process for the Si substrate 100 and the glass substrate 200 are performed.
- the modified layer 103 which is easily peeled is formed.
- the two substrates are separated using a peeling method by a mechanical force or a laminate film peeling method.
- a blade 301 having a sharp tip from the side surface of the substrate is applied to the Si substrate 100 on which the modified layer 103 is formed by the laser irradiation process.
- the cracks and cracks formed in the modified layer 103 are expanded by mechanical force, and the thin film 100 a is peeled from the modified layer 103.
- an adhesive sheet 302 used for dicing or the like as a laminate film is attached to the back surface of the bonded Si substrate 100, and the adhesive sheet 302 and the Si substrate 100 are peeled off simultaneously. As a result, the thin film 100 a is peeled from the modified layer 103.
- the elements (single crystal Si thin film) on the Si substrate (base substrate) are distributed and transferred to a large-area glass substrate (transfer destination substrate) by the methods of the first to fourth embodiments described above. Can do.
- the TFT forming step photolithography, etching, film formation, etc.
- a normal large glass substrate such as a poly-Si process
- a TFT backplane having high performance and low variation TFTs made of single crystal Si can be formed on the glass substrate. Since a high performance and low variation TFT backplane can be obtained, it can be suitably used not only as a liquid crystal panel but also as a backplane such as an organic EL (OLED) panel.
- OLED organic EL
- a part of the semiconductor device is a semi-finished semiconductor device that has not been processed. In other words, it is not a semiconductor device that has been completed up to the final process (multi-layer wiring completion process), but a semi-completed (unfinished) device in which, for example, a gate electrode or even source / drain electrodes are formed. To do.
- the wiring formation that may be performed means that the wiring may be formed on a large area substrate (transfer destination substrate) after the transfer.
- a semiconductor element (a minute transistor) is formed over a base substrate using a general process used for IC manufacturing.
- a general process used for IC manufacturing a general process used for IC manufacturing.
- this embodiment is merely an example of a general IC process, and the present invention is not limited to this.
- FIG. 8 is a cross-sectional view for explaining main steps for forming a transistor (element) on a Si substrate
- FIG. 9 explains main steps for transferring a semiconductor device formed on the Si substrate to a glass substrate.
- the Si substrate 100 ' is thermally oxidized to form a thermal oxide film 101 of about 50 to 100 nm on the surface (thermal oxidation step).
- the thermal oxide film is formed by performing thermal oxidation for about 1 to 3 hours at a temperature of 900 to 1000 ° C. using a general vertical furnace or horizontal furnace.
- an oxide film may be formed by a CVD method or the like.
- n-well n-well
- p-well p-well
- n-well and p-well are separated using LOCOS oxidation used in a general IC process. Thereafter, in order to adjust the threshold voltage of each of the NMOS and PMOS, ion implantation is performed on each channel region in the n-well and p-well as necessary using a resist as a mask. For example, boron ions are implanted under an implantation condition of an implantation energy of 10 to 40 keV and an implantation amount of about 1 ⁇ 10 12 to 1 ⁇ 10 13 / cm 2 .
- a gate electrode material is formed or sputtered, and then patterned by photolithography to form a gate electrode 108 having a thickness of about 200 to 400 nm (gate electrode formation).
- a material for the gate electrode 108 an n + Poly gate or a p + Poly gate doped with phosphorus or boron at a high concentration may be formed by CVD, or a metal such as W, Mo, or MoW may be formed by sputtering.
- Etching methods for forming patterning include chlorine-based gases such as CCl 4 , BCl 3 , SiCl 4 , and Cl 2 , fluorine-based gases such as SF 6 , CF 4 , and NF 3 , and Ar, O 2. For example, dry etching using a combination of such gases.
- a resist pattern 102b is formed so as to cover the gate electrode 108 on the n-well 106, and low concentration phosphorus is implanted using the gate electrode 108 and the resist pattern 102b as a mask.
- the LDD region 109 is formed in the NMOS (LDD region forming step). That is, phosphorus is implanted under the conditions that the implantation energy is 10 to 40 keV and the implantation amount is about 1 ⁇ 10 13 to 1 ⁇ 10 14 / cm 2 .
- the LDD region forming step can be omitted.
- an insulating film such as a high-temperature oxide film is formed on the entire surface of the Si substrate 100 'to a thickness of about 200 to 600 nm and then etched back.
- the sidewall 110 is formed on the side portion of the gate electrode 108 with high accuracy in a self-aligned manner (sidewall formation step).
- the length of the LDD region 109 is defined by the width of the sidewall 110.
- a resist pattern 102 c is formed so as to cover the gate electrode 108 and the sidewall 109 on the n-well 106. Then, as shown in FIG. 8 (f), high concentration phosphorus is implanted using the gate electrode 108 and the side wall 109 on the p-well 107 and the resist pattern 102c on the n-well 106 as a mask.
- a source / drain region 111 which is an n + region is formed on the well 107 (source / drain region forming step).
- high concentration boron is implanted using the gate electrode 108 and the sidewall 109 on the n-well 106 and the resist pattern on the p-well 107 as a mask to form a p + region on the n-well 106.
- a certain source / drain region 111 is formed.
- phosphorus or arsenic is implanted into the n + region under the condition that the implantation energy is 20 to 100 keV and the implantation amount is about 1 ⁇ 10 15 to 5 ⁇ 10 15 / cm 2 , and n on the p-well 107.
- a source / drain region 111 of the + region is formed.
- boron or BF 2 is implanted into the p + region under the condition that the implantation energy is 20 to 100 keV and the implantation amount is about 1 ⁇ 10 15 to 5 ⁇ 10 15 / cm 2 , and is formed on the n-well 106.
- a source / drain region 111 of the p + region is formed.
- an interlayer insulating film 112 is formed on the entire surface of the thermal oxide film 101 by using the CVD method on the Si substrate 100 '(interlayer insulating film forming step).
- a SiNO film having a thickness of about 50 to 200 nm, a TEOS film having a thickness of about 200 to 600 nm, or a laminated film thereof is used as the interlayer insulating film 112.
- the Si substrate 100 ′ is subjected to activation annealing at a temperature of 800 to 900 ° C. for about 1 to 2 hours to activate the impurity ions implanted into the source / drain regions.
- contact holes are formed in the interlayer insulating film 112 by performing photolithography and etching.
- etching method for forming the contact hole dry etching using a gas such as Cl 2 or wet etching using HF or the like is employed.
- an interlayer insulating film 114 is further formed on the entire surface of the interlayer insulating film 112 using the CVD method on the Si substrate 100 ′ (interlayer insulating film re-forming step).
- the interlayer insulating film 114 a SiN film having a thickness of about 100 to 300 nm, a TEOS film having a thickness of about 200 to 600 nm, or a stacked film thereof can be used.
- hydrogen sintering may be performed at a temperature of 450 degrees for about 30 to 60 minutes.
- the surface of the interlayer insulating film 114 is polished and planarized by CMP (polishing step).
- the back surface of the Si substrate 100 ′ may be polished by CMP at the same time so that laser light is not scattered by laser irradiation in a subsequent process.
- a resist pattern 102d is formed on the entire surface of the interlayer insulating film 114, and photolithography and etching are performed using the resist pattern 102d as a mask.
- the process is performed until the Si substrate 100 ′ is etched to a predetermined depth, and as shown in FIG. 9D, the transistors are separated for each transistor (element isolation step).
- etching method for element isolation dry etching of Si includes fluorine-based gas such as CF 4 , SF 6 , NF 3 , chlorine-based gas such as Cl 2 , HCl, BCl 3 , and Ar , O 2 and other gases are used in combination.
- gases such as CF 4 , CHF 3 , C 2 F 6 , H 2 , O 2 and Ar may be used in combination.
- wet etching using HF, BHF, hydrofluoric acid, hot phosphoric acid, or the like may be combined.
- the entire Si substrate 100 ′ is ashed and immersed in an organic stripping solution to remove the resist pattern 102 d on the surface, and the surface of the interlayer insulating film 114 is exposed.
- a Si base substrate 100 in which minute transistors are formed on the Si substrate 100 ′ as shown in FIG. 9E is obtained.
- the Si substrate after element isolation is represented by the Si substrate 100.
- the glass substrate 200 is formed by the same method as described in the first to fourth embodiments (see FIG. 3). Further, the surface treatment of the Si substrate 100 and the glass substrate 200, the bonding step, the subsequent laser irradiation step, the transfer step, and the like are the same as those described in the first embodiment (see FIG. 10). ).
- the thin film separated from the Si substrate main body is separated in the Si substrate 100 by the portion of the modified layer 103 formed therein. (Single crystal Si thin film, part of the base substrate) is transferred to the glass substrate 200 together with the transistor. A part of the transferred base substrate may be removed by performing etch back with a dry etching apparatus.
- a sub-micron level fine transistor that is difficult to be finely processed on a large-area insulating substrate such as a glass substrate can be formed on the large-area insulating substrate.
- the surface of the interlayer insulating film 112 is polished and planarized by CMP.
- the fragile layer 104 is formed by implanting or doping hydrogen ions to a predetermined depth inside the Si substrate 100 ′.
- the implantation energy is about 150 to 250 keV, and the implantation amount is 1 ⁇ 10 16 to 1 ⁇ 10 17 / cm 2. do it.
- the implantation energy is about 150 to 250 keV, and the implantation amount is 2 ⁇ 10 17 / cm 2 to 1 ⁇ 10 18 / cm 2. Ion doping may be used.
- the implanted or doped hydrogen ion layer forms a fragile layer 104 in the Si substrate 100 by subsequent thermal annealing (fragile layer forming step).
- the predetermined depth can be appropriately adjusted by changing the implantation energy in consideration of the thickness of the thin film transferred to the glass substrate in a later step.
- This fragile layer forming step may be performed after the thermal oxide film 101 is formed on the Si substrate 100 ′ (FIG. 8A).
- the steps after the fragile layer forming step are the same as those described in the first to fifth embodiments.
- the transfer process of a minute transistor will be briefly described.
- multiphoton absorption is performed from the back surface of the Si substrate 100 to the bonded Si substrate 100 and the glass substrate 200.
- a modified layer 103 including a melt-processed region (amorphous silicon having a disordered crystal structure periodicity) is formed at the laser irradiation position inside the Si substrate 100, and this is the starting point. Cracks and cracks occur.
- the fragile layer 104 is formed in advance by implantation of hydrogen ions, cracks and cracks run along the fragile layer 104, and as shown in FIG.
- the substrate 100 is separated, and the Si substrate 100 and the glass substrate 200 are separated.
- the light absorbing layer 105 can be formed by the same process as the light absorbing layer forming process in the third embodiment, detailed description is omitted.
- the light absorbing layer 105 may be formed after the thermal oxide film 101 is formed on the Si substrate 100 ′ (FIG. 8A).
- the surface of the interlayer insulating film 112 may be polished and planarized by CMP.
- the implantation energy is higher than the conditions in the third embodiment. Is preferably increased.
- the implantation energy is about 150 to 300 keV and the implantation amount is 1 ⁇ 10 15 / cm 2 or more.
- the steps after the formation process of the light absorption layer are the same as those described in the sixth embodiment. That is, when a laser having a multiphoton absorption wavelength is irradiated to the bonded Si substrate 100 and glass substrate 200 from the back surface of the Si substrate 100, a melt processing region (crystal structure) is formed at the laser irradiation position inside the Si substrate 100. A reformed layer 103 containing amorphous silicon having a disturbed periodicity is formed, and cracks and cracks are generated.
- the light absorption layer 105 is formed by ion implantation of boron or the like in advance, it absorbs more laser light and has amorphous silicon (melting treatment region) whose crystal structure periodicity is more disturbed.
- the modified layer 103 can be formed. Therefore, the Si substrate 100 and the glass substrate 200 can be more easily separated.
- the Si substrate 100 and the glass substrate 200 are formed by any of the methods according to the fifth to seventh embodiments, and the surface treatment, the bonding process, and the laser irradiation process for the Si substrate 100 and the glass substrate 200 are performed.
- the modified layer 103 which is easily peeled is formed.
- the two substrates are separated by using a mechanical peeling method or a laminate film peeling method.
- a blade 301 having a sharp tip from the side surface of the substrate is applied to the Si substrate 100 on which the modified layer 103 is formed by the laser irradiation process.
- the cracks and cracks formed in the modified layer 103 are expanded by mechanical force, and on the Si substrate 100 along with the thin film made of the Si substrate material on the Si substrate 100 at the position of the modified layer 103.
- the formed transistor is peeled from the Si substrate 100.
- an adhesive sheet 302 used for dicing or the like as a laminate film is attached to the back surface of the bonded Si substrate 100, and the adhesive sheet 302 and the Si substrate 100 are peeled off simultaneously.
- the transistor formed on the Si substrate 100 together with the thin film made of the Si substrate material on the Si substrate 100 is peeled off from the Si substrate 100 at the position of the modified layer 103.
- the semiconductor devices on the Si substrate can be distributed and transferred onto a large-area glass substrate (transfer destination substrate).
- an adhesive when the element is transferred from the base substrate to the transfer destination substrate, an adhesive may be required depending on the transfer destination substrate.
- plastic substrates with high warpage, undulation, and surface roughness can be bonded to glass substrates with low surface roughness (surface roughness Ra) by intermolecular force without using an adhesive.
- bonding with an adhesive or the like is necessary because bonding is not performed by intermolecular force.
- an adhesive in the flat transfer destination substrate, an adhesive may be applied in advance only to the position where the element is bonded, or in the transfer destination substrate on which the island pattern ridges are formed, An adhesive may be applied only on the top.
- the present invention can also be realized by the following configuration.
- the transferred partial elements form a matrix island pattern on the second substrate.
- the elements to be transferred transferred onto the transfer destination substrate can be distributed and arranged in a matrix, a high-performance and low-cost semiconductor device can be manufactured.
- a pitch of the island pattern of the second substrate is an integral multiple of a pitch of the island pattern of the first substrate.
- the pitch of the island pattern of the second substrate of the transfer destination is an integer multiple of the island pattern of the first substrate, even if the pitch of the island pattern of the second substrate is changed by an integral multiple, (For example, even when the pitch is changed from 2 times to 4 times), the layout of the island pattern of the first substrate is kept as it is, and only the layout of the second substrate needs to be changed. It can be arranged in a distributed manner corresponding to the transfer position of the substrate.
- the laser irradiation may be performed at a predetermined position of the base substrate while scanning a laser light source along the substrate surface or scanning a stage on which the substrate is mounted along the substrate surface. It is preferable to carry out with respect to.
- the laser irradiation can be performed on the entire surface even at a predetermined position having a peeling area larger than the spot diameter of the laser. This can be done more reliably.
- a fragile layer is formed inside the base substrate and the fragile layer is irradiated with the laser.
- the fragile layer can be formed by ion implantation or ion doping of at least one of hydrogen atoms, hydrogen molecules, hydrogen ions, and rare gas ions into the base substrate.
- the fragile layer refers to a layer whose strength is weaker than other portions in the base substrate. According to the above method, since the modified region by laser irradiation is formed along the fragile layer inside the base substrate, the separation in the modified region becomes easier.
- a light absorption layer is formed inside the base substrate and the light absorption layer is irradiated with the laser.
- the light absorption layer may be formed by ion implantation of boron, phosphorus, arsenic, gallium, indium, titanium, palladium, carbon, silicon, antimony, zinc, tellurium, and cadmium into the base substrate. It can be formed by ion doping.
- the light absorption layer refers to a layer that has more levels for carrier transition and absorbs more light than other portions in the base substrate. According to the above method, when the laser irradiation is performed inside the base substrate, more light can be absorbed by the light absorption layer, and the multiphoton absorption phenomenon easily occurs. For this reason, the modification by laser irradiation becomes more intense and separation becomes easier.
- the semiconductor device manufacturing method it is preferable to perform laser irradiation in a state where the temperature of the base substrate is raised to room temperature or higher.
- the band gap is narrowed and more light can be absorbed. For this reason, a multiphoton absorption phenomenon easily occurs, and a modified region having a weaker structure can be formed.
- an Nd: YAG laser In the semiconductor device manufacturing method, it is preferable to use any one of an Nd: YAG laser, an Nd: YVO4 laser, an Nd: YLF laser, and a titanium sapphire laser.
- the laser mentioned above since the laser mentioned above has a long wavelength, the surface of the substrate is transmitted even to a substrate that is not transparent with UV light, and is condensed inside the substrate by a multiphoton absorption phenomenon. A modified region having a weak structure can be formed.
- a part of the element to be transferred is separated from the first substrate by applying a mechanical force from the side surface of the base substrate.
- the separation in the modified region inside the base substrate becomes easier by the external mechanical force.
- the element is a semiconductor thin film, a semiconductor device, or a part of a semiconductor device.
- the semiconductor device semi-finished product being formed can be selectively transferred to the transfer destination substrate, which is difficult on a large area substrate.
- the above element a part of a semiconductor device
- the above element can be transferred and then formed on a larger area substrate.
- fine processing is not required, after the semiconductor thin film is transferred as an element to a large area substrate, batch processing can be performed on the large area substrate.
- fine processing is necessary in all steps, a fine semiconductor device completed on a small area substrate as an element can be transferred onto a large area substrate.
- Examples of the semiconductor device include a light emitting element, a liquid crystal control element, a photoelectric exchange element, a piezoelectric element, a thin film transistor element, a thin film diode element, a resistance element, a switching element, a minute magnetic element, and a minute optical element.
- the element may be a single crystal Si thin film or a semiconductor device containing single crystal Si.
- a single crystal Si thin film or a semiconductor device containing single crystal Si can be selectively transferred to the second substrate.
- the semiconductor device containing the single crystal Si includes a transistor.
- the laser is irradiated under conditions where a peak power density is 1 ⁇ 10 8 W / cm 2 or more and a pulse width is 1 ⁇ s or less. More preferably, the laser is irradiated with a peak power density of 1 ⁇ 10 11 W / cm 2 to 1 ⁇ 10 12 W / cm 2 and a pulse width of 1 ns to 200 ns.
- a modified layer having a weak structure such as a modified layer including cracks or a modified layer including a melt processing region, inside the base substrate.
- the modified layer including the refractive index change region can be stably formed.
- any one of a silicon substrate, an SOI substrate, a sapphire substrate, a GaN substrate, and a GaAs substrate as the base substrate.
- various semiconductor devices such as transistors, power generation elements, and light emitting elements can be dispersed and disposed on the second substrate.
- the method for manufacturing a semiconductor device it is preferable to use any one of a glass substrate, a plastic substrate, and a film bonded to a supporting substrate as the substrate constituting the second substrate. According to the above method, elements can be dispersed and arranged on a soft substrate.
- the element is preferably a single crystal Si thin film, a semiconductor device containing single crystal Si, or a part of a semiconductor element.
- the present invention is applied to a manufacturing method of a semiconductor device in which minute semiconductor elements formed on a small substrate are dispersed and transferred to a large-area substrate.
Abstract
Description
以下の第1~第4の実施の形態では、半導体装置の製造工程において、Si基板(ベース基板)上の単結晶Si薄膜を、大面積のガラス基板(転写先基板)に分散配置して転写する方法について説明する。
以下図1~4を参照して、本発明の第1の実施の形態を説明する。図1は、本発明に係る半導体装置の製造方法の主なステップを示すフローチャートであり、図2は、ベース基板を形成する方法の主なステップを示す断面図であり、図3は、転写先基板を形成する方法の主なステップを示す断面図であり、図4は、転写したい薄膜をベース基板から転写先基板に転写する方法の主なステップを示す断面図である。
本実施の形態では、上記第1の実施の形態における説明のように、Si基板の単結晶Si薄膜(素子)をガラス基板に直接分散配置し転写する場合の例を説明する。第1の実施の形態に比べ、本実施の形態では、ガラス基板に形成される改質層での分離をより容易にするために、ベース基板の内部に予め基板内の他の部分よりも強度の弱い脆弱層を形成する工程を追加した場合の例を説明する。
本実施の形態では、Si基板に形成される改質層での分離をより容易にするために、脆弱層の代わりに、ベース基板の基板本体の内部に、予め基板内の他の部分よりも光をより多く吸収する光吸収層を形成しておく場合の例を説明する。光吸収層形成ステップ以外の工程は、上記第1,2の実施の形態の説明のとおりであるので、それについては簡単に説明する。なお、上記第2の実施の形態と同じ図面を参照して説明する。
本実施の形態では、Si基板とガラス基板とを分離する方法について説明する。
以下の実施の形態においては、素子の一例となる微小なトランジスタの転写ステップを説明する。また、上記第1~第4の実施の形態のように、ベース基板としてSi基板を用い、転写先基板としてガラス基板を用いた場合の例を説明する。
本実施の形態において、IC製造に用いられる一般的なプロセス用いてベース基板に半導体素子(微小なトランジスタ)を形成する。もちろん、本実施の形態は、一般的なICプロセスの一例を示すものに過ぎず、本発明はこれに限定されるものではない。
本実施の形態においては、Si基板上の微小なトランジスタをガラス基板に転写する時、レーザ照射によりSi基板の内部で形成された改質層での分離をより容易にするために、Si基板の内部に予め基板内の他の部分よりも強度の弱い脆弱層を形成する工程を追加した場合の例を説明する。
上記第6の実施の形態に対して、本実施の形態では、脆弱層104の代わりに、Si基板100の内部に予め光吸収層105を形成しておく場合の例を説明する。光吸収層105により、レーザを照射する際に、光吸収層105でこれら準位を介した多光子吸収が起こりやすくなって、結晶構造周期性がより乱れた非晶質シリコン(溶融処理領域)が形成され、剥れやすい改質層103を形成することができる。
本実施の形態では、Si基板100とガラス基板200とを分離する方法について説明する。ここで、Si基板100とガラス板200とを分離するステップ以外は、上記第5~7の実施の形態と同じである。つまり、上記第5~7の実施の形態による何れかの方法により、Si基板100およびガラス基板200を形成し、Si基板100とガラス基板200とに対する表面処理、貼り合わせ工程およびレーザ照射工程を経由して、剥れやすい改質層103を形成する。
100” アイランド(隆起部)
103 改質層
104 脆弱層
105 光吸収層
108 ゲート電極
113 ソース・ドレイン電極
200 ガラス基板(転写先基板、第2基板)
200” アイランド(隆起部)
301 ブレード
302 接着シート
Claims (21)
- ベース基板上に複数の素子が配列したアイランドパターンを形成して第1基板を形成する工程と、
上記第1基板と、上記第1基板とは異なる第2基板とを上記複数の素子の一部を介して貼り合わせる工程と、
上記第1基板上に形成された複数の素子のうちの上記一部の素子が形成されている位置に対して、多光子吸収を起こす波長を有するレーザを照射することで、上記一部の素子を上記第1基板から分離し、上記第2基板上に選択的に転写する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 転写された上記一部の素子が、上記第2基板にマトリクス状のアイランドパターンを形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 上記第2基板の上記アイランドパターンのピッチが、上記第1基板の上記アイランドパターンのピッチの整数倍であることを特徴とする請求項2に記載の半導体装置の製造方法。
- 上記レーザの照射は、レーザ光源を基板面に沿って走査しながら、あるいは基板が搭載されたステージを基板面に沿って走査しながら、上記ベース基板の所定の位置に対して行うことを特徴とする請求項1~3の何れか1項に記載の半導体装置の製造方法。
- 上記ベース基板の内部に脆弱層を形成し、当該脆弱層に対して上記レーザを照射することを特徴とする請求項1~4の何れか1項に記載の半導体装置の製造方法。
- 上記脆弱層は、水素原子、水素分子、水素イオン、および希ガスイオンのうち、少なくとも1つを、上記第1基板の内部にイオン注入またはイオンドーピングして形成されることを特徴とする請求項5に記載の半導体装置の製造方法。
- 上記ベース基板の内部に光吸収層を形成し、当該光吸収層に対して上記レーザを照射することを特徴とする請求項1~4の何れか1項に記載の半導体装置の製造方法。
- 上記光吸収層は、ボロン、リン、ヒ素、ガリウム、インジウム、チタン、パラジウム、炭素、シリコン、アンチモン、亜鉛、テルル、およびカドミウムのうち、何れか1つを、上記ベース基板の内部にイオン注入又はイオンドーピングして形成されることを特徴とする、請求項7に記載の半導体装置の製造方法。
- 上記ベース基板の温度を室温以上に上げた状態で、上記レーザを照射することを特徴とする、請求項1~8の何れか1項に記載の半導体装置の製造方法。
- 上記レーザは、Nd:YAGレーザ、Nd:YVO4レーザ、Nd:YLFレーザ、およびチタンサファイアレーザのうちの何れかであることを特徴とする請求項1~9の何れか1項に記載の半導体装置の製造方法。
- 上記ベース基板の側面から機械的力を加えて、転写したい上記一部の素子を、上記第1基板から分離することを特徴とする請求項1~10の何れか1項に記載の半導体装置の製造方法。
- 上記素子は、半導体薄膜、半導体デバイスまたは半導体デバイスの一部であることを特徴とする請求項1~11の何れか1項に記載の半導体装置の製造方法。
- 上記半導体デバイスは、発光素子、液晶制御素子、光電交換素子、圧電素子、薄膜トランジスタ素子、薄膜ダイオード素子、抵抗素子、スイッチング素子、微小磁気素子、微小光学素子であることを特徴とする請求項12に記載の半導体装置の製造方法。
- 上記素子は、単結晶Si薄膜または単結晶Siを含む半導体デバイスであることを特徴とする請求項12に記載の半導体装置の製造方法。
- 上記レーザを、ピークパワー密度が1×108W/cm2以上で、かつパルス幅が1μs以下の条件で照射することを特徴とする、請求項1~14の何れか1項に記載の半導体装置の製造方法。
- 上記レーザを、ピークパワー密度が1×1011W/cm2~1×1012W/cm2で、かつパルス幅が1ns~200nsの条件で照射することを特徴とする請求項15に記載の半導体装置の製造方法。
- 上記レーザを、ピークパワー密度が1×108W/cm2以上で、かつパルス幅が1ns以下の条件で照射することを特徴とする、請求項1~14の何れか1項に記載の半導体装置の製造方法。
- 上記ベース基板として、シリコン基板、SOI基板、サファイア基板、GaN基板、およびGaAs基板のうちの何れかを用いることを特徴とする請求項1~17の何れか1項に記載の半導体装置の製造方法。
- 上記第2基板を構成する基板として、ガラス基板、プラスチック基板、および支持基板に貼り合わせたフィルムのうちの何れかを用いることを特徴とする請求項1~18の何れか1項に記載の半導体装置の製造方法。
- 絶縁基板上に素子が転写されて形成された半導体装置であって、
上記絶縁基板は、所定の間隔で配列した隆起部を有しており、
上記素子は、その上面が上記隆起部に接し、かつその下面が上記隆起部から離れるように上記隆起部に直接形成されていることを特徴とする半導体装置。 - 上記素子は、単結晶Si薄膜、単結晶Siを含む半導体デバイスまたは半導体デバイスの一部であることを特徴とする請求項20に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201080055250.5A CN102754185B (zh) | 2009-12-11 | 2010-10-18 | 半导体装置的制造方法和半导体装置 |
JP2011545139A JP5547212B2 (ja) | 2009-12-11 | 2010-10-18 | 半導体装置の製造方法 |
US13/514,104 US8759951B2 (en) | 2009-12-11 | 2010-10-18 | Method for manufacturing semiconductor device, and semiconductor device |
EP10835777A EP2511942A1 (en) | 2009-12-11 | 2010-10-18 | Method for manufacturing semiconductor device, and semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009282189 | 2009-12-11 | ||
JP2009-282189 | 2009-12-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011070855A1 true WO2011070855A1 (ja) | 2011-06-16 |
Family
ID=44145408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/068291 WO2011070855A1 (ja) | 2009-12-11 | 2010-10-18 | 半導体装置の製造方法および半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8759951B2 (ja) |
EP (1) | EP2511942A1 (ja) |
JP (1) | JP5547212B2 (ja) |
CN (1) | CN102754185B (ja) |
WO (1) | WO2011070855A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015032690A (ja) * | 2013-08-02 | 2015-02-16 | 株式会社ディスコ | 積層ウェーハの加工方法 |
Families Citing this family (200)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8948562B2 (en) * | 2008-11-25 | 2015-02-03 | Regents Of The University Of Minnesota | Replication of patterned thin-film structures for use in plasmonics and metamaterials |
US8669778B1 (en) | 2009-04-14 | 2014-03-11 | Monolithic 3D Inc. | Method for design and manufacturing of a 3D semiconductor device |
US8058137B1 (en) | 2009-04-14 | 2011-11-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9509313B2 (en) | 2009-04-14 | 2016-11-29 | Monolithic 3D Inc. | 3D semiconductor device |
US8754533B2 (en) | 2009-04-14 | 2014-06-17 | Monolithic 3D Inc. | Monolithic three-dimensional semiconductor device and structure |
US9577642B2 (en) | 2009-04-14 | 2017-02-21 | Monolithic 3D Inc. | Method to form a 3D semiconductor device |
US8362482B2 (en) | 2009-04-14 | 2013-01-29 | Monolithic 3D Inc. | Semiconductor device and structure |
US8395191B2 (en) | 2009-10-12 | 2013-03-12 | Monolithic 3D Inc. | Semiconductor device and structure |
US11018133B2 (en) | 2009-10-12 | 2021-05-25 | Monolithic 3D Inc. | 3D integrated circuit |
US10366970B2 (en) | 2009-10-12 | 2019-07-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8148728B2 (en) | 2009-10-12 | 2012-04-03 | Monolithic 3D, Inc. | Method for fabrication of a semiconductor device and structure |
US10910364B2 (en) | 2009-10-12 | 2021-02-02 | Monolitaic 3D Inc. | 3D semiconductor device |
US8742476B1 (en) | 2012-11-27 | 2014-06-03 | Monolithic 3D Inc. | Semiconductor device and structure |
US9099424B1 (en) | 2012-08-10 | 2015-08-04 | Monolithic 3D Inc. | Semiconductor system, device and structure with heat removal |
US8536023B2 (en) * | 2010-11-22 | 2013-09-17 | Monolithic 3D Inc. | Method of manufacturing a semiconductor device and structure |
US10354995B2 (en) | 2009-10-12 | 2019-07-16 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11374118B2 (en) | 2009-10-12 | 2022-06-28 | Monolithic 3D Inc. | Method to form a 3D integrated circuit |
US10388863B2 (en) | 2009-10-12 | 2019-08-20 | Monolithic 3D Inc. | 3D memory device and structure |
US10043781B2 (en) | 2009-10-12 | 2018-08-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10157909B2 (en) | 2009-10-12 | 2018-12-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8461035B1 (en) | 2010-09-30 | 2013-06-11 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8492886B2 (en) | 2010-02-16 | 2013-07-23 | Monolithic 3D Inc | 3D integrated circuit with logic |
US9099526B2 (en) | 2010-02-16 | 2015-08-04 | Monolithic 3D Inc. | Integrated circuit device and structure |
US8026521B1 (en) | 2010-10-11 | 2011-09-27 | Monolithic 3D Inc. | Semiconductor device and structure |
US9953925B2 (en) | 2011-06-28 | 2018-04-24 | Monolithic 3D Inc. | Semiconductor system and device |
US8901613B2 (en) | 2011-03-06 | 2014-12-02 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US8642416B2 (en) | 2010-07-30 | 2014-02-04 | Monolithic 3D Inc. | Method of forming three dimensional integrated circuit devices using layer transfer technique |
US10217667B2 (en) | 2011-06-28 | 2019-02-26 | Monolithic 3D Inc. | 3D semiconductor device, fabrication method and system |
US9219005B2 (en) | 2011-06-28 | 2015-12-22 | Monolithic 3D Inc. | Semiconductor system and device |
US11482440B2 (en) | 2010-12-16 | 2022-10-25 | Monolithic 3D Inc. | 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits |
US8273610B2 (en) | 2010-11-18 | 2012-09-25 | Monolithic 3D Inc. | Method of constructing a semiconductor device and structure |
US8163581B1 (en) | 2010-10-13 | 2012-04-24 | Monolith IC 3D | Semiconductor and optoelectronic devices |
US10497713B2 (en) | 2010-11-18 | 2019-12-03 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11227897B2 (en) | 2010-10-11 | 2022-01-18 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US10896931B1 (en) | 2010-10-11 | 2021-01-19 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11257867B1 (en) | 2010-10-11 | 2022-02-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with oxide bonds |
US11024673B1 (en) | 2010-10-11 | 2021-06-01 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11469271B2 (en) | 2010-10-11 | 2022-10-11 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11158674B2 (en) | 2010-10-11 | 2021-10-26 | Monolithic 3D Inc. | Method to produce a 3D semiconductor device and structure |
US11315980B1 (en) | 2010-10-11 | 2022-04-26 | Monolithic 3D Inc. | 3D semiconductor device and structure with transistors |
US10290682B2 (en) | 2010-10-11 | 2019-05-14 | Monolithic 3D Inc. | 3D IC semiconductor device and structure with stacked memory |
US11018191B1 (en) | 2010-10-11 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11600667B1 (en) | 2010-10-11 | 2023-03-07 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US10679977B2 (en) | 2010-10-13 | 2020-06-09 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11404466B2 (en) | 2010-10-13 | 2022-08-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US10978501B1 (en) | 2010-10-13 | 2021-04-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US10943934B2 (en) | 2010-10-13 | 2021-03-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11437368B2 (en) | 2010-10-13 | 2022-09-06 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11327227B2 (en) | 2010-10-13 | 2022-05-10 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US11869915B2 (en) | 2010-10-13 | 2024-01-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11063071B1 (en) | 2010-10-13 | 2021-07-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US11163112B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US11164898B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11855100B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11694922B2 (en) | 2010-10-13 | 2023-07-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11855114B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US9197804B1 (en) | 2011-10-14 | 2015-11-24 | Monolithic 3D Inc. | Semiconductor and optoelectronic devices |
US11133344B2 (en) | 2010-10-13 | 2021-09-28 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US10833108B2 (en) | 2010-10-13 | 2020-11-10 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11929372B2 (en) | 2010-10-13 | 2024-03-12 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11043523B1 (en) | 2010-10-13 | 2021-06-22 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11605663B2 (en) | 2010-10-13 | 2023-03-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US10998374B1 (en) | 2010-10-13 | 2021-05-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11443971B2 (en) | 2010-11-18 | 2022-09-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11482439B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors |
US11355380B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | Methods for producing 3D semiconductor memory device and structure utilizing alignment marks |
US11610802B2 (en) | 2010-11-18 | 2023-03-21 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes |
US11031275B2 (en) | 2010-11-18 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11854857B1 (en) | 2010-11-18 | 2023-12-26 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11569117B2 (en) | 2010-11-18 | 2023-01-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11521888B2 (en) | 2010-11-18 | 2022-12-06 | Monolithic 3D Inc. | 3D semiconductor device and structure with high-k metal gate transistors |
US11923230B1 (en) | 2010-11-18 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11508605B2 (en) | 2010-11-18 | 2022-11-22 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11862503B2 (en) | 2010-11-18 | 2024-01-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11735462B2 (en) | 2010-11-18 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11164770B1 (en) | 2010-11-18 | 2021-11-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11901210B2 (en) | 2010-11-18 | 2024-02-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11804396B2 (en) | 2010-11-18 | 2023-10-31 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11211279B2 (en) | 2010-11-18 | 2021-12-28 | Monolithic 3D Inc. | Method for processing a 3D integrated circuit and structure |
US11355381B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11018042B1 (en) | 2010-11-18 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11094576B1 (en) | 2010-11-18 | 2021-08-17 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11121021B2 (en) | 2010-11-18 | 2021-09-14 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11615977B2 (en) | 2010-11-18 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11107721B2 (en) | 2010-11-18 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with NAND logic |
US11004719B1 (en) | 2010-11-18 | 2021-05-11 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11784082B2 (en) | 2010-11-18 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11482438B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11495484B2 (en) | 2010-11-18 | 2022-11-08 | Monolithic 3D Inc. | 3D semiconductor devices and structures with at least two single-crystal layers |
US8975670B2 (en) | 2011-03-06 | 2015-03-10 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US10388568B2 (en) | 2011-06-28 | 2019-08-20 | Monolithic 3D Inc. | 3D semiconductor device and system |
US8687399B2 (en) | 2011-10-02 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
CN103890908B (zh) * | 2011-10-18 | 2016-08-24 | 富士电机株式会社 | 固相键合晶片的支承基板的剥离方法及半导体装置的制造方法 |
US9029173B2 (en) | 2011-10-18 | 2015-05-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9218968B2 (en) * | 2011-11-29 | 2015-12-22 | Joled Inc | Method for forming crystalline thin-film and method for manufacturing thin film transistor |
US9000557B2 (en) | 2012-03-17 | 2015-04-07 | Zvi Or-Bach | Semiconductor device and structure |
US9847445B2 (en) * | 2012-04-05 | 2017-12-19 | Koninklijke Philips N.V. | LED thin-film device partial singulation prior to substrate thinning or removal |
US11735501B1 (en) | 2012-04-09 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11476181B1 (en) | 2012-04-09 | 2022-10-18 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11694944B1 (en) | 2012-04-09 | 2023-07-04 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US8557632B1 (en) | 2012-04-09 | 2013-10-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US11164811B2 (en) | 2012-04-09 | 2021-11-02 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers and oxide-to-oxide bonding |
US11616004B1 (en) | 2012-04-09 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11410912B2 (en) | 2012-04-09 | 2022-08-09 | Monolithic 3D Inc. | 3D semiconductor device with vias and isolation layers |
US11881443B2 (en) | 2012-04-09 | 2024-01-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11088050B2 (en) | 2012-04-09 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers |
US10600888B2 (en) | 2012-04-09 | 2020-03-24 | Monolithic 3D Inc. | 3D semiconductor device |
US11594473B2 (en) | 2012-04-09 | 2023-02-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US8686428B1 (en) | 2012-11-16 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US8574929B1 (en) | 2012-11-16 | 2013-11-05 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US8674470B1 (en) | 2012-12-22 | 2014-03-18 | Monolithic 3D Inc. | Semiconductor device and structure |
US11916045B2 (en) | 2012-12-22 | 2024-02-27 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11784169B2 (en) | 2012-12-22 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11217565B2 (en) | 2012-12-22 | 2022-01-04 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11018116B2 (en) | 2012-12-22 | 2021-05-25 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11063024B1 (en) | 2012-12-22 | 2021-07-13 | Monlithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11309292B2 (en) | 2012-12-22 | 2022-04-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US10903089B1 (en) | 2012-12-29 | 2021-01-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10600657B2 (en) | 2012-12-29 | 2020-03-24 | Monolithic 3D Inc | 3D semiconductor device and structure |
US11430668B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11087995B1 (en) | 2012-12-29 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9385058B1 (en) | 2012-12-29 | 2016-07-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US11004694B1 (en) | 2012-12-29 | 2021-05-11 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10651054B2 (en) | 2012-12-29 | 2020-05-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10115663B2 (en) | 2012-12-29 | 2018-10-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9871034B1 (en) | 2012-12-29 | 2018-01-16 | Monolithic 3D Inc. | Semiconductor device and structure |
US11177140B2 (en) | 2012-12-29 | 2021-11-16 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10892169B2 (en) | 2012-12-29 | 2021-01-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11430667B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11869965B2 (en) | 2013-03-11 | 2024-01-09 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US11935949B1 (en) | 2013-03-11 | 2024-03-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US10325651B2 (en) | 2013-03-11 | 2019-06-18 | Monolithic 3D Inc. | 3D semiconductor device with stacked memory |
US8902663B1 (en) | 2013-03-11 | 2014-12-02 | Monolithic 3D Inc. | Method of maintaining a memory state |
US8994404B1 (en) | 2013-03-12 | 2015-03-31 | Monolithic 3D Inc. | Semiconductor device and structure |
US11398569B2 (en) | 2013-03-12 | 2022-07-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11088130B2 (en) | 2014-01-28 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10840239B2 (en) | 2014-08-26 | 2020-11-17 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11923374B2 (en) | 2013-03-12 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US9117749B1 (en) | 2013-03-15 | 2015-08-25 | Monolithic 3D Inc. | Semiconductor device and structure |
US10224279B2 (en) | 2013-03-15 | 2019-03-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US11574109B1 (en) | 2013-04-15 | 2023-02-07 | Monolithic 3D Inc | Automation methods for 3D integrated circuits and devices |
US11487928B2 (en) | 2013-04-15 | 2022-11-01 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11341309B1 (en) | 2013-04-15 | 2022-05-24 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11030371B2 (en) | 2013-04-15 | 2021-06-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US9021414B1 (en) | 2013-04-15 | 2015-04-28 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11720736B2 (en) | 2013-04-15 | 2023-08-08 | Monolithic 3D Inc. | Automation methods for 3D integrated circuits and devices |
US11270055B1 (en) | 2013-04-15 | 2022-03-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11107808B1 (en) | 2014-01-28 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10297586B2 (en) | 2015-03-09 | 2019-05-21 | Monolithic 3D Inc. | Methods for processing a 3D semiconductor device |
US11031394B1 (en) | 2014-01-28 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11011507B1 (en) | 2015-04-19 | 2021-05-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10825779B2 (en) | 2015-04-19 | 2020-11-03 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10381328B2 (en) | 2015-04-19 | 2019-08-13 | Monolithic 3D Inc. | Semiconductor device and structure |
US11056468B1 (en) | 2015-04-19 | 2021-07-06 | Monolithic 3D Inc. | 3D semiconductor device and structure |
WO2017008253A1 (en) * | 2015-07-14 | 2017-01-19 | Goertek. Inc | Transferring method, manufacturing method, device and electronic apparatus of micro-led |
US11956952B2 (en) | 2015-08-23 | 2024-04-09 | Monolithic 3D Inc. | Semiconductor memory device and structure |
CN115942752A (zh) | 2015-09-21 | 2023-04-07 | 莫诺利特斯3D有限公司 | 3d半导体器件和结构 |
US10522225B1 (en) | 2015-10-02 | 2019-12-31 | Monolithic 3D Inc. | Semiconductor device with non-volatile memory |
US10847540B2 (en) | 2015-10-24 | 2020-11-24 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11114464B2 (en) | 2015-10-24 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11296115B1 (en) | 2015-10-24 | 2022-04-05 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10418369B2 (en) | 2015-10-24 | 2019-09-17 | Monolithic 3D Inc. | Multi-level semiconductor memory device and structure |
US11937422B2 (en) | 2015-11-07 | 2024-03-19 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11114427B2 (en) | 2015-11-07 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor processor and memory device and structure |
DE102016100565B4 (de) * | 2016-01-14 | 2022-08-11 | Infineon Technologies Ag | Verfahren zum herstellen einer halbleitervorrichtung |
GB2546966B (en) * | 2016-01-21 | 2021-08-04 | Univ Southampton | Trimming optical device structures |
US10410883B2 (en) * | 2016-06-01 | 2019-09-10 | Corning Incorporated | Articles and methods of forming vias in substrates |
US10794679B2 (en) | 2016-06-29 | 2020-10-06 | Corning Incorporated | Method and system for measuring geometric parameters of through holes |
US10134657B2 (en) | 2016-06-29 | 2018-11-20 | Corning Incorporated | Inorganic wafer having through-holes attached to semiconductor wafer |
CN109690757B (zh) * | 2016-10-04 | 2023-02-28 | 维耶尔公司 | 施体衬底中的微装置布置 |
US11869591B2 (en) | 2016-10-10 | 2024-01-09 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11812620B2 (en) | 2016-10-10 | 2023-11-07 | Monolithic 3D Inc. | 3D DRAM memory devices and structures with control circuits |
US11930648B1 (en) | 2016-10-10 | 2024-03-12 | Monolithic 3D Inc. | 3D memory devices and structures with metal layers |
US11251149B2 (en) | 2016-10-10 | 2022-02-15 | Monolithic 3D Inc. | 3D memory device and structure |
US11711928B2 (en) | 2016-10-10 | 2023-07-25 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11329059B1 (en) | 2016-10-10 | 2022-05-10 | Monolithic 3D Inc. | 3D memory devices and structures with thinned single crystal substrates |
US20180138357A1 (en) * | 2016-11-11 | 2018-05-17 | QMAT, Inc. | Micro-light emitting diode (led) fabrication by layer transfer |
US11078112B2 (en) | 2017-05-25 | 2021-08-03 | Corning Incorporated | Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same |
US10580725B2 (en) | 2017-05-25 | 2020-03-03 | Corning Incorporated | Articles having vias with geometry attributes and methods for fabricating the same |
JP6990577B2 (ja) * | 2017-12-22 | 2022-01-12 | 東レエンジニアリング株式会社 | 実装方法および実装装置 |
KR102113200B1 (ko) * | 2017-12-22 | 2020-06-03 | 엘씨스퀘어(주) | 변형필름을 이용한 전사방법 |
US11554984B2 (en) | 2018-02-22 | 2023-01-17 | Corning Incorporated | Alkali-free borosilicate glasses with low post-HF etch roughness |
JP6431631B1 (ja) * | 2018-02-28 | 2018-11-28 | 株式会社フィルネックス | 半導体素子の製造方法 |
US11152294B2 (en) | 2018-04-09 | 2021-10-19 | Corning Incorporated | Hermetic metallized via with improved reliability |
WO2019217976A2 (en) * | 2018-04-26 | 2019-11-14 | QMAT, Inc. | Patterning on layer transferred templates |
WO2019239829A1 (ja) * | 2018-06-13 | 2019-12-19 | 国立大学法人東北大学 | Memsデバイスの製造方法およびmemsデバイス |
US10796938B2 (en) | 2018-10-17 | 2020-10-06 | X Display Company Technology Limited | Micro-transfer printing with selective component removal |
US10573544B1 (en) * | 2018-10-17 | 2020-02-25 | X-Celeprint Limited | Micro-transfer printing with selective component removal |
US11414782B2 (en) | 2019-01-13 | 2022-08-16 | Bing Hu | Method of separating a film from a main body of a crystalline object |
WO2020171940A1 (en) | 2019-02-21 | 2020-08-27 | Corning Incorporated | Glass or glass ceramic articles with copper-metallized through holes and processes for making the same |
CN109904065B (zh) * | 2019-02-21 | 2021-05-11 | 中国科学院上海微系统与信息技术研究所 | 异质结构的制备方法 |
KR20200104981A (ko) * | 2019-02-27 | 2020-09-07 | 삼성디스플레이 주식회사 | 표시 장치 및 그 리페어 방법 |
US11296106B2 (en) | 2019-04-08 | 2022-04-05 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11018156B2 (en) | 2019-04-08 | 2021-05-25 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11763864B2 (en) | 2019-04-08 | 2023-09-19 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures with bit-line pillars |
US11158652B1 (en) | 2019-04-08 | 2021-10-26 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US10892016B1 (en) | 2019-04-08 | 2021-01-12 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11328942B1 (en) * | 2019-09-10 | 2022-05-10 | Facebook Technologies, Llc | Liquid crystalline elastomer for pick and place of semiconductor devices |
CN112967982B (zh) * | 2020-09-10 | 2022-04-19 | 重庆康佳光电技术研究院有限公司 | 转移基板及制作方法、芯片转移方法及显示面板 |
JP2022136755A (ja) | 2021-03-08 | 2022-09-21 | キオクシア株式会社 | 半導体製造装置および半導体装置の製造方法 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0348201B2 (ja) | 1981-03-11 | 1991-07-23 | Daiichi Togyo Kk | |
JPH11142878A (ja) * | 1997-11-12 | 1999-05-28 | Sharp Corp | 表示用トランジスタアレイパネルの形成方法 |
JP3408805B2 (ja) | 2000-09-13 | 2003-05-19 | 浜松ホトニクス株式会社 | 切断起点領域形成方法及び加工対象物切断方法 |
JP3447619B2 (ja) | 1999-06-25 | 2003-09-16 | 株式会社東芝 | アクティブマトリクス基板の製造方法、中間転写基板 |
JP3474187B1 (ja) | 2002-11-19 | 2003-12-08 | 英樹 松村 | 画素制御素子の選択転写方法、及び、画素制御素子の選択転写方法に使用される画素制御素子の実装装置 |
JP2006032435A (ja) | 2004-07-12 | 2006-02-02 | Sharp Corp | 半導体装置の製造方法及び半導体装置の製造装置 |
JP2006041430A (ja) * | 2004-07-30 | 2006-02-09 | Denso Corp | 半導体基板の製造方法 |
JP2006053171A (ja) | 2004-08-09 | 2006-02-23 | Sharp Corp | 半導体装置の製造方法、半導体装置及び半導体回路基板 |
JP3994681B2 (ja) | 2001-04-11 | 2007-10-24 | ソニー株式会社 | 素子の配列方法及び画像表示装置の製造方法 |
JP2009064831A (ja) * | 2007-09-04 | 2009-03-26 | Sharp Corp | 半導体装置、表示装置及びそれらの製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JP4659300B2 (ja) | 2000-09-13 | 2011-03-30 | 浜松ホトニクス株式会社 | レーザ加工方法及び半導体チップの製造方法 |
US6872635B2 (en) | 2001-04-11 | 2005-03-29 | Sony Corporation | Device transferring method, and device arraying method and image display unit fabricating method using the same |
JP4524561B2 (ja) * | 2001-07-24 | 2010-08-18 | セイコーエプソン株式会社 | 転写方法 |
JP2003077940A (ja) * | 2001-09-06 | 2003-03-14 | Sony Corp | 素子の転写方法及びこれを用いた素子の配列方法、画像表示装置の製造方法 |
US7585703B2 (en) | 2002-11-19 | 2009-09-08 | Ishikawa Seisakusho, Ltd. | Pixel control element selection transfer method, pixel control device mounting device used for pixel control element selection transfer method, wiring formation method after pixel control element transfer, and planar display substrate |
TWI520269B (zh) * | 2002-12-03 | 2016-02-01 | Hamamatsu Photonics Kk | Cutting method of semiconductor substrate |
JP2004319538A (ja) * | 2003-04-10 | 2004-11-11 | Seiko Epson Corp | 半導体装置の製造方法、集積回路、電子光学装置及び電子機器 |
US7052978B2 (en) * | 2003-08-28 | 2006-05-30 | Intel Corporation | Arrangements incorporating laser-induced cleaving |
US7202141B2 (en) * | 2004-03-29 | 2007-04-10 | J.P. Sercel Associates, Inc. | Method of separating layers of material |
US7875530B2 (en) * | 2005-12-02 | 2011-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
-
2010
- 2010-10-18 WO PCT/JP2010/068291 patent/WO2011070855A1/ja active Application Filing
- 2010-10-18 JP JP2011545139A patent/JP5547212B2/ja not_active Expired - Fee Related
- 2010-10-18 CN CN201080055250.5A patent/CN102754185B/zh not_active Expired - Fee Related
- 2010-10-18 US US13/514,104 patent/US8759951B2/en not_active Expired - Fee Related
- 2010-10-18 EP EP10835777A patent/EP2511942A1/en not_active Withdrawn
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0348201B2 (ja) | 1981-03-11 | 1991-07-23 | Daiichi Togyo Kk | |
JPH11142878A (ja) * | 1997-11-12 | 1999-05-28 | Sharp Corp | 表示用トランジスタアレイパネルの形成方法 |
JP3406207B2 (ja) | 1997-11-12 | 2003-05-12 | シャープ株式会社 | 表示用トランジスタアレイパネルの形成方法 |
JP3447619B2 (ja) | 1999-06-25 | 2003-09-16 | 株式会社東芝 | アクティブマトリクス基板の製造方法、中間転写基板 |
JP3408805B2 (ja) | 2000-09-13 | 2003-05-19 | 浜松ホトニクス株式会社 | 切断起点領域形成方法及び加工対象物切断方法 |
JP3994681B2 (ja) | 2001-04-11 | 2007-10-24 | ソニー株式会社 | 素子の配列方法及び画像表示装置の製造方法 |
JP3474187B1 (ja) | 2002-11-19 | 2003-12-08 | 英樹 松村 | 画素制御素子の選択転写方法、及び、画素制御素子の選択転写方法に使用される画素制御素子の実装装置 |
JP2006032435A (ja) | 2004-07-12 | 2006-02-02 | Sharp Corp | 半導体装置の製造方法及び半導体装置の製造装置 |
JP2006041430A (ja) * | 2004-07-30 | 2006-02-09 | Denso Corp | 半導体基板の製造方法 |
JP2006053171A (ja) | 2004-08-09 | 2006-02-23 | Sharp Corp | 半導体装置の製造方法、半導体装置及び半導体回路基板 |
JP2009064831A (ja) * | 2007-09-04 | 2009-03-26 | Sharp Corp | 半導体装置、表示装置及びそれらの製造方法 |
Non-Patent Citations (2)
Title |
---|
"Stealth Dicing Technical Information for Mems", TLAS9005J02, May 2009 (2009-05-01) |
"The Stealth Dicing Technologies and Their Applications", TLAS9004J01, March 2005 (2005-03-01) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015032690A (ja) * | 2013-08-02 | 2015-02-16 | 株式会社ディスコ | 積層ウェーハの加工方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102754185A (zh) | 2012-10-24 |
EP2511942A1 (en) | 2012-10-17 |
US20120241919A1 (en) | 2012-09-27 |
JPWO2011070855A1 (ja) | 2013-04-22 |
CN102754185B (zh) | 2015-06-03 |
US8759951B2 (en) | 2014-06-24 |
JP5547212B2 (ja) | 2014-07-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5547212B2 (ja) | 半導体装置の製造方法 | |
KR100532557B1 (ko) | 반도체 장치 및 그의 제조 방법, soi기판 및 그것을사용하는 표시 장치 및 soi기판의 제조 방법 | |
US8685837B2 (en) | Transfer method, method for manufacturing semiconductor device, and semiconductor device | |
JP4451488B2 (ja) | 半導体素子の転写方法及び半導体装置の製造方法 | |
US6759277B1 (en) | Crystalline silicon die array and method for assembling crystalline silicon sheets onto substrates | |
JP4027740B2 (ja) | 半導体装置の作製方法 | |
JP5072946B2 (ja) | 液晶表示装置の作製方法 | |
TW200416965A (en) | Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device | |
JP4527068B2 (ja) | 剥離方法、半導体装置の作製方法、及び電子書籍の作製方法 | |
JP5866086B2 (ja) | 半導体装置の作製方法 | |
CN107170759A (zh) | 一种阵列基板及其制作方法、显示装置 | |
US8946820B2 (en) | Method for manufacturing semiconductor substrate, substrate for forming semiconductor substrate, stacked substrate, semiconductor substrate, and electronic device | |
WO2010109712A1 (ja) | 半導体装置用の絶縁基板、及び、半導体装置 | |
KR100879047B1 (ko) | 반도체 장치 및 그 제조방법 | |
WO2009084312A1 (ja) | 半導体装置、単結晶半導体薄膜付き基板及びそれらの製造方法 | |
JP2010141246A (ja) | 半導体装置の製造方法 | |
JP5172250B2 (ja) | 半導体装置、表示装置及びそれらの製造方法 | |
JP2004119636A (ja) | 半導体装置およびその製造方法 | |
JP4545449B2 (ja) | 半導体装置の製造方法 | |
WO2009084284A1 (ja) | 半導体装置用の絶縁基板、半導体装置、及び、半導体装置の製造方法 | |
US9041147B2 (en) | Semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescent apparatus, semiconductor substrate manufacturing method, and semiconductor substrate manufacturing apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201080055250.5 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10835777 Country of ref document: EP Kind code of ref document: A1 |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10835777 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011545139 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13514104 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2010835777 Country of ref document: EP |