JP5547212B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5547212B2 JP5547212B2 JP2011545139A JP2011545139A JP5547212B2 JP 5547212 B2 JP5547212 B2 JP 5547212B2 JP 2011545139 A JP2011545139 A JP 2011545139A JP 2011545139 A JP2011545139 A JP 2011545139A JP 5547212 B2 JP5547212 B2 JP 5547212B2
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description
以下の第1〜第4の実施の形態では、半導体装置の製造工程において、Si基板(ベース基板)上の単結晶Si薄膜を、大面積のガラス基板(転写先基板)に分散配置して転写する方法について説明する。
以下図1〜4を参照して、本発明の第1の実施の形態を説明する。図1は、本発明に係る半導体装置の製造方法の主なステップを示すフローチャートであり、図2は、ベース基板を形成する方法の主なステップを示す断面図であり、図3は、転写先基板を形成する方法の主なステップを示す断面図であり、図4は、転写したい薄膜をベース基板から転写先基板に転写する方法の主なステップを示す断面図である。
本実施の形態では、上記第1の実施の形態における説明のように、Si基板の単結晶Si薄膜(素子)をガラス基板に直接分散配置し転写する場合の例を説明する。第1の実施の形態に比べ、本実施の形態では、ガラス基板に形成される改質層での分離をより容易にするために、ベース基板の内部に予め基板内の他の部分よりも強度の弱い脆弱層を形成する工程を追加した場合の例を説明する。
本実施の形態では、Si基板に形成される改質層での分離をより容易にするために、脆弱層の代わりに、ベース基板の基板本体の内部に、予め基板内の他の部分よりも光をより多く吸収する光吸収層を形成しておく場合の例を説明する。光吸収層形成ステップ以外の工程は、上記第1,2の実施の形態の説明のとおりであるので、それについては簡単に説明する。なお、上記第2の実施の形態と同じ図面を参照して説明する。
本実施の形態では、Si基板とガラス基板とを分離する方法について説明する。
以下の実施の形態においては、素子の一例となる微小なトランジスタの転写ステップを説明する。また、上記第1〜第4の実施の形態のように、ベース基板としてSi基板を用い、転写先基板としてガラス基板を用いた場合の例を説明する。
本実施の形態において、IC製造に用いられる一般的なプロセス用いてベース基板に半導体素子(微小なトランジスタ)を形成する。もちろん、本実施の形態は、一般的なICプロセスの一例を示すものに過ぎず、本発明はこれに限定されるものではない。
本実施の形態においては、Si基板上の微小なトランジスタをガラス基板に転写する時、レーザ照射によりSi基板の内部で形成された改質層での分離をより容易にするために、Si基板の内部に予め基板内の他の部分よりも強度の弱い脆弱層を形成する工程を追加した場合の例を説明する。
上記第6の実施の形態に対して、本実施の形態では、脆弱層104の代わりに、Si基板100の内部に予め光吸収層105を形成しておく場合の例を説明する。光吸収層105により、レーザを照射する際に、光吸収層105でこれら準位を介した多光子吸収が起こりやすくなって、結晶構造周期性がより乱れた非晶質シリコン(溶融処理領域)が形成され、剥れやすい改質層103を形成することができる。
本実施の形態では、Si基板100とガラス基板200とを分離する方法について説明する。ここで、Si基板100とガラス板200とを分離するステップ以外は、上記第5〜7の実施の形態と同じである。つまり、上記第5〜7の実施の形態による何れかの方法により、Si基板100およびガラス基板200を形成し、Si基板100とガラス基板200とに対する表面処理、貼り合わせ工程およびレーザ照射工程を経由して、剥れやすい改質層103を形成する。
100” アイランド(隆起部)
103 改質層
104 脆弱層
105 光吸収層
108 ゲート電極
113 ソース・ドレイン電極
200 ガラス基板(転写先基板、第2基板)
200” アイランド(隆起部)
301 ブレード
302 接着シート
Claims (18)
- ベース基板をエッチングすることにより上部に複数の素子が配列したアイランドパターンが形成された第1基板を形成する工程と、
上記第1基板と、上記第1基板とは異なる第2基板とを上記複数の素子の一部を介して貼り合わせる工程と、
上記第1基板上に形成された複数の素子のうちの上記一部の素子が形成されている位置に対して、多光子吸収を起こす波長を有するレーザを照射することで、上記一部の素子を上記第1基板から分離し、上記第2基板上に選択的に転写する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 転写された上記一部の素子が、上記第2基板にマトリクス状のアイランドパターンを形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 上記第2基板の上記アイランドパターンのピッチが、上記第1基板の上記アイランドパターンのピッチの整数倍であることを特徴とする請求項2に記載の半導体装置の製造方法。
- 上記レーザの照射は、レーザ光源を基板面に沿って走査しながら、あるいは基板が搭載されたステージを基板面に沿って走査しながら、上記一部の素子が形成されている位置に対して行うことを特徴とする請求項1〜3の何れか1項に記載の半導体装置の製造方法。
- ベース基板の内部に脆弱層、又は、光吸収層を形成する工程と、
上記脆弱層、又は上記光吸収層を形成した後、上記ベース基板をエッチングすることにより上部に複数の素子が配列したアイランドパターンが形成された第1基板を形成する工程と、
上記第1基板と、上記第1基板とは異なる第2基板とを上記複数の素子の一部を介して貼り合わせる工程と、
第1基板上に形成された複数の素子のうちの上記一部の素子が形成されている位置に対応する、上記脆弱層、又は、光吸収層に対して、多光子吸収を起こす波長を有するレーザを照射することで、上記一部の素子を上記第1基板から分離し、上記第2基板上に選択的に転写する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 上記脆弱層は、水素原子、水素分子、水素イオン、および希ガスイオンのうち、少なくとも1つを、上記ベース基板の内部にイオン注入またはイオンドーピングして形成されることを特徴とする請求項5に記載の半導体装置の製造方法。
- 上記光吸収層は、ボロン、リン、ヒ素、ガリウム、インジウム、チタン、パラジウム、炭素、シリコン、アンチモン、亜鉛、テルル、およびカドミウムのうち、何れか1つを、上記ベース基板の内部にイオン注入又はイオンドーピングして形成されることを特徴とする、請求項5に記載の半導体装置の製造方法。
- 上記第1基板の温度を室温以上に上げた状態で、上記レーザを照射することを特徴とする、請求項1〜7の何れか1項に記載の半導体装置の製造方法。
- 上記レーザは、Nd:YAGレーザ、Nd:YVO4レーザ、Nd:YLFレーザ、およびチタンサファイアレーザのうちの何れかであることを特徴とする請求項1〜8の何れか1項に記載の半導体装置の製造方法。
- 上記第1基板の側面から機械的力を加えて、転写したい上記一部の素子を、上記第1基板から分離することを特徴とする請求項1〜9の何れか1項に記載の半導体装置の製造方法。
- 上記素子は、半導体薄膜、半導体デバイスまたは半導体デバイスの一部であることを特徴とする請求項1〜10の何れか1項に記載の半導体装置の製造方法。
- 上記半導体デバイスは、発光素子、液晶制御素子、光電交換素子、圧電素子、薄膜トランジスタ素子、薄膜ダイオード素子、抵抗素子、スイッチング素子、微小磁気素子、微小光学素子であることを特徴とする請求項11に記載の半導体装置の製造方法。
- 上記素子は、単結晶Si薄膜または単結晶Siを含む半導体デバイスであることを特徴とする請求項11に記載の半導体装置の製造方法。
- 上記レーザを、ピークパワー密度が1×108W/cm2以上で、かつパルス幅が1μs以下の条件で照射することを特徴とする、請求項1〜13の何れか1項に記載の半導体装置の製造方法。
- 上記レーザを、ピークパワー密度が1×1011W/cm2〜1×1012W/cm2で、かつパルス幅が1ns〜200nsの条件で照射することを特徴とする請求項14に記載の半導体装置の製造方法。
- 上記レーザを、ピークパワー密度が1×108W/cm2以上で、かつパルス幅が1ns以下の条件で照射することを特徴とする、請求項1〜13の何れか1項に記載の半導体装置の製造方法。
- 上記ベース基板として、シリコン基板、SOI基板、サファイア基板、GaN基板、およびGaAs基板のうちの何れかを用いることを特徴とする請求項1〜16の何れか1項に記載の半導体装置の製造方法。
- 上記第2基板を構成する基板として、ガラス基板、プラスチック基板、および支持基板に貼り合わせたフィルムのうちの何れかを用いることを特徴とする請求項1〜17の何れか1項に記載の半導体装置の製造方法。
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US8759951B2 (en) | 2014-06-24 |
WO2011070855A1 (ja) | 2011-06-16 |
CN102754185B (zh) | 2015-06-03 |
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JPWO2011070855A1 (ja) | 2013-04-22 |
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