WO2010116737A1 - A/d変換装置 - Google Patents
A/d変換装置 Download PDFInfo
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- WO2010116737A1 WO2010116737A1 PCT/JP2010/002557 JP2010002557W WO2010116737A1 WO 2010116737 A1 WO2010116737 A1 WO 2010116737A1 JP 2010002557 W JP2010002557 W JP 2010002557W WO 2010116737 A1 WO2010116737 A1 WO 2010116737A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/502—Analogue/digital converters with intermediate conversion to time interval using tapped delay lines
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/60—Analogue/digital converters with intermediate conversion to frequency of pulses
Definitions
- the present invention relates to an A / D converter that converts an analog input voltage into a digital value using a pulse delay circuit that delays a pulse signal by a delay time corresponding to the magnitude of the analog input voltage.
- the pulse delay circuit 11 has a configuration in which a plurality of delay units (NAND1, BUF1,..., BUF15) each consisting of various gate circuits are connected in a ring shape. ing. An analog input voltage Vin to be A / D converted is supplied as a power supply voltage for each delay unit.
- NAND1, BUF1,..., BUF15 delay units
- the SP When a sampling pulse (SP) is input to the pulse delay circuit 11, the SP sequentially passes through each delay unit with a delay time corresponding to the power supply voltage, and circulates in the pulse delay circuit 11.
- the number of stages of delay units through which the SP passes is determined by the delay time of each delay unit, that is, the analog input voltage Vin supplied as the power supply voltage.
- the pulse passage stage number detection circuit 21 detects the number of passage stages (and the number of turns).
- the output circuit 31 captures the detection result of the passing stage number by the pulse passing stage number detection circuit 21 at the timing when the latch pulse (LP) is input after the sampling time has elapsed after the SP input is started. Further, the output circuit 31 outputs a value obtained by encoding the number of passing stages as a digital value (out) after A / D conversion.
- the delay time of the delay unit varies depending on environmental factors such as temperature, element type, element variation, and the like, and as shown by the straight line L11 in FIG.
- the range that the A / D conversion result can take for a predetermined voltage range (Vmin to Vmax) is ⁇ out0.
- the range that the A / D conversion result can take for a predetermined voltage range (Vmin to Vmax) is ⁇ out1.
- the sampling time is the same. Since the slopes of the straight line L10 and the straight line L11 are different, as shown in FIG. 9, ⁇ out0 and ⁇ out1 which are A / D conversion result ranges for the same voltage range (Vmin to Vmax) are different. For this reason, a stable A / D conversion result cannot be obtained.
- the present invention has been made in view of the above-described problems, and an object thereof is to provide an A / D conversion device that suppresses fluctuations in the slope (resolution) of input / output characteristics.
- the A / D conversion device is an A / D conversion device that converts an analog input voltage into a digital value, and receives a first pulse signal at a first timing, and the magnitude of the first analog voltage.
- a first pulse delay circuit in which a plurality of delay units for delaying the first pulse signal with a delay time corresponding to the first pulse signal are connected, and the first pulse signal passes through the delay unit in the first pulse delay circuit
- a first pulse passing stage number detection circuit for detecting the first stage number, and a second pulse signal input at a second timing that is the same as the first timing, and a second pulse signal that is different from the first analog voltage.
- a second pulse delay circuit in which a plurality of delay units for delaying the second pulse signal with a delay time corresponding to the magnitude of the analog voltage are connected, and the second pulse signal is the second pulse delay circuit Inside A second pulse passing stage number detection circuit for detecting a second stage number that has passed through the extension unit, and a timing signal indicating a timing at which a difference between the first stage number and the second stage number becomes a predetermined number of stages.
- a third pulse signal is input at the same timing as the timing output circuit and the first timing and the second timing, and the third pulse signal is output with a delay time corresponding to the magnitude of the analog input voltage.
- a third pulse delay circuit in which a plurality of delay units to be delayed are connected, and a third pulse passage for detecting a third number of stages in which the third pulse signal has passed through the delay units in the third pulse delay circuit;
- a stage number detection circuit and an output circuit that outputs the digital value corresponding to the third stage number detected at the timing indicated by the timing signal.
- the A / D conversion device of the present invention further includes a memory circuit that stores a sampling time corresponding to the timing indicated by the timing signal, and the third pulse delay circuit further includes the first timing and the second timing. And at a fourth timing after the third timing, the third pulse passing stage number detection circuit further receives the fourth pulse signal from the fourth timing.
- the timing at which the sampling time stored in the memory circuit has elapsed since the output of the fourth pulse signal is further detected by detecting the fourth stage number that has passed through the delay unit in the pulse delay circuit.
- the digital value corresponding to the fourth stage number detected in step S1 may be output.
- the A / D converter of the present invention further includes a control circuit that stops the operation of the first pulse delay circuit or the second pulse delay circuit after the sampling time is stored in the memory circuit. Also good.
- the A / D converter according to the present invention further includes a control circuit that stops the operations of the first pulse delay circuit and the second pulse delay circuit after the sampling time is stored in the memory circuit. Also good.
- the A / D converter according to the present invention provides an analog input at a timing when the difference between the first stage number corresponding to the first analog voltage and the second stage number corresponding to the second analog voltage becomes a predetermined number of stages.
- a third stage number corresponding to the voltage is detected.
- the slope (resolution) of the input / output characteristics is reduced. Variation can be suppressed.
- FIG. 1 is a block diagram showing a configuration of an A / D conversion device according to a first embodiment of the present invention. It is a flowchart which shows the process sequence of the A / D converter by the 1st Embodiment of this invention. It is a block diagram which shows the structure of the A / D converter by the 2nd Embodiment of this invention. It is a flowchart which shows the process sequence of the A / D converter by the 2nd Embodiment of this invention. It is a timing chart which shows the waveform of the sampling pulse and latch pulse in the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the A / D converter by the 3rd Embodiment of this invention.
- FIG. 1 shows the configuration of the A / D converter according to the present embodiment.
- the A / D converter 100 includes pulse delay circuits 11, 12, 13, pulse passing stage number detection circuits 21, 22, 23, an output circuit 31, and a timing output circuit 41.
- the pulse delay circuit 11 has a configuration in which a plurality of delay units that delay the sampling pulse (SP) with a delay time corresponding to the magnitude of Vin (analog input voltage) are connected.
- the pulse delay circuit 12 has a configuration in which a plurality of delay units that delay the SP by a delay time corresponding to the maximum value (Vmax) of the voltage range that Vin can take are connected.
- the pulse delay circuit 13 has a configuration in which a plurality of delay units that delay the SP with a delay time corresponding to the minimum value (Vmin) of the voltage range that Vin can take are connected.
- the pulse passage stage number detection circuit 21 detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 11.
- the pulse passage stage number detection circuit 22 detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 12.
- the pulse passage stage number detection circuit 23 detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 13.
- the timing output circuit 41 generates a latch pulse (LP2) based on the output signals of the pulse passage stage number detection circuit 22 and the pulse passage stage number detection circuit 23 and outputs the latch pulse (LP2) to the output circuit 31.
- the output circuit 31 latches the output signal of the pulse passage stage number detection circuit 21 based on LP2, encodes the output signal, and outputs a digital value (out) corresponding to Vin.
- the pulse delay circuit 11 is a ring delay line (RDL) that has a configuration in which 16 stages of delay units that give an input signal a delay amount corresponding to a power supply voltage are connected in a ring shape, and this configuration circulates an SP.
- the first-stage delay unit NAND has two input terminals, SP is input to one input terminal, and the output of the 16th-stage delay unit BUF15 is input to the other input terminal.
- the delay unit NAND inverts the logic of the output of the 16th stage delay unit BUF15 whenever the pulse delay circuit 11 is operating.
- Each delay unit from the second-stage delay unit BUF1 to the sixteenth-stage delay unit BUF15 has a gate circuit that outputs the value input to the input terminal to the output terminal (for example, a buffer in which two stages of NOT gates are connected). Circuit). Vin is applied as a power supply voltage to each delay unit (NAND1, BUF1,..., BUF15). Each delay unit delays the SP input from the preceding delay unit by a delay time corresponding to the voltage level of the power supply voltage (Vin) and outputs the delayed SP to the subsequent delay unit. Each delay unit connected in a ring shape operates in the same manner, and the SP is sequentially transmitted from the preceding stage to the subsequent delay unit, so that the SP circulates in the pulse delay circuit 11.
- the process in which the SP circulates in the pulse delay circuit 11 will be specifically described as follows.
- the level of the output terminal of the delay unit NAND does not depend on the input of the other input terminal, Becomes “H” level.
- the level of the output terminal of each delay unit after the second-stage delay unit BUF1 also becomes “H” level.
- SP is inputted to one input terminal of the first delay unit NAND (SP becomes “H” level). Since the level of the other input terminal of the delay unit NAND is “H” level due to the SP output from the delay unit BUF15 in the final stage, the level of the output terminal of the delay unit NAND is the power supply voltage (Vin). It switches to the “L” level with a delay time corresponding to the voltage level. The level of the output terminal of each delay unit after the second-stage delay unit BUF1 is also sequentially switched to the “L” level with a delay time corresponding to the voltage level of the power supply voltage (Vin).
- the level of the output terminal of the last-stage delay unit BUF15 When the level of the output terminal of the last-stage delay unit BUF15 is switched to the “L” level, the level of the output terminal of the first-stage delay unit NAND is “H” over a delay time corresponding to the voltage level of the power supply voltage (Vin). “Switch to level. The level of the output terminal of each delay unit after the second-stage delay unit BUF1 is also sequentially switched to the “H” level with a delay time corresponding to the voltage level of the power supply voltage (Vin).
- the level of the output terminal of the final stage delay unit BUF15 When the level of the output terminal of the final stage delay unit BUF15 is switched to the “H” level, the level of the output terminal is switched to the “L” level in order from the first delay unit NAND in the next round. Thereafter, while the SP is being input, an operation in which the level of the output terminal is sequentially switched from the first delay unit NAND to the opposite level every time the level of the output terminal of the delay unit BUF15 of the final stage is switched is repeated. As a result, the SP continues to circulate in the pulse delay circuit 11.
- the time required from when the level of the input terminal of each delay unit is switched to when the level of the output terminal is switched is a delay time corresponding to Vin which is the power supply voltage of each delay unit. For this reason, the number of stages of delay units through which the SP passes within a predetermined time depends on the analog input voltage (Vin).
- the pulse passage stage number detection circuit 21 is a circuit that detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 11. An output signal of each delay unit in the pulse delay circuit 12 is input to the pulse passage stage number detection circuit 21.
- the pulse passing stage number detection circuit 21 is the number of times that the level of the output terminal of the 16th delay unit BUF15 in the pulse delay circuit 11 is switched from “H” level to “L” level or from “L” level to “H” level. Is output as an 8-bit count value.
- the pulse passing stage number detection circuit 21 outputs 16-bit data representing a state in which the output terminal level of each of the 16 delay units of the pulse delay circuit 11 is “H” level or “L” level. To do.
- the above 8-bit count value and 16-bit data output from the pulse passage stage number detection circuit 21 indicate how many rounds the SP has traveled through the pulse delay circuit 11 and to which delay unit has been advanced. .
- the SP sets the delay unit.
- the pulse passing stage number detection circuit 21 uses the 8-bit + 16-bit digital signal to indicate the number of stages that the SP has passed through the pulse delay circuit 11 constituted by the delay unit to which the analog input voltage (Vin) is applied as the power supply voltage. To output.
- the configurations of the pulse delay circuit 12 and the pulse passage stage number detection circuit 22 are the same as those of the pulse delay circuit 11 and the pulse passage stage number detection circuit 21, respectively.
- the pulse passing stage number detection circuit 22 outputs the number of stages that the SP has passed through the pulse delay circuit 12 constituted by a delay unit to which the analog voltage (Vmax) is applied as a power supply voltage as a digital signal of 8 bits + 16 bits.
- the configurations of the pulse delay circuit 13 and the pulse passage stage number detection circuit 23 are the same as those of the pulse delay circuit 11 and the pulse passage stage number detection circuit 21, respectively.
- the pulse passing stage number detection circuit 23 outputs the number of stages that the SP has passed through the pulse delay circuit 13 constituted by a delay unit to which an analog voltage (Vmin) is applied as a power supply voltage, as a digital signal of 8 bits + 16 bits.
- SP is simultaneously input to the pulse delay circuits 11, 12, and 13 (the SP level is switched from the “L” level to the “H” level) (step S1).
- SP has different delay times in the pulse delay circuits 11, 12, and 13 (in the pulse delay circuit 11, a delay time based on Vin, in the pulse delay circuit 12, a delay time based on Vmax, and in the pulse delay circuit 13 Vmin). Is started at a delay time based on (step S2).
- the pulse passage stage number detection circuits 21, 22, and 23 detect the number of stages that the SP passes through each delay unit (step S3).
- the timing output circuit 41 outputs the latch pulse (LP2) at the timing when the difference between Cmax and Cmin exceeds ⁇ out, that is, the timing satisfying the condition of the following expression (1) (step S4) (the level of LP2 is set). ("L" level is switched to "H” level) (step S5). ⁇ out ⁇ Cmax ⁇ Cmin (1)
- the output circuit 31 receives the number of stages (count value) detected by the pulse passing stage number detection circuit 21 at the timing when the LP2 is input from the timing output circuit 41 (the timing at which the LP2 level is switched from the “L” level to the “H” level). And the output value of each delay unit). Further, the output circuit 31 encodes the latched number of stages into 12 bits and outputs the result as the final A / D conversion result (out) (step S6).
- a signal (8 bits + 16 bits digital signal) from the pulse passage stage number detection circuit 21 represents the following value.
- Output value of each delay unit of 1 to 16 stages “0000000011111111”
- Count value indicating the number of SP laps “00111110”
- the output circuit 31 outputs a value (“0011111101000”) obtained by encoding the number of stages into a 12-bit digital signal.
- the input / output characteristic at the temperature T1 is the straight line L10 in FIG. 9, and the input / output characteristic at the temperature T2 is the straight line L11 in FIG. To do.
- SP is simultaneously input to the pulse delay circuits 11, 12, and 13, and sampling of Vmax and Vmin for determining the output timing of LP2 and sampling of desired Vin are performed in parallel. Therefore, the result of suppressing the change in the slope (resolution) of the input / output characteristics can be obtained by one sampling, so that the A / D conversion result can be obtained at high speed. For example, instead of determining the timing at which Vin sampling ends (LP2 output timing) in real time from the sampling results of Vmax and Vmin as in this embodiment, sampling of Vmax and Vmin is performed for a certain period of time at the first sampling.
- the sampling time of Vin is determined by two or more samplings such that the sampling time (Ts) of the next Vin is determined from the result, and fluctuations in the slope (resolution) of the input / output characteristics are suppressed.
- a method is also conceivable.
- FIG. 3 shows the configuration of the A / D converter according to the present embodiment.
- the A / D converter 200 includes a pulse delay circuit 11, 12, 13, a pulse passage stage number detection circuit 21, 22, 23, an output circuit 31, a timing output circuit 41, a memory circuit 51,
- the control circuit 61 is configured.
- the configurations of the pulse delay circuits 11, 12, 13, the pulse passage stage number detection circuits 21, 22, 23, the output circuit 31, and the timing output circuit 41 are the same as the configurations of the A / D converter 100 according to the first embodiment. The same. However, the timing output circuit 41 outputs the latch pulse LP2 to the output circuit 31 and the memory circuit 51.
- the memory circuit 51 stores a sampling time based on the SP and LP2 from the timing output circuit 41. This sampling time is the time from when SP is input to the pulse delay circuits 11, 12, and 13 until LP2 is output from the timing output circuit 41.
- the control circuit 61 controls the pulse delay circuit 12 and the pulse delay circuit 13.
- step S5 When the latch pulse (LP2) is output from the timing output circuit 41 in step S5, the memory circuit 51 determines the time (sampling time) from the timing of step S1 when SP is input to the timing of step S5 when LP2 is input. (Ts: see FIG. 5) is stored (step S7). Subsequently, the control circuit 61 stops the operations of the pulse delay circuit 12 and the pulse delay circuit 13 (step S8).
- the output circuit 31 detects the number of stages (detected by the pulse passage stage number detection circuit 21 at the timing when the LP2 is input from the timing output circuit 41 (the timing at which the LP2 level is switched from the “L” level to the “H” level)). The count value and the output value of each delay unit) are latched. Further, the output circuit 31 encodes the latched number of stages into 12 bits and outputs the result as the final A / D conversion result (out) (step S6).
- the A / D conversion for one time is completed by the processing up to step S6.
- the processing can be completed with this, but in the present embodiment, it is possible to efficiently perform continuous A / D conversion processing. That is, when the continuous process is not performed (step S9), the process is completed, but when the continuous process is performed (step S9), the processes of steps S10 to S15 are performed.
- the continuous processing steps S10 to S15 will be described.
- step S10 When performing continuous processing, the value of Vin is first changed (step S10). However, this step is not necessary when the same input signal is A / D converted a plurality of times by oversampling or the like.
- the SP starts the circulation of the delay unit in the pulse delay circuit 11 with the delay time based on Vin (step S12).
- the memory circuit 51 outputs a latch pulse (LP2) after the sampling time Ts stored in step S8 has elapsed after SP is input again in step S11 (step S13).
- the output circuit 31 receives the LP2 from the memory circuit 51 (the LP2 level is switched from the “L” level to the “H” level) at the timing when the pulse passing stage number detection circuit 21 detects the count (count value and each value).
- the output value of the delay unit is latched. Further, the output circuit 31 encodes the latched number of stages into 12 bits and outputs the result as the final A / D conversion result (out) (step S14).
- step S15 Thereafter, when the continuous process is repeated, the processes of steps S10 to S14 are repeated (step S15).
- the slope of the input / output characteristics can be made constant. Therefore, according to the present embodiment, it is possible to suppress fluctuations in the slope (resolution) of the input / output characteristics regardless of temperature fluctuations and fluctuations in the characteristics of the transistors constituting the pulse delay circuit.
- SP is simultaneously input to the pulse delay circuits 11, 12 and 13, and sampling of Vmax and Vmin for determining the output timing of LP2 is performed. Since sampling of the desired Vin is performed in parallel, the first A / D conversion result can be obtained at high speed.
- the pulse delay circuits 12 and 13 can be stopped by storing the output timing of LP2 in the memory circuit 51. Therefore, power consumption can be reduced. Note that only one of the pulse delay circuits 12 and 13 may be stopped, and in this case, power consumption can be reduced.
- FIG. 6 shows the configuration of the A / D converter according to the present embodiment.
- the A / D converter 300 includes a pulse delay circuit 12, 14, a pulse passage stage number detection circuit 22, 24, an output circuit 31, a timing output circuit 41, a memory circuit 51, a control circuit 61, and the like. , And a selector 71.
- the configurations of the pulse delay circuit 12, the pulse passage stage number detection circuit 22, the output circuit 31, the timing output circuit 41, the memory circuit 51, and the control circuit 61 are the same as the configurations of the A / D converter 200 according to the second embodiment. The same.
- the configurations of the pulse delay circuit 14 and the pulse passage stage number detection circuit 24 are the same as those of the pulse delay circuit 11 and the pulse passage stage number detection circuit 21 according to the first embodiment, respectively. Further, the pulse passing stage number detection circuit 24 outputs the number of stages that the SP has passed through the pulse delay circuit 14 constituted by a delay unit to which the output voltage of the selector 71 is applied as a power supply voltage as an 8-bit + 16-bit digital signal. . The selector 71 can switch the voltage to be output, and outputs either Vin or Vmin.
- step S0 the output of the selector 71 is switched to Vmin (step S0). Subsequently, the same processing as the processing in steps S1 to S7 shown in FIG. 4 is performed. After the memory circuit 51 stores the sampling time Ts in step S7, the control circuit 61 stops the operation of the pulse delay circuit 12 (step S16).
- step S17 the output of the selector 71 is switched to Vin (step S17).
- SP is input again, and A / D conversion based on Vin is performed (steps S11 to S14).
- steps S11 to S14 shown in FIG. 8 is the same as the processing in steps S11 to S14 shown in FIG.
- step S15 When repeating the continuous processing (step S15), the value of Vin is changed (step S18), and the processing from steps S11 to S15 is repeated.
- the slope of the input / output characteristics can be made constant. Therefore, according to the present embodiment, it is possible to suppress fluctuations in the slope (resolution) of the input / output characteristics regardless of temperature fluctuations and fluctuations in the characteristics of the transistors constituting the pulse delay circuit.
- the pulse delay circuit 12 can be stopped by storing the output timing of LP2 in the memory circuit 51. Therefore, power consumption can be reduced.
- the pulse delay circuit 14 in which the pulse delay circuit 11 and the pulse delay circuit 13 are shared is used.
- the pulse delay circuit 11 and the pulse delay circuit 12 may be shared.
- the present invention makes it possible to provide an A / D converter that suppresses fluctuations in the slope (resolution) of input / output characteristics.
Abstract
Description
本願は、2009年4月9日に日本国に出願された特願2009-095010号に基づき優先権を主張し、その内容をここに援用する。
まず、本発明の第1の実施形態を説明する。図1は、本実施形態によるA/D変換装置の構成を示している。図1において、A/D変換装置100は、パルス遅延回路11,12,13と、パルス通過段数検出回路21,22,23と、出力回路31と、タイミング出力回路41から構成される。
Δout≧Cmax-Cmin ・・・(1)
1~16段の各遅延ユニットの出力値=“0000000011111111”
SPの周回数を示すカウント値=“00111110”
次に、本発明の第2の実施形態を説明する。図3は、本実施形態によるA/D変換装置の構成を示している。図3において、A/D変換装置200は、パルス遅延回路11,12,13と、パルス通過段数検出回路21,22,23と、出力回路31と、タイミング出力回路41と、メモリ回路51と、制御回路61から構成される。パルス遅延回路11,12,13、パルス通過段数検出回路21,22,23、出力回路31、タイミング出力回路41の構成はそれぞれ、第1の実施形態によるA/D変換装置100が有する各構成と同じである。ただし、タイミング出力回路41は、ラッチパルスLP2を出力回路31とメモリ回路51に出力する。
次に、本発明の第3の実施形態を説明する。図6は、本実施形態によるA/D変換装置の構成を示している。図6において、A/D変換装置300は、パルス遅延回路12,14と、パルス通過段数検出回路22,24と、出力回路31と、タイミング出力回路41と、メモリ回路51と、制御回路61と、セレクタ71から構成される。パルス遅延回路12、パルス通過段数検出回路22、出力回路31、タイミング出力回路41、メモリ回路51、制御回路61の構成はそれぞれ、第2の実施形態によるA/D変換装置200が有する各構成と同じである。
21,22,23,24 パルス通過段数検出回路
31 出力回路
41 タイミング出力回路
51 メモリ回路
61 制御回路
71 セレクタ
100,200,300,400 A/D変換装置
Claims (4)
- アナログ入力電圧をデジタル値に変換するA/D変換装置であって、
第1のタイミングで第1のパルス信号が入力され、第1のアナログ電圧の大きさに応じた遅延時間で該第1のパルス信号を遅延させる遅延ユニットを複数段接続した第1のパルス遅延回路と、
前記第1のパルス信号が前記第1のパルス遅延回路内の遅延ユニットを通過した第1の段数を検出する第1のパルス通過段数検出回路と、
前記第1のタイミングと同一の第2のタイミングで第2のパルス信号が入力され、前記第1のアナログ電圧と異なる第2のアナログ電圧の大きさに応じた遅延時間で該第2のパルス信号を遅延させる遅延ユニットを複数段接続した第2のパルス遅延回路と、
前記第2のパルス信号が前記第2のパルス遅延回路内の遅延ユニットを通過した第2の段数を検出する第2のパルス通過段数検出回路と、
前記第1の段数と前記第2の段数との差が所定の段数となるタイミングを示すタイミング信号を出力するタイミング出力回路と、
前記第1のタイミングおよび前記第2のタイミングと同一のタイミングで第3のパルス信号が入力され、前記アナログ入力電圧の大きさに応じた遅延時間で該第3のパルス信号を遅延させる遅延ユニットを複数段接続した第3のパルス遅延回路と、
前記第3のパルス信号が前記第3のパルス遅延回路内の遅延ユニットを通過した第3の段数を検出する第3のパルス通過段数検出回路と、
前記タイミング信号が示すタイミングで検出された前記第3の段数に対応する前記デジタル値を出力する出力回路と、
を有するA/D変換装置。 - 前記タイミング信号が示すタイミングに対応するサンプリング時間を記憶するメモリ回路をさらに有し、
前記第3のパルス遅延回路はさらに、前記第1のタイミング、前記第2のタイミング、および前記第3のタイミングよりも後の第4のタイミングで第4のパルス信号が入力され、
前記第3のパルス通過段数検出回路はさらに、前記第4のパルス信号が前記第4のパルス遅延回路内の遅延ユニットを通過した第4の段数を検出し、
前記出力回路はさらに、前記第4のパルス信号が入力されてから、前記メモリ回路に記憶された前記サンプリング時間が経過したタイミングで検出された前記第4の段数に対応する前記デジタル値を出力する、
請求項1に記載のA/D変換装置。 - 前記メモリ回路に前記サンプリング時間が記憶された後、前記第1のパルス遅延回路または前記第2のパルス遅延回路の動作を停止させる制御回路をさらに有する、請求項2に記載のA/D変換装置。
- 前記メモリ回路に前記サンプリング時間が記憶された後、前記第1のパルス遅延回路および前記第2のパルス遅延回路の動作を停止させる制御回路をさらに有する、請求項2に記載のA/D変換装置。
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CN201080015982.1A CN102379086B (zh) | 2009-04-09 | 2010-04-07 | A/d转换装置 |
JP2011508247A JP5059968B2 (ja) | 2009-04-09 | 2010-04-07 | A/d変換装置 |
US13/267,632 US8593323B2 (en) | 2009-04-09 | 2011-10-06 | A/D conversion device |
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US13/267,632 Continuation US8593323B2 (en) | 2009-04-09 | 2011-10-06 | A/D conversion device |
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JP (1) | JP5059968B2 (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004274157A (ja) * | 2003-03-05 | 2004-09-30 | Denso Corp | A/d変換出力データの非直線性補正方法及び非直線性補正装置 |
JP2006279839A (ja) * | 2005-03-30 | 2006-10-12 | Denso Corp | A/d変換装置、およびa/d変換装置を備えたセンサ装置 |
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JP3064644B2 (ja) | 1992-03-16 | 2000-07-12 | 株式会社デンソー | A/d変換回路 |
US6711202B2 (en) * | 2000-06-09 | 2004-03-23 | Cymer, Inc. | Discharge laser with porous insulating layer covering anode discharge surface |
JP2002118467A (ja) * | 2000-10-11 | 2002-04-19 | Denso Corp | A/d変換回路 |
JP4396063B2 (ja) * | 2001-07-13 | 2010-01-13 | 株式会社デンソー | A/d変換方法及び装置 |
JP3960267B2 (ja) * | 2003-05-29 | 2007-08-15 | 株式会社デンソー | A/d変換方法及び装置 |
JP3991969B2 (ja) * | 2003-09-17 | 2007-10-17 | 株式会社デンソー | A/d変換回路 |
US6977605B2 (en) * | 2003-11-26 | 2005-12-20 | Texas Instruments Incorporated | Dummy delay line based DLL and method for clocking in pipeline ADC |
US6967603B1 (en) * | 2004-07-19 | 2005-11-22 | Realtek Semiconductor Corp. | ADC background calibration timing |
JP2006279389A (ja) * | 2005-03-29 | 2006-10-12 | Fuji Photo Film Co Ltd | 固体撮像装置およびその信号処理方法 |
US7612699B2 (en) * | 2007-05-17 | 2009-11-03 | Denso Corporation | A/D converter circuit and A/D conversion method |
US7639169B2 (en) * | 2007-05-17 | 2009-12-29 | Denso Corporation | A/D converter circuit and A/D conversion method |
US8164493B2 (en) * | 2008-05-29 | 2012-04-24 | Realtek Semiconductor Corporation | High-resolution circular interpolation time-to-digital converter |
JP5086937B2 (ja) * | 2008-08-19 | 2012-11-28 | ルネサスエレクトロニクス株式会社 | パルス位相差検出回路及びこれを用いたa/d変換回路 |
JP5206833B2 (ja) * | 2010-09-28 | 2013-06-12 | 株式会社デンソー | A/d変換回路 |
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JP2006279839A (ja) * | 2005-03-30 | 2006-10-12 | Denso Corp | A/d変換装置、およびa/d変換装置を備えたセンサ装置 |
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CN102379086A (zh) | 2012-03-14 |
CN102379086B (zh) | 2014-08-13 |
US20120075136A1 (en) | 2012-03-29 |
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