WO2010104098A1 - 太陽電池の製造方法及び太陽電池 - Google Patents
太陽電池の製造方法及び太陽電池 Download PDFInfo
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- WO2010104098A1 WO2010104098A1 PCT/JP2010/053949 JP2010053949W WO2010104098A1 WO 2010104098 A1 WO2010104098 A1 WO 2010104098A1 JP 2010053949 W JP2010053949 W JP 2010053949W WO 2010104098 A1 WO2010104098 A1 WO 2010104098A1
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 172
- 239000000758 substrate Substances 0.000 claims description 46
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 19
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022433—Particular geometry of the grid contacts
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
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- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a method for manufacturing a back junction solar cell and a solar cell.
- Solar cells are expected to be a new energy source because they can directly convert clean and inexhaustible sunlight into electricity.
- the solar cell described in Patent Document 1 includes an i-type semiconductor layer that covers the back surface of an n-type semiconductor substrate, and a plurality of p-type semiconductor layers formed along a predetermined direction on the i-type semiconductor layer. And an n-type semiconductor layer covering the i-type semiconductor layer and the plurality of p-type semiconductor layers.
- Each p-side electrode is formed on each p-type semiconductor layer via an n-type semiconductor layer.
- Each n-side electrode is formed between two p-side electrodes.
- the manufacturing process of the solar cell can be simplified.
- the n-side electrode and the p-side electrode are formed on the n-type semiconductor layer. Therefore, there is a problem that leakage is likely to occur between the n-side electrode and the p-side electrode, and the solar cell characteristics are deteriorated.
- the present invention has been made in view of the above-described problems, and an object thereof is to provide a method of manufacturing a back junction solar cell and a solar cell that can improve the solar cell characteristics.
- a method for manufacturing a solar cell includes: a step A of forming a first semiconductor layer having a first conductivity type on a first region of one main surface of a semiconductor substrate; Step B for forming a second semiconductor layer having a second conductivity type across the first semiconductor layer from two regions, Step C for forming an electrode layer on the second semiconductor layer, and the electrode layer Step D of applying a protective film on the first region and the region corresponding to the second region, Step E of removing the portion of the electrode layer exposed from the protective film, and removing the protective film A step F, wherein in the step F, at least a part of the second semiconductor layer exposed from the mask is removed together with the protective film.
- the thickness of the second semiconductor layer can be reduced between the electrode layers. Therefore, leakage between the electrode layers can be suppressed without patterning the second semiconductor layer with a mask or the like. As a result, the solar cell characteristics can be improved.
- a solar cell includes a semiconductor substrate, a first semiconductor layer formed on a first region on one main surface of the semiconductor substrate, having a first conductivity type, and on one main surface of the semiconductor substrate.
- a second semiconductor layer formed on the second region and having a second conductivity type, a first electrode formed on the first semiconductor layer on the first region, and a second semiconductor layer on the second region A second semiconductor layer formed on the first semiconductor layer from the second region, the second semiconductor layer being formed from the first electrode and the second electrode.
- the gist is that the exposed portion has a portion of the second semiconductor layer having a smaller thickness than the portion covered with the first electrode and the second electrode.
- the conductivity type of the second semiconductor layer may be n-type.
- the semiconductor substrate may be a crystalline silicon substrate.
- the semiconductor substrate may have a p-type conductivity type.
- the first semiconductor layer and the second semiconductor layer may be made of an amorphous semiconductor.
- FIG. 1 is a plan view of the back side of the solar cell 100 according to the first embodiment of the present invention.
- FIG. 2 is an enlarged sectional view taken along line AA in FIG.
- FIG. 3 is a diagram for explaining a method of manufacturing the solar cell 10 according to the first embodiment of the present invention.
- FIG. 4 is a diagram for explaining a method of manufacturing the solar cell 10 according to the first embodiment of the present invention.
- FIG. 5 is a diagram for explaining a method of manufacturing the solar cell 10 according to the first embodiment of the present invention.
- FIG. 6 is a diagram for explaining a method of manufacturing the solar cell 10 according to the first embodiment of the present invention.
- FIG. 7 is a diagram for explaining a method of manufacturing the solar cell 10 according to the first embodiment of the present invention.
- FIG. 1 is a plan view of the back side of the solar cell 100 according to the first embodiment of the present invention.
- FIG. 2 is an enlarged sectional view taken along line AA in FIG.
- FIG. 3 is a
- FIG. 8 is a plan view of the back side of the solar cell 100 according to the second embodiment of the present invention.
- FIG. 9 is an enlarged cross-sectional view taken along line BB in FIG.
- FIG. 10 is a cross-sectional view showing the configuration of the solar cell 100 according to the embodiment of the present invention.
- FIG. 1 is a plan view of the back surface side of the solar cell 100 according to the first embodiment.
- FIG. 2 is an enlarged sectional view taken along line AA in FIG.
- the solar cell 100 includes an n-type crystalline silicon substrate 10n, an i-type amorphous semiconductor layer 11i, a p-type amorphous semiconductor layer 11p, an i-type amorphous semiconductor layer 12i, n A type amorphous semiconductor layer 12n, a p-side electrode 20p, and an n-side electrode 20n are provided.
- the n-type crystalline silicon substrate 10n is made of thin single crystal silicon or polycrystalline silicon.
- N-type crystalline silicon substrate 10n has a light receiving surface for receiving sunlight and a back surface provided on the opposite side of the light receiving surface.
- the n-type crystalline silicon substrate 10n generates carriers (electrons and holes) by receiving light on the light receiving surface.
- no structure for example, a metal electrode
- no structure that blocks the incidence of light is formed on the light receiving surface of the n-type crystalline silicon substrate 10n, and light can be received over the entire light receiving surface. It should be noted.
- the i-type amorphous semiconductor layer 11i is formed along the first direction on the back surface of the n-type crystalline silicon substrate 10n.
- the i-type amorphous semiconductor layer 11i is formed without positively introducing impurities.
- the i-type amorphous semiconductor layer 11i has a thickness that does not substantially contribute to power generation, for example, about several to 250 inches.
- the p-type amorphous semiconductor layer 11p is formed along the first direction on the i-type amorphous semiconductor layer 11i. As will be described later, a plurality of p-type amorphous semiconductor layers 11p are formed by patterning.
- the p-type amorphous semiconductor layer 11p has p-type conductivity.
- the thickness of the p-type amorphous semiconductor layer 11p is, for example, about 10 nm.
- HIT registered trademark, Sanyo Electric Co., Ltd.
- the i-type amorphous semiconductor layer 12i is formed from the back surface of the n-type crystalline silicon substrate 10n to the p-type amorphous semiconductor layer 11p.
- the i-type amorphous semiconductor layer 12i is formed so as to cover the entire back surface of the n-type crystalline silicon substrate 10n.
- the i-type amorphous semiconductor layer 12i is formed without positively introducing impurities.
- the thickness of the i-type amorphous semiconductor layer 12i is, for example, about several to 250 inches.
- the n-type amorphous semiconductor layer 12n is formed on the i-type amorphous semiconductor layer 12i.
- the n-type amorphous semiconductor layer 12n is formed so as to cover the i-type amorphous semiconductor layer 12i. That is, the n-type amorphous semiconductor layer 12n is formed so as to straddle the plurality of patterned p-type amorphous semiconductor layers 11p.
- the n-type amorphous semiconductor layer 12n has an n-type conductivity type different from that of the p-type amorphous semiconductor layer 11p.
- the back surface of the n-type crystalline silicon substrate 10n, the amorphous semiconductor layer, Minority carrier recombination at the interface can be suppressed.
- the back surface of the n-type crystalline silicon substrate 10n can be improved.
- Each of the i-type amorphous semiconductor layer 11i, the i-type amorphous semiconductor layer 12i, the p-type amorphous semiconductor layer 11p, and the n-type amorphous semiconductor layer 12n is composed of an amorphous semiconductor containing silicon. be able to. Examples of such an amorphous semiconductor include amorphous silicon, amorphous silicon carbide, and amorphous silicon germanium. However, the present invention is not limited to this, and other amorphous semiconductors may be used.
- Each of the i-type amorphous semiconductor layer 11i, the i-type amorphous semiconductor layer 12i, the p-type amorphous semiconductor layer 11p, and the n-type amorphous semiconductor layer 12n is composed of one kind of amorphous semiconductor. In addition, two or more kinds of amorphous semiconductors may be combined.
- the p-side electrode 20p is a collecting electrode that collects carriers.
- the p-side electrode 20p is composed of a metal layer such as Ag, Al, or conductive paste.
- the p-side electrode 20p is formed on the p-type amorphous semiconductor layer 11p via the i-type amorphous semiconductor layer 12i and the n-type amorphous semiconductor layer 12n. Therefore, the p-side electrode 20p is formed in a line shape along the first direction.
- a transparent electrode layer made of indium tin oxide (ITO), tin oxide, zinc oxide, or the like is interposed between the p-side electrode 20p and the n-type amorphous semiconductor layer 12n. May be.
- the n-side electrode 20n is a collecting electrode that collects carriers.
- the n-side electrode 20n is composed of a metal layer such as Ag, Al, or conductive paste.
- the n-side electrode 20n is formed on the back surface of the n-type crystalline silicon substrate 10n via the i-type amorphous semiconductor layer 12i and the n-type amorphous semiconductor layer 12n. Therefore, the n-side electrode 20n is formed in a line shape along the first direction between the one p-side electrode 20p and the other p-side electrode 20p.
- the above-mentioned transparent electrode layer may be interposed between the n-side electrode 20n and the n-type amorphous semiconductor layer 12n.
- the thickness ⁇ of the portion exposed from the p-side electrode 20p and the n-side electrode 20n in the n-type amorphous semiconductor layer 12n is determined by the n-type amorphous semiconductor layer. It is smaller than the thickness ⁇ of the portion covered with the p-side electrode 20p or the n-side electrode 20n in 12n. That is, the n-type amorphous semiconductor layer 12n is formed thin between the p-side electrode 20p and the n-side electrode 20n.
- the thickness ⁇ is about several nm and the thickness ⁇ is about 10 nm, but is not limited thereto.
- each figure (a) is the top view which looked at the n-type crystalline silicon substrate 10n from the back surface side
- each figure (b) is sectional drawing of each figure (a).
- an i-type amorphous semiconductor layer 11i and a p-type amorphous semiconductor layer 11p are sequentially formed on the entire back surface of the n-type crystalline silicon substrate 10n using a CVD method.
- a resist film 30 is applied in a predetermined pattern on the p-type amorphous semiconductor layer 11p.
- the predetermined pattern is set corresponding to a region where the p-side electrode 20p is formed.
- the region R1 exposed from the resist film 30 in the i-type amorphous semiconductor layer 11i and the p-type amorphous semiconductor layer 11p is removed.
- the i-type amorphous semiconductor layer 11i and the p-type amorphous semiconductor layer 11p are patterned, and substantially half of the n-type crystalline silicon substrate 10n is exposed.
- an exposed region of the n-type crystalline silicon substrate 10n is cleaned by performing a wet etching process and a hydrogen plasma process.
- the i-type amorphous semiconductor layer 12i and the n-type are straddled across the p-type amorphous semiconductor layer 11p from the back surface of the n-type crystalline silicon substrate 10n.
- Amorphous semiconductor layers 12n are sequentially formed.
- the electrode layer 40 is formed on the n-type amorphous semiconductor layer 12n by using a CVD method, a sputtering method, a vapor deposition method, a plating method, a printing method, or the like.
- a photoresist film (protective film) is applied on the electrode layer 40, and the photoresist film is patterned by exposure with a predetermined pattern.
- a patterned resist film 50 (protective film) is formed on the electrode layer 40 on the region where the p-type amorphous semiconductor layer 11p is formed and on the other region. Applied.
- a portion of the electrode layer 40 exposed from the resist film 50 is removed with a sodium hydroxide solution or the like.
- the p-side electrode 20p and the n-side electrode 20n are formed, and a part of the n-type amorphous semiconductor layer 12n is exposed.
- the resist film 50 is removed, and a part of the n-type amorphous semiconductor layer 12n is removed. Thereby, the thickness of the portion exposed from the resist film 50 in the n-type amorphous semiconductor layer 12n is reduced.
- the method for manufacturing the solar cell 100 according to the first embodiment includes a step of removing the resist film 50 and removing a part of the n-type amorphous semiconductor layer 12n.
- the thickness ⁇ of the portion exposed from the p-side electrode 20p and the n-side electrode 20n in the n-type amorphous semiconductor layer 12n is determined by the p-side electrode 20p or the n-side electrode 20n in the n-type amorphous semiconductor layer 12n. It is formed smaller than the thickness ⁇ of the portion to be covered. That is, the n-type amorphous semiconductor 12n is a portion of the n-type amorphous semiconductor 12n that is covered with the p-side electrode 20p and the n-side electrode 20n in a portion exposed from the p-side electrode 20p and the n-side electrode 20n. A portion having a thickness ⁇ smaller than the thickness ⁇ is provided.
- the resistance of the n-type amorphous semiconductor layer 12n can be increased between the p-side electrode 20p and the n-side electrode 20n. Therefore, leakage between the p-side electrode 20p and the n-side electrode 20n can be suppressed without patterning the n-type amorphous semiconductor layer 12n with a mask or the like. As a result, the characteristics of the solar cell 100 can be improved.
- FIG. 8 is a plan view of the solar cell 100 as seen from the back side.
- FIG. 9 is an enlarged cross-sectional view taken along line BB in FIG.
- the i-type amorphous semiconductor layer 12i and the n-type amorphous semiconductor layer 12n are removed between the p-side electrode 20p and the n-side electrode 20n. Between the p-side electrode 20p and the n-side electrode 20n, the back surface of the n-type crystalline silicon substrate 10n is exposed.
- an etching solution having a high etching rate for the amorphous semiconductor layer is used when the resist film 50 is removed.
- the resist film 50 can be removed, and not only the n-type amorphous semiconductor layer 12n but also the i-type amorphous semiconductor layer 12i can be removed.
- the method for manufacturing the solar cell 100 according to the second embodiment includes the steps of removing the resist film 50 and removing the i-type amorphous semiconductor layer 12i and the n-type amorphous semiconductor layer 12n.
- leakage between the p-side electrode 20p and the n-side electrode 20n can be suppressed without patterning the i-type amorphous semiconductor layer 12i and the n-type amorphous semiconductor layer 12n with a mask or the like. As a result, the characteristics of the solar cell 100 can be further improved.
- the n-type crystalline silicon substrate 10n is used as the substrate of the solar cell 100, but is not limited thereto.
- the substrate of the solar cell 100 may have a p-type conductivity type.
- the substrate of the solar cell 100 may be made of a general semiconductor material including a crystalline semiconductor material such as polycrystalline Si or microcrystalline Si, or a compound semiconductor material such as GaAs or InP.
- the p-type amorphous semiconductor layer 11p and the n-type amorphous semiconductor layer 12n are formed opposite to the above-described embodiment. . That is, the p-type amorphous semiconductor layer 11p is formed over the plurality of patterned n-type amorphous semiconductor layers 12n.
- the p-type amorphous semiconductor is likely to have an electric resistance larger than that of the n-type amorphous semiconductor, so that leakage occurs between the p-side electrode 20p and the n-side electrode 20n. It can be suppressed more.
- the n-type amorphous semiconductor layer 12n is formed so as to straddle the plurality of patterned p-type amorphous semiconductor layers 11p.
- the type may be reversed. Specifically, as shown in FIG. 10, the p-type amorphous semiconductor layer 11p is formed on the back surface of the n-type crystalline silicon substrate 10n so as to straddle the plurality of patterned n-type amorphous semiconductor layers 12n. It may be formed.
- p-type amorphous silicon has a higher electrical resistance than n-type amorphous silicon, it is possible to further suppress the occurrence of leakage between the p-side electrode 20p and the n-side electrode 20n. Can do.
- the i-type amorphous semiconductor layer 11i and the i-type amorphous semiconductor layer 12i are formed without positively introducing impurities, but contain a small amount of dopant. May be.
- the i-type amorphous semiconductor layer 13i may not be formed on the back surface of the n-type crystalline silicon substrate 10n. In this case, the resistance on the back side of the n-type crystalline silicon substrate 10n can be further reduced.
- the i-type amorphous semiconductor layer 12i is removed together with the n-type amorphous semiconductor layer 12n. However, at least a part of the i-type amorphous semiconductor layer 12i is formed on the substrate. It may be left. Even if only the n-type amorphous semiconductor layer 12n is removed, the leakage suppressing effect can be improved.
- the method for manufacturing a solar cell and the solar cell according to the present invention can provide a method for manufacturing a back junction solar cell and a solar cell that can improve the solar cell characteristics. It is useful in the manufacturing field.
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Abstract
Description
(太陽電池の構成)
本発明の第1実施形態に係る太陽電池の構成について、図1及び図2を参照しながら説明する。図1は、第1実施形態に係る太陽電池100の裏面側の平面図である。図2は、図1のA-A線における拡大断面図である。
次に、太陽電池100の製造方法について、図3乃至図7を参照しながら説明する。なお、各図(a)は、n型結晶シリコン基板10nを裏面側から見た平面図であり、各図(b)は、各図(a)の断面図である。
第1実施形態に係る太陽電池100の製造方法は、レジスト膜50を除去するとともに、n型非晶質半導体層12nの一部を除去する工程を備える。
以下において、第2実施形態に係る太陽電池100について、図面を参照しながら説明する。以下においては、第1実施形態との相違点について主に説明する。
第2実施形態に係る太陽電池100の製造方法は、レジスト膜50を除去するとともに、i型非晶質半導体層12i及びn型非晶質半導体層12nを除去する工程を備える。
本発明は上記の実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
10n…n型結晶シリコン基板
11i…i型非晶質半導体層
11p…p型非晶質半導体層
12i…i型非晶質半導体層
12n…n型非晶質半導体層
20n…n側電極
20p…p側電極
30,50…レジスト膜
40…電極層
100…太陽電池
Claims (6)
- 半導体基板の一主面の第1領域上において、第1導電型を有する第1半導体層を形成する工程Aと、
前記一主面の前記第2領域上から前記第1半導体層上に跨って、第2導電型を有する第2半導体層を形成する工程Bと、
前記第2半導体層上に電極層を形成する工程Cと、
前記電極層のうち前記第1領域及び前記第2領域に対応する領域上に保護膜を施す工程Dと、
前記電極層のうち前記保護膜から露出する部分を除去する工程Eと、
前記保護膜を除去する工程Fとを備え、
前記工程Fにおいて、
前記第2半導体層のうち前記マスクから露出する部分の少なくとも一部を前記保護膜とともに除去することを特徴とする太陽電池の製造方法。 - 半導体基板と、
前記半導体基板の一主面上における第1領域上に形成され、第1導電型を有する第1半導体層と、
前記半導体基板の前記一主面上における第2領域上に形成され、第2導電型を有する第2半導体層と、
前記第1領域上において、前記第1半導体層上に形成された第1電極と、
前記第2領域上において、前記第2半導体層上に形成された第2電極とを備え、
前記第2半導体層は、前記第2領域上から前記第1半導体層上に跨って形成されており、
前記第2半導体層は、前記第1電極及び前記第2電極から露出する部分に、前記第2半導体層のうち前記第1電極及び前記第2電極に被覆される部分よりも厚みの小さい部分を有することを特徴とする太陽電池。 - 前記第2半導体層の導電型はp型であることを特徴とする請求項2に記載の太陽電池。
- 前記半導体基板は、結晶シリコン基板であることを特徴とする請求項2又は3に記載の太陽電池。
- 前記半導体基板は、n型の導電型を有することを特徴とする請求項2又は3に記載の太陽電池。
- 前記第1半導体層及び前記第2半導体層は、非晶質半導体からなることを特徴とする請求項4に記載の太陽電池。
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JP2011503835A JP5538360B2 (ja) | 2009-03-10 | 2010-03-10 | 太陽電池の製造方法及び太陽電池 |
CN2010800112007A CN102349166A (zh) | 2009-03-10 | 2010-03-10 | 太阳能电池的制造方法和太阳能电池 |
EP10750851.7A EP2408021A4 (en) | 2009-03-10 | 2010-03-10 | Process for producing solar battery, and solar battery |
US13/255,616 US9006564B2 (en) | 2009-03-10 | 2010-03-10 | Method of manufacturing solar cell and solar cell |
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JP6136024B2 (ja) * | 2012-03-08 | 2017-05-31 | パナソニックIpマネジメント株式会社 | 太陽電池の製造方法 |
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