WO2010097986A1 - Registre à décalage et dispositif d'affichage - Google Patents

Registre à décalage et dispositif d'affichage Download PDF

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Publication number
WO2010097986A1
WO2010097986A1 PCT/JP2009/068226 JP2009068226W WO2010097986A1 WO 2010097986 A1 WO2010097986 A1 WO 2010097986A1 JP 2009068226 W JP2009068226 W JP 2009068226W WO 2010097986 A1 WO2010097986 A1 WO 2010097986A1
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WIPO (PCT)
Prior art keywords
stage
output
terminal
voltage
transistor
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PCT/JP2009/068226
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English (en)
Japanese (ja)
Inventor
正彦 中溝
政司 米丸
健一 石井
泰章 岩瀬
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シャープ株式会社
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Priority to US13/202,950 priority Critical patent/US9281077B2/en
Publication of WO2010097986A1 publication Critical patent/WO2010097986A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to a shift register used for a gate driver of a display panel.
  • Gate monolithic construction has been promoted to reduce costs by forming gate drivers with amorphous silicon on a liquid crystal panel.
  • Gate monolithic is also referred to as a gate driverless, panel built-in gate driver, gate-in panel, or the like.
  • FIG. 27 shows the configuration of such a gate driver (scan driving circuit) described in Patent Document 1.
  • the gate driver has a configuration in which a plurality of unit stages SRC11, SRC12,..., SRC1N and SRC1D are connected in cascade.
  • the first clock CKV is input to the odd stages and the second clock CKVB is input to the even stages.
  • the first clock CKV and the second clock CKVB are in an opposite phase relationship.
  • a gate signal (G1, G2,... GN, GD) supplied to the gate bus line is output from the output terminal OUT.
  • the scan input signal STV is input to the first input terminal IN1 of the first unit stage SRC11, and the gate output from the previous stage is input to the first input terminal IN1 of the subsequent stages SRC12, SRC13,... SRC1N, SRC1D.
  • a signal is input.
  • the gate signal output from the next unit stage is input to the second input terminal IN2 of the unit stages SRC11, SRC12,..., SRC1N.
  • each unit stage includes a first voltage terminal VOFF.
  • Patent Document 1 discloses a circuit configuration of a unit stage 100 as shown in FIG. 28 as each of the unit stages SRC11, SRC12,..., SRC1N, and SRC1D.
  • the unit stage 100 includes a buffer unit 110, a charging unit 120, a driving unit 130, a discharging unit 140, and a holding unit 150.
  • the first clock CKV or the second clock CKVB of FIG. 29 set by the applicant is input to the unit stage 100. That is, when the unit stage 100 is an odd-numbered one, the first clock CKV of FIG. 29 is input to the clock terminal CK, and when the unit stage 100 is an even-numbered one, the clock terminal It is assumed that the second clock CKVB of FIG. 29 is input to CK.
  • the first clock CKV and the second clock CKVB are in an opposite phase relationship.
  • this gate pulse is input to the next unit stage 100 and a gate pulse is output from the next unit stage 100
  • the gate pulse is input to the second input terminal IN2 of the own unit stage 100.
  • the transistor Q3 of the driving unit 130 and the transistor Q4 of the discharging unit 140 are turned on, and the output terminal OUT, the gate bus line, and the node N1 are connected to the first voltage terminal VOFF and reset to the low level. .
  • the transistor Q5 of the holding unit 150 is turned on every time the second clock CKVB input to the clock terminal CK becomes High level, and the node N1 is periodically switched. To the output terminal OUT.
  • the odd-numbered unit stage 100 performs the same operation at a timing shifted by one clock pulse from the timing of FIG.
  • the gate monolithic circuit configuration described above can increase the driving capability by sufficiently reducing the channel resistance of the output transistor such as the transistor Q2 by the bootstrap effect even if only the n-channel TFT is used. Accordingly, even when a gate driver is monolithically formed in a panel using a material that is difficult to manufacture TFTs such as an amorphous silicon, it is disadvantageous such as high threshold voltage and low electron mobility of the amorphous silicon TFT. There is an advantage that it is possible to sufficiently overcome such characteristics and meet the demand for lower panel voltage.
  • the output transistor indicated by the transistor Q2 in FIG. 28 includes a gate-drain parasitic capacitance (hereinafter referred to as drain parasitic capacitance) and a gate-source parasitic capacitance (hereinafter referred to as source parasitic capacitance).
  • drain parasitic capacitance a gate-drain parasitic capacitance
  • source parasitic capacitance a gate-source parasitic capacitance
  • the fluctuation DN of the potential of the node N1 through the drain parasitic capacitance acts in a direction to increase the current by decreasing the channel resistance of the transistor Q2.
  • the fluctuation DN of the potential at the node N1 outside the gate pulse output period becomes noise.
  • the WXGA resolution panel has 768 gate bus lines, but each stage has a period of 767 clocks other than the period in which the original gate pulse is output to the corresponding gate bus line.
  • the increase in the potential of the node N1 during the vertical blanking period provided at the boundary between frames defined by the vertical synchronization signal Vsync becomes noise.
  • the source parasitic capacitance has an effect of pushing up the potential of the node N1 when the gate pulse is output, and thus advantageously works to increase the driving capability of the transistor Q2.
  • the bootstrap capacitance shown by the capacitor C in the transistor Q2 in FIG. 28 actively enhances this function by synthesizing the capacitance in parallel with the source parasitic capacitance. It is a thing.
  • the boot effect is not exhibited until the potential of the output terminal OUT completely rises, so that there is a drawback that the rise TR of the gate pulse is delayed. The delay of the rising TR becomes a waveform distortion of the gate pulse.
  • stage configuration of FIG. 28 has a problem of inducing stage output noise.
  • the noise is also propagated in a chain to the subsequent stage, which may cause a malfunction of the shift register.
  • transistors Q45 and Q46 are provided, and the output terminal OUT and the gate bus line are connected to the first voltage terminal VOFF each time the clock rises outside the gate pulse output period so as to be kept at the low level.
  • a control circuit including transistors Q31 to Q34 is provided in order to make the transistor Q45 function.
  • the unit stage 400 is provided with two clocks, the first clock terminal CK1 and the second clock terminal CK2, and clocks having phases opposite to each other are input.
  • the transistor Q45 and the transistor Q46 are alternately turned on.
  • the configuration as shown in FIG. 31 requires an additional circuit as described above, which increases the number of circuit elements and the area, which is not preferable.
  • the present invention has been made in view of the above-described conventional problems, and an object of the present invention is to realize a shift register and a display device capable of satisfactorily suppressing noise at each stage output without increasing the circuit scale. There is.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first output transistor that is an output transistor in which a first DC voltage is applied to the drain and the source is a first output terminal that constitutes one output terminal of the above-described stage; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; One end is connected to the other end of the first capacitor, the first DC voltage is applied to the other end, and the period of the active clock pulse is shifted to the stage of the own stage at the conduction cutoff control terminal.
  • the first DC voltage is applied to the drain of the first output transistor, and the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the gate bus line can be driven by a DC power supply by applying a DC voltage to the drain of the first output transistor, and the gate bus line can be driven by inputting a clock signal to the drain of the first output transistor.
  • the load of the external level shifter for generating the control signal of the shift register can be greatly reduced.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first output transistor that is an output transistor in which a first DC voltage is applied to the drain and the source is a first output terminal that constitutes one output terminal of the above-described stage; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; One end is connected to the other end of the first capacitor, the first DC voltage is applied to the other end, and the period of the active clock pulse is shifted to the stage of the own stage at the conduction cutoff control terminal.
  • a first switching element to which a first clock signal corresponding to each stage that does not overlap a pulse period is input; One end is connected to the other end of the first capacitor, a fourth DC voltage lower than the first DC voltage is applied to the other end, and the conduction cut-off control terminal is connected to the stage of the own stage.
  • a continuous stage group having a terminal and a fourth switching element to which a first conduction cut-off control signal corresponding to each stage that does not overlap with the first clock signal does not overlap with the first clock signal; It is characterized by being.
  • the first DC voltage is applied to the drain of the first output transistor, and the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the gate bus line can be driven by a DC power supply by applying a DC voltage to the drain of the first output transistor, and the gate bus line can be driven by inputting a clock signal to the drain of the first output transistor.
  • the load of the external level shifter for generating the control signal of the shift register can be greatly reduced.
  • the fourth DC voltage supplied independently of the second DC voltage is applied to the other end of the second switching element and the other end of the third switching element, the fourth DC voltage
  • the fourth DC voltage By adjusting the above, it is possible to change the amplitude of the control signal for performing the set / reset of the shift register at the previous stage or the subsequent stage, and to reduce the leakage of the input gate and the first output transistor OFF. Further, by setting the value of the fourth voltage so that a change in the threshold voltage of the transistor is unlikely to occur, there is an effect that it is possible to suppress a change in performance over time.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first clock signal corresponding to each stage in which the period of the active clock pulse does not overlap with the period of the shift pulse to the stage in its own stage is applied to the drain, and one output of the stage in which the source is in its own stage A first output transistor which is an output transistor serving as a first output terminal constituting the terminal; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; A first switching element, one end of which is connected to the other end of the first capacitor, a first DC voltage is applied
  • a second switching element to which a shift pulse is input One end is connected to one end of the first capacitor, the second DC voltage is applied to the other end, and the phase is delayed from the shift pulse output by the stage of its own stage at the conduction cutoff control terminal.
  • the first clock signal is input to the drain of the first output transistor, and the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the first clock signal is at the low level, fluctuation due to noise or coupling at one end of the first capacitor does not appear at the first output terminal with respect to the low level output at the first output terminal. .
  • the potential at the first output terminal is prevented from rising due to signal fluctuation or leakage when the output at the first output terminal is at a low level, and thus charge leakage from the pixel electrode or malfunction of the shift register occurs. There is an effect that can be prevented.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first clock signal corresponding to each stage in which the period of the active clock pulse does not overlap with the period of the shift pulse to the stage in its own stage is applied to the drain, and one output of the stage in which the source is in its own stage A first output transistor which is an output transistor serving as a first output terminal constituting the terminal; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; A first switching element, one end of which is connected to the other end of the first capacitor, a first DC voltage is applied
  • a continuous stage group having a terminal and a fourth switching element to which a first conduction cut-off control signal corresponding to each stage that does not overlap with the first clock signal does not overlap with the first clock signal; It is characterized by being.
  • the first clock signal is input to the drain of the first output transistor, and the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the first clock signal is at the low level, fluctuation due to noise or coupling at one end of the first capacitor does not appear at the first output terminal with respect to the low level output at the first output terminal. .
  • the potential at the first output terminal is prevented from rising due to signal fluctuation or leakage when the output at the first output terminal is at a low level, and thus charge leakage from the pixel electrode or malfunction of the shift register occurs. There is an effect that can be prevented.
  • the fourth DC voltage supplied independently of the second DC voltage is applied to the other end of the second switching element and the other end of the third switching element, the fourth DC voltage
  • the fourth DC voltage By adjusting the above, it is possible to change the amplitude of the control signal for setting / resetting the preceding or succeeding shift register, and to reduce the OFF leak of the input gate and the first output transistor. Further, by setting the value of the fourth voltage so that a change in the threshold voltage of the transistor is unlikely to occur, there is an effect that it is possible to suppress a change in performance over time.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first clock signal corresponding to each stage in which the period of the active clock pulse does not overlap with the period of the shift pulse to the stage in its own stage is applied to the drain, and one output of the stage in which the source is in its own stage A first output transistor which is an output transistor serving as a first output terminal constituting the terminal; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; A first switching element, one end of which is connected to the other end of the first capacitor, a first DC voltage is applied
  • a second switching element to which a shift pulse is input One end is connected to one end of the first capacitor, the second DC voltage is applied to the other end, and the phase is delayed from the shift pulse output by the stage of its own stage at the conduction cutoff control terminal.
  • the circuit area can be reduced.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first clock signal corresponding to each stage in which the period of the active clock pulse does not overlap with the period of the shift pulse to the stage in its own stage is applied to the drain, and one output of the stage in which the source is in its own stage A first output transistor which is an output transistor serving as a first output terminal constituting the terminal; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; A first switching element, one end of which is connected to the other end of the first capacitor, a first DC voltage is applied
  • a second switching element to which a shift pulse is input One end is connected to one end of the first capacitor, the fourth DC voltage is applied to the other end, and the phase is delayed from the shift pulse output by the stage of its own stage at the conduction cutoff control terminal.
  • the circuit area can be reduced.
  • the display device of the present invention provides The shift register is provided.
  • the display device of the present invention provides The shift register is provided.
  • a shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first output transistor having a first DC voltage applied to the drain and a source serving as a first output terminal constituting one output terminal of the stage; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; One end is connected to the other end of the first capacitor, the first DC voltage is applied to the other end, and the period of the active clock pulse is shifted to the stage of the own stage at the conduction cutoff control terminal.
  • a third switching element to which a pulse signal output from one output terminal of the first predetermined other stage included in any of the cascade connection circuits is input; One end is connected to the first output terminal, the second DC voltage is applied to the other end, and the active control period is not overlapped with the first clock signal for the conduction cutoff control terminal.
  • a continuous stage group including a fourth switching element to which the first conduction cutoff control signal is input.
  • FIG. 1 illustrates an embodiment of the present invention, and is a circuit diagram illustrating a configuration of a stage included in a shift register of a first example. It is a block diagram which shows the structure of the shift register of a 1st Example. It is a wave form diagram which shows operation
  • FIG. 11, showing an embodiment of the present invention is a block diagram illustrating a configuration of a shift register of a second example. It is a wave form diagram which shows operation
  • FIG. 9, showing an embodiment of the present invention, is a block diagram illustrating a configuration of a shift register of a third example.
  • FIG. 11 is a circuit diagram illustrating a configuration of a stage included in the shift register of the fourth example, according to the embodiment of the present invention.
  • FIG. 9 illustrates an embodiment of the present invention, and is a diagram illustrating a configuration of a stage included in the shift register of the fifth example, and (a) illustrates a configuration of the stage included in the shift register of the fifth example.
  • FIG. 4B is a circuit diagram showing a configuration of a modification of the stage of FIG. FIG.
  • FIG. 17 is a circuit diagram illustrating a configuration of a stage included in the shift register of the sixth example, illustrating the embodiment of the present invention.
  • FIG. 17 is a circuit diagram illustrating a configuration of a stage included in the shift register of the seventh example, illustrating the embodiment of the present invention.
  • FIG. 17 is a circuit diagram illustrating a configuration of a stage included in the shift register of the eighth example, illustrating the embodiment of the present invention.
  • FIG. 17 is a circuit diagram illustrating a configuration of a stage included in the shift register of the ninth example, illustrating the embodiment of the present invention.
  • FIG. 24, showing an embodiment of the present invention is a circuit diagram illustrating a configuration of a stage included in a shift register of a tenth example.
  • FIG. 17 is a circuit diagram illustrating a configuration of a stage included in the shift register of the eleventh example according to the embodiment of the present invention.
  • FIG. 24, showing an embodiment of the present invention, is a circuit diagram illustrating a configuration of a stage included in a shift register of a twelfth example.
  • FIG. 17 is a circuit diagram illustrating a configuration of a stage included in the shift register of the thirteenth example, according to the embodiment of the present invention.
  • FIG. 24, showing an embodiment of the present invention is a circuit diagram illustrating a configuration of a stage included in a shift register of a fourteenth example.
  • FIG. 32, which shows the embodiment of the present invention, is a waveform diagram for explaining a fifteenth example. 1, showing an embodiment of the present invention, is a block diagram illustrating a configuration of a display device.
  • FIG. It is a figure explaining the form of a capacity
  • FIG. It is a block diagram which shows a prior art and shows the structure of a shift register. It is a circuit diagram which shows a prior art and shows the 1st structural example of the stage with which a shift register is provided. It is a 1st waveform diagram explaining the subject with which the conventional shift register is provided.
  • FIG. 24 is a circuit diagram illustrating a configuration of a stage included in the shift register of the seventeenth example, according to the embodiment of the present invention.
  • FIG. 24 is a circuit diagram illustrating a configuration of a stage included in the shift register of the seventeenth example, according to the embodiment of the present invention.
  • FIG. 32 is a circuit diagram illustrating a configuration of a stage included in the shift register of the eighteenth example according to the embodiment of the present invention.
  • FIG. 24, showing an embodiment of the present invention is a circuit diagram illustrating a first configuration of a stage included in a shift register of a nineteenth example.
  • FIG. 24 is a circuit diagram illustrating a second configuration of the stage included in the shift register of the nineteenth example, according to the embodiment of the present invention.
  • FIG. 29 is a circuit diagram illustrating a third configuration of the stage included in the shift register of the nineteenth example, according to the embodiment of the present invention.
  • FIG. 24 is a circuit diagram showing a fourth configuration of the stage included in the shift register of the nineteenth example, showing the embodiment of the present invention.
  • FIGS. 1 to 26 and FIGS. 32 to 40 Embodiments of the present invention will be described with reference to FIGS. 1 to 26 and FIGS. 32 to 40 as follows.
  • FIG. 25 shows a configuration of the liquid crystal display device 11 which is a display device according to the present embodiment.
  • the liquid crystal display device 11 includes a display panel 12, a flexible printed circuit board 13, and a control board 14.
  • the display panel 12 uses amorphous silicon on a glass substrate, a display region 12a, a plurality of gate bus lines (scanning signal lines) GL, a plurality of source bus lines (data signal lines) SL, and a gate driver (scanning).
  • This is an active matrix display panel in which a signal line driver circuit) 15 is built.
  • the display panel 12 can also be manufactured using polycrystalline silicon, CG silicon, microcrystalline silicon, or the like.
  • the display area 12a is an area in which a plurality of picture elements PIX ... are arranged in a matrix.
  • the picture element PIX includes a TFT 21, which is a picture element selection element, a liquid crystal capacitor CL, and an auxiliary capacitor Cs.
  • the gate of the TFT 21 is connected to the gate bus line GL, and the source of the TFT 21 is connected to the source bus line SL.
  • the liquid crystal capacitor CL and the auxiliary capacitor Cs are connected to the drain of the TFT 21.
  • the plurality of gate bus lines GL are composed of gate bus lines GL1, GL2, GL3,... GLn, and are connected to the output of the gate driver (scanning signal line drive circuit) 15, respectively.
  • the plurality of source bus lines SL are made up of source bus lines SL1, SL2, SL3,..., SLm, and are connected to the output of a source driver 16, which will be described later. Further, although not shown, auxiliary capacitance lines for applying an auxiliary capacitance voltage to the auxiliary capacitances Cs of the picture elements PIX... Are formed.
  • the gate driver 15 is provided on the display panel 12 in an area adjacent to the display area 12a on one side in the extending direction of the gate bus lines GL, and sequentially applies gate pulses to the gate bus lines GL. (Scanning pulse) is supplied. Further, another gate driver is provided in a region adjacent to the display region 12a on the other side of the display region 12a in the direction in which the gate bus lines GL extend, and is different from the gate driver 15. The GL may be scanned. Further, the gate driver provided in the region adjacent to one side in the extending direction of the gate bus line GL with respect to the display region 12a and the gate driver provided in the region adjacent to the other side are the same gate bus line. The GL may be scanned. These gate drivers are built monolithically with the display area 12a on the display panel 12, and gate drivers called gate monolithic, gate driverless, panel built-in gate drivers, gate-in panels, etc. are all in the gate driver 15. May be included.
  • the flexible printed circuit board 13 includes a source driver 16.
  • the source driver 16 supplies a data signal to each of the source bus lines SL.
  • the source driver 16 may be monolithically formed on the display panel 12 with the display area 12a.
  • the control board 14 is connected to the flexible printed board 13 and supplies necessary signals and power to the gate driver 15 and the source driver 16. Signals and power supplied to the gate driver 15 output from the control board 14 are supplied from the display panel 12 to the gate driver 15 via the flexible printed board 13.
  • FIG. 2 shows the configuration of the shift register 1 of this embodiment.
  • the shift register 1 has a configuration in which a plurality of stages Xi (i is a natural number) are cascade-connected by the number of gate bus lines GL.
  • a cascade connection circuit one circuit in which the stages Xi are connected in cascade.
  • Each stage Xi includes terminals V1, V2, S1, S2, S3, S4, and OUT.
  • the terminal V1 has a power supply voltage (first DC voltage) VDD at a high level (ie, a gate pulse level) of the gate drive voltage, and a terminal V2.
  • first DC voltage first DC voltage
  • second DC voltage second DC voltage
  • the terminal S1 is the output signal OUTi-1 from the terminal OUT of the preceding stage Xi-1
  • the terminal S2 is the clock signal (first signal).
  • Clock signal) CLK1 the output signal OUTi + 1 from the terminal OUT of the next stage X to the terminal S3
  • the output signal OUTi of its own stage Xi is output from the terminal (first output terminal) OUT.
  • the gate start pulse SP is input to the terminal S1 of the stage X1 instead of the output signal OUTi-1.
  • an output pulse signal from another stage whose phase is delayed by one pulse from the output signal OUTi-1 of its own stage Xi in the cascade connection circuit at the terminal S3 of the final stage Xn for i For example, there is an output pulse signal output from one output terminal of a dummy stage that has the same configuration as the stage Xi and does not output to the gate bus line GL, following the final stage Xn. .
  • the output pulse of this dummy stage is called a gate end pulse EP.
  • the gate end pulse EP has the same waveform and the same phase as the pulse of the output signal OUTi.
  • an output pulse signal delayed in phase (here, delayed in phase by one pulse) from the output signal OUTi of the stage Xi of the stage Xi is supplied to the terminal S3 of each stage Xi. It may be input from one output terminal of another stage.
  • the first stage X1 may include a dummy stage having the same configuration as the preceding stage, and a gate start pulse may be input to the dummy stage, and an output pulse signal of the dummy stage may be input to the stage X1.
  • These dummy stages are provided to operate the first stage X1 and the final stage Xn under the same conditions as the other stages Xi. These are the same in other embodiments.
  • a power supply voltage (first DC voltage) VDD at a high level (that is, a gate pulse level) of the gate drive voltage is applied to the terminal V1 and a terminal V2.
  • the terminal S1 is the output signal OUTi-1 from the terminal OUT of the preceding stage Xi-1
  • the terminal S2 is the clock signal (first signal).
  • Clock signal) CLK2 the output signal OUTi + 1 from the terminal OUT of the next stage Xi + 1 is input to the terminal S3, and the clock signal (first conduction cutoff control signal, second clock signal) CLK1 is input to the terminal S4, respectively.
  • the output signal OUTi of the stage Xi of its own stage is output from the terminal OUT.
  • the second DC voltage is lower than the first DC voltage.
  • FIG. 1 shows the configuration of each stage Xi.
  • Stage Xi includes transistors M1, M2, M3, M4, M5, and M6 and a capacitor C1.
  • the transistors M1 to M6 are all N-channel TFTs here, but P-channel TFTs can also be used, and the same applies to all transistors in all the embodiments. Note that the gate of each switching element described below is a control terminal for turning off conduction in the switching element.
  • the gate of the transistor (input gate, fifth switching element, first transistor) M1 is connected to the terminal S1, the drain is connected to the terminal V1, and the source is connected to the node N1 connected to the gate of the transistor M5.
  • One end of the capacitor (first capacitor) C1 is connected to the node N1.
  • the gate of the transistor (first switching element) M2 is connected to the terminal S2, the drain is connected to the terminal V1, and the source is connected to the other end of the capacitor C1 opposite to the node N1 side.
  • the other end of the capacitor C1 is connected to the node N2.
  • the gate of the transistor (second switching element) M3 is connected to the terminal S1, the drain is connected to the node N2, and the source is connected to the terminal V2.
  • the gate of the transistor (third switching element) M4 is connected to the terminal S3, the drain is connected to the node N1, and the source is connected to the terminal V2.
  • the drain of the transistor (first output transistor) M5 is connected to the terminal V1, and the source is connected to the terminal OUT. That is, a DC voltage called the power supply voltage VDD is applied to the drain of the transistor M5, and the source of the transistor M5 functions as a first output terminal that is one output terminal of the stage Xi.
  • the gate of the transistor (fourth switching element) M6 is connected to the terminal S4, the drain is connected to the terminal OUT, and the source is connected to the terminal V2.
  • the active periods of the clock signal CLK1 and the clock signal CLK2 do not overlap each other.
  • the clock signal CLK1 and the clock signal CLK2 are in an opposite phase relationship.
  • the high level of the clock signals CLK1 and CLK2 is VDD and the low level is VSS, but the high level of the clock signals CLK1 and CLK2 may be VDD or higher and the low level may be VSS or lower.
  • the pulse widths of the clock signals CLK1 and CLK2 and the gate start pulse SP are values corresponding to one horizontal period (1H).
  • the gate start pulse SP is out of phase with the clock signal CK1 by a half period.
  • the clock signal input to the terminal S2 is the first clock signal, the clock signal CLK1 for the odd-numbered stage Xi, and the clock signal CLK2 for the even-numbered stage Xi, respectively.
  • the clock signal input to the terminal S4 is the first conduction cutoff control signal and the second clock signal, the clock signal CLK2 for the odd-numbered stage Xi, and the clock for the even-numbered stage Xi.
  • Signal CLK1 corresponds to a first conduction cutoff control signal and a second clock signal, respectively. Then, the shift pulse input to the stage Xi and the first clock signal do not overlap with each other in the period of the active clock pulse (here, the High level period).
  • a potential difference of (power supply voltage VDD) ⁇ (threshold voltage Vth of transistor M1) ⁇ (power supply voltage VSS) is generated at both ends of the capacitor C1, and the potential of the node N1 rises, and this state is maintained.
  • the magnitude of the power supply voltage VDD is such that the voltage (the voltage at the terminal OUT) input to the terminal S1 of the next stage X2 determined by the potential of the node N1 at this time is the threshold value of the transistor M1 of the next stage X2.
  • the voltage is set to be equal to or lower than Vth.
  • the transistor M1 functions as an input gate that receives a shift pulse to the stage Xi of its own stage and passes a voltage applied to the node N1 during the pulse period of the shift pulse.
  • the shift pulse is a gate start pulse SP for the stage X1 and a gate pulse included in the output signal OUTi-1 of the preceding stage Xi-1 for the other stages Xi.
  • the gate of the transistor M5 has a sufficiently high potential V (N1) with respect to VDD, and the transistor M5 is turned on so as to have a sufficiently small channel resistance, so that the power supply voltage VDD is supplied from the terminal V1 to the transistor M5.
  • the output signal OUT1 from the terminal OUT is a gate pulse with an amplitude of VDD-VSS.
  • the gate pulse is inputted to the terminal S1 of the next stage X2, and charges the capacitor C1 of the stage X2. Then, the potential of the node N1 of the stage X2 is pushed up when the high level of the clock signal CLK2 that is the first clock signal is input to the terminal S2, and the transistor M5 is turned on. As a result, the power supply voltage VDD is output as the output signal OUT2 from the terminal OUT via the transistor M5, and becomes a gate pulse.
  • the gate pulse of the output signal OUT2 is input to the terminal S3 of the stage X1, the transistor M4 is turned on, and the potential of the node N1 is lowered to the power supply voltage VSS. As a result, the gate pulse as the output signal OUT1 falls, and the stage X1 is reset.
  • the gate pulse of the output signal OUTi is sequentially output to each gate bus line GL.
  • each stage Xi every time the first conduction cutoff control signal or the second clock signal input to the terminal S4 becomes the high level, the transistor M6 is turned on and the output terminal OUT becomes the low level. Is done.
  • the first DC voltage called the power supply voltage VDD is applied to the drain (one end opposite to the gate drive output side) of the transistor M5 that outputs the gate pulse, and the transistor
  • the transistor By performing the switched capacitor operation using M2 and M3 and the capacitor C1, the output voltage fluctuation generated when the clock signal is input to the drain of the transistor M5 and the liquid crystal picture generated due to the output voltage fluctuation Charge leakage from the elementary electrode can be prevented.
  • the gate bus line can be driven by a DC power source by applying a DC voltage to the drain of the transistor M5, and the gate bus line is driven by the clock signal by inputting a clock signal to the drain of the transistor M5.
  • the load of the external level shifter that generates the control signal of the shift register can be greatly reduced.
  • the amplitude of the clock signal can be set to an arbitrary value by setting the Low level to VSS or lower and the High level to VDD or higher.
  • the High level is set to a value higher than VDD, the ON current of a transistor whose high level is input to the gate increases, and the operation speed can be improved.
  • the Low level is set to a value lower than VSS, the OFF current of the transistor that is input to the gate of the Low level is reduced, and it is possible to prevent the malfunction of the level shifter due to the leakage current.
  • the gate potential can be made lower than the source potential and the drain potential, so that the threshold voltage Vth generated due to the DC voltage component applied to the gate is elapsed.
  • the change can be kept small, and the performance degradation of the shift register can be suppressed.
  • the first conduction cutoff control signal may be an output of a subsequent stage (second predetermined other stage).
  • the terminal OUT can be set to the low level every time the second clock signal is in an active period. is there.
  • clock feedthrough occurs from the gate of the transistor M6, which is the fourth switching element, via the drain parasitic capacitance, and noise is easily applied to the terminal OUT.
  • the transistor M6 in which the clock signal is input to the gate the period during which the high level is input to the gate becomes long, and thus the deterioration speed of the threshold voltage Vth increases. As the threshold voltage Vth increases, the voltage for turning on the transistor M6 increases, and feedthrough becomes more prominent. Therefore, the noise performance of the transistor M6 gradually deteriorates.
  • the cascade circuit in the example of FIG. 2 is the continuous stage group itself.
  • the cascade connection circuit may partially include a continuous stage group, such as a serial stage group and the aforementioned dummy stage.
  • the dummy stage has the same configuration as that described in each claim for the stage Xi, it is possible to regard the dummy stage connected in cascade to the stage Xi as a continuous stage group.
  • a plurality of continuous stage groups may be provided in one cascade connection circuit with one or more other stages different from the stage Xi sandwiched between them.
  • each of these successive stage groups can be suitably used when driving a plurality of gate bus lines GL... Constituting a corresponding unit. The same applies to the other embodiments.
  • a fifth DC voltage different from the first DC voltage may be applied to the gate of the transistor M1. Thereby, the charging potential of the node N1 is not restricted by the power supply voltage VDD.
  • FIG. 4 shows the configuration of the shift register 2 of this embodiment.
  • the shift register 2 includes a shift register 2a and a shift register 2b.
  • the shift register 2a has stages Xi (X1, X3, X5,..., X (2j-1),..., J: a natural number) for driving odd-numbered gate bus lines GL of all the gate bus lines GL.
  • One cascade connection circuit formed by cascade connection is provided.
  • the cascade connection circuit of the shift register 2a is also one continuous stage group (first continuous stage group).
  • stages Xi (X2, X4, X6,..., X (2k),..., K is a natural number) for driving even-numbered gate bus lines GL.
  • One cascade connection circuit is provided.
  • the cascade connection circuit of the shift register 2b is also one continuous stage group (second continuous stage group).
  • the shift register 2a and the shift register 2b have the same configuration as that obtained by replacing Xi with Xj and Xk in the shift register 1 of FIG.
  • the gate start pulse SP1 of FIG. 5 is applied to the terminal S1 of the stage X1
  • the clock signal CLK1 of FIG. 5 is applied to the terminal S2 of each odd-numbered stage Xj for j
  • the odd-numbered stages for j. 5 to the terminal S4 of Xj
  • the clock signal CLK2 of FIG. 5 to the terminal S2 of each even-numbered stage Xj for j
  • the clock signal CLK2 of FIG. 5 to the terminal S4 of each even-numbered stage Xj for j.
  • CLK2 is input.
  • the clock signal CLK3 of FIG. 5 is applied to the terminal S2 of each odd-numbered stage Xk for k, and the odd-numbered stages for k.
  • the clock signal CLK4 of FIG. 5 is applied to the terminal S4 of Xk
  • the clock signal CLK4 of FIG. 5 is applied to the terminal S2 of each even-numbered stage Xk with respect to k
  • the clock signal CLK of FIG. The difference from the shift register 1 is that CLK3 is input.
  • each cascade connection circuit of the shift register 2a and the shift register 2b may be provided with the aforementioned dummy stage.
  • the shift register 2 includes a plurality of cascade connection circuits in total.
  • the shift register 2a may be provided with a plurality of continuous stage groups, and the first continuous stage group may be included in a number equal to or less than the number of continuous stage groups.
  • the shift register 2b may be provided with a plurality of continuous stage groups, of which the second continuous stage group may be included in a number equal to or less than the number of continuous stage groups.
  • the first continuous stage group and the second continuous stage group have the connection relationship of FIG. 4 and the stage configuration of FIG. 1, respectively, but the stage of FIG. 4 has the stage configuration of FIG. 1 and other drawings. What is different from the configuration is a continuous stage group other than the first continuous stage group or a continuous stage group other than the second continuous stage group. The same applies to other embodiments.
  • any stage (not limited to Xj and Xk, any stage) in the cascade connection circuit of the shift registers 2a and 2b is used as a pulse signal input to the terminal S3 of each stage Xj of the shift register 2a.
  • Output pulse signal may be used, or any stage (not limited to Xj and Xk) in the cascade connection circuit of the shift registers 2a and 2b as a pulse signal input to the terminal S3 of each stage Xk of the shift register 2b.
  • An output pulse signal of any stage may be used. The same applies to other embodiments.
  • the high level of the clock signals CLK1, CLK2, CLK3, and CLK4 is VDD, and the low level is VSS, but the high level of the clock signals CLK1, CLK2, CLK3, and CLK4 is VDD or higher, and the low level is VSS or lower. If it is.
  • the pulse widths of the clock signals CLK1, CLK2, CLK3, CLK4 and the gate start pulses SP1, SP2 are values corresponding to two horizontal periods (2H).
  • the clock signal CLK1 and the clock signal CLK2 are in an opposite phase relationship, and the clock signal CLK3 and the clock signal CLK4 are in an opposite phase relationship.
  • the clock signal CLK3 is delayed in phase by a quarter of the clock signal CLK1
  • the clock signal CLK4 is delayed in phase by a quarter of the clock signal CLK2.
  • the gate start pulse SP1 is out of phase with the clock signal CLK1 by a half cycle
  • the gate start pulse SP2 is delayed in phase by a quarter cycle of the clock signals CLK1 to CLK4 from the gate start pulse SP1. Yes.
  • the clock signal input to the terminal S2 is the first clock signal, the clock signal CLK1 for the odd-numbered stage Xj for j, the clock signal CLK2 for the even-numbered stage Xj for j, and the odd-number for k.
  • the clock signal CLK3 corresponds to the first stage Xk
  • the clock signal CLK4 corresponds to the first clock signal for the even-numbered stage Xk for k.
  • the clock signal input to the terminal S4 is the first conduction cutoff control signal and the second clock signal, the clock signal CLK2 for the odd-numbered stage Xj for j, and the even-numbered stage Xj for j.
  • the shift pulse input to the stage Xi and the first clock signal do not overlap with each other in the period of the active clock pulse (here, the High level period).
  • each of the shift registers 2a and 2b operates in the same manner as the shift register 1 of FIG.
  • the gate bus line driven by the shift register 2a is represented by GLj
  • the gate bus line driven by the shift register 2b is represented by GLk
  • the output signal OUTj of the stage Xj for driving the gate bus line GLj and the output signal OUTk of the stage Xk for driving the gate bus line GLk have gate pulses of the clock signals CLK1 ⁇ CLK. Overlaps only for a period of a quarter of CLK4.
  • the picture elements PIX... Connected to each gate bus line GL are transferred to the horizontal period PH immediately before the horizontal period WH in which the gate bus line GL is selected for writing the data signal. Precharging can be performed using the data signal of the previous horizontal period.
  • the liquid crystal picture element when performing source line inversion driving in which the polarity of the data signal in the same data signal line is the same for one frame period, the liquid crystal picture element can be sufficiently charged to the target voltage with a long charging time. Therefore, the charging rate of the liquid crystal picture element is increased, and the display quality can be improved.
  • FIG. 6 shows the configuration of the shift register 3 of this embodiment.
  • the shift register 3 includes a shift register 3a and a shift register 3b.
  • FIG. 7 shows the operation waveform of the shift register of FIG. 4 together with the voltage of the node N2 when a phenomenon not considered in the second embodiment occurs.
  • ⁇ V (N2) (C1 / (C1 + Cm2s + Cm3s)) ⁇ (2 ⁇ VDD ⁇ (VSS + 2 ⁇ Vth) ⁇ VSS) It is.
  • Cm2s is a gate-source capacitance of the transistor M2
  • Cm3s is a gate-source capacitance of the transistor M3.
  • the potential V (N2) of the node N2 becomes VDD ⁇ Vth.
  • the node N1 is in a floating state, and the potential V (N1) of the node N1 is pushed up by capacitive coupling ⁇ V (N1) by the capacitor C1.
  • ⁇ V (N1) (C1 / (C1 + Cm1s + Cm4d + Cm5s + Cm5d)) ⁇ ⁇ V (N2) It becomes.
  • Cm1s is the gate-source capacitance of the transistor M1
  • Cm4d is the gate-drain capacitance of the transistor M4
  • Cm5s is the gate-source capacitance of the transistor M5
  • Cm5d is the gate-drain capacitance of the transistor M5.
  • FIG. 8 shows operation waveforms of the shift register of FIG. If the potential of the node N1 of the stage X1 is reset by the gate pulse output from the terminal OUT2 of the stage X2 that drives the gate bus line GL of the next stage at the time T3, the transistor M2 is in the ON state, so that the node N2 is not floating And no potential drop from the node N1. For this reason, it is possible to prevent the potential of the terminal OUT from being increased due to the potential of the node N1 of the stage X1 being pushed up at an arbitrary time T4 after the output of the gate pulse from the terminal OUT1 is completed.
  • FIG. 9 shows the configuration of the stage Xi provided in the shift register of this embodiment.
  • the stage Xi in FIG. 9 has a configuration in which a transistor (sixth switching element) M91 is added to the stage Xi in FIG.
  • the gate of the transistor M91 is connected to the terminal S5, the drain is connected to the terminal V1, and the source is connected to the node N2.
  • the same signal as that of the terminal S3 is input to the terminal S5.
  • the transistor M4 when the transistor M4 is turned on and the potential of the node N1 is reset, the transistor M91 is also turned on at the same time. Therefore, the potential of the node N2 is kept at a constant value of VDD ⁇ Vth, and the potential drop of the node N2 due to capacitive coupling through the capacitor C1 can be prevented. Accordingly, as in the third embodiment, the potential increase of the terminal OUT caused by the potential V (N1) of the node N1 fluctuating via capacitive coupling is prevented, and the leakage of charge from the liquid crystal pixel electrode and the malfunction of the shift register are suppressed. can do.
  • transistor M91 can also be applied to the stages of other embodiments.
  • FIG. 10A shows the configuration of the stage Xi provided in the shift register of the present embodiment.
  • the stage Xi in FIG. 10A has a configuration in which a transistor (third transistor) M101 is added to the stage Xi in FIG. At this time, the transistor M2 is a second transistor.
  • the gate of the transistor M101 is connected to the terminal S6, and the drain and source thereof are connected to the node N2.
  • a signal having a phase opposite to that of the terminal S2 is input to the terminal S6.
  • the transistor M2 repeats the ON state and the OFF state alternately, the charge of the gate-source capacitance and the gate-drain capacitance of the transistor M2 is charged / discharged. Accordingly, when the node N2 is in a floating state, the potential of the node N2 can be changed by the charge / discharge charge of the gate-source capacitance of the transistor M2. If this fluctuation is capacitively coupled to the node N1 via the capacitor C1 and affects the gate pulse waveform, charge leakage from the liquid crystal pixel electrode and malfunction of the shift register may occur.
  • the transistor M101 having the source and the drain connected to each other at the node N2 is disposed, and a signal having a phase opposite to that of the gate of the transistor M2 is input to the gate of the transistor M101, thereby increasing the gate-source capacitance of the transistor M2.
  • the influence of the charge flowing to the node N2 can be offset by the charge / discharge charge of the gate-source capacitance and the gate-drain capacitance of the transistor M101. Since the charge / discharge of the gate-source capacitance of the transistor M2 is canceled by the charge / discharge of the gate-source capacitance and the gate-drain capacitance of the transistor M101, the channel width of the transistor M101 is divided by two of the channel width of the transistor M2. 1
  • a capacitor (second capacitor) C101 connected between the gate of the transistor M101 and the node N2 may be further provided.
  • the transistor M5 can be surely turned off, and the DC voltage component applied to the gate of the transistor M5 can be made smaller to improve the threshold voltage shift phenomenon. Can be suppressed.
  • the potential increase of the terminal OUT caused by the change in the potential V (N2) of the node N2 due to the charge injection from the transistor M2 is prevented, and charge leakage from the liquid crystal pixel electrode and A malfunction of the shift register can be suppressed.
  • the transistor M101 can also be applied to the stages of other embodiments.
  • the transistor M101 can be used in combination with the stage Xi in FIGS.
  • FIG. 11 shows the configuration of the stage Xi provided in the shift register of this embodiment.
  • the stage Xi in FIG. 11 has a configuration in which a transistor (seventh switching element) M111 is added to the stage Xi in FIG.
  • the gate of the transistor M111 is connected to the terminal S7, the drain is connected to the node N1, and the source is connected to the terminal V2.
  • the potential of the node N2 becomes VDD ⁇ Vth by the pulse and the potential of the node N1 is pushed up, the transistor M111 is turned on and the node N1 is connected to the terminal V2.
  • the transistor M111 can be applied to the stages of other embodiments.
  • the transistor M111 can be used in combination with the stage Xi in FIGS. 9 and 10A and 10B.
  • FIG. 12 shows the configuration of the stage Xi provided in the shift register of this embodiment.
  • the stage Xi in FIG. 12 has a configuration in which a transistor (fifth transistor) M121 is added to the stage Xi in FIG. At this time, the transistor M6 is a fourth transistor.
  • the gate of the transistor M121 is connected to the terminal S8, the drain is connected to the terminal OUT, and the source is connected to the terminal V2.
  • the gate pulse 12 can be applied to any of the shift register 1 in FIG. 2, the shift register 2 in FIG. 4, and the shift register 3 in FIG.
  • the same signal as that of the terminal S3 is input to the terminal S8, and in the shift registers 2 and 3, the output signal OUTi + 2 of Xi + 2 that is two stages after i is input to the terminal S8.
  • the gate pulse first output from the other stage Xi after the completion of the output of the gate pulse from the stage Xi is input to the terminal S8.
  • the threshold voltage Vth gradually increases due to a shift phenomenon as it is used. For this reason, the transistor M6 is not easily turned on, and it is difficult to quickly lower the terminal OUT to the Low level. Then, the falling waveform of the gate pulse is reduced, and the data signal to be written to the picture element connected to the next-stage gate bus line GL is written to the picture element connected to the next-stage gate bus line GL. Deterioration may occur. However, by disposing the transistor M121 as described above, the potential of the terminal OUT can be reset by the transistor M6 and the transistor M121, so that the fall of the waveform of the gate pulse can be made steep.
  • the falling of the waveform of the gate pulse can be made steep, so that the charging time becomes unnecessarily long and the picture element connected to the next-stage gate bus line GL It is possible to improve the display quality by preventing the data signal to be written from being written to the picture element connected to the gate bus line GL of the own stage.
  • the transistor M121 can be applied to a stage of another embodiment.
  • the transistor M121 can be used in combination with the stages Xi in FIGS. 9 and 10 and the stage Xi in FIG.
  • FIG. 13 shows the configuration of the stage Xi provided in the shift register of this embodiment.
  • the stage Xi in FIG. 13 has a configuration in which the transistor M1 in the stage Xi in FIG. 1 is replaced with a transistor (input gate, fifth switching element, first transistor) M11.
  • the gate and drain of the transistor M11 are connected to each other and to the terminal S1, and the source is connected to the node N1.
  • the threshold voltage Vth gradually decreases due to the shift phenomenon, and the leakage current of the first transistor is reduced. Increase.
  • the potential V (N1) of the node N1 rises, leading to charge leakage from the liquid crystal picture element electrode and malfunction of the shift register.
  • the drain of the transistor M11 is connected to the terminal S1, it is possible to prevent the gate potential from becoming lower than the drain potential, and thus it is possible to suppress a decrease in the threshold voltage Vth of the transistor M11.
  • the leakage current of the first transistor can be suppressed, and the charge leakage from the liquid crystal picture element electrode and the malfunction of the shift register can be prevented.
  • the transistor M11 can be applied to a stage of another embodiment.
  • the transistor M11 can be used in combination with the stage Xi in FIGS. 9 and 10A, 10B, 11 and 12.
  • FIG. 14 shows the configuration of the stage Xi provided in the shift register of this embodiment.
  • FIG. 14 is a configuration in which a transistor (second output transistor) M141 and a transistor (eighth switching element) M142 are added to the stage Xi of FIG.
  • the gate of the transistor M141 is connected to the node N1, the drain is connected to the terminal V1, and the source is connected to the terminal (second output terminal) Z. That is, a DC voltage called the power supply voltage VDD is applied to the drain of the transistor M141, and the source of the transistor M141 functions as a second output terminal that is one output terminal of the stage Xi, which is different from the first output terminal. In this way, a continuous stage group having other output terminals in addition to the first output terminal is defined as a multiple output continuous stage group.
  • the gate of the transistor M142 is connected to the terminal S4, the drain is connected to the terminal Z, and the source is connected to the terminal V2.
  • the signal input to the gate of the transistor M142 is a second conduction cutoff control signal.
  • the second conduction cutoff control signal is a signal whose active period does not overlap with the first clock signal, and in this embodiment, is the same signal as the first conduction cutoff control signal input to the gate of the transistor M6.
  • the second conduction cutoff control signal is a clock signal having a phase opposite to that of the first clock signal, that is, the same clock signal as the second clock signal.
  • the second conduction cutoff control signal may not be the same signal as the first conduction cutoff control signal.
  • the terminal OUT is connected to the gate bus line GL driven by the stage Xi of its own stage, and the transistor M5 outputs a gate pulse.
  • the transistor M6 resets the terminal OUT to the low level.
  • the terminal Z is connected to the terminal S1 of another stage Xi to which the shift pulse output from the stage Xi of its own stage is input, and the transistor M141 outputs the shift pulse.
  • the transistor M142 resets the terminal Z to the low level.
  • the stage for outputting the gate pulse and the stage for outputting the set / reset control signal such as the set signal (shift pulse) and reset signal of the other stage Xi are separated from each other. Further, any number of stages separated in the same manner may be provided.
  • the control signal if the stage for outputting the set signal (shift pulse) of another stage and the stage for outputting the reset signal of another stage are further separated, the output of the set signal and the output of the reset signal are performed. Can be avoided, and can be operated more stably.
  • a third output transistor similar to the transistor M141 and a ninth switching element similar to the transistor M142 are added to the configuration of FIG.
  • the source of the third output transistor is a third output terminal that is one output terminal of the stage Xi, which is different from the first output terminal and the second output terminal. For example, from the second output terminal (terminal Z) A set signal (shift pulse) is output and a reset signal is output from the third output terminal.
  • the signal input to the conduction cutoff control terminal of the ninth switching element is the third conduction cutoff control signal.
  • the third conduction cutoff control signal is a signal whose active period does not overlap with the first clock signal.
  • the third conduction cutoff control signal is the same signal as the first conduction cutoff control signal input to the gate of the transistor M6.
  • the second conduction cutoff control signal is a clock signal having a phase opposite to that of the first clock signal, that is, the same clock signal as the second clock signal.
  • the third conduction cutoff control signal may not be the same signal as each of the first conduction cutoff control signal and the second conduction cutoff control signal.
  • transistors M141 and M142 can be applied to the stages of other embodiments.
  • the transistors M141 and M142 can be used in combination with the stage Xi in FIGS. 9 and 10 (a) and (b), FIG. 11, FIG. 12, and FIG. Further, any number of stages separated in the same manner may be provided.
  • FIG. 15 shows the configuration of the stage Xi provided in the shift register of this embodiment.
  • the transistor M4 is a third switching element.
  • the gate of the transistor M141 is connected to the node N1, the drain is connected to the terminal S2, and the source is connected to the terminal (second output terminal) Z. That is, the first clock signal is input to the drain of the transistor M141, and the source of the transistor M141 functions as a second output terminal that is one output terminal of the stage Xi, which is different from the first output terminal. In this way, a continuous stage group having other output terminals in addition to the first output terminal is defined as a multiple output continuous stage group.
  • the gate of the transistor M142 is connected to the terminal S4, the drain is connected to the terminal Z, and the source is connected to the terminal V2.
  • the signal input to the gate of the transistor M142 is a second conduction cutoff control signal.
  • the second conduction cutoff control signal is a signal whose active period does not overlap with the first clock signal, and in this embodiment, is the same signal as the first conduction cutoff control signal input to the gate of the transistor M6.
  • the second conduction cutoff control signal is a clock signal having a phase opposite to that of the first clock signal, that is, the same clock signal as the second clock signal.
  • the second conduction cutoff control signal may not be the same signal as the first conduction cutoff control signal.
  • the terminal Z is connected to the terminal S1 of the other stage Xi to which the shift pulse output from the stage Xi is input, and the transistor M141 outputs the shift pulse.
  • the transistor M142 resets the terminal Z to the low level.
  • the stage for outputting the gate pulse and the stage for outputting the set / reset control signal such as the set signal (shift pulse) and reset signal of the other stage Xi are separated from each other. Further, any number of stages separated in the same manner may be provided.
  • the control signal if the stage for outputting the set signal (shift pulse) of another stage and the stage for outputting the reset signal of another stage are further separated, the output of the set signal and the output of the reset signal are performed. Can be avoided, and can be operated more stably.
  • a third output transistor similar to the transistor M141 and a ninth switching element similar to the transistor M142 are added to the configuration of FIG.
  • the source of the third output transistor is a third output terminal that is one output terminal of the stage Xi, which is different from the first output terminal and the second output terminal. For example, from the second output terminal (terminal Z) A set signal (shift pulse) is output and a reset signal is output from the third output terminal.
  • the signal input to the conduction cutoff control terminal of the ninth switching element is the third conduction cutoff control signal.
  • the third conduction cutoff control signal is a signal whose active period does not overlap with the first clock signal.
  • the third conduction cutoff control signal is the same signal as the first conduction cutoff control signal input to the gate of the transistor M6.
  • the second conduction cutoff control signal is a clock signal having a phase opposite to that of the first clock signal, that is, the same clock signal as the second clock signal.
  • the third conduction cutoff control signal may not be the same signal as each of the first conduction cutoff control signal and the second conduction cutoff control signal.
  • the drain of the transistor M141 that outputs a control signal for setting and resetting the stage Xi on the front stage side and the rear stage side is connected to the terminal S2, so that the potential V (N1) of the node N1 is capacitively coupled. It is possible to prevent the potential of the terminal Z from being raised due to the thrust.
  • Stage Xi in FIG. 15 includes shift register 1 in FIG. 2, shift register 2 in FIG. 4, shift register 3 in FIG. 6, shift register 4 in FIG. 16 to be described next, and shift register 5 in FIG. Any of them can be applied.
  • FIG. 16 shows the configuration of the shift register 4.
  • the shift register 4 has a configuration in which a plurality of stages Xi (i is a natural number) are cascaded by the number of gate bus lines GL.
  • the terminal V1 has a power supply voltage (first DC voltage) VDD at a high level (ie, a gate pulse level) of the gate drive voltage, and a terminal V2.
  • first DC voltage first DC voltage
  • second DC voltage second DC voltage
  • the terminal S1 is an output signal from the terminal Z of the preceding stage Xi-1
  • the terminal S2 is a clock signal (first clock signal).
  • CLK1 terminal S3 has an output signal from the terminal Z of the next stage Xi + 1
  • terminal S4 has a clock signal (first conduction cutoff control signal, second conduction cutoff control signal, second clock signal) CLK2.
  • the gate start pulse SP is input to the terminal S1 of the stage X1 instead of the output signal OUTi-1.
  • a power supply voltage (first DC voltage) VDD at a high level (that is, a gate pulse level) of the gate drive voltage is applied to the terminal V1 and a terminal V2.
  • first DC voltage DC voltage
  • second DC voltage VSS of the gate drive voltage
  • the terminal S1 is an output signal from the terminal Z of the preceding stage Xi-1
  • the terminal S2 is a clock signal (first clock signal).
  • CLK3 terminal S3 has an output signal from the terminal Z of the next stage Xi + 1
  • terminal S4 has a clock signal (first conduction cutoff control signal, second conduction cutoff control signal, second clock signal) CLK4.
  • the second DC voltage is lower than the first DC voltage.
  • FIG. 17 shows an operation waveform of the shift register 4.
  • the clock signal CK2 has a pulse width twice the pulse width (1H) of the clock signal CK1, and each of the high level period (active period) and the low level period (inactive period) of the clock signal CK2 Corresponds to a period in which one Low level period (inactive period) and one High level period (active period) of the clock signal CK1 continue in this order.
  • the clock signal CK4 has a pulse width that is twice the pulse width (1H) of the clock signal CK3, and each High level period (active period) and each Low level period (inactive period) of the clock signal CK4. Corresponds to a period in which one Low level period (inactive period) and one High level period (active period) of the clock signal CK3 continue in this order.
  • the clock signal CK1 and the clock signal CK3 are in an opposite phase relationship.
  • the gate start pulse SP corresponds to one clock pulse of the clock signal CK3.
  • the gate pulse output from the terminal OUT is the output signal OUT1.
  • the shift pulse output from the terminal Z is a clock signal corresponding to the latter half period of the gate pulse of the stage Xi of its own stage, as shown in the waveform of the output signal Z (X1), Z (X2),. Only a period of one clock pulse of CLK1 and CLK2 is output. Accordingly, the pixel is precharged in the first half period of the gate pulse, the data signal is written in the second half period, and the shift pulse can be transmitted to the next stage Xi + 1.
  • the shift register 4 as compared with the shift register 2 of FIG. 4, the number of gate start pulses which are input signals necessary for obtaining an equivalent output signal for precharging can be reduced.
  • FIG. 18 shows the configuration of the shift register 5.
  • the shift register 5 has a configuration in which a plurality of stages Xi (i is a natural number) are cascaded by the number of gate bus lines GL.
  • the terminal V1 has a power supply voltage (first DC voltage) VDD at a high level (ie, a gate pulse level) of the gate drive voltage, and a terminal V2.
  • first DC voltage first DC voltage
  • second DC voltage second DC voltage
  • the terminal S1 is an output signal from the terminal Z of the preceding stage Xi-1
  • the terminal S2 is a clock signal (first clock signal).
  • the output signal from the terminal Z of the next stage Xi + 1 is input to CLK1 and the terminals S3 and S4, respectively, and the output signal OUTi of its own stage Xi is output from the terminal OUT.
  • the gate start pulse SP is input to the terminal S1 of the stage X1 instead of the output signal OUTi-1.
  • a power supply voltage (first DC voltage) VDD at a high level (that is, a gate pulse level) of the gate drive voltage is applied to the terminal V1 and a terminal V2.
  • first DC voltage DC voltage
  • second DC voltage VSS of the gate drive voltage
  • the terminal S1 is an output signal from the terminal Z of the preceding stage Xi-1
  • the terminal S2 is a clock signal (first clock signal).
  • the output signal from the terminal Z of the next stage Xi + 1 is input to CLK2 and the terminals S3 and S4, respectively, and the output signal OUTi of the own stage Xi is output from the terminal OUT.
  • the second DC voltage is lower than the first DC voltage.
  • FIG. 19 shows an operation waveform of the shift register 5.
  • the clock signal CK1 and the clock signal CK2 have a pulse width of 1H and are in an opposite phase relationship to each other.
  • the gate start pulse SP corresponds to one clock pulse of the clock signal CK2.
  • the gate pulse output from the terminal OUT is the output signal OUT1.
  • the shift pulse output from the terminal Z is a clock signal corresponding to the latter half period of the gate pulse of the stage Xi of its own stage, as shown in the waveform of the output signal Z (X1), Z (X2),. Only a period of one clock pulse of CLK1 and CLK2 is output. Accordingly, the pixel is precharged in the first half period of the gate pulse, the data signal is written in the second half period, and the shift pulse can be transmitted to the next stage Xi + 1.
  • the transistor M91 in FIG. 9, the transistor M101 in FIG. 10, the transistor M111 in FIG. 11, the transistor M121 in FIG. 12, and the transistor in FIG. M11 can be used in combination. If the output stage of the set signal supplied to the other stage Xi and the output stage of the reset signal are further separated, the operation can be performed more stably.
  • FIG. 20 shows the configuration of the stage Xi provided in the shift register of this embodiment.
  • the stage Xi in FIG. 20 has a configuration in which a transistor (second output transistor) M141 and a transistor (eighth switching element) M142 are added to the stage Xi in FIG.
  • the gate of the transistor M141 is connected to the node N1, the drain is connected to the terminal V3, and the source is connected to the terminal (second output terminal) Z.
  • a third DC voltage whose magnitude is larger than the power supply voltage VSS and can be arbitrarily set is supplied and applied to the terminal V3 independently of the power supply voltage VDD. That is, the third DC voltage is applied to the drain of the transistor M141, and the source of the transistor M141 functions as a second output terminal that is different from the first output terminal and is one output terminal of the stage Xi. In this way, a continuous stage group having other output terminals in addition to the first output terminal is defined as a multiple output continuous stage group.
  • the gate of the transistor M142 is connected to the terminal S4, the drain is connected to the terminal Z, and the source is connected to the terminal V2.
  • the signal input to the gate of the transistor M142 is a second conduction cutoff control signal.
  • the second conduction cutoff control signal is a signal whose active period does not overlap with the first clock signal, and in this embodiment, is the same signal as the first conduction cutoff control signal input to the gate of the transistor M6.
  • the second conduction cutoff control signal is a clock signal having a phase opposite to that of the first clock signal, that is, the same clock signal as the second clock signal.
  • the second conduction cutoff control signal may not be the same signal as the first conduction cutoff control signal.
  • the terminal Z is connected to the terminal S1 of the other stage Xi to which the shift pulse output from the stage Xi is input, and the transistor M141 outputs the shift pulse.
  • the transistor M142 resets the terminal Z to the low level.
  • the stage for outputting the gate pulse and the stage for outputting the set / reset control signal such as the set signal (shift pulse) and reset signal of the other stage Xi are separated from each other. Further, any number of stages separated in the same manner may be provided.
  • the control signal if the stage for outputting the set signal (shift pulse) of another stage and the stage for outputting the reset signal of another stage are further separated, the output of the set signal and the output of the reset signal are performed. Can be avoided, and can be operated more stably.
  • a third output transistor similar to the transistor M141 and a ninth switching element similar to the transistor M142 are added to the configuration of FIG.
  • the source of the third output transistor is a third output terminal that is one output terminal of the stage Xi, which is different from the first output terminal and the second output terminal. For example, from the second output terminal (terminal Z) A set signal (shift pulse) is output and a reset signal is output from the third output terminal.
  • the signal input to the conduction cutoff control terminal of the ninth switching element is the third conduction cutoff control signal.
  • the third conduction cutoff control signal is a signal whose active period does not overlap with the first clock signal.
  • the third conduction cutoff control signal is the same signal as the first conduction cutoff control signal input to the gate of the transistor M6.
  • the second conduction cutoff control signal is a clock signal having a phase opposite to that of the first clock signal, that is, the same clock signal as the second clock signal.
  • the third conduction cutoff control signal may not be the same signal as each of the first conduction cutoff control signal and the second conduction cutoff control signal.
  • the drain of the transistor M141 that outputs the control signal for setting and resetting the stage Xi on the front stage side and the rear stage side is connected to the terminal V3, so that the potential V (N1) of the node N1 is capacitively coupled. It is possible to prevent the potential of the terminal Z from being raised due to the thrust.
  • the drain of the transistor M141 which is the output transistor for the control signal for setting / resetting the other stage Xi, is connected to the terminal V3, the amplitude of the control signal can be set. Therefore, the ON current and OFF leak characteristics of the transistor M141 can be improved, and the shift register can be prevented from malfunctioning and more stable operation can be realized. Further, the third DC voltage applied to the terminal V3 is set so as to suppress the variation of the threshold voltage Vth due to the shift phenomenon generated by the difference between the gate potential, the source potential, and the drain potential of the transistor M141. Reliability can be improved.
  • the 20 is applicable to any of the shift register 1 in FIG. 2, the shift register 2 in FIG. 4, and the shift register 3 in FIG. Further, it is possible to combine the other embodiments with the stage Xi in FIG. 20, for example, the transistor M91 in FIG. 9, the transistor M101 in FIG. 10, the transistor M111 in FIG. 11, the transistor M121 in FIG. These transistors M11 can be used in combination.
  • FIG. 21 shows the configuration of the stage Xi provided in the shift register of this embodiment.
  • the source of the transistors M3 and M4 in the stage Xi of FIG. 1 is connected to the terminal V4 instead of being connected to the terminal V2, and the transistor (second output transistor) M141 and the transistor (eighth switching) are connected. Element) M142 is added.
  • the gate of the transistor M141 is connected to the node N1, the drain is connected to the terminal V1, and the source is connected to the terminal (second output terminal) Z. That is, the first DC voltage called the power supply voltage VDD is applied to the drain of the transistor M141, and the source of the transistor M141 is different from the first output terminal as a second output terminal that is one output terminal of the stage Xi. Function. In this way, a continuous stage group having other output terminals in addition to the first output terminal is defined as a multiple output continuous stage group.
  • the gate of the transistor M142 is connected to the terminal S4, the drain is connected to the terminal Z, and the source is connected to the terminals V2 and V4.
  • a fourth DC voltage whose magnitude is smaller than the power supply voltage VDD and can be arbitrarily set is supplied to the terminal V4 and supplied independently from the power supply voltage VSS.
  • the signal input to the gate of the transistor M142 is a second conduction cutoff control signal.
  • the second conduction cutoff control signal is a signal whose active period does not overlap with the first clock signal, and in this embodiment, is the same signal as the first conduction cutoff control signal input to the gate of the transistor M6.
  • the second conduction cutoff control signal is a clock signal having a phase opposite to that of the first clock signal, that is, the same clock signal as the second clock signal.
  • the second conduction cutoff control signal may not be the same signal as the first conduction cutoff control signal.
  • the terminal Z is connected to the terminal S1 of the other stage Xi to which the shift pulse output from the stage Xi is input, and the transistor M141 outputs the shift pulse.
  • the transistor M142 resets the terminal Z to the low level.
  • the stage for outputting the gate pulse and the stage for outputting the set / reset control signal such as the set signal (shift pulse) and reset signal of the other stage Xi are separated from each other. Further, any number of stages separated in the same manner may be provided.
  • the control signal if the stage for outputting the set signal (shift pulse) of another stage and the stage for outputting the reset signal of another stage are further separated, the output of the set signal and the output of the reset signal are performed. Can be avoided, and can be operated more stably.
  • a third output transistor similar to the transistor M141 and a ninth switching element similar to the transistor M142 are added to the configuration of FIG.
  • the source of the third output transistor is a third output terminal that is one output terminal of the stage Xi, which is different from the first output terminal and the second output terminal. For example, from the second output terminal (terminal Z) A set signal (shift pulse) is output and a reset signal is output from the third output terminal.
  • the signal input to the conduction cutoff control terminal of the ninth switching element is the third conduction cutoff control signal.
  • the third conduction cutoff control signal is a signal whose active period does not overlap with the first clock signal.
  • the third conduction cutoff control signal is the same signal as the first conduction cutoff control signal input to the gate of the transistor M6.
  • the second conduction cutoff control signal is a clock signal having a phase opposite to that of the first clock signal, that is, the same clock signal as the second clock signal.
  • the third conduction cutoff control signal may not be the same signal as each of the first conduction cutoff control signal and the second conduction cutoff control signal.
  • the drain of the transistor M141 that outputs a control signal for setting and resetting the stage Xi on the front stage side and the rear stage side is connected to the terminal V1, so that the potential V (N1) of the node N1 is capacitively coupled. It is possible to prevent the potential of the terminal Z from being raised due to the thrust.
  • the transistor M91 in FIG. 9, the transistor M101 in FIG. 10, the transistor M111 in FIG. 11, the transistor M121 in FIG. 12, and the transistor M11 in FIG. 15 can be used in combination with the isolation of the output stage of FIG. 15 and the transistor M141 of FIG.
  • FIG. 22 shows the configuration of the stage Xi provided in the shift register of the present embodiment.
  • the stage Xi in FIG. 22 has a configuration in which a transistor (tenth switching element) M221 is added to the stage Xi in FIG.
  • the gate of the transistor M221 is connected to the terminal S8, the drain is connected to the node N1, and the source is connected to the terminal V2.
  • a clear signal that is set to a high level (active level) at a predetermined timing is input to the terminal S8.
  • the shift register can have a clear function for arbitrarily clearing the node N1.
  • stage Xi in FIG. 22 for example, the transistor M91 in FIG. 9, the transistor M101 in FIG. 10, the transistor M111 in FIG. 11, the transistor M121 in FIG. A combination of M11, separation of the output stage of FIG. 15, transistor M141 of FIG. 20, and VSS of FIG. 21 can be used in combination.
  • FIG. 23 shows the configuration of the stage Xi provided in the shift register of this embodiment.
  • Stage Xi includes transistors M1, M2, M3, M4, M5, and M6 and a capacitor C1.
  • the transistors M1 to M6 are all N-channel TFTs here, but P-channel TFTs can also be used. Note that the gate of each switching element described below is a control terminal for turning off conduction in the switching element.
  • the gate of the transistor (input gate, fifth switching element, first transistor) M1 is connected to the terminal S1, the drain is connected to the terminal V1, and the source is connected to the node N1 connected to the gate of the transistor M5.
  • One end of the capacitor (first capacitor) C1 is connected to the node N1.
  • the gate of the transistor (first switching element) M2 is connected to the terminal S2, the drain is connected to the terminal V1, and the source is connected to the other end of the capacitor C1 opposite to the node N1 side.
  • the other end of the capacitor C1 is connected to the node N2.
  • the gate of the transistor (second switching element) M3 is connected to the terminal S1, the drain is connected to the node N2, and the source is connected to the terminal V2.
  • the gate of the transistor (third switching element) M4 is connected to the terminal S3, the drain is connected to the node N1, and the source is connected to the terminal V2.
  • the drain of the transistor (first output transistor) M5 is connected to the terminal S2, and the source is connected to the terminal OUT. That is, a DC voltage called the power supply voltage VDD is applied to the drain of the transistor M5, and the source of the transistor M5 functions as a first output terminal.
  • the gate of the transistor (fourth switching element) M6 is connected to the terminal S4, the drain is connected to the terminal OUT, and the source is connected to the terminal V2.
  • transistor M91 in FIG. 9 can be combined with other embodiments, for example, the transistor M91 in FIG. 9, the transistor M101 in FIG. 10, the transistor M111 in FIG. 11, the transistor M121 in FIG. 12, and the FIG. These transistors M11 can be used in combination.
  • FIG. 24 shows the potential of the node N1 at the gate X-source of the transistor M5 at the time before the node N1 is pushed up when the shift pulse is inputted and the node N1 is charged in the stage Xi having the configuration shown in FIG.
  • the magnitude relationship between the power supply voltage VDD and the threshold voltage Vth is set so that the voltage between the voltages exceeds the threshold voltage Vth.
  • the gate pulse appearing at the terminal OUT is the period T11 after the start of charging of the node N1 and before receiving the push-up by the node N2, and until the node N1 is pushed by the push-up by the node N2 and is reset.
  • the transistor M5 is turned on and a gate pulse is output.
  • the gate pulse output in the period T11 is set to be equal to or lower than the threshold voltage Vth of the transistor M1 so as not to become the set signal level of the next stage. That is, a certain voltage drop appears in the channel of the transistor M5.
  • the panel is driven by a driving method in which the same data signal line is supplied with the same polarity data signal during one frame period, such as source bus line inversion driving, in the period T11, the previous gate bus line Using the data signal of the pixel connected to GL, the pixel connected to the own gate bus line GL is precharged, and in the period T12, the pixel connected to the own gate bus line GL is precharged.
  • This writing can be performed. In this embodiment, this is possible by not using the bootstrap effect for raising the potential of the node N1.
  • This embodiment is an effective configuration for preventing malfunction in the case where a leak occurs in the transistor M3 in the shift register described so far.
  • the leakage of the large-sized transistor M3 causes a voltage drop at the node N2, and the node N2 must be originally maintained at a high voltage when the stage Xi is not output. It becomes difficult to satisfy the condition. For this reason, in the state (1), when the clock signal is input to the terminal S2 when the stage Xi is not output, the node N2 changes from the low voltage state to the high voltage state. As a result, the voltage at the node N1 rises.
  • the output is made when there should be no output from the stage Xi. Since the output signal OUTi of the stage Xi is a set signal of the next stage, the above-mentioned erroneous output increases as it goes to the subsequent stage and eventually oscillates.
  • the drain and the source of the transistor (sixth transistor) M9 are connected between the node N1 and the output terminal OUT, that is, between the gate and the source of the transistor M5. .
  • the gate of the transistor M9 is connected to the terminal V1.
  • the drain-source of the transistor M9 may be connected between the gate-source of the transistor M141 (between the gate of the transistor M141 and the output terminal Z).
  • Transistor M9 can be added to the configurations of all previous embodiments. That is, in the transistor M9, the drain-source is connected between the gate and the source of the output transistor, and the same voltage is applied to the drain of the output transistor connected to the gate between the drain and the source. A transistor to which a voltage is applied, or the drain-source is connected between the gate of the output transistor and the second DC voltage application terminal, and the drain-source is connected to the gate. A transistor to which the same voltage as that applied to the drains of the output transistors connected to each other can be applied.
  • the size (channel width) of the transistor M9 is reduced to prevent the potential of the node N1 from greatly decreasing when the stage Xi is in the output state. It is preferable to reduce the current.
  • FIG. 33 the effect of the present embodiment will be described with reference to FIGS. 33 and 34.
  • FIG. 33 shows an operation waveform of the configuration when the transistor M9 is not provided in FIG.
  • the output signal OUTi-1 of the previous stage Xi-1 is input to the terminal S1, and the node N1 is charged.
  • the node N2 is lowered to a low level when the transistor M3 is turned on.
  • an example is shown in which the potential of the node N1 turns on the transistor M5 during the period t1, and a slight output is obtained at the output terminal OUT.
  • the node N2 rises to High, and the potential of the node N1 is pushed up. As a result, an output is made to the output terminal OUT ⁇ Z.
  • the potential of the node N1 is reset and the stage Xi shifts to a non-output period.
  • the output terminal OUT ⁇ Z has a period. Forcibly set to Low level.
  • the transistor M2 is turned on in the cycle of the clock signal CLK1 from the period t6.
  • the potential of the node N2 slightly decreases due to the leakage of the transistor M3 in the period t5, and the node N2 is in the High level immediately after the period t6.
  • the potential of the node N1 is slightly pushed up, and an unnecessary output is generated at the output terminals OUT and Z as surrounded by a broken-line circle in the drawing.
  • the stage Xi of the shift register of this embodiment has a configuration in which the gate of the transistor M9 is connected to the node N2, that is, the other end of the capacitor C1 instead of FIG. 32 in the configuration of FIG.
  • the gate-source voltage Vgs 0 during one horizontal period when the node N2 is at the low level, so that the DC bias component applied to the gate of the transistor M9 is lower than that in the sixteenth embodiment. Thus, deterioration can be further suppressed.
  • the drain-source of the transistor M9 may be connected between the gate-source of the transistor M141 (between the gate of the transistor M141 and the output terminal Z).
  • Transistor M9 can be added to the configurations of all previous embodiments. That is, the transistor M9 can be a transistor in which the drain-source is connected between the gate and the source of the output transistor and the gate is connected to the other end of the capacitor C1, or the drain-source. The gap is connected between the gate of the output transistor and the second DC voltage application terminal, and the gate is connected to the other end of the capacitor C1.
  • the stage Xi of the shift register of this embodiment has a configuration in which the gate of the transistor M9 is connected to the terminal S2 instead of FIG. 32 in the configuration of FIG.
  • the high (active) gate voltage Vgs of the transistor M9 is 1 ⁇ 2 duty of the clock signal CLK1, so that the transistor M9 is further compared to the seventeenth embodiment.
  • the DC bias component applied to the gate of the transistor M9 decreases, and the transistor M9 is less degraded. Therefore, the size of the transistor M9 can be further reduced.
  • the drain-source of the transistor M9 may be connected between the gate-source of the transistor M141 (between the gate of the transistor M141 and the output terminal Z).
  • Transistor M9 can be added to the configurations of all previous embodiments. That is, the transistor M9 can be a transistor in which the drain-source is connected between the gate and the source of the output transistor and the first clock signal is input to the gate, or the drain-source Are connected between the gate of the output transistor and the second DC voltage application terminal, and the first clock signal is input to the gate.
  • the stage Xi of the shift register of this embodiment shown in FIG. 37 is obtained by removing the transistor M142 from the stage Xi of FIG. Since the clock signal is input to the drain of the transistor M141 from the terminal S2, the active level of the clock signal (here, the High level) is output to the output terminal OUT via the transistor M141, If a period in which the inactive level (here, Low level) of the clock signal is output to the output terminal OUT via the transistor M141 is provided, the output terminal OUT is reset to the Low level even if the transistor M142 is not provided. It can be performed.
  • the number of transistors that is, the number of switching elements (herein, the eighth switching element) can be reduced, the time and area can be reduced.
  • stage Xi of the shift register of this embodiment shown in FIG. 38 is the stage Xi of FIG. 32
  • the stage Xi of the shift register of this embodiment shown in FIG. 39 is the stage Xi of FIG.
  • the stage Xi of the shift register of this embodiment shown is obtained by removing the transistor M142 from the stage Xi of FIG.
  • the active level of the clock signal is the third level. If a period in which the inactive level of the clock signal is output to the output terminal via the third output transistor is provided following the period output to the output terminal via the output transistor, the ninth switching It is possible to have a configuration in which the element is removed.
  • the active level of the clock signal is the first level. If a period in which the inactive level of the clock signal is output to the output terminal via the first output transistor is provided following the period output to the output terminal via the output transistor, the fourth switching It is possible to have a configuration in which the element is removed.
  • capacitor C1 and the capacitor C101 for example, as shown in FIG. 26A, a parallel plate capacitor in which an insulator is sandwiched between two conductor plates facing each other, or FIG.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first output transistor that is an output transistor in which a first DC voltage is applied to the drain and the source is a first output terminal that constitutes one output terminal of the above-described stage; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; One end is connected to the other end of the first capacitor, the first DC voltage is applied to the other end, and the period of the active clock pulse is shifted to the stage of the own stage at the conduction cutoff control terminal.
  • the first DC voltage is applied to the drain of the first output transistor, and the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the gate bus line can be driven by a DC power supply by applying a DC voltage to the drain of the first output transistor, and the gate bus line can be driven by inputting a clock signal to the drain of the first output transistor.
  • the load of the external level shifter for generating the control signal of the shift register can be greatly reduced.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first output transistor that is an output transistor in which a first DC voltage is applied to the drain and the source is a first output terminal that constitutes one output terminal of the above-described stage; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; One end is connected to the other end of the first capacitor, the first DC voltage is applied to the other end, and the period of the active clock pulse is shifted to the stage of the own stage at the conduction cutoff control terminal.
  • a first switching element to which a first clock signal corresponding to each stage that does not overlap a pulse period is input; One end is connected to the other end of the first capacitor, a fourth DC voltage lower than the first DC voltage is applied to the other end, and the conduction cut-off control terminal is connected to the stage of the own stage.
  • a continuous stage group having a terminal and a fourth switching element to which a first conduction cut-off control signal corresponding to each stage that does not overlap with the first clock signal does not overlap with the first clock signal; It is characterized by being.
  • the first DC voltage is applied to the drain of the first output transistor, and the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the gate bus line can be driven by a DC power supply by applying a DC voltage to the drain of the first output transistor, and the gate bus line can be driven by inputting a clock signal to the drain of the first output transistor.
  • the load of the external level shifter for generating the control signal of the shift register can be greatly reduced.
  • the fourth DC voltage supplied independently of the second DC voltage is applied to the other end of the second switching element and the other end of the third switching element, the fourth DC voltage
  • the fourth DC voltage By adjusting the above, it is possible to change the amplitude of the control signal for performing the set / reset of the shift register at the previous stage or the subsequent stage, and to reduce the leakage of the input gate and the first output transistor OFF. Further, by setting the value of the fourth voltage so that a change in the threshold voltage of the transistor is unlikely to occur, there is an effect that it is possible to suppress a change in performance over time.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first clock signal corresponding to each stage in which the period of the active clock pulse does not overlap with the period of the shift pulse to the stage in its own stage is applied to the drain, and one output of the stage in which the source is in its own stage A first output transistor which is an output transistor serving as a first output terminal constituting the terminal; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; A first switching element, one end of which is connected to the other end of the first capacitor, a first DC voltage is applied
  • a second switching element to which a shift pulse is input One end is connected to one end of the first capacitor, the second DC voltage is applied to the other end, and the phase is delayed from the shift pulse output by the stage of its own stage at the conduction cutoff control terminal.
  • the first clock signal is input to the drain of the first output transistor, and the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the first clock signal is at the low level, fluctuation due to noise or coupling at one end of the first capacitor does not appear at the first output terminal with respect to the low level output at the first output terminal. .
  • the potential at the first output terminal is prevented from rising due to signal fluctuation or leakage when the output at the first output terminal is at a low level, and thus charge leakage from the pixel electrode or malfunction of the shift register occurs. There is an effect that can be prevented.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first clock signal corresponding to each stage in which the period of the active clock pulse does not overlap with the period of the shift pulse to the stage in its own stage is applied to the drain, and one output of the stage in which the source is in its own stage A first output transistor which is an output transistor serving as a first output terminal constituting the terminal; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; A first switching element, one end of which is connected to the other end of the first capacitor, a first DC voltage is applied
  • a continuous stage group having a terminal and a fourth switching element to which a first conduction cut-off control signal corresponding to each stage that does not overlap with the first clock signal does not overlap with the first clock signal; It is characterized by being.
  • the first clock signal is input to the drain of the first output transistor, and the switched capacitor operation using the first switching element, the second switching element, and the first capacitor is performed.
  • the first clock signal is at the low level, fluctuation due to noise or coupling at one end of the first capacitor does not appear at the first output terminal with respect to the low level output at the first output terminal. .
  • the potential at the first output terminal is prevented from rising due to signal fluctuation or leakage when the output at the first output terminal is at a low level, and thus charge leakage from the pixel electrode or malfunction of the shift register occurs. There is an effect that can be prevented.
  • the fourth DC voltage supplied independently of the second DC voltage is applied to the other end of the second switching element and the other end of the third switching element, the fourth DC voltage
  • the fourth DC voltage By adjusting the above, it is possible to change the amplitude of the control signal for setting / resetting the preceding or succeeding shift register, and to reduce the OFF leak of the input gate and the first output transistor. Further, by setting the value of the fourth voltage so that a change in the threshold voltage of the transistor is unlikely to occur, there is an effect that it is possible to suppress a change in performance over time.
  • the shift register of the present invention provides The first clock signal is in an opposite phase relationship between the odd-numbered stage and the even-numbered stage in the continuous stage group,
  • the shift pulse input to the first stage in the continuous stage group is out of phase with the first clock signal input to the odd-numbered stage by a half period. It is said.
  • the shift register of the present invention provides A first shift register including the cascade connection circuit including one or more first continuous stage groups each including the continuous stage group, and the first continuous stage group, provided corresponding to each of the first shift stage and the first continuous stage group; A second shift register including the cascade connection circuit including a second continuous stage group composed of the continuous stage group different from the first continuous stage group; About the first continuous stage group and the second continuous stage group corresponding to each other, The first clock signal is in an opposite phase relationship between the odd-numbered stage and the even-numbered stage in the first continuous stage group, and the odd-numbered above-mentioned number in the second continuous stage group.
  • the stage and the even-numbered stage are in an opposite phase relationship with each other,
  • the first clock signal input to the odd-numbered stages in the second continuous stage group is more than the first clock signal input to the odd-numbered stages in the first continuous stage group.
  • the first clock signal that is delayed by a quarter cycle and is input to the even-numbered stages in the second continuous stage group is input to the even-numbered stages in the first continuous stage group. Delayed by a quarter of the first clock signal,
  • the shift pulse input to the first stage in the first continuous stage group is half the first clock signal input to the odd numbered stage in the first continuous stage group.
  • the phase is shifted by the period,
  • the shift pulse input to the first stage in the second continuous stage group is 4 times the first clock signal than the shift pulse input to the first stage in the first continuous stage group. It is characterized by being delayed by a period of one cycle.
  • the picture element connected to each gate bus line in the display device is displayed in the horizontal period immediately before the horizontal period in which the gate bus line is selected for writing the data signal. It is possible to precharge using the data signal of the previous horizontal period.
  • the pixel in the case of performing source line inversion driving in which the polarity of the data signal in the same data signal line is the same for one frame period, the pixel can be sufficiently charged to the target voltage with a long charging time. Therefore, there is an effect that the charging rate of the picture element is increased and the display quality can be improved.
  • the shift register of the present invention provides About the first continuous stage group and the second continuous stage group corresponding to each other,
  • the control terminal for turning off the third switching element of the j-th (j is a natural number) stage in the first continuous stage group is the first terminal of the j-th stage in the second continuous stage group.
  • the k-th (k is a natural number) stage in the second continuous stage group has a control terminal for turning off the third switching element.
  • the control terminal of the k + 1th stage in the first continuous stage group is the first terminal. It is connected to the output terminal.
  • the other end of the first capacitor in resetting the potential of one end of the first capacitor, since the first switching element is in the ON state, the other end of the first capacitor is not floating but the potential from one end of the first capacitor. I will not be pushed down. For this reason, at an arbitrary time after the output of the pulse from the first output terminal is completed, the potential of one end of the first capacitor in the stage of its own stage is pushed up, and the potential of the first output terminal rises. Can be prevented.
  • the shift register of the present invention provides The input gate is applied with the first DC voltage at one end, the other end is connected to one end of the first capacitor, and a shift pulse to the stage at its own stage is input to a conduction cutoff control terminal. It is a fifth switching element.
  • the shift register of the present invention provides The input gate is applied with a fifth DC voltage at one end, the other end is connected to one end of the first capacitor, and a shift pulse to the stage is input to the conduction cutoff control terminal.
  • 5 is a switching element.
  • the potential supplied to one end of the first capacitor can be set to any fifth DC voltage different from the first DC voltage, thereby preventing a shift register from malfunctioning. There is an effect.
  • the fifth switching element is a first transistor in which a gate is a conduction cutoff control terminal, a drain is one end of the fifth switching element, and a source is connected to one end of the first capacitor. It is characterized by that.
  • the fifth switching element can be easily configured.
  • the input gate is a fifth switching element in which a shift pulse to the first stage is input to one end and a conduction cutoff control terminal, and the other end is connected to one end of the first capacitor. It is said.
  • the shift pulse to the stage of its own stage is input to one end of the fifth switching element and the control terminal for shutting off the conduction, leakage to one end of the first capacitor through the input gate is prevented. Can be reduced. As a result, it is possible to suppress the leakage current of the input gate and to prevent the charge leakage from the pixel electrode and the malfunction of the shift register.
  • the shift register of the present invention provides The fifth switching element is a first transistor in which a drain and a gate are connected to each other, the first DC voltage is applied, and a source is connected to one end of the first capacitor. .
  • the threshold voltage gradually decreases due to the shift phenomenon.
  • the leakage current increases.
  • the potential at one end of the first capacitor increases, leading to charge leakage from the pixel electrode and malfunction of the shift register.
  • a shift pulse is input to the drain of the first transistor in the same manner as the gate, it is possible to prevent the gate potential from becoming lower than the drain potential, and thus suppress the decrease in the threshold voltage of the first transistor. be able to.
  • the leakage current of the input gate can be further suppressed, and the charge leakage from the pixel electrode and the malfunction of the shift register can be prevented more satisfactorily.
  • the shift register of the present invention provides In the above continuous stage group, In each stage, one end is connected to the other end of the first capacitor, the first DC voltage is applied to the other end, and the conduction cutoff control terminal of the third switching element is connected to the conduction cutoff control terminal.
  • a sixth switching element for receiving the same input as the input to the terminal; The above-mentioned continuous stage group is included.
  • the sixth switching element when the third switching element is turned on and the potential at one end of the first capacitor is reset, the sixth switching element is also turned on at the same time. Therefore, the potential of the other end of the first capacitor is maintained at a constant value of (first DC voltage-threshold voltage), and the potential of the other end is prevented from being lowered due to capacitive coupling through the first capacitor. Can do. Therefore, it is possible to prevent the potential of the first output terminal from rising due to the potential at one end of the first capacitor being fluctuated via capacitive coupling, and to suppress charge leakage from the pixel electrode and malfunction of the shift register. There is an effect.
  • the shift register of the present invention provides In the above continuous stage group,
  • the first switching element is a second transistor in which a gate is a control terminal for turning off conduction, the first DC voltage is applied to a drain, and a source is connected to the other end of the first capacitor.
  • Each of the stages includes a third transistor whose gate is inputted with a signal having a phase opposite to that of the input to the gate of the second transistor, and whose drain and source are connected to the other end of the first capacitor.
  • the signal flows to one end of the first capacitor by the gate-source capacitance of the second transistor.
  • the influence of the charge can be offset by the charge / discharge charge of the gate-source capacitance and the gate-drain capacitance of the third transistor.
  • the potential increase of the first output terminal caused by the fluctuation of the potential of the other end of the first capacitor due to the charge injection from the first switching element is prevented, and the charge leakage from the pixel electrode and the malfunction of the shift register are prevented. There exists an effect that it can control.
  • the shift register of the present invention provides The channel width of the third transistor is one half of the channel width of the second transistor.
  • the influence of the electric charge flowing to one end of the first capacitor due to the gate-source capacitance of the second transistor is determined by charging / discharging the gate-source capacitance and the gate-drain capacitance of the third transistor. There is an effect that the charges can be appropriately offset.
  • the shift register of the present invention provides In the above continuous stage group, Each of the stages includes a second capacitor connected between the gate of the third transistor and the other end of the first capacitor.
  • the above-mentioned continuous stage group is included.
  • the threshold voltage shift phenomenon can be satisfactorily suppressed.
  • the shift register of the present invention provides In the above continuous stage group, Each stage is a signal having a High level period in the period of the active clock pulse of the second first clock signal after the shift pulse is input to its own stage in the conduction cutoff control terminal. Is provided, one end is connected to one end of the first capacitor, and the other end includes a seventh switching element to which the second DC voltage is applied.
  • the above-mentioned continuous stage group is included.
  • the potential at the first output terminal caused by the potential at one end of the first capacitor swinging through capacitive coupling is prevented, and the leakage of charge from the pixel electrode and the malfunction of the shift register are suppressed. There is an effect that can be done.
  • the fourth switching element is a fourth transistor in which a gate is a conduction cutoff control terminal, a drain is connected to the first output terminal, and the second DC voltage is applied to a source.
  • a gate is a conduction cutoff control terminal
  • a drain is connected to the first output terminal
  • the second DC voltage is applied to a source.
  • Each of the stages receives the shift pulse output from the other stage first after completing the output of the shift pulse from its own stage to the gate, and the drain of the first stage of its own stage.
  • the above-mentioned continuous stage group is included.
  • the charging time becomes unnecessarily long, and the next stage gate bus line This prevents the data signal to be written to the picture element connected to the picture element connected to the gate bus line of the own stage from being written and improves the display quality.
  • the shift register of the present invention provides The first conduction cut-off control signal is a second clock signal having a phase opposite to that of the first clock signal.
  • the potential fluctuation of the first output terminal can be prevented by applying the second DC voltage to the first output terminal every time the second clock signal becomes active. There is an effect that can be.
  • the shift register of the present invention provides The first conduction cut-off control signal is provided in a second predetermined other stage included in any one of the cascade connection circuits, the phase of which is delayed from the shift pulse output by the stage of the first stage. It is a pulse signal output from one output terminal.
  • the output of the second predetermined other stage is inputted to the conduction cutoff control terminal of the fourth switching element, the clock generated by the clock signal being inputted to the conduction cutoff control terminal.
  • the clock generated by the clock signal is inputted to the conduction cutoff control terminal.
  • the continuous stage group includes the continuous stage group in which a shift pulse transmitted between the stages is a source output of the first output transistor.
  • the shift register of the present invention provides In the above continuous stage group, Each of the stages has a gate connected to one end of the first capacitor, the first clock signal is input to the drain, and a source that is different from the first output terminal of the stage having the source.
  • a second output transistor which is an output transistor serving as a second output terminal constituting the terminal;
  • the shift pulse transmitted between the stages is the source output of the second output transistor,
  • a multi-output continuous stage group which is the continuous stage group is included.
  • blocking control signal corresponding to can be input may be provided.
  • the potential at one end of the first capacitor is pushed up by capacitive coupling, and the output of the second output terminal can be prevented from rising during an unnecessary period to prevent the shift register from malfunctioning. Play.
  • the second output transistor is used for outputting a shift pulse transmitted between the stages, the size of the second output transistor is greatly reduced as compared with the first output transistor used for outputting to the outside of the shift register. be able to. Accordingly, the drain parasitic capacitance of the second output transistor is sufficiently smaller than the drain parasitic capacitance and source parasitic capacitance of the first output transistor and the first capacitance, and the drain capacitance of the second output transistor is connected to the drain of the second output transistor. Even if one clock signal is input, the effect that the potential at one end of the first capacitor is pushed up by capacitive coupling can be reduced to a negligible level.
  • the load driven by the second output terminal is sufficiently smaller than the load driven by the first output terminal, so that the amount of change in the load of the external level shifter that generates the control signal of the shift register can be ignored. There is an effect that it can be made smaller.
  • the shift register of the present invention provides In the above continuous stage group, Each of the stages has a gate connected to one end of the first capacitor, the first clock signal is input to the drain, and a source that is different from the first output terminal of the stage having the source.
  • a second output transistor which is an output transistor serving as a second output terminal constituting the terminal;
  • the shift pulse transmitted between the stages is the source output of the second output transistor,
  • a multi-output continuous stage group which is the continuous stage group is included.
  • the control terminal may include an eighth switching element to which a second conduction cutoff control signal corresponding to each of the stages in which an active period does not overlap with the first clock signal is input.
  • the potential at one end of the first capacitor is pushed up by capacitive coupling, and the output of the second output terminal can be prevented from rising during an unnecessary period to prevent the shift register from malfunctioning. Play.
  • the shift register of the present invention provides In the above continuous stage group, Each of the stages has a gate connected to one end of the first capacitor, the first clock signal is input to the drain, and a source that is different from the first output terminal of the stage having the source.
  • a second output transistor which is an output transistor serving as a second output terminal constituting the terminal;
  • the output from the second output terminal of the next stage is input to the control terminal for turning off the conduction of the third switching element,
  • the shift pulse transmitted between the stages is the source output of the second output transistor,
  • the first clock signal is in an opposite phase relationship between the odd-numbered stage and the even-numbered stage in each of the successive stage groups, In each of the odd-numbered stages and the even-numbered stages in each of the successive stage groups, the second clock signal in which the first conduction cutoff control signal is in a phase opposite to that of the first clock signal.
  • each of the active periods and the inactive periods of the second clock signal has a pulse width that is twice the pulse width of the first clock signal.
  • One inactive period and one active period are consecutive periods in this order, In each of the successive stage groups, the shift pulse input to the first stage corresponds to one clock pulse of the first clock signal of the even-numbered stage.
  • a multi-output continuous stage group which is the continuous stage group is included.
  • blocking control signal corresponding to can be input may be provided.
  • the first output transistor is turned on by the potential of the one end of the first capacitor (first DC voltage-threshold voltage) when the shift pulse is input to the stage of the first stage.
  • the pulse output from the first output terminal is output for a period of two clock pulses while the potential increases stepwise.
  • the shift pulse output from the second output terminal corresponds to the period of the second half of the pulse output from the first output terminal of the own stage, and corresponds to the first clock signal and the second clock signal. Only a period of one clock pulse is output. Therefore, it is possible to precharge the picture element in the first half period of the pulse output from the first output terminal, to perform the main writing of the data signal in the second half period and to transmit the shift pulse to the subsequent stage. Play.
  • the shift register of the present invention provides In the above continuous stage group, Each of the stages has a gate connected to one end of the first capacitor, the first clock signal is input to the drain, and a source that is different from the first output terminal of the stage having the source.
  • a second output transistor which is an output transistor serving as a second output terminal constituting the terminal;
  • the output from the second output terminal of the next stage is input to the control terminal for turning off the conduction of the third switching element,
  • the shift pulse transmitted between the stages is the source output of the second output transistor,
  • the first clock signal is in an opposite phase relationship between the odd-numbered stage and the even-numbered stage in each of the successive stage groups, In each of the successive stage groups, the shift pulse input to the first stage corresponds to one clock pulse of the first clock signal of the even-numbered stage.
  • a multi-output continuous stage group which is the continuous stage group is included.
  • one end is connected to the second output terminal, the second DC voltage is applied to the other end, and an output from the second output terminal of the next stage is input to the conduction cutoff control terminal.
  • the 8th switching element may be provided.
  • the first output transistor is turned on by the potential of the one end of the first capacitor (first DC voltage-threshold voltage) when the shift pulse is input to the stage of the first stage.
  • the pulse output from the first output terminal is output for a period of two clock pulses while the potential increases stepwise.
  • the shift pulse output from the second output terminal is a period corresponding to one clock pulse of the first clock signal, which corresponds to the latter half of the pulse output from the first output terminal of the stage of its own stage. Is only output. Therefore, it is possible to precharge the picture element in the first half period of the pulse output from the first output terminal, to perform the main writing of the data signal in the second half period and to transmit the shift pulse to the subsequent stage. Play.
  • the shift register of the present invention provides Among the multiple output continuous stage group, In each of the stages, the gate is connected to one end of the first capacitor, the first clock signal is input to the drain, and the source is the first output terminal and the second output of the stage.
  • the multi-output continuous stage group is included.
  • blocking control signal corresponding to can be input may be provided.
  • the shift register of the present invention provides Among the multiple output continuous stage group, In each of the stages, the gate is connected to one end of the first capacitor, the first clock signal is input to the drain, and the source is the first output terminal and the second output of the stage.
  • the multi-output continuous stage group is included.
  • control terminal may be provided with a ninth switching element to which a third conduction cutoff control signal corresponding to each stage in which the active period does not overlap with the first clock signal is input.
  • the shift register of the present invention provides In the above continuous stage group, In each stage, the gate is connected to one end of the first capacitor, the first DC voltage is applied to the drain, and the source is one output different from the first output terminal of the stage of the stage.
  • a second output transistor which is an output transistor serving as a second output terminal constituting the terminal, and one end connected to the second output terminal, and the second DC voltage is applied to the other end,
  • An eighth switching element to which a second conduction cutoff control signal corresponding to each stage in which an active period does not overlap with the first clock signal is input to the control terminal;
  • the shift pulse transmitted between the stages is a source output of the second output transistor.
  • a multi-output continuous stage group which is the continuous stage group is included.
  • both outputs are mutually connected. Interference can be avoided. Therefore, it is possible to prevent the shift register from malfunctioning and performance deterioration due to interference between the output outside the shift register and the output of the control signal for setting / resetting other stages.
  • the shift register of the present invention provides In the above continuous stage group, In each stage, the gate is connected to one end of the first capacitor, the first DC voltage is applied to the drain, and the source is one output different from the first output terminal of the stage of the stage.
  • a second output transistor which is an output transistor serving as a second output terminal constituting the terminal, one end of which is connected to the second output terminal and the other end of which is lower than the first DC voltage
  • a fourth DC voltage supplied independently of the DC voltage is applied, and a second conduction cutoff control corresponding to each stage in which the active period does not overlap with the first clock signal at the conduction cutoff control terminal.
  • An eighth switching element to which a signal is input, The shift pulse transmitted between the stages is a source output of the second output transistor.
  • a multi-output continuous stage group which is the continuous stage group is included.
  • both outputs are mutually connected. Interference can be avoided. Therefore, it is possible to prevent the shift register from malfunctioning and performance deterioration due to interference between the output outside the shift register and the output of the control signal for setting / resetting other stages.
  • the shift register of the present invention provides Among the multiple output continuous stage group, In each of the stages, the gate is connected to one end of the first capacitor, the first DC voltage is applied to the drain, and the source is the first output terminal and the second output terminal of its own stage.
  • a ninth switching element to which a third conduction cutoff control signal corresponding to each stage in which an active period does not overlap with the first clock signal is input to the control terminal;
  • the source output of the third output transistor is input to the control terminal for turning off the third switching element of the stage, which uses the stage of the third stage as the first predetermined other stage.
  • the multi-output continuous stage group is included.
  • the shift register of the present invention provides Among the multiple output continuous stage group, In each of the stages, the gate is connected to one end of the first capacitor, the first DC voltage is applied to the drain, and the source is the first output terminal and the second output terminal of its own stage.
  • a third output transistor constituting a third output terminal constituting one different output terminal, one end of which is connected to the second output terminal and the other end of which is lower than the first DC voltage.
  • a sixth DC voltage supplied independently of the DC voltage is applied, and a third conduction cutoff control corresponding to each stage in which the active period does not overlap with the first clock signal at the conduction cutoff control terminal. 9th switching to which a signal is input, The source output of the third output transistor is input to the control terminal for turning off the third switching element of the stage, which uses the stage of the third stage as the first predetermined other stage.
  • the multi-output continuous stage group is included.
  • the shift register of the present invention provides In the above continuous stage group, Each of the stages has a gate connected to one end of the first capacitor, and a drain applied with a third DC voltage that is higher than the second DC voltage and is supplied independently of the first DC voltage. And a second output transistor that is an output transistor serving as a second output terminal that constitutes one output terminal different from the first output terminal of the stage whose source is the stage, and one end of which is the second output terminal. A second continuity cut-off corresponding to each stage that is connected to the output terminal, the second DC voltage is applied to the other end, and an active period does not overlap the continuity cut-off control terminal with the first clock signal.
  • An eighth switching element to which a control signal is input, The shift pulse transmitted between the stages is a source output of the second output transistor.
  • a multi-output continuous stage group which is the continuous stage group is included.
  • both outputs are mutually connected. Interference can be avoided. Therefore, it is possible to prevent the shift register from malfunctioning and performance deterioration due to interference between the output outside the shift register and the output of the control signal for setting / resetting other stages.
  • the third DC voltage is applied to the drain of the second output transistor, which is the output transistor of the control signal for setting / resetting other stages, the amplitude of the control signal can be set. Therefore, the ON current and OFF leak characteristics of the second output transistor can be improved, and a more stable operation can be realized by preventing the shift register from malfunctioning. Further, by setting the third DC voltage so as to suppress the variation of the threshold voltage due to the shift phenomenon caused by the difference between the gate potential, the source potential, and the drain potential of the second output transistor, the reliability of the shift register is improved. There is an effect that improvement can be achieved.
  • the shift register of the present invention provides In the above continuous stage group, Each of the stages has a gate connected to one end of the first capacitor, and a drain applied with a third DC voltage that is higher than the second DC voltage and is supplied independently of the first DC voltage. And a second output transistor that is an output transistor serving as a second output terminal that constitutes one output terminal different from the first output terminal of the stage whose source is the stage, and one end of which is the second output terminal. A fourth DC voltage, which is connected to the output terminal and is supplied independently from the second DC voltage, is applied to the other end of the first DC voltage.
  • An eighth switching element to which a second conduction cutoff control signal corresponding to each stage in which the active period does not overlap with the clock signal is input;
  • the shift pulse transmitted between the stages is a source output of the second output transistor.
  • a multi-output continuous stage group which is the continuous stage group is included.
  • both outputs are mutually connected. Interference can be avoided. Therefore, it is possible to prevent the shift register from malfunctioning and performance deterioration due to interference between the output outside the shift register and the output of the control signal for setting / resetting other stages.
  • the shift register of the present invention provides Among the multiple output continuous stage group, In each stage, the gate is connected to one end of the first capacitor, the third DC voltage is applied to the drain, and the source is the first output terminal and the second output of the stage.
  • the multi-output continuous stage group is included.
  • the shift register of the present invention provides Among the multiple output continuous stage group, In each stage, the gate is connected to one end of the first capacitor, the third DC voltage is applied to the drain, and the source is the first output terminal and the second output of the stage.
  • a third output transistor serving as a third output terminal constituting one output terminal different from the output terminal, one end of which is connected to the second output terminal, and the other end of which is lower than the first DC voltage.
  • a sixth DC voltage supplied independently of the second DC voltage is applied, and the third clock corresponding to each stage in which the active period does not overlap with the first clock signal at the conduction cutoff control terminal.
  • the source output of the third output transistor is input to the control terminal for turning off the third switching element of the stage, which uses the stage of the third stage as the first predetermined other stage.
  • the multi-output continuous stage group is included.
  • the second conduction cut-off control signal is a second clock signal having a phase opposite to that of the first clock signal.
  • the shift register of the present invention provides The second conduction cut-off control signal is provided in a third predetermined other stage included in any of the cascade connection circuits, the phase of which is delayed from the shift pulse output from the stage of the own stage. It is a pulse signal output from one output terminal.
  • the threshold voltage shift phenomenon or the like is applied to the conduction cutoff control terminal of the eighth switching element.
  • the shift register of the present invention provides The third conduction cutoff control signal is a second clock signal having a phase opposite to that of the first clock signal.
  • the shift register of the present invention provides The third conduction cut-off control signal is provided in a third predetermined other stage included in any one of the cascade connection circuits, the phase of which is delayed with respect to the shift pulse output from the stage of the own stage. It is a pulse signal output from one output terminal.
  • the threshold voltage shift phenomenon or the like is applied to the conduction cutoff control terminal of the eighth switching element.
  • the shift register of the present invention provides In the above continuous stage group, One end of each stage is connected to one end of the first capacitor, the second DC voltage is applied to the other end, and a signal that becomes an active level at a predetermined timing is input to the conduction cutoff control terminal.
  • a tenth switching element; The above-mentioned continuous stage group is included.
  • the shift register can be provided with a clear function for arbitrarily clearing one end of the first capacitor.
  • the shift register of the present invention provides In the above continuous stage group, Each stage has one end connected to one end of the first capacitor and the other end applied with a fourth DC voltage that is lower than the first DC voltage and is supplied independently of the second DC voltage.
  • a tenth switching element that receives a signal that becomes an active level at a predetermined timing to the control terminal for shutting off the electrical connection; The above-mentioned continuous stage group is included.
  • the potential at one end of the first capacitor is forcibly fixed to the fourth DC voltage when an active level is input to the conduction cutoff control terminal of the tenth switching element. it can.
  • the shift register can be provided with a clear function for arbitrarily clearing one end of the first capacitor.
  • the shift register of the present invention provides The drain-source is connected between the gate and source of the output transistor, and the same voltage as the voltage applied to the drain of the output transistor connected between the drain and source is applied to the gate.
  • a sixth transistor is provided.
  • the potential of the one end is lowered by connecting the one end to the low potential side via the sixth transistor.
  • the shift register of the present invention provides The drain-source is connected between the gate of the output transistor and the second DC voltage application terminal, and is applied to the gate of the output transistor connected to the drain-source.
  • a sixth transistor to which the same voltage as the applied voltage is applied is provided.
  • the potential of the one end is lowered by connecting the one end to the low potential side via the sixth transistor.
  • the shift register of the present invention provides A drain-source is connected between a gate and a source of the output transistor, and a sixth transistor having a gate connected to the other end of the first capacitor is provided.
  • the potential of the one end is lowered by connecting the one end to the low potential side via the sixth transistor.
  • the gate-source voltage of the sixth transistor is lower than the first DC voltage, it is possible to further suppress the deterioration of the sixth transistor. Further, this brings about an effect that it is not necessary to increase the size of the sixth transistor for compensating for the deterioration. Further, since the gate-source voltage of the sixth transistor is small during the period when the other end of the first capacitor is at the low level by the second DC voltage, the DC bias component applied to the gate of the sixth transistor. Is reduced and deterioration can be further suppressed.
  • the shift register of the present invention provides The drain-source is connected between the gate of the output transistor and the second DC voltage application terminal, and the gate is connected to the other end of the first capacitor. It is characterized by having.
  • the potential of the one end is lowered by connecting the one end to the low potential side via the sixth transistor.
  • the gate-source voltage of the sixth transistor is lower than the first DC voltage, it is possible to further suppress the deterioration of the sixth transistor. Further, this brings about an effect that it is not necessary to increase the size of the sixth transistor for compensating for the deterioration. Further, since the gate-source voltage of the sixth transistor is small during the period when the other end of the first capacitor is at the low level by the second DC voltage, the DC bias component applied to the gate of the sixth transistor. Is reduced and deterioration can be further suppressed.
  • the shift register of the present invention provides A drain-source is connected between a gate and a source of the output transistor, and a sixth transistor in which the first clock signal is input to the gate is provided.
  • the potential of the one end is lowered by connecting the one end to the low potential side via the sixth transistor.
  • the active gate voltage of the sixth transistor is 1 ⁇ 2 duty of the first clock signal
  • the DC bias component applied to the gate of the sixth transistor is greatly reduced, and the sixth transistor There is an effect that the deterioration is further reduced. Therefore, an effect is obtained that the size of the sixth transistor can be further reduced.
  • the shift register of the present invention provides A drain-source is connected between the gate of the output transistor and the application terminal for the second DC voltage, and a sixth transistor is provided in which the first clock signal is input to the gate. It is characterized by being.
  • the potential of the one end is lowered by connecting the one end to the low potential side via the sixth transistor.
  • the active gate voltage of the sixth transistor is 1 ⁇ 2 duty of the first clock signal
  • the DC bias component applied to the gate of the sixth transistor is greatly reduced, and the sixth transistor There is an effect that the deterioration is further reduced. Therefore, an effect is obtained that the size of the sixth transistor can be further reduced.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first clock signal corresponding to each stage in which the period of the active clock pulse does not overlap with the period of the shift pulse to the stage in its own stage is applied to the drain, and one output of the stage in which the source is in its own stage A first output transistor which is an output transistor serving as a first output terminal constituting the terminal; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; A first switching element, one end of which is connected to the other end of the first capacitor, a first DC voltage is applied
  • a second switching element to which a shift pulse is input One end is connected to one end of the first capacitor, the second DC voltage is applied to the other end, and the phase is delayed from the shift pulse output by the stage of its own stage at the conduction cutoff control terminal.
  • the circuit area can be reduced.
  • the shift register of the present invention provides A shift register having at least one cascade connection circuit in which stages are cascaded so as to transmit shift pulses, In at least one of the cascade connection circuits, among all the stages of each cascade connection circuit, a continuous stage group consisting of a plurality of successive stages, wherein each of the stages is A first clock signal corresponding to each stage in which the period of the active clock pulse does not overlap with the period of the shift pulse to the stage in its own stage is applied to the drain, and one output of the stage in which the source is in its own stage A first output transistor which is an output transistor serving as a first output terminal constituting the terminal; A first capacitor having one end connected to the gate of the first output transistor; An input gate that receives a shift pulse to the stage of the own stage and passes a potential supplied to one end of the first capacitor during a pulse period of the shift pulse to the stage of the own stage; A first switching element, one end of which is connected to the other end of the first capacitor, a first DC voltage is applied
  • a second switching element to which a shift pulse is input One end is connected to one end of the first capacitor, the fourth DC voltage is applied to the other end, and the phase is delayed from the shift pulse output by the stage of its own stage at the conduction cutoff control terminal.
  • the circuit area can be reduced.
  • the display device of the present invention provides The shift register is provided.
  • the present invention can be suitably used for an active matrix display device.

Abstract

Chaque étage (Xi) d'un registre à décalage comprend un premier transistor de sortie (M5), un premier condensateur (C1), une grille d'entrée (M1), un premier élément de commutation (M2), un deuxième élément de commutation (M3), un troisième élément de commutation (M4) et un quatrième élément de commutation (M6).
PCT/JP2009/068226 2009-02-25 2009-10-23 Registre à décalage et dispositif d'affichage WO2010097986A1 (fr)

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JP2009-136330 2009-06-05

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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011092924A1 (fr) * 2010-01-29 2011-08-04 シャープ株式会社 Registre à décalage et dispositif d'affichage
WO2011114569A1 (fr) * 2010-03-15 2011-09-22 シャープ株式会社 Registre à décalage, circuit d'attaque de ligne de signal de balayage et dispositif d'affichage
JP2011204343A (ja) * 2010-03-24 2011-10-13 Au Optronics Corp 低電力消費のシフトレジスタ
CN102750987A (zh) * 2011-04-21 2012-10-24 乐金显示有限公司 移位寄存器
JPWO2010146738A1 (ja) * 2009-06-15 2012-11-29 シャープ株式会社 シフトレジスタおよび表示装置
WO2012169590A1 (fr) * 2011-06-10 2012-12-13 シャープ株式会社 Registre à décalage et dispositif d'affichage équipé de ce registre à décalage
US8422622B2 (en) 2009-06-15 2013-04-16 Sharp Kabushiki Kaisha Shift register and display device
JP5420072B2 (ja) * 2010-05-24 2014-02-19 シャープ株式会社 シフトレジスタ
US9281077B2 (en) 2009-02-25 2016-03-08 Sharp Kabushiki Kaisha Shift register and display device
TWI550587B (zh) * 2014-02-27 2016-09-21 上海和輝光電有限公司 一種閘極驅動電路及顯示面板
WO2016197531A1 (fr) * 2015-06-08 2016-12-15 京东方科技集团股份有限公司 Unité de registre à décalage et son procédé d'attaque, circuit d'attaque de grille et appareil d'affichage
CN106548744A (zh) * 2017-01-20 2017-03-29 京东方科技集团股份有限公司 栅极驱动单元及其驱动方法、栅极驱动电路和显示装置
CN112037718A (zh) * 2020-09-23 2020-12-04 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
CN112444733A (zh) * 2020-11-10 2021-03-05 海光信息技术股份有限公司 一种芯片老化状态检测方法及装置
WO2021217468A1 (fr) * 2020-04-28 2021-11-04 京东方科技集团股份有限公司 Panneau d'affichage, procédé d'attaque et dispositif d'affichage

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011108345A1 (fr) * 2010-03-02 2011-09-09 Semiconductor Energy Laboratory Co., Ltd. Circuit de sortie de signal par imuplsion et registre de décalage
TWI635501B (zh) * 2012-07-20 2018-09-11 半導體能源研究所股份有限公司 脈衝輸出電路、顯示裝置、及電子裝置
CN103578433B (zh) * 2012-07-24 2015-10-07 北京京东方光电科技有限公司 一种栅极驱动电路、方法及液晶显示器
JP6245422B2 (ja) * 2013-07-24 2017-12-13 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 走査回路、及び表示装置
CN103500551B (zh) * 2013-10-23 2015-12-30 合肥京东方光电科技有限公司 移位寄存器单元、goa电路、阵列基板以及显示装置
TWI539435B (zh) * 2014-08-29 2016-06-21 友達光電股份有限公司 驅動電路
CN104361856B (zh) * 2014-10-27 2017-04-12 京东方科技集团股份有限公司 有源矩阵有机发光二极管像素电路的驱动电路及驱动方法
CN104835476B (zh) 2015-06-08 2017-09-15 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、阵列基板
WO2017150443A1 (fr) * 2016-03-02 2017-09-08 シャープ株式会社 Substrat à matrice active, et dispositif d'affichage à cristaux liquides doté dudit substrat
KR102578838B1 (ko) * 2016-09-30 2023-09-18 엘지디스플레이 주식회사 게이트 구동부 및 이를 포함하는 표시장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58151719A (ja) * 1982-03-05 1983-09-09 Sony Corp パルス発生回路
JP2006106320A (ja) * 2004-10-05 2006-04-20 Alps Electric Co Ltd 液晶表示装置の駆動回路
JP2006178165A (ja) * 2004-12-22 2006-07-06 Alps Electric Co Ltd ドライバ回路、シフトレジスタ及び液晶駆動回路

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4110664A (en) * 1977-04-15 1978-08-29 Westinghouse Electric Corp. Electroluminescent bargraph with integral thin-film transistor control circuitry
JPH02246098A (ja) 1989-03-17 1990-10-01 Fujitsu Ltd 半導体回路
JP3144166B2 (ja) 1992-11-25 2001-03-12 ソニー株式会社 低振幅入力レベル変換回路
TW440742B (en) * 1997-03-03 2001-06-16 Toshiba Corp Flat panel display device
JPH1186586A (ja) 1997-09-03 1999-03-30 Furontetsuku:Kk シフトレジスタ装置および表示装置
JP4181710B2 (ja) 1998-10-21 2008-11-19 エルジー ディスプレイ カンパニー リミテッド シフトレジスタ
KR100438525B1 (ko) 1999-02-09 2004-07-03 엘지.필립스 엘시디 주식회사 쉬프트 레지스터 회로
KR100281336B1 (ko) 1998-10-21 2001-03-02 구본준 쉬프트 레지스터 회로
JP4310939B2 (ja) 2001-06-29 2009-08-12 カシオ計算機株式会社 シフトレジスタ及び電子装置
JP4473492B2 (ja) 2002-05-28 2010-06-02 東芝モバイルディスプレイ株式会社 シフトレジスタ
US7486269B2 (en) 2003-07-09 2009-02-03 Samsung Electronics Co., Ltd. Shift register, scan driving circuit and display apparatus having the same
GB0417132D0 (en) 2004-07-31 2004-09-01 Koninkl Philips Electronics Nv A shift register circuit
US7830352B2 (en) * 2005-01-14 2010-11-09 Au Optronics Corp. Driving circuit for flat panel display which provides a horizontal start signal to first and second shift register cells
US7432737B2 (en) * 2005-12-28 2008-10-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device, and electronic device
CN101361110B (zh) * 2006-01-23 2013-03-06 夏普株式会社 驱动电路、具备该驱动电路的显示装置以及显示装置的驱动方法
KR101533221B1 (ko) * 2006-10-13 2015-07-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 액티브 매트릭스형 표시장치
CN100583295C (zh) * 2007-02-09 2010-01-20 群康科技(深圳)有限公司 移位寄存器及液晶显示装置
CN101359511B (zh) * 2007-08-03 2011-04-27 群康科技(深圳)有限公司 移位寄存器和采用该移位寄存器的液晶显示装置
EP2189987B1 (fr) 2007-09-12 2013-02-13 Sharp Kabushiki Kaisha Registre à décalage
WO2009104307A1 (fr) 2008-02-19 2009-08-27 シャープ株式会社 Circuit de registre à décalage, dispositif d'affichage et procédé pour commander un circuit de registre à décalage
US9281077B2 (en) 2009-02-25 2016-03-08 Sharp Kabushiki Kaisha Shift register and display device
US8422622B2 (en) * 2009-06-15 2013-04-16 Sharp Kabushiki Kaisha Shift register and display device
US8384461B2 (en) * 2009-06-15 2013-02-26 Sharp Kabushiki Kaisha Shift register and display device
TWM373545U (en) * 2009-08-03 2010-02-01 Chunghwa Picture Tubes Ltd Gate driving circuit of display panel
KR101250158B1 (ko) 2009-11-04 2013-04-05 샤프 가부시키가이샤 시프트 레지스터, 그것을 구비한 주사 신호선 구동 회로 및 표시 장치
US8731135B2 (en) * 2010-01-29 2014-05-20 Sharp Kabushiki Kaisha Shift register and display device
WO2011114563A1 (fr) 2010-03-19 2011-09-22 シャープ株式会社 Registre à décalage
US8781059B2 (en) 2010-05-24 2014-07-15 Sharp Kabushiki Kaisha Shift register
JP5774011B2 (ja) 2011-12-28 2015-09-02 株式会社Ｊｏｌｅｄ シフトレジスタ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58151719A (ja) * 1982-03-05 1983-09-09 Sony Corp パルス発生回路
JP2006106320A (ja) * 2004-10-05 2006-04-20 Alps Electric Co Ltd 液晶表示装置の駆動回路
JP2006178165A (ja) * 2004-12-22 2006-07-06 Alps Electric Co Ltd ドライバ回路、シフトレジスタ及び液晶駆動回路

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281077B2 (en) 2009-02-25 2016-03-08 Sharp Kabushiki Kaisha Shift register and display device
US8384461B2 (en) 2009-06-15 2013-02-26 Sharp Kabushiki Kaisha Shift register and display device
JP5405570B2 (ja) * 2009-06-15 2014-02-05 シャープ株式会社 シフトレジスタおよび表示装置
JP5410521B2 (ja) * 2009-06-15 2014-02-05 シャープ株式会社 シフトレジスタおよび表示装置
JPWO2010146738A1 (ja) * 2009-06-15 2012-11-29 シャープ株式会社 シフトレジスタおよび表示装置
US8422622B2 (en) 2009-06-15 2013-04-16 Sharp Kabushiki Kaisha Shift register and display device
US8731135B2 (en) 2010-01-29 2014-05-20 Sharp Kabushiki Kaisha Shift register and display device
WO2011092924A1 (fr) * 2010-01-29 2011-08-04 シャープ株式会社 Registre à décalage et dispositif d'affichage
WO2011114569A1 (fr) * 2010-03-15 2011-09-22 シャープ株式会社 Registre à décalage, circuit d'attaque de ligne de signal de balayage et dispositif d'affichage
US8537094B2 (en) 2010-03-24 2013-09-17 Au Optronics Corporation Shift register with low power consumption and liquid crystal display having the same
JP2011204343A (ja) * 2010-03-24 2011-10-13 Au Optronics Corp 低電力消費のシフトレジスタ
JP5420072B2 (ja) * 2010-05-24 2014-02-19 シャープ株式会社 シフトレジスタ
KR101756667B1 (ko) 2011-04-21 2017-07-11 엘지디스플레이 주식회사 쉬프트 레지스터 및 이를 포함하는 표시장치
CN102750987A (zh) * 2011-04-21 2012-10-24 乐金显示有限公司 移位寄存器
WO2012169590A1 (fr) * 2011-06-10 2012-12-13 シャープ株式会社 Registre à décalage et dispositif d'affichage équipé de ce registre à décalage
TWI550587B (zh) * 2014-02-27 2016-09-21 上海和輝光電有限公司 一種閘極驅動電路及顯示面板
WO2016197531A1 (fr) * 2015-06-08 2016-12-15 京东方科技集团股份有限公司 Unité de registre à décalage et son procédé d'attaque, circuit d'attaque de grille et appareil d'affichage
CN106548744A (zh) * 2017-01-20 2017-03-29 京东方科技集团股份有限公司 栅极驱动单元及其驱动方法、栅极驱动电路和显示装置
WO2018133520A1 (fr) * 2017-01-20 2018-07-26 京东方科技集团股份有限公司 Unité d'attaque de grille et son procédé d'attaque, circuit d'attaque de grille et appareil d'affichage
US11107380B2 (en) 2017-01-20 2021-08-31 Boe Technology Group Co., Ltd. GOA unit and method of driving the same, GOA circuit and display apparatus
WO2021217468A1 (fr) * 2020-04-28 2021-11-04 京东方科技集团股份有限公司 Panneau d'affichage, procédé d'attaque et dispositif d'affichage
US11929030B2 (en) 2020-04-28 2024-03-12 Chengdu Boe Optoelectronics Technology Co., Ltd. Display panel, driving method, and display device
CN112037718A (zh) * 2020-09-23 2020-12-04 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
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