WO2010087269A1 - 不揮発ロジック回路 - Google Patents
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- WO2010087269A1 WO2010087269A1 PCT/JP2010/050708 JP2010050708W WO2010087269A1 WO 2010087269 A1 WO2010087269 A1 WO 2010087269A1 JP 2010050708 W JP2010050708 W JP 2010050708W WO 2010087269 A1 WO2010087269 A1 WO 2010087269A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5607—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using magnetic storage elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/18—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
Definitions
- the present invention relates to a nonvolatile logic circuit, and more particularly to a nonvolatile logic circuit using a magnetoresistive element.
- Reconfigurable logic which is a rewritable logic device
- Reconfigurable logic for example, a field programmable gate array (FPGA) in which basic logic blocks are arranged on an array and logic can be reconfigured has been put into practical use.
- FPGA field programmable gate array
- variable logic integrated circuit As an example of the FPGA, a variable logic integrated circuit is disclosed in Japanese Patent Laid-Open No. 9-148440 (corresponding US Pat. No. 5,825,203).
- This variable logic integrated circuit includes a plurality of variable logic blocks configured to change logic functions and a plurality of variable wiring circuits configured to change wiring connections in a vertical direction and a horizontal direction on a semiconductor chip. They are arranged alternately, and wirings used for other purposes are formed above the variable logic block without being connected to the variable logic block.
- Japanese Patent Application Laid-Open No. 2006-32951 discloses a unipolar resistance variable PCMO register adjusting circuit.
- This single polarity variable resistance PCMO register adjustment circuit is a circuit that reversibly adjusts the resistance value of the matching register with respect to the resistance value of the reference register.
- the material of the matching resistor is composed of a programmable resistance material having a single polarity variable resistance characteristic.
- the circuit comprises a resistor bridge network comprising a reference register and a matching register, and a pulse feedback circuit.
- the resistive bridge network compares the resistance states of the reference register and the matching register and generates a comparison signal that indicates the difference between the reference register and the matching register.
- the pulse feedback circuit is connected to the resistor bridge network and supplies a single polarity electrical pulse signal in response to the comparison signal to modify the resistance value of the matching register relative to the resistance value of the reference register.
- configuration information is stored in an SRAM (Static Random Access Memory). Therefore, in order to retain the configuration information when the power is turned off, it is necessary to separately provide a nonvolatile memory such as a flash memory. Therefore, there is a problem that the area of the element is increased by the amount of the nonvolatile memory.
- SRAM Static Random Access Memory
- a method of making a non-volatile logic circuit in which the logic element and the memory are replaced with an element having both the logic element and the memory can be considered. If this method can be realized, the element can be configured more compactly than the above-described method in which the SRAM is replaced with a nonvolatile memory.
- An example of this method is a single polarity variable resistance PCMO register adjustment circuit disclosed in Japanese Patent Application Laid-Open No. 2006-32951, which is a reconfigurable nonvolatile logic circuit using a Spin MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor). .
- the Spin MOSFET has a problem that stable operation at room temperature is difficult due to poor spin injection efficiency from the magnetic material to the semiconductor.
- An object of the present invention is to provide a nonvolatile logic circuit that can operate at room temperature and has both a logic element and a memory.
- the nonvolatile logic circuit of the present invention includes an input unit, a control unit, and an output unit.
- the input unit includes a ferromagnetic layer having perpendicular magnetic anisotropy and capable of changing a magnetization state.
- the control unit includes a ferromagnetic layer.
- the output unit includes a magnetic tunnel coupling element provided in the vicinity of the input unit and the control unit and capable of changing the magnetization state.
- the magnetization state of the input unit changes corresponding to the input data.
- the magnetization state of the magnetic tunnel coupling element of the output unit changes corresponding to the magnetization state of the input unit and the control unit.
- the non-volatile logic circuit includes an input unit including a ferromagnetic layer having perpendicular magnetic anisotropy and a changeable magnetization state, and a control unit including a ferromagnetic layer. And an output unit provided in the vicinity of the input unit and the control unit and including a magnetic tunnel coupling element capable of changing a magnetization state.
- the operation method of the non-volatile logic circuit includes the step of inputting control data to the control unit and setting the magnetization state of the ferromagnetic layer of the control unit to correspond to the control data; The step of inputting input data and setting the magnetization state of the ferromagnetic layer of the input unit to correspond to the input data; the magnetization state of the ferromagnetic material of the control unit; and the ferromagnetic state of the ferromagnetic material of the input unit Reading the magnetization state of the magnetic tunnel coupling element of the output section that has changed based on the magnetization state.
- a nonvolatile logic circuit that can operate at room temperature and has both a logic element and a memory can be provided.
- FIG. 1 is a schematic diagram showing the principle of a nonvolatile logic circuit according to an embodiment of the present invention.
- FIG. 2A is a cross-sectional view showing the configuration of the nonvolatile logic circuit according to the first embodiment of the present invention.
- FIG. 2B is a cross-sectional view showing another configuration example of the output unit according to the first embodiment of the present invention.
- FIG. 2C is a plan view schematically showing the structure of the main part of the nonvolatile logic circuit according to the first embodiment of the present invention.
- FIG. 3A is a cross-sectional view showing an example of the magnetization state of the nonvolatile logic circuit according to the first exemplary embodiment of the present invention.
- FIG. 3A is a cross-sectional view showing an example of the magnetization state of the nonvolatile logic circuit according to the first exemplary embodiment of the present invention.
- FIG. 3B is a cross-sectional view showing an example of the magnetization state of the nonvolatile logic circuit according to the first exemplary embodiment of the present invention.
- FIG. 3C is a cross-sectional view showing an example of the magnetization state of the nonvolatile logic circuit according to the first exemplary embodiment of the present invention.
- FIG. 3D is a cross-sectional view showing an example of the magnetization state of the nonvolatile logic circuit according to the first embodiment of the present invention.
- FIG. 3E is a cross-sectional view showing an example of the magnetization state of the nonvolatile logic circuit according to the first exemplary embodiment of the present invention.
- FIG. 3F is a cross-sectional view showing an example of the magnetization state of the nonvolatile logic circuit according to the first exemplary embodiment of the present invention.
- FIG. 3G is a cross-sectional view showing an example of the magnetization state of the nonvolatile logic circuit according to the first embodiment of the present invention.
- FIG. 3H is a cross-sectional view showing an example of the magnetization state of the nonvolatile logic circuit according to the first exemplary embodiment of the present invention.
- FIG. 4 is a schematic diagram showing an example of the relationship between the magnetization direction in the xy plane of the sense layer and the x-direction component of the magnetization according to the first embodiment of the present invention.
- FIG. 5 is a graph showing the relationship between the x component of the magnetization of the sense layer and the x direction component of the combined magnetic field according to the first embodiment of the invention.
- FIG. 6 is a graph showing the relationship between the resistance of the magnetic tunnel junction of the output unit and the x-direction component of the combined magnetic field according to the first embodiment of the present invention.
- FIG. 7A is a table showing the relationship between the magnetization direction of the storage layer A, the magnetization direction of the bias layer, and the combined magnetic field according to the first embodiment of the present invention.
- FIG. 7B is a table showing the relationship between the magnetization direction of the storage layer B, the magnetization direction of the bias layer, and the combined magnetic field according to the first embodiment of the present invention.
- FIG. 8 is a graph showing the relationship between the resistance of the magnetic tunnel junction of the output unit and the x-direction component of the combined magnetic field according to the first embodiment of the present invention.
- FIG. 9A is a table showing the relationship between the magnetization direction of the storage layer A, the magnetization direction of the bias layer, and the input / output data according to the first embodiment of the present invention.
- FIG. 9B is a table showing the relationship between the magnetization direction of the storage layer B, the magnetization direction of the bias layer, and the input / output data according to the first embodiment of the present invention.
- FIG. 10 is a cross-sectional view for explaining the data writing principle in the first embodiment of the present invention.
- FIG. 11 is a cross-sectional view for explaining the principle of reading data in the first embodiment of the present invention.
- FIG. 12 is a block diagram showing an example of the logic gate in the first embodiment of the present invention.
- FIG. 13 is a cross-sectional view showing another configuration example of the nonvolatile logic circuit according to the first embodiment of the present invention.
- FIG. 14 is a cross-sectional view showing a configuration of a nonvolatile logic circuit according to the second embodiment of the present invention.
- FIG. 15 is a perspective view showing the configuration of a nonvolatile logic circuit according to the third embodiment of the present invention.
- FIG. 16 is a sectional view showing the configuration and operation of the input unit 3 according to the third embodiment of the present invention.
- FIG. 17 is a perspective view showing an example of a state of a nonvolatile logic circuit according to the third embodiment of the present invention.
- FIG. 18 is a perspective view showing the configuration of the nonvolatile logic circuit according to the fourth embodiment of the present invention.
- FIG. 19 is a cross-sectional view schematically showing the magnetization state of the nonvolatile logic circuit according to the fourth embodiment of the present invention.
- FIG. 20A is a perspective view showing a configuration of a nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- FIG. 20B is a cross-sectional view showing the configuration of the nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- FIG. 21A is a table showing the relationship between the magnetization directions of the storage layers A and B, the bias layer, and the sense layer according to the fifth embodiment of the present invention.
- FIG. 21A is a table showing the relationship between the magnetization directions of the storage layers A and B, the bias layer, and the sense layer according to the fifth embodiment of the present invention.
- FIG. 21B is a table showing the relationship between the magnetization directions of the storage layers A and B, the bias layer, and the sense layer according to the fifth embodiment of the present invention.
- FIG. 22 is a block diagram showing an example of a logic gate according to the fifth embodiment of the present invention.
- FIG. 23A is a schematic diagram showing a modification of the configuration of the nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- FIG. 23B is a schematic diagram showing a modification of the configuration of the nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- FIG. 23C is a schematic diagram showing a modification of the configuration of the nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- FIG. 23A is a schematic diagram showing a modification of the configuration of the nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- FIG. 23B is a schematic diagram showing a modification of the configuration of the nonvolatile logic circuit according to the fifth exemplary
- FIG. 23D is a schematic diagram showing a modification of the configuration of the nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- FIG. 24A is a diagram for explaining another modification of the configuration of the nonvolatile logic circuit according to the fifth embodiment of the present invention.
- FIG. 24B is a diagram describing another modification of the configuration of the nonvolatile logic circuit according to the fifth embodiment of the present invention.
- FIG. 24C is a diagram illustrating another modification of the configuration of the nonvolatile logic circuit according to the fifth embodiment of the present invention.
- FIG. 25A is a schematic diagram showing still another modified example of the configuration of the nonvolatile logic circuit according to the fifth embodiment of the present invention.
- FIG. 25B is a schematic diagram showing still another modification example of the configuration of the nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- FIG. 26 is a schematic diagram showing another modification of the configuration of the nonvolatile logic circuit according to the fifth embodiment of the present invention.
- FIG. 27 is a schematic diagram showing the principle of the nonvolatile logic circuit according to the embodiment of the present invention.
- FIG. 28A is a perspective view showing a configuration of a nonvolatile logic circuit according to the sixth exemplary embodiment of the present invention.
- FIG. 28B is a cross-sectional view showing the configuration of the nonvolatile logic circuit according to the sixth exemplary embodiment of the present invention.
- FIG. 29A is a table showing the relationship between the magnetization directions of the storage layer A, the bias layer, and the sense layer according to the sixth embodiment of the present invention.
- FIG. 29B is a table showing the relationship between the magnetization directions of the storage layer A, the bias layer, and the sense layer according to the sixth embodiment of the present invention.
- FIG. 30 is a block diagram showing an example of a logic gate in the sixth embodiment of the present invention.
- FIG. 31 is a perspective view showing the configuration of the nonvolatile logic circuit according to the seventh embodiment of the present invention.
- FIG. 32A is a table showing the relationship between the magnetization directions of the memory layers A and B, the bias layer, and the sense layer of each nonvolatile logic circuit according to the seventh embodiment of the present invention.
- FIG. 32B is a table showing the relationship between the magnetization directions of the memory layers A and B, the bias layer, and the sense layer in each nonvolatile logic circuit according to the seventh embodiment of the present invention.
- FIG. 33A is a perspective view showing a configuration of a nonvolatile logic circuit according to the eighth exemplary embodiment of the present invention.
- FIG. 33B is a plan view showing the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 34A is a table showing a relationship between the magnetization switching region and the magnetization direction of the sense layer according to the eighth embodiment of the present invention.
- FIG. 34B is a table showing the relationship between the magnetization switching region and the magnetization direction of the sense layer according to the eighth embodiment of the present invention.
- FIG. 34A is a table showing a relationship between the magnetization switching region and the magnetization direction of the sense layer according to the eighth embodiment of the present invention.
- FIG. 34B is a table showing the relationship between the magnetization switching region and
- FIG. 35A is a schematic diagram showing a modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 35B is a schematic diagram illustrating a modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 35C is a schematic diagram illustrating a modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 35D is a schematic diagram showing a modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 36A is a diagram for explaining another modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 36A is a diagram for explaining another modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 36B is a diagram for explaining another modified example of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 36C is a diagram for explaining another modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 37A is a diagram explaining still another modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 37B is a diagram describing still another modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 38 is a perspective view showing another modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 39 is a schematic diagram showing still another modified example of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- FIG. 40A is a perspective view showing a configuration of a nonvolatile logic circuit according to the ninth exemplary embodiment of the present invention.
- FIG. 40B is a plan view showing the configuration of the nonvolatile logic circuit according to Embodiment 9 of the present invention.
- FIG. 41A is a table showing the relationship between the magnetization switching region and the magnetization direction of the sense layer according to the ninth embodiment of the present invention.
- FIG. 41B is a table showing the relationship between the magnetization switching region and the magnetization direction of the sense layer according to the ninth embodiment of the present invention.
- FIG. 40A is a table showing the relationship between the magnetization switching region and the magnetization direction of the sense layer according to the ninth embodiment of the present invention.
- FIG. 41B is a table showing the relationship between the magnetization switching region and the magnetization direction of the sense layer according to the ninth embodiment of the present
- FIG. 42 is a perspective view showing the configuration of the nonvolatile logic circuit according to the tenth embodiment of the present invention.
- FIG. 43A is a table showing the relationship between the magnetization switching region and the magnetization direction of the sense layer in each nonvolatile logic circuit according to the tenth embodiment of the present invention.
- FIG. 43B is a table showing the relationship between the magnetization switching region and the magnetization direction of the sense layer in each nonvolatile logic circuit according to the tenth embodiment of the present invention.
- FIG. 1 is a schematic diagram showing the principle of a nonvolatile logic circuit according to an embodiment of the present invention.
- the nonvolatile logic circuit includes a plurality of input units, a control unit, and an output unit.
- the plurality of input units include a ferromagnetic layer having perpendicular magnetic anisotropy and capable of changing the magnetization state.
- the control unit includes a ferromagnetic layer (in this figure, the case of in-plane magnetic anisotropy is illustrated).
- the output unit includes a magnetic tunnel coupling element provided in the vicinity of the plurality of input units and the control unit and capable of changing a magnetization state.
- the magnetization state of each of the plurality of input units changes corresponding to the input data.
- the magnetization state of the magnetic tunnel coupling element of the output unit changes corresponding to the magnetization states of the plurality of input units and the control unit. That is, the magnetization state of the magnetic tunnel coupling element of the output unit changes due to the leakage magnetic fields (H1, H2, and H0) that change in accordance with the magnetization states of the plurality of input units and the control unit.
- the control unit, the plurality of input units, and the output unit constitute an element having both a logic element and a memory.
- the magnetization state of the magnetic tunnel coupling element of the output unit is controlled by the leakage magnetic fields (H1, H2, and H0) of two input units and one control unit. It is not limited. That is, as can be understood from the principle diagram shown in FIG. 1, one input unit is omitted, and even one input unit and one control unit are output by the leakage magnetic field (H1, H0). It is possible to control the magnetization state of the magnetic tunnel coupling element. Furthermore, even if the original control unit in FIG. 1 is omitted and one of the input units is used as the control unit, the magnetization state of the magnetic tunnel coupling element of the output unit can be controlled by their leakage magnetic fields (H1, H2). . In these cases, one control unit, one input unit, and one output unit constitute an element having both a logic element and a memory. Conversely, three or more input units may exist. However, these details will be described later.
- FIG. 2A is a cross-sectional view showing the configuration of the nonvolatile logic circuit according to the first embodiment of the present invention.
- the nonvolatile logic circuit 1 includes input units 3 and 4, an output unit 2, and a control unit 5.
- the input unit 3 is, for example, a spin polarized current writing type GMR (Giant MagnetoResistance) element.
- the input unit 3 includes a pinned layer 31, an intermediate layer 32, and a storage layer A33 stacked in the + z direction.
- the pinned layer 31 is provided adjacent to one surface of the intermediate layer 32, and the memory layer A 33 is provided adjacent to the other surface of the intermediate layer 32.
- the pinned layer 31 is a ferromagnetic layer having perpendicular magnetic anisotropy and having a fixed magnetization direction.
- the perpendicular magnetic anisotropy means having a magnetic anisotropy in the z direction perpendicular to the xy plane in the example of this figure. The same applies hereinafter.
- the magnetization direction of the pinned layer 31 is fixed in the ⁇ z direction in the example of this figure.
- the pinned layer 31 is composed of a plurality of ferromagnetic layers having a laminated ferricouple to firmly fix the magnetization (ferromagnetic layer 31a, nonmagnetic layer 31b, ferromagnetic layer 31c).
- An antiferromagnetic layer may be adjacent to the ferromagnetic layer to firmly fix the magnetization.
- the storage layer A33 is a ferromagnetic layer whose magnetization direction can be changed.
- the memory layer A33 preferably has perpendicular magnetic anisotropy.
- the magnetization direction of the memory layer A33 can be reversed to either the + z direction or the -z direction in the example of this drawing.
- Input data is input to the memory layer A33. Specifically, a write current corresponding to input data is supplied.
- the direction of magnetization of the memory layer A33 is reversed by the interaction with the spin electrons of the pinned layer 31 when the write current passes through the input unit 3 in the z direction. Thereby, input data is stored corresponding to the magnetization direction of the storage layer A33.
- the storage layer A33 can be said to be a free layer in the GMR element.
- the storage layer A33 is magnetically coupled to the output unit 2 as will be described later. Therefore, the magnetization direction of the storage layer A33 affects the magnetization state of the output unit 2.
- the intermediate layer 32 is a nonmagnetic film provided between the pinned layer 31 and the storage layer A33.
- the input unit 4 is, for example, a spin polarized current writing type GMR element.
- the input unit 4 includes a pinned layer 41 (ferromagnetic layer 41a, nonmagnetic layer 41b, ferromagnetic layer 41c), an intermediate layer 42, and a storage layer B43 stacked in the + z direction. These are the same as the pinned layer 31 (the ferromagnetic layer 31a, the nonmagnetic layer 31b, and the ferromagnetic layer 31c), the intermediate layer 32, and the storage layer A33 of the input unit 3, respectively, and thus description thereof is omitted.
- the control unit 5 is a spin polarized current writing type GMR element.
- the control unit 5 includes a bias layer 53, an intermediate layer 52, and a pinned layer 51 that are stacked in the + z direction.
- the pinned layer 51 is provided adjacent to one surface of the intermediate layer 52, and the bias layer 53 is provided adjacent to the other surface of the intermediate layer 52.
- the pinned layer 51 is a ferromagnetic layer having in-plane magnetic anisotropy and a fixed magnetization direction.
- in-plane magnetic anisotropy means having magnetic anisotropy in a direction parallel to the xy plane in the example of this figure. The same applies hereinafter.
- the magnetization direction of the pinned layer 51 is fixed in the + x direction in the example of this figure.
- the pinned layer 51 is composed of a plurality of ferromagnetic layers having a laminated ferri coupling in order to firmly fix the magnetization (ferromagnetic layer 51a, nonmagnetic layer 51b, ferromagnetic layer 51c).
- An antiferromagnetic layer may be adjacent to the ferromagnetic layer to firmly fix the magnetization.
- the bias layer 53 is, for example, a ferromagnetic layer having in-plane magnetic anisotropy and capable of changing the magnetization direction.
- the direction of magnetization of the bias layer 53 can be reversed to either the + x direction or the ⁇ x direction in the example of FIG.
- Control data is input to the bias layer 53. Specifically, a write current corresponding to the control data is supplied.
- the magnetization direction of the bias layer 53 is reversed by the interaction with the spin electrons of the pinned layer 51 when the write current passes through the control unit 5 in the z direction. Thereby, control data is stored corresponding to the magnetization direction of the bias layer 53.
- the bias layer 53 can be referred to as a free layer in the GMR element.
- the bias layer 53 is magnetically coupled to the output unit 2 as will be described later. Therefore, the magnetization direction of the bias layer 53 affects the magnetization state of the output unit 2.
- the bias layer 53 may be a ferromagnetic layer whose magnetization is fixed in the sense of realizing a nonvolatile logic circuit that can operate at room temperature and has both a logic element and a memory.
- a ferromagnetic layer whose magnetization direction can be changed is used.
- the intermediate layer 52 is a nonmagnetic film provided between the pinned layer 51 and the bias layer 53.
- the output unit 2 is a TMR (Tunnel MagnetoResistance) element.
- the output unit 2 includes a sense layer 23, a barrier layer 22, and a reference layer 21 stacked in the + z direction.
- the reference layer 21 is provided adjacent to one surface of the barrier layer 22, and the sense layer 23 is provided adjacent to the other surface of the barrier layer 22.
- the sense layer 23, the barrier layer 22, and the reference layer 21 form a magnetic tunnel junction (MTJ: Magnetoresistive Tunneling Junction).
- MTJ Magnetoresistive Tunneling Junction
- the reference layer 21 is a ferromagnetic layer having in-plane magnetic anisotropy and having a magnetization direction fixed.
- the magnetization direction of the reference layer 21 is fixed in the + x direction in the example of FIG.
- the reference layer 21 may be composed of a plurality of ferromagnetic layers having a laminated ferri coupling (not shown) in order to firmly fix the magnetization, or an antiferromagnetic layer is adjacent to the ferromagnetic layer. It may be configured (not shown).
- the sense layer 23 is a ferromagnetic layer having in-plane magnetic anisotropy and capable of changing the direction of magnetization.
- the magnetization direction of the sense layer 23 can be reversed to either the + x direction or the ⁇ x direction in the example of this drawing.
- the sense layer 23 is magnetically coupled to the storage layer A33, the storage layer B43, and the bias layer 53, as will be described later. Therefore, the magnetization direction of the sense layer 23 is affected by the magnetization state (magnetization direction) of the storage layer A33, the storage layer B43, and the bias layer 53.
- the sense layer 23 output unit 2 is formed so that the y direction is in the easy axis direction and the x direction is in the hard axis direction.
- the magnetization of the sense layer 23 is oriented in the y direction and does not have an x direction component unless it is affected by other influences.
- the direction when affected by the magnetization states of the storage layer A33, the storage layer B43, and the bias layer 53, the direction changes to the magnetization state and has an x-direction component. That is, the direction of magnetization changes due to the combined magnetic field of the storage layer A33, the storage layer B43, and the bias layer 53.
- output data is stored corresponding to the direction of magnetization of the sense layer 23.
- the barrier layer 22 is an insulating film provided between the reference layer 21 and the sense layer 23.
- FIG. 2B is a cross-sectional view showing another configuration example of the output unit according to the first embodiment of the present invention.
- the output unit 2 includes reference layers 21 on both sides of the input units 3 and 4 and the control unit 5 side, and is laminated with a central sense layer 23 via barrier layers 22 respectively. In this case, since the value of the MTJ resistance is doubled, detection becomes easier.
- the input units 3 and 4 and the control unit 5 may be TMR elements.
- the TMR element preferably has a low resistance value.
- the output unit 2 may be a GMR element.
- the memory layer A33 and the memory layer B43 having perpendicular magnetic anisotropy include at least one material selected from Fe, Co, and Ni. Furthermore, perpendicular magnetic anisotropy can be stabilized by including Pt and Pd.
- B, C, N, O, Al, Si, P, Ti, V, Cr, Mn, Cu, Zn, Zr, Nb, Mo, Tc, Ru, Rh, Ag, Hf, Ta, W , Re, Os, Ir, Au, Sm, and the like can be added so that desired magnetic properties are expressed.
- Co Co, Co—Pt, Co—Pd, Co—Cr, Co—Pt—Cr, Co—Cr—Ta, Co—Cr—B, Co—Cr—Pt—B, Co—Cr—Ta— B, Co-V, Co-Mo, Co-W, Co-Ti, Co-Ru, Co-Rh, Fe-Pt, Fe-Pd, Fe-Co-Pt, Fe-Co-Pd, Sm-Co, Examples thereof include Gd—Fe—Co, Tb—Fe—Co, and Gd—Tb—Fe—Co.
- the magnetic anisotropy in the perpendicular direction can also be expressed by alternately stacking layers containing any one material selected from Fe, Co, and Ni and different layers. Specific examples include a laminated film in which Co / Pd, Co / Pt, Co / Ni, and Fe / Au are alternately laminated.
- the pinned layers 31 and 41 can be made of the above ferromagnetic material or an antiferromagnetic material such as PtMn, NiMn, or FeMn.
- the sense layer 23 and the bias layer 53 having in-plane magnetic anisotropy are formed of a ferromagnetic material including at least one material selected from Fe, Co, and Ni.
- B, C, N, O, Al, Si, P, Ti, V, Cr, Mn, Cu, Zn, Zr, Nb, Mo, Tc, Ru, Rh, Ag, Hf, Ta, W , Re, Os, Ir, Au, etc. can be added so that desired magnetic properties can be expressed.
- Ni—Fe, Co—Fe, Fe—Co—Ni, Ni—Fe—Zr, Co—Fe—B, Co—Fe—Zr—B and the like are exemplified.
- the reference layer 21 and the pinned layer 51 can use the above-described ferromagnetic materials or antiferromagnetic materials such as PtMn, NiMn, and FeMn.
- the intermediate layers 32, 42, and 52 can be used for various materials.
- a conductor such as Al, Cr, or Cu can be used.
- an insulator such as Mg—O may be used.
- the intermediate layers 32, 42, and 52 included in the input units 3 and 4 and the control unit 5 where writing is performed exist on the path of the write current as described later. Generally, it is desirable that the resistance of the write current path is low. In this respect, a material having low resistance is preferable.
- Mg—O is preferable.
- the barrier layer 22 is preferably formed of an insulating material. Specific examples of the material include Mg—O, Al—O, Al—N, Ni—O, and Hf—O. However, it is also possible to use a semiconductor or a metal as a material.
- the storage layer A33 of the input unit 3 and the storage layer B43 of the input unit 4 are connected to the lower side of the metal layer 6 extending in the x direction on the upper side (+ z direction side).
- the sense layer 23 of the output unit 2 is connected to the upper side of the metal layer 6 on the lower side ( ⁇ z direction side).
- the reference layer 21 of the output unit 2 is connected to the lower side of the metal layer 7 on the upper side.
- the bias layer 53 of the control layer 5 is connected to the upper side of the metal layer 7 on the lower side thereof.
- the metal layer 6 is connected to a common terminal (Com) 66.
- the metal layer 7 is connected to an output terminal (Out) 67.
- the pinned layer 31 of the input unit 3 is connected to the first input terminal (IN1) 63.
- the pinned layer 41 of the input unit 4 is connected to the second input terminal (IN2) 64.
- the pinned layer 51 of the control unit 5 is connected to a control terminal (Control) 65.
- the metal layer 6, the metal layer 7, the common terminal 66, the output terminal 67, the first input terminal 63, the second input terminal 64, and the control terminal 65 are normal wirings of semiconductor elements exemplified by Cu, Al, and W. And materials used for terminals and vias can be used.
- FIG. 2C is a plan view schematically showing the structure of the main part of the nonvolatile logic circuit according to the first embodiment of the present invention.
- This figure includes each of the input units 3, 4 (storage layer A 33, storage layer B 43), control unit 5 (bias layer 53), and output unit 2 (sense layer 23), for example, including the bottom surface of the output unit 2.
- the positions of the centroids G3, G4, G5, and G2 of the projections of the input units 3, 4, the control unit 5, and the output unit 2 are shown. That is, the positional relationship between the centroids G3, G4, G5, and G2 of the input units 3 and 4, the control unit 5, and the output unit 2 in the xy plane is shown.
- ⁇ i means the total sum related to i.
- the center of gravity is the intersection of diagonal lines, and in the case of an ellipse, the center of gravity is the center.
- the centroids G3 and G4 of the input units 3 and 4 (storage layer A33, storage layer B43) and the centroid G2 of the output unit 2 (sense layer 23) are shifted in the xy plane. That is, on the xy plane, the centroid G3 of the input unit 3 is shifted in the ⁇ x direction from the centroid G2 of the output unit 2, and the centroid G4 of the input unit 4 is shifted in the + x direction from the centroid G2 of the output unit.
- the input units 3 and 4 and the output unit 2 preferably overlap at least partially in the x direction.
- the overlaps a1 and a2 are such that 0 ⁇ a1 ⁇ b1 / 2 and 0 ⁇ a2 ⁇ b2 / 2 if the widths of the input units 3 and 4 in the x direction are b1 and b2. Is preferred.
- the center of gravity G5 of the control unit 5 bias layer 53
- the center of gravity G2 of the output unit 2 sense layer 23
- the gravity center G5 of the control part 5 and the gravity center G2 of the output part 2 have overlapped substantially. That is, the distance a3 between the centers of gravity is preferably such that 0 ⁇ a3 ⁇ b3 / 2 if the width in the x direction between the control unit 5 and the output unit 2 is b3.
- leakage magnetic fields from the input units 3 and 4 (storage layer A33 and storage layer B43) and the control unit 5 (bias layer 53) are output from the output unit 2. It affects the (sense layer 23) and can change its magnetization state.
- the xy cross-sectional shapes of the input units 3 and 4, the control unit 5, and the output unit 2 are rectangular.
- the present invention is not limited to this example, and may have other cross-sectional shapes as long as the magnetization state described later can be changed.
- FIGS. 3A to 3H are cross-sectional views showing examples of magnetization states of the nonvolatile logic circuit according to the first embodiment of the present invention.
- FIGS. 3A to 3D will be described. However, in the following description, the states shown in FIGS. 3A to 3D are referred to as states ⁇ 1 to ⁇ 4, respectively. In the states ⁇ 1 to ⁇ 4, the magnetization direction of the bias layer 53 of the control unit 5 is the + x direction.
- the magnetization of the storage layer A33 of the input unit 3 is oriented in the + z direction.
- the magnetization of the storage layer B43 of the input unit 4 is in the + z direction.
- the magnetization of the bias layer 53 of the control unit 5 is in the + x direction. Therefore, the memory layer A33 generates a leakage magnetic field Hst1 that exits from the upper portion (the portion on the + z direction side), penetrates the sense layer 23 in the approximately + x direction, and returns to the lower portion (the portion on the ⁇ z direction side).
- the memory layer B43 generates a leakage magnetic field Hst2 that exits from the upper part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the lower part.
- the bias layer 53 generates a leakage magnetic field Hcontrol that exits from the right portion (the + x direction side portion), penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the left portion (the ⁇ x direction side portion). To do.
- FIG. 4 is a schematic diagram showing an example of the relationship between the magnetization direction in the xy plane of the sense layer and the x-direction component of the magnetization according to the first embodiment of the present invention.
- the vertical axis indicates the y-axis direction
- the horizontal axis indicates the x-axis direction.
- the y direction is the easy axis direction. Therefore, when there is no influence of other magnetic fields, the magnetization M of the sense layer 23 is oriented in the y direction and has no x direction component.
- the sense layer 23 is affected by the magnetic field Hs obtained by combining the leakage magnetic field Hst1, the leakage magnetic field Hst2, and the leakage magnetic field Hcontrol.
- the magnetization M of the sense layer 23 rotates from the direction in the y direction according to the direction and magnitude of the synthetic magnetic field Hs.
- the rotation causes a deviation of the angle ⁇ ( ⁇ ⁇ 90 degrees) from the + x direction
- the magnetization M of the sense layer 23 has a component in the ⁇ x direction. Its size and the like will be described later.
- the magnetization of the storage layer A33 of the input unit 3 is oriented in the + z direction.
- the magnetization of the storage layer B43 of the input unit 4 is in the -z direction.
- the magnetization of the bias layer 53 of the control unit 5 is in the + x direction. Therefore, the memory layer A33 generates a leakage magnetic field Hst1 that exits from the upper part, penetrates the sense layer 23 in the + x direction, and returns to the lower part.
- the memory layer B43 generates a leakage magnetic field Hst2 that exits from the lower part, penetrates the sense layer 23 in the + x direction, and returns to the upper part.
- the bias layer 53 generates a leakage magnetic field Hcontrol that exits from the right part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the left part.
- the magnetization M of the sense layer 23 has a component in the + x direction due to the combined magnetic field Hs. Its size and the like will be described later.
- the magnetization of the storage layer A33 of the input unit 3 is in the ⁇ z direction.
- the magnetization of the storage layer B43 of the input unit 4 is in the + z direction.
- the magnetization of the bias layer 53 of the control unit 5 is in the + x direction. Therefore, the memory layer A33 generates a leakage magnetic field Hst1 that exits from the lower part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the upper part. Further, the memory layer B43 generates a leakage magnetic field Hst2 that exits from the upper part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the lower part.
- the bias layer 53 generates a leakage magnetic field Hcontrol that exits from the right part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the left part.
- the magnetization M of the sense layer 23 has a component in the ⁇ x direction due to the combined magnetic field Hs. Its size and the like will be described later.
- the magnetization of the storage layer A33 of the input unit 3 is in the ⁇ z direction.
- the magnetization of the storage layer B43 of the input unit 4 is in the -z direction.
- the magnetization of the bias layer 53 of the control unit 5 is in the + x direction. Therefore, the memory layer A33 generates a leakage magnetic field Hst1 that exits from the lower part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the upper part.
- the memory layer B43 generates a leakage magnetic field Hst2 that exits from the lower part, penetrates the sense layer 23 in the + x direction, and returns to the upper part.
- the bias layer 53 generates a leakage magnetic field Hcontrol that exits from the right part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the left part.
- Hcontrol a leakage magnetic field
- the magnetization M of the sense layer 23 has a component in the ⁇ x direction due to the combined magnetic field Hs. Its size and the like will be described later.
- FIGS. 3E to 3H will be described. However, in the following description, the states shown in FIGS. 3E to 3H are referred to as states ⁇ 1 to ⁇ 4, respectively. In the states ⁇ 1 to ⁇ 4, the magnetization direction of the bias layer 53 of the control unit 5 is the ⁇ x direction.
- the magnetization of the storage layer A33 of the input unit 3 is oriented in the + z direction.
- the magnetization of the storage layer B43 of the input unit 4 is in the + z direction.
- the magnetization of the bias layer 53 of the control unit 5 is in the ⁇ x direction. Therefore, the memory layer A33 generates a leakage magnetic field Hst1 that exits from the upper part, penetrates the sense layer 23 in the + x direction, and returns to the lower part. Further, the memory layer B43 generates a leakage magnetic field Hst2 that exits from the upper part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the lower part.
- the bias layer 53 generates a leakage magnetic field Hcontrol that exits from the left portion (the portion on the ⁇ x direction side), penetrates the sense layer 23 substantially in the + x direction, and returns to the right portion (the portion on the + x direction side). .
- the magnetization of the storage layer A33 has a component in the + x direction due to the combined magnetic field Hs. Its size and the like will be described later.
- the magnetization of the storage layer A33 of the input unit 3 is oriented in the + z direction.
- the magnetization of the storage layer B43 of the input unit 4 is in the -z direction.
- the magnetization of the bias layer 53 of the control unit 5 is in the ⁇ x direction. Therefore, the memory layer A33 generates a leakage magnetic field Hst1 that exits from the upper part, penetrates the sense layer 23 in the + x direction, and returns to the lower part.
- the memory layer B43 generates a leakage magnetic field Hst2 that exits from the lower part, penetrates the sense layer 23 in the + x direction, and returns to the upper part.
- the bias layer 53 generates a leakage magnetic field Hcontrol that exits from the left part, penetrates the sense layer 23 in the + x direction, and returns to the right part.
- the magnetization of the storage layer A33 has a component in the + x direction due to the combined magnetic field Hs. Its size and the like will be described later.
- the magnetization of the storage layer A33 of the input unit 3 is in the ⁇ z direction.
- the magnetization of the storage layer B43 of the input unit 4 is in the + z direction.
- the magnetization of the bias layer 53 of the control unit 5 is in the ⁇ x direction. Therefore, the memory layer A33 generates a leakage magnetic field Hst1 that exits from the lower part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the upper part. Further, the memory layer B43 generates a leakage magnetic field Hst2 that exits from the upper part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the lower part.
- the bias layer 53 generates a leakage magnetic field Hcontrol that exits from the left part, penetrates the sense layer 23 in the + x direction, and returns to the right part.
- the magnetization of the storage layer A33 has a component in the ⁇ x direction due to the combined magnetic field Hs. Its size and the like will be described later.
- the magnetization of the storage layer A33 of the input unit 3 is in the ⁇ z direction.
- the magnetization of the storage layer B43 of the input unit 4 is in the -z direction.
- the magnetization of the bias layer 53 of the control unit 5 is in the ⁇ x direction. Therefore, the memory layer A33 generates a leakage magnetic field Hst1 that exits from the lower part, penetrates the sense layer 23 in the approximately ⁇ x direction, and returns to the upper part.
- the memory layer B43 generates a leakage magnetic field Hst2 that exits from the lower part, penetrates the sense layer 23 in the + x direction, and returns to the upper part.
- the bias layer 53 generates a leakage magnetic field Hcontrol that exits from the left part, penetrates the sense layer 23 in the + x direction, and returns to the right part.
- the magnetization of the storage layer A33 has a component in the + x direction due to the combined magnetic field Hs. Its size and the like will be described later.
- the combined magnetic field Hs obtained by combining the leakage magnetic field Hst1, the leakage magnetic field Hst2, and the leakage magnetic field Hcontrol changes the magnetization direction of the sense layer 23 so that a plurality of types of x-direction components Mx can be obtained. become.
- the leakage magnetic field Hcontrol from the bias layer 53 in FIGS. 3A to 3D functions as a bias magnetic field in the combined magnetic field Hs.
- the leakage magnetic field Hcontrol from the bias layer 53 in FIGS. 3E to 3H functions as a bias magnetic field in the combined magnetic field Hs.
- FIG. 5 is a graph showing the relationship between the x component of the magnetization of the sense layer and the x direction component of the combined magnetic field according to the first embodiment of the invention.
- the vertical axis represents the x-direction component Mx of the magnetization M of the sense layer 23, and the horizontal axis represents the x-direction component Hsx of the combined magnetic field Hs.
- the magnetic field ⁇ Hk indicates the saturation magnetic field of the sense layer 23.
- the magnetization M of the sense layer 23 has the x-direction component Mx according to the combined magnetic field Hs.
- FIG. 6 is a graph showing the relationship between the resistance of the magnetic tunnel junction of the output unit and the x-direction component of the combined magnetic field according to the first embodiment of the present invention.
- the vertical axis represents the resistance of the magnetic tunnel junction (MTJ) of the output unit 2
- the horizontal axis represents the x-direction component Hsx of the combined magnetic field Hs.
- the MTJ resistance is applied as follows by the magnetic field Hsx applied to the sense layer 23.
- FIG. 7A and 7B are tables showing the relationship between the magnetization direction of the storage layers A and B, the magnetization direction of the bias layer, and the combined magnetic field Hsx according to the first embodiment of the present invention.
- FIG. 7A shows a case where the magnetization direction of the bias layer 53 of the control unit 5 is the + x direction.
- FIG. 7B shows a case where the magnetization direction of the bias layer 53 is the + x direction.
- Hsx Leakage magnetic field Hst1 from the storage layer A33 + Leakage magnetic field Hst2 from storage layer B43 + Leakage magnetic field Hcontrol from bias layer 53
- s is the magnitude of the leakage magnetic field (x-direction component) from the storage layer A33 and the storage layer B43
- b is the magnitude of the leakage magnetic field (x-direction component) from the bias layer 53.
- FIG. 7A the relationship between the magnetization direction of the storage layer A and the storage layer B43, the magnetization direction of the bias layer 53, and the combined magnetic field Hsx is as shown in FIG. 7A. become.
- the states ⁇ 1 to ⁇ 4 shown in FIGS. 3E to 3H are as shown in FIG. 7B.
- the magnetization of the storage layer A33 is in the + z direction
- the magnetization of the storage layer B43 is in the + z direction
- the magnetization of the storage layer A33 is in the + z direction
- the magnetization of the storage layer B43 is in the ⁇ z direction
- the magnetization of the storage layer A33 is in the ⁇ z direction
- the magnetization of the storage layer B43 is in the + z direction
- the magnetization of the storage layer A33 is in the ⁇ z direction
- the magnetization of the storage layer B43 is in the ⁇ z direction
- the magnetization of the storage layer A33 is in the + z direction
- the magnetization of the storage layer B43 is in the + z direction
- the magnetization of the bias layer 53 is in the ⁇ x direction.
- the magnetization of the storage layer A33 is in the + z direction
- the magnetization of the storage layer B43 is in the ⁇ z direction
- the magnetization of the storage layer A33 is in the ⁇ z direction
- the magnetization of the storage layer B43 is in the + z direction
- the magnetization of the storage layer A33 is in the ⁇ z direction
- the magnetization of the storage layer B43 is in the ⁇ z direction
- states ⁇ 1 to ⁇ 4 (FIG. 7A) and states ⁇ 1 to ⁇ 4 (FIG. 7B) corresponding to combinations of the magnetization state of the storage layer A33, the magnetization state of the storage layer B43, and the magnetization state of the bias layer 53.
- a combined magnetic field Hsx of leakage magnetic fields (x-direction components) from each layer can be associated with each.
- FIG. 8 is a graph showing the relationship between the resistance of the magnetic tunnel junction of the output unit and the x-direction component of the combined magnetic field according to the first embodiment of the present invention.
- the vertical axis represents the resistance of the magnetic tunnel junction (MTJ) of the output unit 2
- the horizontal axis represents the x-direction component Hsx of the combined magnetic field Hs.
- MTJ magnetic tunnel junction
- Hsx the combined magnetic field Hs.
- one MTJ resistor is determined for each of the combined magnetic fields Hsx in the states ⁇ 1 to ⁇ 4 and the states ⁇ 1 to ⁇ 4 described with reference to FIGS. 7A to 7B.
- the states ⁇ 1, ⁇ 3, ⁇ 4, and ⁇ 3 are set to “1”, and the states ⁇ 2, ⁇ 1, ⁇ 2, and ⁇ 4 are set to “0”. Each can be made to correspond.
- FIG. 9A and 9B are tables showing the relationship between the magnetization directions of the storage layers A and B, the magnetization direction of the bias layer, and the input / output data according to the first embodiment of the present invention.
- FIG. 9A shows a case where the magnetization direction of the bias layer 53 of the control unit 5 is the + x direction.
- FIG. 9B shows a case where the magnetization direction of the bias layer 53 is the + x direction.
- “IN1” indicates the first input data input (stored) in the input unit 3.
- “IN1” is set so that the + z direction (upward arrow) of the magnetization direction of the storage layer A33 corresponds to data “1”, and the ⁇ z direction (downward arrow) corresponds to data “0”.
- anti-parallel corresponds to data “1” and parallel corresponds to data “0”.
- “IN2” indicates the second input data input (stored) in the input unit 4.
- “IN2” is set such that the + z direction of the magnetization direction of the storage layer B43 corresponds to data “0”, and the ⁇ z direction corresponds to data “1”.
- antiparallel corresponds to data “0” and parallel corresponds to data “1”.
- a method of writing (inputting) each data to the input unit 4 will be described later.
- Control indicates control data input (stored) in the control unit 5.
- “Control” is set such that the + x direction (right arrow) of the magnetization direction of the bias layer 53 corresponds to data “1”, and the ⁇ x direction (left arrow) corresponds to data “0”.
- the parallel corresponds to the data “1”
- the antiparallel corresponds to the data “0”.
- “State” indicates any of the states ⁇ 1 to ⁇ 4 in FIGS. 3A to 3D and the states ⁇ 1 to ⁇ 4 in FIGS. 3E to 3H.
- “Storage layer A” indicates the magnetization direction of the storage layer A 33
- “Storage layer B” indicates the magnetization direction of the storage layer B 43
- “Bias layer C” indicates the magnetization direction of the bias layer 53.
- “OUT” indicates the output data written in the output unit 2. When the MTJ resistance of the output unit 2 is larger than the MTJ reference resistance Rref of FIG. 8, the data is “1”, and when it is smaller, the data is “0”. .
- nonvolatile logic circuit 1 In the nonvolatile logic circuit 1 shown in FIG. 9A, data “1” is assigned to control data (“Control”) of the control unit 5. That is, the bias layer 53 (“bias layer C”) faces the + x direction. In this case, the logical relationship of the output “OUT” with respect to the two inputs “IN1” and “IN2” is NAND. Therefore, the nonvolatile logic circuit 1 functions as a NAND circuit. This is the non-volatile logic circuit 1 of FIGS. 3A to 3D.
- the nonvolatile logic circuit 1 in the present embodiment can be used as a NAND circuit or a NOR circuit by controlling the magnetization state of the bias layer 53 (bias layer C). Therefore, by configuring the NAND circuit and the NOR circuit with the nonvolatile logic circuit 1 in this embodiment and combining them, another logic circuit can be assembled.
- FIG. 10 is a cross-sectional view for explaining the data writing principle in the first embodiment of the present invention.
- control data is written in advance before the operation of the nonvolatile logic circuit 1.
- the non-volatile logic circuit 1 is turned into one of a NAND circuit (FIGS. 3A to 3D, 7A, and 9A) and a NOR circuit (FIGS. 3E to 3H, 7B, and 9B). Can be set.
- the input units 3 and 4 are supplied with first input data and second input data, respectively, when the nonvolatile logic circuit 1 operates.
- the control data is written to the control unit 5 by the following method.
- the control unit 5 is a spin polarized current writing type GMR element.
- a write current Iw is applied between a control terminal (Control) 65 and an output terminal (Out) 67.
- the write current Iw is supplied in a direction corresponding to the control data to be written (the magnetization direction of the bias layer 53). In that case, spin electrons flow in the opposite direction to the write current Iw.
- the magnetization direction of the bias layer 53 when the magnetization direction of the bias layer 53 is desired to be directed to the right (+ x direction), it is caused to flow from the output terminal 67 to the control terminal 65. In this case, spin electrons flow from the control terminal 65 to the output terminal 67. As a result, the magnetization direction of the bias layer 53 is rightward due to the spin torque effect due to the interaction between the ferromagnetic layer 51 a of the pinned layer 51 and the bias layer 53.
- the current when it is desired to set the magnetization direction of the bias layer 53 to the left ( ⁇ x direction), the current flows from the control terminal 65 to the output terminal 67. In this case, spin electrons flow from the output terminal 67 to the control terminal 65. As a result, the magnetization direction of the bias layer 53 is leftward due to the spin torque effect due to the interaction between the ferromagnetic layer 51a and the bias layer 53.
- the input unit 3 is a spin polarized current writing type GMR element.
- a write current Iw 1 is applied between the first input terminal (IN 1) 63 and the common terminal (Com) 66.
- the write current Iw1 is supplied in a direction corresponding to the first input data to be written (the magnetization direction of the storage layer A33). In that case, spin electrons flow in the opposite direction to the write current Iw1.
- the magnetization direction of the storage layer A33 when the magnetization direction of the storage layer A33 is desired to be upward (+ z direction), the first input terminal 63 is passed to the common terminal 66. In this case, spin electrons flow from the common terminal 66 to the first input terminal 63. As a result, the magnetization direction of the memory layer A33 becomes upward due to the spin torque effect caused by the interaction between the ferromagnetic layer 31a of the pinned layer 31 and the memory layer A33.
- the magnetization direction of the storage layer A33 when the magnetization direction of the storage layer A33 is desired to be downward ( ⁇ z direction), the current flows from the common terminal 66 to the first input terminal 63. In this case, spin electrons flow from the first input terminal 63 to the common terminal 66. As a result, the magnetization direction of the memory layer A33 becomes downward due to the spin torque effect due to the interaction between the ferromagnetic layer 31a and the memory layer A33.
- the input unit 4 is a spin polarized current writing type GMR element.
- the write current Iw 2 is applied between the second input terminal (IN 2) 64 and the common terminal (Com) 66.
- the write current Iw2 is caused to flow in a direction corresponding to the second input data to be written (the magnetization direction of the storage layer B43). In that case, spin electrons flow in the direction opposite to the write current Iw2.
- the magnetization direction of the storage layer B43 when the magnetization direction of the storage layer B43 is desired to be upward (+ z direction), it is caused to flow from the second input terminal 64 to the common terminal 66. In this case, spin electrons flow from the common terminal 66 to the second input terminal 64. As a result, the magnetization direction of the storage layer B43 becomes upward due to the spin torque effect caused by the interaction between the ferromagnetic layer 41a of the pinned layer 41 and the storage layer B43.
- the magnetization direction of the memory layer B 43 when the magnetization direction of the memory layer B 43 is desired to be downward ( ⁇ z direction), the current flows from the common terminal 66 to the second input terminal 64. In this case, spin electrons flow from the second input terminal 64 to the common terminal 66. As a result, the magnetization direction of the memory layer B43 is downward due to the spin torque effect caused by the interaction between the ferromagnetic layer 41a and the memory layer B43.
- FIG. 11 is a cross-sectional view for explaining the principle of reading data in the first embodiment of the present invention.
- the output unit 2 is a TMR element.
- the output unit 2 is configured to combine the magnetization states of the input units 3, 4 and the control unit 5 by the leakage magnetic field (synthetic magnetic field Hs) from the input units 3, 4 and the control unit 5. It changes to the magnetized state corresponding to. That is, the magnetization of the sense layer 23 of the output unit 2 changes in a direction corresponding to a combination of control data, first input data, and second input data.
- the MTJ resistance of the output unit 2 has a value corresponding to a combination of control data, first input data, and second input data.
- the value of the MTJ resistance can be read by applying a read current IR between the common terminal (Com) 66 and the output terminal (Out) 67.
- the direction of the read current IR is not particularly limited.
- the MTJ resistance becomes output data of the nonvolatile logic circuit 1.
- the output terminal (Out) 67 is different between the write current IW and the read current IR.
- FIG. 12 is a block diagram showing an example of the logic gate in the first embodiment of the present invention.
- the logic gate 80 includes a control circuit 81, a nonvolatile logic circuit 1, an MTJ reference element 83, and a comparator 82.
- the control circuit 81 includes a switch for converting a logic input and a logic control value into a current. In response to the supply of control data, the control circuit 81 generates a write current having a magnitude and direction corresponding to the control data, and controls the control unit 5 (Control) and output terminal (Out) of the nonvolatile logic circuit 1. And supply between. Further, in response to the supply of the first input data, a write current having a magnitude and direction corresponding to the first input data is generated, and the input unit 3 (IN1) of the nonvolatile logic circuit 1 and the common terminal (Com) ) Supply between.
- a write current having a magnitude and direction corresponding to the second input data is generated, and the input unit 4 (IN2) of the nonvolatile logic circuit 1 and the common terminal ( Com). Further, an output read current is passed between the common terminal (Com) and the output terminal (Out).
- the nonvolatile logic circuit 1 is as described with reference to FIGS. That is, based on the input of the write current corresponding to the input data by the control circuit 80, the output current (or output voltage) as the output data is output by supplying the read current.
- the MTJ reference element 83 is a TMR element having an MTJ, for example.
- the MTJ reference element 83 has the MTJ reference resistance Rref shown in FIG. 8 and outputs a reference current (or reference voltage) corresponding to the MTJ reference resistance Rref under the control of the control circuit 80.
- the comparator 82 compares the output current (or output voltage) indicating the output data of the nonvolatile logic circuit 1 with the reference current (or reference voltage), and outputs the final output data.
- control circuit 81 causes a write current to flow between the control terminal (Control) and the output terminal (Out) of the nonvolatile logic circuit 1 in response to the input of the control data.
- the direction of the write current is set so that the magnetization state (magnetization direction) of the control unit 5 (bias layer 53) becomes the magnetization state (magnetization direction) corresponding to the control data.
- the control circuit 81 supplies a write current between the first input terminal (IN1) and the common terminal (Com) of the nonvolatile logic circuit 1 in response to the input of the first input data.
- the direction of the write current is set so that the magnetization state (magnetization direction) of the input unit 3 (storage layer A33) becomes the magnetization state (magnetization direction) corresponding to the first input data.
- the control circuit 81 causes a write current to flow between the second input terminal (IN2) and the common terminal (Com) of the nonvolatile logic circuit 1 in response to the input of the second input data.
- the direction of the write current is set so that the magnetization state (magnetization direction) of the input unit 4 (storage layer B43) becomes a magnetization state (magnetization direction) corresponding to the second input data.
- the control circuit 81 writes control data in the control unit 5 before the operation of the nonvolatile logic circuit 1 (step S1). That is, the write current Iw is applied between the control terminal (Control) 65 and the output terminal (Out) 67. The write current Iw is supplied in a direction corresponding to control data to be written (the direction of magnetization in the bias layer 53).
- the non-volatile logic circuit 1 can be set as a desired logic circuit (example: NAND circuit, NOR circuit).
- control circuit 81 writes the first input data to the input unit 3 during the operation of the nonvolatile logic circuit 1 set to a desired logic circuit (step S2). That is, the write current Iw 1 is applied between the first input terminal (IN 1) 63 and the common terminal (Com) 66. The write current Iw1 flows in a direction corresponding to the first input data to be written (the direction of magnetization in the storage layer A33).
- the control circuit 81 writes the second input data to the input unit 4 (step S3). That is, the write current Iw 2 is applied between the second input terminal (IN 2) 64 and the common terminal (Com) 66. The write current Iw2 is passed in a direction corresponding to the second input data to be written (the direction of magnetization in the storage layer B43).
- the control circuit 81 causes the read current IR to flow through the output unit 2 and also causes the read current to flow through the MTJ reference element 83 (step S4). That is, for the output unit 2, the read current IR is passed between the common terminal (Com) 66 and the output terminal (Out) 67. On the other hand, for the MTJ reference element 83, a read current is passed through the MTJ. Accordingly, the comparator 82 compares the output current (or output voltage) from the nonvolatile logic circuit 1 with the output current (or output voltage) from the MTJ reference element 83, and outputs the comparison result as final output data. (Step S5).
- the nonvolatile logic circuit 1 can be set as a desired logic circuit, and input data can be input to the nonvolatile logic circuit 1 and output data from the nonvolatile logic circuit 1 can be output. It becomes.
- the nonvolatile logic circuit 1 of the present embodiment can reconfigure its logic by changing control data input to the control unit 5. That is, the non-volatile logic circuit 1 of the present embodiment includes a reconfigurable logic circuit using a read / write separation type spin injection device (control unit 5, storage units 3 and 4) and an MTJ (output unit 2). Can be realized.
- the nonvolatile logic circuit of the present embodiment stores configuration information (control data) in the control unit 5.
- the control unit 5 can be regarded as a non-volatile memory using a GMR element or a TMR element. By using this nonvolatile memory, it is not necessary to have an SRAM for holding configuration information when the power is turned off. Therefore, it is possible to solve the increase in area due to the non-volatile memory provided as a problem in the FPGA.
- the control unit 5, the storage units 3, 4 and the output unit 2 use magnetoresistive elements such as GMR elements or TMR elements.
- the control unit 5, the storage units 3 and 4, and the output unit 2 function as an element having both a logic element and a nonvolatile memory as a whole. Therefore, even if a magnetoresistive element is used, the size of the element can be kept small as a whole. Further, since the magnetoresistive element can operate at room temperature, the nonvolatile logic circuit of this embodiment can operate at room temperature.
- the present invention can provide a reconfigurable nonvolatile logic circuit element while suppressing an increase in the area of the element.
- the control unit 5 may have perpendicular magnetic anisotropy similar to the input units 3 and 4 instead of in-plane magnetic anisotropy.
- FIG. 13 is a cross-sectional view showing another configuration example of the nonvolatile logic circuit according to the first embodiment of the present invention.
- the nonvolatile logic circuit 1 is different from the nonvolatile logic circuit of FIG. 2A in that the bias layer 53 and the pinned layer 51 of the control unit 5 are formed of a ferromagnetic layer having perpendicular magnetic anisotropy.
- the configurations of the bias layer 53, the intermediate layer 52, and the pinned layer 51 are the same as those of the storage layer A 33 and the storage layer B 43 of the input units 3 and 4, the intermediate layers 32 and 42, and the pinned layers 31 and 41. have.
- the relative positional relationship between the control unit 5 and the output unit 2 in the xy plane is different from that of the nonvolatile logic circuit of FIG. 2A in that they are shifted from each other in the + x direction or the ⁇ x direction. That is, the center of gravity G5 of the control unit 5 (bias layer 53) is xy with respect to the center of gravity G2 of the output unit 2 (sense layer 23), similarly to the centers of gravity G3 and G4 of the input units 3 and 4 shown in FIG. 2C. It is displaced in the plane. That is, on the xy plane, the center of gravity G5 of the control unit 5 is shifted from the center of gravity G2 of the output unit 2 in the + x direction or the ⁇ x direction.
- the control unit 5 and the output unit 2 preferably overlap at least partially in the x direction. That is, the overlap a3 is preferably a condition such that 0 ⁇ a3 ⁇ b3 / 2 when the width b3 of the control unit 5 in the x direction is set.
- these nonvolatile logic circuits 1 can be used as a ternary input logic circuit.
- FIG. 14 is a cross-sectional view showing a configuration of a nonvolatile logic circuit according to the second embodiment of the present invention.
- the nonvolatile logic circuit 1 includes input units 3 and 4, an output unit 2, and a control unit 5.
- the nonvolatile logic circuit 1 is different from the nonvolatile logic circuit 1 of the first embodiment in that the metal layer 6 is not connected to the input unit 4. Accordingly, another metal layer 8 and a common terminal (Com2) 68 are further provided for the input unit 4.
- Com2 common terminal
- the nonvolatile logic circuit 1 of the first embodiment writes the first input data to the input unit 3 (step S2), and writes the second input data to the input unit 4 (step S3). Cannot be performed at the same time.
- the metal layer 6 is connected to both the input portions 3 and 4.
- the metal layer 6 (and the common terminal (Com1) 66) is dedicated to the input unit 3
- the metal layer 8 is dedicated to the common terminal (Com2) 68. It is. Therefore, the operation of writing the first input data to the input unit 3 and the operation of writing the second input data to the input unit 4 can be performed at the same time, so that the operation can be performed at high speed.
- FIG. 15 is a perspective view showing the configuration of a nonvolatile logic circuit according to the third embodiment of the present invention.
- the nonvolatile logic circuit 1 includes input units 3 and 4, an output unit 2, and a control unit 5.
- This non-volatile logic circuit 1 is different from the non-volatile logic circuit 1 of the first embodiment in that the input units 3 and 4 are configured by a domain wall motion type magnetic recording layer extending in the y direction.
- FIG. 16 is a sectional view showing the configuration and operation of the input unit 3 according to the third embodiment of the present invention.
- the input unit 3 is a ferromagnetic layer having perpendicular magnetic anisotropy.
- the input unit 3 includes a first magnetization fixed region 34a, a second magnetization fixed region 34b, and a magnetization switching region 35.
- the magnetization switching region 35 is sandwiched between the first magnetization fixed region 34a and the second magnetization fixed region 34b.
- the magnetization direction of the first magnetization fixed region 34a is substantially fixed in the ⁇ z direction by, for example, the hard layer 38a.
- the magnetization direction of the second magnetization fixed region 34b is substantially fixed in the + z direction by, for example, the hard layer 38b.
- FIG. 16 shows an aspect in which the hard layers 38a and 38b are in contact with the first magnetization fixed region 34a and the second magnetization fixed region 34b, respectively, but the hard layers 38a and 38b are respectively in the first magnetization fixed region 34a and the second magnetization fixed region 34b. Since it is only necessary to fix the magnetization direction of the fixed region 34b, it may be arranged in the vicinity without being in contact with the first magnetization fixed region 34a and the second magnetization fixed region 34b.
- the magnetization direction of the magnetization switching region 35 is not fixed and can be switched between the ⁇ z direction and the + z direction.
- the magnetization state of the input unit 3 is referred to as a “first magnetization state MS1”.
- the magnetization direction of the magnetization switching region 35 is the ⁇ z direction
- the domain wall DW is formed in the vicinity of the boundary between the second magnetization fixed region 34 b and the magnetization switching region 35.
- the magnetization state of the input unit 3 is referred to as a “second magnetization state MS2”.
- the magnetization state of these input units 3, that is, the magnetization direction of the magnetization switching region 35 can be changed by flowing a write current in the y direction.
- the write current flows between the first input terminal (IN1a) 63a connected to the first magnetization fixed region 34a and the first input terminal (IN1b) 63b connected to the second magnetization fixed region 34b.
- the first write current IW1 is changed from the first input terminal (IN1b) 63b to the first input terminal (IN1a). 63a.
- spin-polarized electrons in the ⁇ z direction are supplied from the first magnetization fixed region 34 a to the magnetization switching region 35. Due to the spin torque effect, the domain wall DW is driven and moves from the first magnetization fixed region 34a side to the second magnetization fixed region 34b side. As a result, the magnetization direction of the magnetization switching region 35 is reversed in the ⁇ z direction, and the second magnetization state MS2 is obtained.
- the second write current IW2 is passed from the first input terminal (IN1a) 63a to the first input terminal (IN1b) 63b.
- spin-polarized electrons in the + z direction are supplied from the second magnetization fixed region 34b to the magnetization switching region 35.
- the domain wall DW is driven by the spin torque effect and moves from the second magnetization fixed region 34b side to the first magnetization fixed region 34a side.
- the magnetization direction of the magnetization switching region 35 is reversed in the + z direction, and the first magnetization state MS1 is obtained.
- the domain wall DW is moved by the write current flowing between the first magnetization fixed region 34a and the second magnetization fixed region 34b.
- the magnetization direction of the magnetization switching region 35 is reversed, and the magnetization state of the input unit 3 is changed. That is, input data is input to the input unit 3.
- Which of the first magnetization state MS1 and the second magnetization state MS2 is obtained depends on the direction of the write current. In other words, input data to be input to the input unit 3 can be set by controlling the direction of the write current.
- the first magnetization fixed region 44a, the second magnetization fixed region 44b, the magnetization switching region 45, the second input terminal (IN2a) 64a, the second input terminal (IN2b) 64b, and the hard layers 48a and 48b in the input unit 4 are: This corresponds to the first magnetization fixed region 34a, the second magnetization fixed region 34b, the magnetization switching region 35, the first input terminal (IN1a) 63a, the first input terminal (IN1b) 63b, and the hard layers 38a and 38b in the input unit 3.
- the same material as the memory layer A33 and the memory layer B43 in the first embodiment can be used for the ferromagnetic layer having perpendicular magnetic anisotropy constituting the input units 3 and 4.
- the hard layers 38a, 38b, 48a, 48b can be made of an antiferromagnetic material such as PtMn, NiMn, FeMn.
- FIG. 2C The positional relationship between the input units 3 and 4 and the output unit 2 is shown in FIG. 2C when the magnetization switching regions 35 and 45 in this embodiment are regarded as the memory layer A33 and the memory layer B43 in the first embodiment. It is as follows.
- FIG. 17 is a perspective view showing an example of the state of the nonvolatile logic circuit according to the third embodiment of the present invention.
- the description of the control layer 5, the metal layers 6 and 7, the control terminal 65, the common terminal 66, and the output terminal 67 is omitted for easy understanding.
- This figure shows the state ⁇ 3 shown in FIG. 2C or the state ⁇ 3 shown in FIG. 3C.
- the input unit 3 is in the second magnetization state MS2, and the input unit 4 is in the first magnetization state MS1.
- the leakage magnetic field Hst1 from the magnetization switching region 35 and the leakage magnetic field Hst2 from the magnetization switching region 45 affect the magnetization state of the sense layer 23 of the output unit 2.
- the functions of the magnetization switching regions 35 and 45 are the same as those of the storage layers A33 and 43 in the input units 3 and 4 of the first embodiment.
- nonvolatile logic 1 of the present embodiment is such that the magnetization switching regions 35 and 45 of the input units 3 and 4 are changed to the storage layers A33 and 43 in the input units 3 and 4 of the first embodiment. Since this is the same as the case where it is considered, the description thereof will be omitted.
- the metal layer 6 may not be electrically connected to the input units 3 and 4. Further, when the metal layer 6 is connected to at least one of the input units 3 and 4, the common terminal (Com) 66 is not provided, and the input terminals of these input units can be substituted.
- the terminals for supplying current to the input units 3 and 4 are independent of each other. That is, the operation of writing the first input data to the input unit 3 and the operation of writing the second input data to the input unit 4 can be performed simultaneously. Thereby, the operation can be speeded up.
- FIG. 18 is a perspective view showing the configuration of the nonvolatile logic circuit according to the fourth embodiment of the present invention.
- the non-volatile logic circuit 1 includes input units 3 and 4, an output unit 2, and other input units 5 and 9.
- This non-volatile logic circuit 1 is different from the first embodiment in which the input unit 5 and 9 are provided above the output unit 2 and the control unit 5 is provided above the output unit 2. That is, the non-volatile logic circuit 1 of this embodiment is different from the 2-input non-volatile logic circuit 1 of the first embodiment in that it has four inputs.
- the configuration of the input units 5 and 9 is the same as the configuration of the input units 3 and 4 inverted upside down. That is, the input unit 5 includes the storage layer C58, the intermediate layer 57, and the pinned layer 56 in this order from the lower side (the ⁇ z direction side).
- the input unit 9 includes a storage layer D93, an intermediate layer 92, and a pinned layer 91 in this order from the lower side.
- the input units 3 and 4 are arranged in the x direction on the lower side ( ⁇ z direction side) of the output unit 2, but the input units 5 and 9 are arranged on the upper side of the output unit 2 (+ z direction side) in the y direction. Are lined up.
- FIG. 19 is a schematic diagram schematically showing the magnetization state of the nonvolatile logic circuit according to the fourth embodiment of the present invention.
- the magnetization state (magnetization direction) of the output unit 2 (sense layer 23) depends on the combination of leakage magnetic fields from the storage layers A33, B43, C58, and D93 of the output units 3, 4, 5, and 9. Determined.
- the output is determined by the MTJ resistance value determined by the relative angle between the magnetization direction of the reference layer 21 of the output unit 2 and the magnetization direction of the sense layer 23.
- FIG. 19 is a schematic diagram schematically showing the magnetization state of the nonvolatile logic circuit according to the fourth embodiment of the present invention.
- the magnetization state (magnetization direction) of the output unit 2 (sense layer 23) depends on the combination of leakage magnetic fields from the storage layers A33, B43, C58, and D93 of the output units 3, 4, 5, and 9. Determined.
- the output is determined by the MTJ resistance value determined by the relative angle between the magnetization
- the direction of the leakage magnetic field exerted on the sense layer 23 by the storage layer C58 and the storage layer D93 is the y direction, and the leakage magnetic field exerted on the sense layer 23 by the storage layer A33 and the storage layer B43.
- the direction of is the x direction.
- the input parts 3 and 4 have perpendicular magnetic anisotropy
- this invention is not limited to this example. That is, as long as a leakage magnetic field component penetrating the sense layer 23 in the + x direction or the ⁇ x direction can be generated, it may have in-plane magnetic anisotropy.
- FIG. 20A is a perspective view showing a configuration of a nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- FIG. 20B is a cross-sectional view showing the configuration of the nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- the nonvolatile logic circuit 301 includes input units 303 and 304, output units 302a and 302b, a control unit 305, a conductor layer 306, and a plug 308.
- the input unit 303 is a spin polarized current writing type GMR element or TMR element.
- the input unit 303 includes a pinned layer 331, an intermediate layer 332, and a storage layer A333 that are stacked in the + z direction.
- the pinned layer 331 is provided adjacent to one surface of the intermediate layer 332, and the memory layer A 333 is provided adjacent to the other surface of the intermediate layer 332.
- the intermediate layer 332 is a nonmagnetic film provided between the pinned layer 331 and the storage layer A333.
- the pinned layer 331 is a ferromagnetic layer having perpendicular magnetic anisotropy and having a fixed magnetization direction.
- the magnetization direction of the pinned layer 331 is fixed in the ⁇ z direction in the example of this figure.
- the pinned layer 331 may be composed of a plurality of ferromagnetic layers having a laminated ferrimagnetic coupling (not shown) in order to firmly fix the magnetization.
- An antiferromagnetic layer may be adjacent to the ferromagnetic layer to firmly fix the magnetization (not shown).
- the memory layer A333 is a ferromagnetic layer whose magnetization direction can be changed.
- the storage layer A333 preferably has perpendicular magnetic anisotropy.
- the thinner the layer the lower the write current while maintaining the thermal stability. It becomes.
- the magnetization direction of the memory layer A333 can be reversed to either the + z direction or the ⁇ z direction in the example of this drawing.
- Input data is input to the memory layer A333. Specifically, a write current corresponding to input data is supplied.
- the direction of magnetization of the memory layer A333 is reversed by the interaction with the spin electrons of the pinned layer 331 when the write current passes through the input portion 303 in the z direction. Thereby, the input data is stored corresponding to the magnetization direction of the storage layer A333.
- the memory layer A333 can be said to be a free layer in a GMR element or a TMR element.
- the storage layer A333 is magnetically coupled to the sensor layer 323a of the output unit 302a. Therefore, the magnetization direction of the memory layer A333 affects the magnetization state of the sensor layer 323a of the output unit 302a.
- the input unit 304 is a spin polarized current writing type GMR element or TMR element.
- the input unit 304 includes a pinned layer 341, an intermediate layer 342, and a storage layer B343 stacked in the + z direction. These are the same as the pinned layer 331, the intermediate layer 332, and the storage layer A333 of the input unit 303, respectively, and thus description thereof is omitted.
- the storage layer B343 is magnetically coupled to the sensor layer 323b of the output unit 302b as will be described later. Therefore, the magnetization direction of the storage layer A343 affects the magnetization state of the sensor layer 323b of the output unit 302b.
- the input unit 304 is provided in parallel with the input unit 303 in the x direction.
- the control unit 305 is a spin polarized current writing type GMR element or TMR element.
- the control unit 305 includes a pinned layer 351, an intermediate layer 352, and a bias layer 353 stacked in the + z direction. These are the same as the pinned layer 331, the intermediate layer 332, and the storage layer A333 of the input unit 303, respectively, and thus description thereof is omitted.
- the bias layer 353 is magnetically coupled to the sensor layer 323a of the output unit 302a and the sensor layer 323b of the output unit 302b as described later. Therefore, the magnetization direction of the bias layer 353 affects the magnetization states of the sensor layer 323a of the output unit 302a and the sensor layer 323b of the output unit 302b.
- the control unit 305 is provided between the input unit 303 and the input unit 304 in a straight line parallel to the input unit 303 and the input unit 304 in the x direction.
- the bias layer 353 may be a ferromagnetic layer whose magnetization is fixed.
- a logic type ex. NOR, AND
- a ferromagnetic layer whose magnetization direction can be changed is used. .
- the output unit 302a is a TMR element.
- the output unit 302a includes a sense layer 323a, a barrier layer 322a, and a reference layer 321a stacked in the + z direction.
- the reference layer 321a is provided adjacent to one surface of the barrier layer 322a, and the sense layer 323a is provided adjacent to the other surface of the barrier layer 322a.
- the sense layer 323a, the barrier layer 322a, and the reference layer 321a of the output unit 302a form a magnetic tunnel junction (MTJ).
- the barrier layer 322a is an insulating film provided between the reference layer 321a and the sense layer 323a.
- the reference layer 321a is a ferromagnetic layer having in-plane magnetic anisotropy and a fixed magnetization direction.
- the magnetization direction of the reference layer 321a is fixed in the + y direction in the example of FIG.
- the reference layer 321a may be composed of a plurality of ferromagnetic layers having a laminated ferrimagnetic coupling (not shown) in order to firmly fix the magnetization.
- the antiferromagnetic layer may be adjacent to the ferromagnetic layer (not shown).
- the sense layer 323a is a ferromagnetic layer having in-plane magnetic anisotropy and capable of changing the direction of magnetization.
- the magnetization direction of the sense layer 323a can be rotated in any of the + y direction, the + x direction, and the -x direction in the example of this drawing.
- the sense layer 323a is magnetically coupled to the storage layer A333 and the bias layer 353 as will be described later. Therefore, the magnetization direction of the sense layer 323a is affected by the magnetization states (magnetization directions) of the storage layer A333 and the bias layer 353.
- the sense layer 323a (output unit 302a) is preferably formed such that the y direction is the easy axis direction and the x direction is the hard axis direction.
- Magnetic anisotropy can be imparted by shape anisotropy, material anisotropy, a leakage magnetic field from a reference layer, or the like. Therefore, the magnetization of the sense layer 323a is directed to the + y direction when the magnetization directions of the storage layer A333 and the bias layer 353 are the same (example: both are + z directions).
- the magnetization directions of the memory layer A333 and the bias layer 353 are different (for example, the memory layer A333 is in the + z direction and the bias layer 353 is in the -z direction), it is directed in the + x direction. That is, the direction of the magnetization is changed and stored by the combined magnetic field of the storage layer A333 and the bias layer 353.
- the output unit 302b is a TMR element.
- the output unit 302b includes a sense layer 323b, a barrier layer 322b, and a reference layer 321b stacked in the + z direction. These are the same as the sense layer 323a, the barrier layer 322a, and the reference layer 321a of the output unit 302a, respectively, and thus description thereof is omitted.
- the sense layer 323b is magnetically coupled to the storage layer B343 and the bias layer 353 as described later. Therefore, the magnetization direction of the sense layer 323b is affected by the magnetization states (magnetization directions) of the storage layer B343 and the bias layer 353.
- the magnetization of the sense layer 323b is directed to the + y direction when the magnetization directions of the storage layer B343 and the bias layer 353 are the same (example: both are + z directions).
- both are + z directions.
- the magnetization directions of the memory layer B 343 and the bias layer 353 are different (for example, the memory layer B 343 is in the + z direction and the bias layer 353 is in the ⁇ z direction), it is directed in the ⁇ x direction. That is, the magnetization direction is changed and stored by the combined magnetic field of the storage layer B343 and the bias layer 353.
- a film used for the memory layer A33 described in the first embodiment can be used.
- the films of the pinned layers 331, 341, and 351 a film used for the pinned layer 31 described in the first embodiment can be used.
- the film having in-plane magnetic anisotropy such as the sense layers 323a and 323b
- a film used for the sense layer 23 described in the first embodiment can be used.
- the films of the reference layers 321a and 321b a film used for the pinned layer 21 described in the first embodiment can be used.
- films of the intermediate layers 332, 342, and 352 films as used for the intermediate layers 32, 42, and 52 described in the first embodiment can be used.
- films of the barrier layers 322a and 322b a film used for the barrier layer 22 described in the first embodiment can be used.
- the storage layer A333 of the input unit 303, the storage layer B343 of the input unit 304, and the bias layer 353 of the control unit 305 are connected to the lower side of the conductor layer 306 extending in the x direction on the upper side (+ z direction side). Yes.
- the sense layers 323a and 323b of the output portions 302a and 302b are connected to the upper side of the conductor layer 306 on the lower side ( ⁇ z direction side).
- the conductor layer 306 is connected to the plug 308 at the end thereof.
- the pin layer 331 of the input unit 303 is connected to the first input terminal 363.
- the pin layer 341 of the input unit 304 is connected to the second input terminal 364.
- the pin layer 351 of the control unit 305 is connected to the control terminal 365. Note that output terminals (not shown) are connected to the reference layers 321a and 321b in the output units 302a and 302b, respectively.
- the conductor layer 306, the plug 308, the first input terminal 363, the second input terminal 364, the control terminal 365, and the output terminal (not shown) are normal wirings and terminals (not shown) of semiconductor elements exemplified by Cu, Al, and W ( The material used for vias) can be used.
- the positional relationship of the input unit 303, the input unit 304, the control unit 305, and the output units 302 a and 302 b as viewed in the xy plane is such that the output unit 302 a is arranged between the input unit 303 and the control unit 305. It is preferable that the output part 302b is arrange
- the center of gravity of the output unit 302a (sense layer 323a) is shifted in the xy plane with respect to the center of gravity of the input unit 303 (memory layer A333) and the center of gravity of the control unit 305 (bias layer 353). That is, in the xy plane, the output unit 302a (sense layer 323a), the input unit 303 (storage layer A333), and the control unit 305 (bias layer 535) are projected onto a plane (xy plane) including the bottom surface of the output unit 302a.
- the position of the center of gravity of the projection of the output unit 302a is the position of the center of gravity of the projection of the control unit 305 (bias layer 535) in the + x direction from the position of the center of gravity of the projection of the input unit 303 (storage layer A333).
- the position is deviated in the ⁇ x direction. Note that the definition of the center of gravity is as in the first embodiment (the same applies hereinafter).
- the center of gravity of the output unit 302b (sense layer 323b) is shifted in the xy plane with respect to the center of gravity of the input unit 304 (memory layer B343) and the center of gravity of the control unit 305 (bias layer 353). That is, in the xy plane, the output unit 302b (sense layer 323b), the input unit 304 (memory layer B343), and the control unit 305 (bias layer 535) are projected onto the plane (xy plane) including the bottom surface of the output unit 302b.
- the position of the center of gravity of the projection of the output unit 302b is the center of gravity of the projection of the control unit 305 (bias layer 535) in the ⁇ x direction from the position of the center of gravity of the projection of the input unit 304 (storage layer B343) Are shifted from each other in the + x direction.
- leakage magnetic fields from the input units 303 and 304 (storage layer A333 and storage layer B343) and the control unit 305 (bias layer 353) are output from the output unit 302a. It affects the (sense layers 323a) and 302b (sense layer 323b) and can change the magnetization state thereof.
- the xy cross-sectional shapes of the input units 303 and 304, the control unit 305, and the output units 302a and 302b are rectangular.
- the present invention is not limited to this example, and may have other cross-sectional shapes (example: ellipse) as long as the magnetization state described later can be changed.
- 21A and 21B are tables showing the relationship between the magnetization directions of the memory layers A and B, the bias layer, and the sense layer according to the fifth embodiment of the present invention.
- “A” indicates input data written to the input unit 303 (storage layer A).
- “B” indicates input data written to the input unit 304 (storage layer B).
- “A” indicates the magnetization direction of the memory layer A333.
- “B” indicates the magnetization direction of the memory layer B343.
- “L” indicates the magnetization direction of the bias layer 353.
- P indicates the magnetization direction of the sense layer 323a.
- Q indicates the magnetization direction of the sense layer 323b.
- “Out” indicates output data.
- a white circle indicates a magnetization in the ⁇ z direction. Black dots on the white circles indicate magnetization in the + z direction.
- An upward arrow indicates magnetization in the + y direction.
- a right-pointing arrow indicates magnetization in the + x direction.
- the left arrow indicates magnetization in the -
- the input data of the input unit 303 is set to “0”. To do.
- antiparallel that is, when the magnetization direction of the memory layer A333 is the + z direction
- the input data of the input unit 303 is set to “1”.
- FIG. 21A shows a case where the magnetization direction of the bias layer 353 of the control unit 305 is preset in the ⁇ z direction (control data “0”).
- the direction of magnetization (“p”) of the sense layer 323a of the output unit 302a is the + y direction, which is the easy axis direction, because both magnetic fields almost cancel each other.
- a magnetic field having a + x direction component (leakage magnetic field) by the input unit 304 and a magnetic field having a ⁇ x direction component (leakage magnetic field) by the control unit 305 are applied to the sense layer 323b of the output unit 302b. Is done.
- the direction of magnetization (“q”) of the sense layer 323b of the output unit 302b is the + y direction, which is the easy axis direction, because both magnetic fields almost cancel each other.
- the magnetization directions of the reference layer 321a and the sense layer 323a of the output unit 302a are parallel, and the MTJ of the output unit 302a has a low resistance.
- the magnetization directions of the reference layer 321b and the sense layer 323b of the output unit 302b are parallel, and the MTJ of the output unit 302b has a low resistance.
- the output data (“out”) when both the output sections are low resistance is set to “1”.
- the direction of magnetization of the sense layer 323a of the output unit 302a is the + y direction, which is the direction of the easy axis of magnetization, since both magnetic fields cancel each other.
- a magnetic field having a ⁇ x direction component by the input unit 304 and a magnetic field having a ⁇ x direction component by the control unit 305 are applied to the sense layer 323b of the output unit 302b.
- the magnetization direction of the sense layer 323b of the output section 302b is in the ⁇ x direction that is substantially parallel to both magnetic fields because the two magnetic fields are substantially intensified.
- the magnetization directions of the reference layer 321a and the sense layer 323a of the output unit 302a are parallel, and the MTJ of the output unit 302a has a low resistance.
- the magnetization directions of the reference layer 321b and the sense layer 323b of the output unit 302b are shifted from each other by 90 degrees, and the MTJ of the output unit 302b has a higher resistance than the parallel case.
- the output data when at least one of the two output units is not low resistance is set to “0”.
- the magnetization direction of the sense layer 323a of the output section 302a is in the + x direction, which is substantially parallel to both magnetic fields, since both magnetic fields are generally intensified.
- a magnetic field having a + x direction component by the input unit 304 and a magnetic field having a ⁇ x direction component by the control unit 305 are applied to the sense layer 323b of the output unit 302b.
- the direction of magnetization of the sense layer 323b of the output unit 302b is the + y direction, which is the direction of the easy axis of magnetization, because both magnetic fields almost cancel each other.
- the magnetization directions of the reference layer 321a and the sense layer 323a of the output unit 302a are shifted from each other by 90 degrees, and the MTJ of the output unit 302a has a higher resistance than that of the parallel case.
- the magnetization directions of the reference layer 321b and the sense layer 323b of the output unit 302b are parallel, and the MTJ of the output unit 302b has a low resistance.
- the output data when at least one of the two output units is not low resistance is set to “0”.
- the magnetization direction of the sense layer 323a of the output section 302a is in the + x direction, which is substantially parallel to both magnetic fields, since both magnetic fields are generally intensified.
- a magnetic field having a ⁇ x direction component by the input unit 304 and a magnetic field having a ⁇ x direction component by the control unit 305 are applied to the sense layer 323b of the output unit 302b.
- the magnetization direction of the sense layer 323b of the output section 302b is in the ⁇ x direction that is substantially parallel to both magnetic fields because the two magnetic fields are substantially intensified.
- the magnetization directions of the reference layer 321a and the sense layer 323a of the output unit 302a are shifted from each other by 90 degrees, and the MTJ of the output unit 302a has a higher resistance than that of the parallel case.
- the magnetization directions of the reference layer 321b and the sense layer 323b of the output unit 302b are shifted from each other by 90 degrees, and the MTJ of the output unit 302b has a higher resistance than that of the parallel case.
- the output data when at least one of the two output units is not low resistance is set to “0”.
- the non-volatile logic circuit 301 outputs the output data “1”, “0”, “0”, “0” with respect to the input data “00”, “01”, “10”, “11”, respectively. Is output. That is, when the control data “0” is set in the control unit 305, the nonvolatile logic circuit 301 can operate as a NOR circuit.
- FIG. 21B shows a case where the magnetization direction of the bias layer 353 of the control unit 305 is preset in the + z direction (control data “1”).
- the magnetization direction (“p”) of the sense layer 323a of the output section 302a is in the ⁇ x direction that is substantially parallel to both magnetic fields because the two magnetic fields are generally intensified.
- a magnetic field (leakage magnetic field) having a + x direction component by the input unit 304 and a magnetic field (leakage magnetic field) having a + x direction component by the control unit 305 are applied to the sense layer 323b of the output unit 302b.
- the magnetization direction (“q”) of the sense layer 323b of the output unit 302b is in the + x direction that is substantially parallel to both magnetic fields because the two magnetic fields are generally intensified.
- the magnetization directions of the reference layer 321a and the sense layer 323a of the output unit 302a are shifted from each other by 90 degrees, and the MTJ of the output unit 302a has a higher resistance than that of the parallel case.
- the magnetization directions of the reference layer 321b and the sense layer 323b of the output unit 302b are shifted from each other by 90 degrees, and the MTJ of the output unit 302b has a higher resistance than that of the parallel case.
- Output data (“out”) when at least one of the two output units is not low resistance is set to “0”.
- the direction of magnetization of the sense layer 323a of the output section 302a is in the ⁇ x direction that is substantially parallel to both magnetic fields because the two magnetic fields are substantially intensified.
- a magnetic field having a ⁇ x direction component by the input unit 304 and a magnetic field having a + x direction component by the control unit 305 are applied to the sense layer 323b of the output unit 302b.
- the direction of magnetization of the sense layer 323b of the output unit 302b is the + y direction of the easy axis direction because both magnetic fields almost cancel each other.
- the magnetization directions of the reference layer 321a and the sense layer 323a of the output unit 302a are shifted from each other by 90 degrees, and the MTJ of the output unit 302a has a higher resistance than that of the parallel case.
- the magnetization directions of the reference layer 321b and the sense layer 323b of the output unit 302b are parallel, and the MTJ of the output unit 302b has a low resistance.
- the output data when at least one of the two output units is not low resistance is set to “0”.
- the direction of magnetization of the sense layer 323a of the output unit 302a is the + y direction of the easy axis direction because both magnetic fields almost cancel each other.
- a magnetic field having a + x direction component by the input unit 304 and a magnetic field having a + x direction component by the control unit 305 are applied to the sense layer 323b of the output unit 302b.
- the magnetization direction of the sense layer 323b of the output unit 302b is in the + x direction, which is substantially parallel to both magnetic fields, since both magnetic fields are generally intensified.
- the magnetization directions of the reference layer 321a and the sense layer 323a of the output unit 302a are parallel, and the MTJ of the output unit 302a has a low resistance.
- the magnetization directions of the reference layer 321b and the sense layer 323b of the output unit 302b are shifted from each other by 90 degrees, and the MTJ of the output unit 302b has a higher resistance than the parallel case.
- the output data when at least one of the two output units is not low resistance is set to “0”.
- the direction of magnetization of the sense layer 323a of the output unit 302a is the + y direction of the easy axis direction because both magnetic fields almost cancel each other.
- a magnetic field having a ⁇ x direction component by the input unit 304 and a magnetic field having a + x direction component by the control unit 305 are applied to the sense layer 323b of the output unit 302b.
- the direction of magnetization of the sense layer 323b of the output unit 302b is the + y direction of the easy axis direction because both magnetic fields almost cancel each other.
- the magnetization directions of the reference layer 321a and the sense layer 323a of the output unit 302a are parallel, and the MTJ of the output unit 302a has a low resistance.
- the magnetization directions of the reference layer 321b and the sense layer 323b of the output unit 302b are parallel, and the MTJ of the output unit 302b has a low resistance.
- the output data when both the output sections are low resistance is set to “1”.
- the nonvolatile logic circuit 301 outputs the output data “0”, “0”, “0”, “1” with respect to the input data “00”, “01”, “10”, “11”, respectively. Is output. That is, when the control data “1” is set in the control unit 305, the nonvolatile logic circuit 301 can operate as an AND circuit.
- the nonvolatile logic circuit 301 in this embodiment can be used as a NOR circuit or an AND circuit by controlling the magnetization state of the bias layer 353. Therefore, a NOR circuit and an AND circuit are configured by the nonvolatile logic circuit 301 in this embodiment, and another logic circuit can be assembled by combining them.
- Data input / output principle of the nonvolatile logic circuit according to the fifth embodiment of the present invention will be described.
- Data is input to the nonvolatile logic circuit 301 by writing data to the GMR elements (or TMR elements) of the control unit 305 and the input units 303 and 304.
- data is output from the non-volatile logic circuit 301 by reading data from the TMR elements of the output units 302a and 302b. This will be described in detail below.
- the control unit 305 is written with control data in advance before the operation of the nonvolatile logic circuit 1.
- the nonvolatile logic circuit 301 can be set to one of a NOR circuit and an AND circuit.
- the input units 303 and 304 are supplied with first input data and second input data, respectively, when the nonvolatile logic circuit 301 operates.
- the control data is written to the control unit 305 by the following method.
- the control unit 305 is a spin polarized current writing type GMR element.
- a write current Iw is applied between the control terminal 365 and, for example, the plug 308.
- the write current Iw is supplied in a direction corresponding to control data to be written (the magnetization direction of the bias layer 353). In that case, spin electrons flow in the opposite direction to the write current Iw.
- the magnetization direction of the bias layer 353 when it is to be set to the + z direction, it is passed from the control terminal 365 to the plug 308. In this case, spin electrons flow from the plug 308 side to the control terminal 365 side. As a result, the magnetization direction of the bias layer 353 becomes the + z direction due to the spin torque effect caused by the interaction between the pinned layer 351 and the bias layer 353.
- the current flows from the plug 308 to the control terminal 365. In this case, spin electrons flow from the control terminal 365 side to the plug 308 side. As a result, the magnetization direction of the bias layer 353 becomes the ⁇ z direction due to the spin torque effect due to the interaction between the pinned layer 351 and the bias layer 353.
- the input data is written to the input units 303 and 304 by the following method.
- the input units 303 and 304 are spin polarized current writing type GMR elements.
- a write current Iw 1 is applied between the first input terminal 363 and, for example, the plug 308.
- the write current Iw1 is supplied in a direction corresponding to the first input data to be written (the magnetization direction of the storage layer A333).
- a write current Iw2 is applied between the second input terminal 364 and, for example, the plug 308.
- the write current Iw2 is caused to flow in a direction corresponding to the second input data to be written (the magnetization direction of the storage layer B343). In these cases, spin electrons flow in the direction opposite to the write currents Iw1 and Iw2.
- the control unit 305 when the magnetization direction of the storage layer A333 is to be set to the + z direction, the first input terminal 363 is passed through the plug 308. On the other hand, when the magnetization direction of the memory layer A333 is to be set to the ⁇ z direction, the current flows from the plug 308 to the first input terminal 363. Similarly, when the magnetization direction of the memory layer B 343 is desired to be in the + z direction, the current flows from the second input terminal 364 to the plug 308. On the other hand, when the magnetization direction of the memory layer B 343 is to be set to the ⁇ z direction, the current flows from the plug 308 to the second input terminal 364.
- data is input to the nonvolatile logic circuit 301.
- the control unit 305 and the input units 303 and 304 are in a desired magnetization state reflecting those data.
- output data is written to the output units 302a and 302b by the leakage magnetic field (synthetic magnetic field) from the control unit 305 and the input units 303 and 304.
- the paths of the write currents IW, IW1, and IW2 are not limited to the above example, and the magnetization directions of the control unit 305, the bias layer 353 of the input units 303 and 304, the storage layer A333, and the storage layer B343 can be changed. If it is.
- the output units 302a and 302b are TMR elements.
- the output unit 302a has a leakage magnetic field (combined magnetic field) from the input unit 303 and the control unit 305
- the output unit 302b has a magnetization corresponding to the leakage magnetic field by the leakage magnetic field (synthetic magnetic field) from the input unit 304 and the control unit 305. The state has changed.
- each MTJ resistance of the output units 302a and 302b has a value corresponding to a combination of control data, first input data, and second input data.
- the resistance values of those MTJs can be read out.
- the direction of the read current IR is not particularly limited.
- the output data of the nonvolatile logic circuit 301 is determined based on the resistance of the MTJ (the sum of the output unit 302a and the output unit 302b). Note that the path of the read current IR is not limited to the above example, and it is sufficient that the MTJ resistance value of each output unit can be measured individually or collectively.
- FIG. 22 is a block diagram showing an example of a logic gate according to the fifth embodiment of the present invention.
- the logic gate 380 includes a control circuit 381, a nonvolatile logic circuit 301, an MTJ reference element 383, and a comparator 382.
- the control circuit 381 includes a switch for converting a logic input and a logic control value into a current.
- the control circuit 381 generates a write current IW having a magnitude and direction corresponding to the control data in response to the supply of the control data.
- the signal is supplied to the path of the control terminal 365, the control unit 305, the conductor layer 306, and the plug 308 of the nonvolatile logic circuit 301 through the terminal Control and the terminal 392.
- control data can be set in the control unit 305 (bias layer 353).
- the non-volatile logic circuit 301 can be set to a desired logic operation circuit (example: NOR circuit).
- the control circuit 381 first generates a write current IW1 having a magnitude and direction corresponding to the first input data in response to the supply of the first input data. Then, the signal is supplied to the first input terminal 363, the input portion 303, the conductor layer 308, and the plug 308 of the nonvolatile logic circuit 301 through the terminal IN 1 and the terminal 392. Next, in response to the supply of the second input data, a write current IW2 having a magnitude and direction corresponding to the second input data is generated.
- the signal is supplied to the path of the second input terminal 364, the input unit 304, the conductor layer 306, and the plug 308 of the nonvolatile logic circuit 301 through the terminal IN 2 and the terminal 392.
- input data first input data, second input data
- the control circuit 381 generates a read current IR.
- the current flows through the terminal 391 and the terminal 392 to the path of the output terminal (not shown), the output unit 302a, the conductor layer 306, the output unit 302b, and another output terminal (not shown).
- a voltage (output voltage) corresponding to the MTJ resistance value of the output unit 302 a and the output unit 302 b is output from the terminal Out to the comparator 382.
- the comparator 382 compares the output voltage from the non-volatile logic circuit 301 with the reference voltage from the MTJ reference element 383, and outputs final output data. Thereby, the non-volatile logic circuit 301 can output the output data which shows a desired logic operation result with respect to input data.
- the nonvolatile logic circuit 301 is set to a desired logic circuit, and input data is input to the nonvolatile logic circuit 301 and output data is output from the nonvolatile logic circuit 301. It becomes possible.
- the nonvolatile logic circuit 301 of this embodiment can reconfigure its logic by changing control data (configuration information) input to the control unit 305. That is, the non-volatile logic circuit 301 of this embodiment includes a reconfigurable logic using a GMR (or TMR) spin injection element (control unit 305, storage unit 303, 304) and MTJ (output units 302a, 302b). A circuit can be realized.
- GMR or TMR
- MTJ output units 302a, 302b
- the nonvolatile logic circuit of the present embodiment stores configuration information (control data) in the control unit 305.
- the control unit 305 can be regarded as a non-volatile memory using a GMR element or a TMR element. By using this nonvolatile memory, it is not necessary to have an SRAM for holding configuration information when the power is turned off. Therefore, it is possible to solve the increase in area due to the non-volatile memory provided as a problem in the FPGA.
- the control unit 305, the storage units 303 and 304, and the output units 302a and 302b use magnetoresistive elements such as GMR elements or TMR elements.
- magnetoresistive elements such as GMR elements or TMR elements.
- they function as an element having both a logic element and a nonvolatile memory as a whole. Therefore, even if a magnetoresistive element is used, the size of the element can be kept small as a whole. Further, since the magnetoresistive element can operate at room temperature, the nonvolatile logic circuit of this embodiment can operate at room temperature.
- the present invention can provide a reconfigurable nonvolatile logic circuit element while suppressing an increase in the area of the element.
- the logic of the nonvolatile logic circuit 301 can be changed by changing the setting of the reference voltage level.
- the original NAND logic can be changed to NAND logic.
- “1” is set when the MTJ resistance value of the output units 302a and 302b is maximum, and “0” is set otherwise.
- FIG. 21B if the output of case ⁇ 1 is set to “0” and the outputs of other cases ⁇ 2 to ⁇ 4 are set to “1”, the original AND logic can be changed to OR logic. In this case, “1” is set when the MTJ resistance value of the output units 302a and 302b is maximum, and “0” is set otherwise.
- the control unit 305 is provided between the input unit 303 and the input unit 304.
- the order of arrangement of the input units 303 and 304 and the control unit 305 is arbitrary.
- the output data is set to “1” when the magnetization directions of the output units 302a and 302b, such as the case ⁇ 1 and the case ⁇ 4, are both in the + y direction. This is because the output data is set to “0”.
- the relative positional relationship between the input units 303 and 304 and the control unit 305 eventually becomes irrelevant.
- FIG. 23A to FIG. 23D are schematic diagrams showing modifications of the configuration of the nonvolatile logic circuit according to the fifth exemplary embodiment of the present invention.
- the sense layers 323a and 323b of the output units 302a and 302b may overlap (overlap) the input units 303 and 304 and the control unit 305.
- the storage layer A333 of the input unit 303, the storage layer B343 of the input unit 304, and the bias layer 353 of the control unit 305 have the maximum leakage magnetic field at their edges. Therefore, the sensitivity of the sense layers 323a and 323b can be further increased by providing an overlapping (overlapping) arrangement. In this case, the length of each sense layer in the x direction is larger than the interval between each input unit and the control unit.
- the overlapping (overlapping) portions may be only the sense layers 323a and 323b as shown in FIG. 23B or the entire output units 302a and 302b as shown in FIG. 23C. Good.
- the sense layers 323a and 323b of the output units 302a and 302b may be arranged in the + y direction with respect to the input units 303 and 304 and the control unit 305. Shifting each output unit in the + y direction has an advantage that the magnetization of the sense layer can be easily directed in the + y direction when the magnetizations of the left and right input units and the control unit are parallel to each other. Also in this case, the arrangement may overlap as shown in FIG. 23B or FIG. 23C.
- FIG. 24A to FIG. 24C are diagrams for explaining another modification of the configuration of the nonvolatile logic circuit according to the fifth embodiment of the present invention.
- the sense layers of the output units 302a and 302b may be one large sense layer 323.
- the sense layer 323 has a multi-domain structure.
- “p” and “q” in FIG. 21A indicate the magnetization directions of magnetic domains corresponding to the respective positions of the output units 302a and 302b (shown by broken lines), as shown in FIG. 24B (corresponding to FIG.
- the output unit (entire MTJ) including the reference layer may be one large output unit 302.
- the sense layer 323 has a multi-domain structure as shown in FIG. 24B. By comprising in this way, manufacture of an output part can be made still easier. Even in these cases, two output terminals for supplying / extracting the read current to / from the output unit are provided at the same positions as in FIG. 20A.
- the pinned layers of the input units 303 and 304 and the control unit 305 may be provided with an initialization magnetization fixed layer (hard layer) adjacent to each other (not shown).
- an initialization magnetization fixed layer hard layer
- the positions of the magnetization fixed layers are arbitrary as long as they are adjacent to each other.
- FIG. 25A and FIG. 25B are schematic views showing still another modified example of the configuration of the nonvolatile logic circuit according to the fifth embodiment of the present invention.
- the input units 303 and 304 and the control unit 305 may be inverted with respect to the xy plane, and the pin layers 331, 341, and 351 may be in contact with the conductor layer 306.
- the vertical (z-direction) relationship between the input units 303 and 304, the control unit 305, and the output units 302a and 302b may be reversed.
- FIG. 26 is a schematic diagram showing another modification of the configuration of the nonvolatile logic circuit according to the fifth embodiment of the present invention.
- FIG. 26 there may be a plurality of input units and output units.
- input units 307 and 309 are added, and output units 302c and 302d are added.
- the diagram is As in 21A and FIG. 21B, a NOR operation and an AND operation can be performed.
- FIG. 27 is a schematic diagram showing the principle of the nonvolatile logic circuit according to the embodiment of the present invention.
- the nonvolatile logic circuit includes one input unit, a control unit, and an output unit.
- the input unit and the control unit include a ferromagnetic layer having perpendicular magnetic anisotropy and capable of changing a magnetization state.
- the output unit includes a magnetic tunnel coupling element provided in the vicinity of the input unit and the control unit and capable of changing the magnetization state. The magnetization state of the input unit changes corresponding to the input data.
- the magnetization state of the magnetic tunnel coupling element of the output unit changes corresponding to the magnetization state of the input unit and the control unit. That is, the magnetization state of the magnetic tunnel coupling element of the output unit changes due to the leakage magnetic fields (H1, H0) that change in accordance with the magnetization states of the input unit and the control unit. By detecting the resistance value of the magnetic tunnel coupling whose magnetization state has changed, output data corresponding to the input data can be obtained.
- the control unit, the input unit, and the output unit constitute an element having both a logic element and a memory.
- FIG. 28A is a perspective view showing a configuration of a nonvolatile logic circuit according to the sixth exemplary embodiment of the present invention.
- FIG. 28B is a cross-sectional view showing the configuration of the nonvolatile logic circuit according to the sixth exemplary embodiment of the present invention.
- the nonvolatile logic circuit 401 includes an input unit 403, an output unit 402, a control unit 405, a conductor layer 406, and a plug 408.
- the non-volatile logic circuit 401 is the same as the non-volatile logic circuit 301 except that the non-volatile logic circuit 301 has fewer input units and one output unit than the non-volatile logic circuit 301 (fifth embodiment). Therefore, the description is omitted.
- the input unit 403 pinned layer 431, intermediate layer 432, storage layer A433)
- output unit 402 reference layer 421, barrier layer 422, sense layer 423)
- control unit 405 pinned layer 451, intermediate layer 452, and bias
- conductor layer 406, and plug 408 include an input portion 303 (pin layer 331, intermediate layer 332, storage layer A333), output portion 302a (reference layer 321a, barrier layer 322a, sense layer 323a), control portion, respectively.
- 305 a pin layer 351, an intermediate layer 352, and a bias layer 353
- a conductor layer 306, and a plug 308 are provided.
- 29A and 29B are tables showing the relationship between the magnetization directions of the memory layer A, the bias layer, and the sense layer according to the sixth embodiment of the present invention.
- “A” indicates input data written to the input unit 403.
- “A” indicates the magnetization direction of the memory layer A433.
- “L” indicates the magnetization direction of the bias layer 453.
- “R” indicates the magnetization direction of the sense layer 423.
- “Out” indicates output data.
- a white circle indicates a magnetization in the ⁇ z direction. Black dots on the white circles indicate magnetization in the + z direction.
- An upward arrow indicates magnetization in the + y direction.
- a right-pointing arrow indicates magnetization in the + x direction.
- the left arrow indicates magnetization in the -x direction.
- FIG. 29A shows a case where the magnetization direction of the bias layer 453 of the control unit 405 is preset in the + z direction (control data “0”).
- the magnetization direction (“r”) of the sense layer 423 of the output unit 402 is in the ⁇ x direction substantially parallel to both magnetic fields because both magnetic fields strengthen each other.
- the magnetization directions of the reference layer 421 and the sense layer 423 of the output unit 402 are shifted from each other by 90 degrees, and the MTJ of the output unit 402 has a higher resistance than when parallel.
- the output data (“out”) when the output unit 402 has a high resistance is set to “0”.
- the magnetization directions of the reference layer 421 and the sense layer 423 of the output unit 402 are parallel, and the MTJ of the output unit 402 has a low resistance.
- the output data when the output unit 402 has a low resistance is set to “1”.
- the nonvolatile logic circuit 401 outputs the output data “0” and “1” for the input data “0” and “1”, respectively. That is, when the control data “0” is set in the control unit 405, the nonvolatile logic circuit 401 outputs the input data as it is.
- a logic circuit is defined as a Through circuit.
- FIG. 29B shows a case where the magnetization direction of the bias layer 453 of the control unit 405 is preset in the ⁇ z direction (control data “1”).
- the direction of magnetization (“r”) of the sense layer 423 of the output unit 402 is the + y direction, which is the direction of the easy axis of magnetization, because the two magnetic fields almost cancel each other.
- the magnetization directions of the reference layer 421 and the sense layer 423 of the output unit 402 are parallel, and the MTJ of the output unit 402 has a low resistance.
- the output data (“out”) when the output unit 402 has a low resistance is set to “1”.
- the magnetization directions of the reference layer 421 and the sense layer 423 of the output unit 402 are shifted from each other by 90 degrees, and the MTJ of the output unit 402 has a higher resistance than when parallel.
- the output data when the output unit 402 has a high resistance is set to “0”.
- the non-volatile logic circuit 401 outputs the output data “1” and “0” for the input data “0” and “1”, respectively. That is, when the control data “1” is set in the control unit 405, the nonvolatile logic circuit 401 can operate as a NOT circuit.
- the nonvolatile logic circuit 401 in this embodiment can be used as a Through circuit or a NOT circuit by controlling the magnetization state of the bias layer 353. Therefore, by forming a Through circuit and a NOT circuit with the nonvolatile logic circuit 401 in this embodiment and combining them, another logic circuit can be assembled. Note that if the “1” and “0” are reversed in the output data setting, the Through circuit and the NOT circuit can be reversed.
- FIG. 30 is a block diagram showing an example of a logic gate in the sixth embodiment of the present invention.
- the logic gate 480 includes a control circuit 481, a nonvolatile logic circuit 401, an MTJ reference element 483, and a comparator 482.
- the control circuit 481 includes a switch for converting a logic input and a logic control value into a current. In response to the supply of control data, the control circuit 481 generates a write current IW having a magnitude and direction corresponding to the control data as a pre-setting operation of the nonvolatile logic circuit 401. Then, the signal is supplied to the control terminal 465, the control unit 405, the conductor layer 406, and the plug 408 of the nonvolatile logic circuit 401 through the terminal Control and the terminal 492. Thus, control data can be set in the control unit 405 (bias layer 453). As a result, the nonvolatile logic circuit 401 can be set to a desired logic operation circuit (eg, NOT circuit).
- a desired logic operation circuit eg, NOT circuit
- the control circuit 481 first generates a write current IW1 having a magnitude and direction corresponding to the input data in response to the supply of the input data. Then, the signal is supplied to the path of the first input terminal 463, the input unit 403, the conductor layer 406, and the plug 408 of the nonvolatile logic circuit 401 through the terminal IN 1 and the terminal 492. Thereby, input data can be input to the input unit 403. Thereafter, the control circuit 481 generates a read current IR. Then, the current flows through the terminals of the output terminal (not shown), the output portion 402, the conductor layer 406, and the plug 408 through the terminal 491 and the terminal 492.
- a voltage (output voltage) corresponding to the MTJ resistance value of the output unit 402 is output from the terminal Out to the comparator 482.
- the comparator 482 compares the output voltage from the non-volatile logic circuit 401 with the reference voltage from the MTJ reference element 483, and outputs final output data. Thereby, the non-volatile logic circuit 401 can output the output data which shows a desired logic operation result with respect to input data.
- the nonvolatile logic circuit 401 is set to a desired logic circuit, and input data is input to the nonvolatile logic circuit 401 and output data is output from the nonvolatile logic circuit 401. It becomes possible.
- nonvolatile logic circuit 401 of this embodiment the same effect as that of the nonvolatile logic circuit 301 of the fifth embodiment can be obtained.
- configuration of the nonvolatile logic circuit 401 of the present embodiment can be modified in the same manner as the nonvolatile logic circuit 301 of the fifth embodiment as long as no technical contradiction occurs.
- FIG. 31 is a perspective view showing the configuration of the nonvolatile logic circuit according to the seventh embodiment of the present invention.
- the nonvolatile logic circuit 496 includes a nonvolatile logic circuit 301 according to the fifth embodiment, a nonvolatile logic circuit 401 according to the sixth embodiment, and a signal transmission circuit 497.
- the nonvolatile logic circuit 496 is a circuit combining the nonvolatile logic circuit 301 (fifth embodiment) and the nonvolatile logic circuit 401 (sixth embodiment). That is, the output data of the nonvolatile logic circuit 301 is used as input data of the nonvolatile logic circuit 401. Specifically, first, the first input data is input to the input unit 303 of the nonvolatile logic circuit 301 and the second input data is input to the input unit 304. Next, the signal transmission circuit 497 detects the magnetization state (output data) of the output units 302a and 302b changed by the input data.
- the signal transmission circuit 497 detects the resistance values of the output units 302a and 302b and determines whether the output data is “0” or “1”. Then, the signal transmission circuit 497 inputs the determined output data as input data to the input unit 403 of the nonvolatile logic circuit 401.
- the magnetization state (output data) of the output unit 402 changed by the input data is used as final output data of the nonvolatile logic circuit 496.
- Others are the same as those of the non-volatile logic circuits 301 and 401. Therefore, the description is omitted.
- 32A and 32B are tables showing the relationship between the magnetization directions of the memory layers A and B, the bias layer, and the sense layer of each nonvolatile logic circuit according to the seventh embodiment of the present invention.
- “A” indicates input data written to the input unit 303 (storage layer A).
- “B” indicates input data written to the input unit 304 (storage layer B).
- “A” indicates the magnetization direction of the memory layer A333.
- “B” indicates the magnetization direction of the memory layer B343.
- “L1” indicates the magnetization direction of the bias layer 353.
- P indicates the magnetization direction of the sense layer 323a.
- Q indicates the magnetization direction of the sense layer 323b.
- “O-1” is output data from the output units 302 a and 302 b and indicates input data written to the input unit 403.
- “O” indicates the magnetization direction of the memory layer A433.
- “12” indicates the magnetization direction of the bias layer 453.
- “R” indicates the magnetization direction of the sense layer 423.
- “O-2” indicates output data from the output unit 402, that is, output data of the nonvolatile logic circuit 496.
- a white circle indicates a magnetization in the ⁇ z direction. Black dots on the white circles indicate magnetization in the + z direction.
- An upward arrow indicates magnetization in the + y direction.
- a right-pointing arrow indicates magnetization in the + x direction. The left arrow indicates magnetization in the -x direction.
- the setting of “0” and “1” for each input data, each control data, and each output data is the same as that of the nonvolatile logic circuits 301 and 401. Therefore, the description is omitted.
- FIG. 32A will be described.
- the magnetization direction of the bias layer 353 of the control unit 305 is in the ⁇ z direction (control data “0”)
- the magnetization direction of the bias layer 453 of the control unit 405 is in the + z direction (control data “0”).
- the non-volatile logic circuit 301 operates as a NOR circuit as shown in FIG. 21A.
- the non-volatile logic circuit 401 operates as a Through circuit as shown in FIG. 29A. That is, the nonvolatile logic circuit 496 operates as a NOR circuit as a whole.
- the nonvolatile logic circuit 496 outputs the output data “1”, “0”, “0”, “0” with respect to the input data “00”, “01”, “10”, “11”, respectively. Is output. That is, when the control data “0” and “0” are set in the control units 305 and 405, the nonvolatile logic circuit 496 can operate as a NOR circuit.
- FIG. 32B the magnetization direction of the bias layer 353 of the control unit 305 is in the + z direction (control data “1”), and the magnetization direction of the bias layer 453 of the control unit 405 is in the ⁇ z direction (control data “1”).
- the non-volatile logic circuit 301 operates as an AND circuit as shown in FIG. 21B.
- the non-volatile logic circuit 401 operates as a NOT circuit as shown in FIG. 29B. That is, the nonvolatile logic circuit 496 operates as a NAND circuit as a whole.
- the nonvolatile logic circuit 496 outputs the output data “1”, “1”, “1”, “0” for the input data “00”, “01”, “10”, “11”, respectively. Is output. That is, when the control data “1” and “1” are set in the control units 305 and 405, the nonvolatile logic circuit 496 can operate as a NAND circuit.
- the non-volatile logic circuit 496 in this embodiment can be used as a NOR circuit or a NAND circuit by controlling the magnetization states of the control units 305 and 405 of the non-volatile logic circuits 301 and 401. Therefore, by forming a NOR circuit and a NAND circuit with the nonvolatile logic circuit 496 in this embodiment and combining them, another logic circuit can be assembled.
- the fifth embodiment (using the nonvolatile logic circuit 301 is used).
- the logic gate 380 shown in FIG. 22) and the sixth embodiment (logic gate 480 using the non-volatile logic circuit 401: FIG. 30) can be executed, and the description thereof is omitted.
- the signal transmission circuit 497 can be configured by, for example, the comparator 382 in FIG. 22, the MTJ reference element 383, and a part of the control circuit 381 that controls the comparator 382 and the MTJ reference element 383.
- nonvolatile logic circuit 496 of this embodiment the same effects as those of the nonvolatile logic circuit 301 of the fifth embodiment and the nonvolatile logic circuit 401 of the sixth embodiment can be obtained. Furthermore, since a NOR circuit and a NAND circuit can be configured, any logic circuit can be assembled by combining them. In addition, in the nonvolatile logic circuit 496 of the present embodiment, as long as no technical contradiction occurs, the nonvolatile logic circuit 301 of the fifth embodiment and the nonvolatile logic circuit 401 of the sixth embodiment are the same. The configuration can be modified.
- FIG. 33A is a perspective view showing a configuration of a nonvolatile logic circuit according to the eighth exemplary embodiment of the present invention.
- FIG. 33B is a plan view showing the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- the nonvolatile logic circuit 101 includes input units 103 and 104, output units 102 a and 102 b, a control unit 105, and a conductor layer 106.
- the input unit 103 is a domain wall motion element extending in the + y direction, and is a ferromagnetic layer having perpendicular magnetic anisotropy.
- the input unit 103 includes a first magnetization fixed region 134a, a second magnetization fixed region 134b, and a magnetization switching region 135.
- the magnetization switching region 135 is sandwiched between the first magnetization fixed region 134a and the second magnetization fixed region 134b.
- the magnetization direction of the first magnetization fixed region 134a is substantially fixed in the + z direction.
- the magnetization direction of the second magnetization fixed region 134b is substantially fixed in the ⁇ z direction.
- the magnetization direction of the magnetization switching region 135 is not fixed and can be switched between the ⁇ z direction and the + z direction.
- the magnetization switching region 135 is magnetically coupled to the sensor layer 123a of the output unit 102a as described later. Therefore, the magnetization direction of the magnetization switching region 135 affects the magnetization state of the sensor layer 123a of the output unit 102a.
- the magnetization state of the input unit 103 is referred to as a “first magnetization state MS1”.
- the magnetization direction of the magnetization switching region 135 is the ⁇ z direction
- the domain wall DW is formed in the vicinity of the boundary between the first magnetization fixed region 134 a and the magnetization switching region 135.
- the magnetization state of the input unit 103 is referred to as a “second magnetization state MS2”.
- the magnetization state of these input units 103 that is, the magnetization direction of the magnetization switching region 135 can be changed by flowing a write current in the y direction.
- the write current flows between the first input terminal 163a connected to the first magnetization fixed region 134a and the second input terminal 163b connected to the second magnetization fixed region 134b.
- the first write current IW1 is passed from the first input terminal 163a to the second input terminal 163b.
- spin-polarized electrons in the ⁇ z direction are supplied from the second magnetization fixed region 134b to the magnetization switching region 135. Due to the spin torque effect, the domain wall DW is driven and moves from the second magnetization fixed region 134b side to the first magnetization fixed region 134a side. As a result, the magnetization direction of the magnetization switching region 135 is reversed in the ⁇ z direction, and the second magnetization state MS2 is obtained.
- the second write current IW2 is passed from the second input terminal 163b to the first input terminal 163a.
- spin-polarized electrons in the + z direction are supplied from the first magnetization fixed region 134a to the magnetization switching region 135.
- the domain wall DW is driven by the spin torque effect and moves from the first magnetization fixed region 134a side to the second magnetization fixed region 134b side.
- the magnetization direction of the magnetization switching region 135 is reversed in the + z direction, and the first magnetization state MS1 is obtained.
- the domain wall DW is moved by the write current flowing between the first magnetization fixed region 134a and the second magnetization fixed region 134b.
- the magnetization direction of the magnetization switching region 135 is reversed, and the magnetization state of the input unit 103 changes. That is, input data is input to the input unit 103.
- Which of the first magnetization state MS1 and the second magnetization state MS2 is obtained depends on the direction of the write current. In other words, the input data to be input to the input unit 103 can be set by controlling the direction of the write current.
- the input unit 104 is a domain wall motion element extending in the + y direction, and is a ferromagnetic layer having perpendicular magnetic anisotropy.
- the input unit 104 includes a first magnetization fixed region 144a, a second magnetization fixed region 144b, and a magnetization switching region 145. Since these are the same as the first magnetization fixed region 134a, the second magnetization fixed region 134b, and the magnetization switching region 135 of the input unit 103, description thereof is omitted.
- the magnetization switching region 145 is magnetically coupled to the sensor layer 123b of the output unit 102b as will be described later. Therefore, the magnetization direction of the magnetization switching region 145 affects the magnetization state of the sensor layer 123b of the output unit 102b.
- the input unit 104 is provided in parallel with the input unit 103 in the x direction.
- control unit 105 is a domain wall motion element extending in the + y direction, and is a ferromagnetic layer having perpendicular magnetic anisotropy.
- the control unit 105 includes a first magnetization fixed region 154a, a second magnetization fixed region 154b, and a magnetization switching region 155. Since these are the same as the first magnetization fixed region 134a, the second magnetization fixed region 134b, and the magnetization switching region 135 of the input unit 103, description thereof is omitted.
- the magnetization switching region 155 is magnetically coupled to the sensor layer 123a of the output unit 102a and the sensor layer 323b of the output unit 302b as will be described later.
- the magnetization direction of the magnetization switching region 155 affects the magnetization states of the sensor layer 123a of the output unit 102a and the sensor layer 123b of the output unit 102b.
- the control unit 105 is provided between the input unit 103 and the input unit 104 in a straight line parallel to the input unit 103 and the input unit 104 in the x direction.
- the magnetization switching region 155 may be a ferromagnetic layer with fixed magnetization.
- a logic type ex. NOR, AND
- a ferromagnetic layer whose magnetization direction can be changed is used. .
- a film used for the memory layer A33 described in the first embodiment can be used.
- the output unit 102a is a TMR element, and includes a sense layer 123a, a barrier layer 122a, and a reference layer 121a (MTJ element) stacked in the + z direction.
- the output unit 102ab is a TMR element, and includes a sense layer 123b, a barrier layer 122b, and a reference layer 121b (MTJ element) stacked in the + z direction. These are the same as the sense layers 323a and 323b barrier layers 322a and 322b and the reference layers 321a and 321b of the output units 302a and 302b in the fifth embodiment, respectively, and thus description thereof is omitted.
- the magnetization switching regions 135, 145, and 155 are magnetically coupled to the sensor layer 123a of the output unit 102a and the sensor layer 323b of the output unit 302b.
- the magnetization switching region 135 of the input unit 103, the magnetization switching region 145 of the input unit 104, and the magnetization switching region 155 of the control unit 105 are on the upper side (+ z direction side) below the conductor layer 106 extending in the x direction. It is connected.
- the sense layers 123a and 123b of the output portions 102a and 102b are connected to the upper side of the conductor layer 106 on the lower side ( ⁇ z direction side).
- the first magnetization fixed region 134a and the second magnetization fixed region 134b of the input unit 103 are connected to the first input terminal 163a and the second input terminal 163b, respectively.
- the first magnetization fixed region 144a and the second magnetization fixed region 144b of the input unit 104 are connected to the first input terminal 164a and the second input terminal 164b, respectively.
- the first magnetization fixed region 154a and the second magnetization fixed region 154b of the control unit 105 are connected to the first control terminal 165a and the second control terminal 165b, respectively.
- output terminals (not shown) are connected to the reference layers 121a and 121b in the output units 102a and 102b, respectively.
- the conductor layer 106, the first input terminals 163a, 164a, the second input terminals 163b, 164b, the first control terminal 165a, the second control terminal 165b, and the output terminal are exemplified by Cu, Al, and W.
- a material used for a normal wiring or a terminal (via) of a semiconductor element can be used.
- the positional relationship of the input unit 103, the input unit 104, the control unit 105, and the output units 102 a and 302 b viewed in the xy plane is between the magnetization switching region 135 of the input unit 103 and the magnetization switching region 155 of the control unit 105.
- 102a is disposed, and the output unit 102b is disposed between the magnetization switching region 155 of the control unit 305 and the magnetization switching region 145 of the input unit 104, and they are preferably arranged in a straight line in the x direction.
- it can be set as follows.
- the center of gravity of the output unit 102a (sense layer 123a) is shifted in the xy plane with respect to the center of gravity of the magnetization switching region 135 of the input unit 103 and the center of magnetization of the magnetization switching region 155 of the control unit 105. That is, on the xy plane, the output unit 102a (sense layer 123a), the magnetization switching region 135 of the input unit 103, and the magnetization switching region 155 of the control unit 105 are projected onto a plane (xy plane) including the bottom surface of the output unit 102a.
- the position of the center of gravity of the projection of the output unit 102a is the position of the center of gravity of the projection of the magnetization switching region 155 of the control unit 105 in the + x direction from the position of the projection center of gravity of the magnetization switching region 135 of the input unit 103.
- the position is deviated in the ⁇ x direction.
- the centroid of the output unit 102b (sense layer 123b) is shifted in the xy plane with respect to the centroid of the magnetization switching region 145 of the input unit 104 and the centroid of the magnetization switching region 155 of the control unit 105. That is, on the xy plane, the output unit 102b (sense layer 123b), the magnetization switching region 145 of the input unit 104, and the magnetization switching region 155 of the control unit 105 are projected onto a plane (xy plane) including the bottom surface of the output unit 102b.
- the position of the center of gravity of the projection of the output unit 102b is the center of gravity of the projection of the magnetization switching region 155 of the control unit 105 in the ⁇ x direction from the position of the projection center of gravity of the magnetization switching region 145 of the input unit 104. Are shifted from each other in the + x direction.
- leakage magnetic fields from the magnetization switching regions 135 and 145 of the input units 103 and 104 and the magnetization switching region 155 of the control unit 105 are output from the output unit 102a (sense.
- the layers 123a) and 102b are affected, and the magnetization state thereof can be changed.
- the xy cross-sectional shapes of the input units 103 and 104, the control unit 105, and the output units 102a and 102b are rectangular.
- the present invention is not limited to this example, and may have other cross-sectional shapes (example: ellipse) as long as the magnetization state described later can be changed.
- 34A and 34B are tables showing the relationship between the magnetization switching region and the magnetization direction of the sense layer according to the eighth embodiment of the present invention.
- “A” indicates input data written to the input unit 103 (magnetization switching region 135).
- “B” indicates input data written to the input unit 104 (magnetization switching region 145).
- “A” indicates the magnetization direction of the magnetization switching region 135.
- “B” indicates the magnetization direction of the magnetization switching region 145.
- “L” indicates the magnetization direction of the magnetization switching region 155.
- P indicates the magnetization direction of the sense layer 123a.
- “Q” indicates the magnetization direction of the sense layer 123b.
- “Out” indicates output data.
- a white circle indicates a magnetization in the ⁇ z direction. Black dots on the white circles indicate magnetization in the + z direction.
- An upward arrow indicates magnetization in the + y direction.
- a right-pointing arrow indicates magnetization in the + x direction.
- the input data of the input unit 103 is set to “0”.
- the input data is “1”.
- the input unit 104 (relationship between input data and the magnetization direction of the magnetization switching region 145) and the control unit 105 (relationship between control data and the magnetization direction of the magnetization switching region 155) are the same as those of the input unit 103.
- FIG. 34A shows a case where the magnetization direction of the magnetization switching region 155 of the control unit 105 is preset in the ⁇ z direction (control data “0”).
- the magnetization direction (“p”) of the sense layer 123a of the output unit 102a is the + y direction, which is the direction of the easy axis of magnetization, because both magnetic fields almost cancel each other.
- a magnetic field having a + x direction component (leakage magnetic field) by the input unit 104 and a magnetic field having a ⁇ x direction component (leakage magnetic field) by the control unit 105 are applied to the sense layer 123b of the output unit 102b. Is done.
- the magnetization direction (“q”) of the sense layer 123b of the output unit 102b is the + y direction, which is the easy axis direction, because both magnetic fields almost cancel each other.
- the magnetization directions of the reference layer 121a and the sense layer 323a of the output unit 102a are parallel, and the MTJ of the output unit 102a has a low resistance.
- the magnetization directions of the reference layer 121b and the sense layer 323b of the output unit 102b are parallel, and the MTJ of the output unit 102b has a low resistance.
- the output data (“out”) when both the output sections are low resistance is set to “1”.
- the direction of magnetization of the sense layer 123a of the output unit 102a is the + y direction, which is the direction of the easy axis of magnetization, because both magnetic fields almost cancel each other.
- a magnetic field having a ⁇ x direction component by the input unit 104 and a magnetic field having a ⁇ x direction component by the control unit 105 are applied to the sense layer 123b of the output unit 102b.
- the magnetization direction of the sense layer 123b of the output unit 102b is in the ⁇ x direction that is substantially parallel to both magnetic fields because the two magnetic fields are generally intensified.
- the magnetization directions of the reference layer 121a and the sense layer 123a of the output unit 102a are parallel, and the MTJ of the output unit 102a has a low resistance.
- the magnetization directions of the reference layer 121b and the sense layer 123b of the output unit 102b are shifted from each other by 90 degrees, and the MTJ of the output unit 102b has a higher resistance than the parallel case.
- the output data when at least one of the two output units is not low resistance is set to “0”.
- the direction of magnetization of the sense layer 123a of the output unit 102a is in the + x direction, which is substantially parallel to both magnetic fields, since both magnetic fields are generally intensified.
- a magnetic field having a + x direction component by the input unit 104 and a magnetic field having a ⁇ x direction component by the control unit 105 are applied to the sense layer 123b of the output unit 102b.
- the direction of magnetization of the sense layer 123b of the output unit 102b is the + y direction, which is the easy axis direction of magnetization, because both magnetic fields almost cancel each other.
- the magnetization directions of the reference layer 121a and the sense layer 123a of the output unit 102a are shifted from each other by 90 degrees, and the MTJ of the output unit 102a has a higher resistance than that in the parallel case.
- the magnetization directions of the reference layer 121b and the sense layer 123b of the output unit 102b are parallel, and the MTJ of the output unit 102b has a low resistance.
- the output data when at least one of the two output units is not low resistance is set to “0”.
- the direction of magnetization of the sense layer 123a of the output unit 102a is in the + x direction, which is substantially parallel to both magnetic fields, since both magnetic fields are generally intensified.
- a magnetic field having a ⁇ x direction component by the input unit 104 and a magnetic field having a ⁇ x direction component by the control unit 105 are applied to the sense layer 123b of the output unit 102b.
- the magnetization direction of the sense layer 123b of the output unit 102b is in the ⁇ x direction that is substantially parallel to both magnetic fields because the two magnetic fields are generally intensified.
- the magnetization directions of the reference layer 121a and the sense layer 123a of the output unit 102a are shifted from each other by 90 degrees, and the MTJ of the output unit 102a has a higher resistance than that in the parallel case.
- the magnetization directions of the reference layer 121b and the sense layer 123b in the output unit 102b are shifted from each other by 90 degrees, and the MTJ of the output unit 102b has a higher resistance than in the parallel case.
- the output data when at least one of the two output units is not low resistance is set to “0”.
- the non-volatile logic circuit 301 outputs the output data “1”, “0”, “0”, “0” with respect to the input data “00”, “01”, “10”, “11”, respectively. Is output. That is, when the control data “0” is set in the control unit 105, the nonvolatile logic circuit 101 can operate as a NOR circuit.
- FIG. 34B shows a case where the magnetization direction of the bias layer 153 of the control unit 105 is preset in the + z direction (control data “1”).
- the magnetization direction (“p”) of the sense layer 123a of the output unit 102a is in the ⁇ x direction that is substantially parallel to both magnetic fields because the two magnetic fields are generally intensified.
- a magnetic field (leakage magnetic field) having a + x direction component by the input unit 104 and a magnetic field (leakage magnetic field) having a + x direction component by the control unit 105 are applied to the sense layer 123b of the output unit 102b.
- the magnetization direction (“q”) of the sense layer 123b of the output unit 102b is in the + x direction that is substantially parallel to both magnetic fields because the two magnetic fields are generally intensified.
- the magnetization directions of the reference layer 121a and the sense layer 123a of the output unit 102a are shifted from each other by 90 degrees, and the MTJ of the output unit 102a has a higher resistance than that in the parallel case.
- the magnetization directions of the reference layer 121b and the sense layer 123b in the output unit 102b are shifted from each other by 90 degrees, and the MTJ of the output unit 102b has a higher resistance than in the parallel case.
- Output data (“out”) when at least one of the two output units is not low resistance is set to “0”.
- the magnetization direction of the sense layer 123a of the output unit 102a is in the ⁇ x direction that is substantially parallel to both magnetic fields because the two magnetic fields are generally intensified.
- a magnetic field having a ⁇ x direction component by the input unit 104 and a magnetic field having a + x direction component by the control unit 105 are applied to the sense layer 123b of the output unit 102b.
- the magnetization direction of the sense layer 123b of the output unit 102b is the + y direction of the easy axis direction because both magnetic fields cancel each other.
- the magnetization directions of the reference layer 121a and the sense layer 123a of the output unit 102a are shifted from each other by 90 degrees, and the MTJ of the output unit 102a has a higher resistance than that in the parallel case.
- the magnetization directions of the reference layer 121b and the sense layer 123b of the output unit 102b are parallel, and the MTJ of the output unit 102b has a low resistance.
- the output data when at least one of the two output units is not low resistance is set to “0”.
- the direction of magnetization of the sense layer 123a of the output unit 102a is + y direction of the easy axis direction because both magnetic fields almost cancel each other.
- a magnetic field having a + x direction component by the input unit 104 and a magnetic field having a + x direction component by the control unit 105 are applied to the sense layer 123b of the output unit 102b.
- the magnetization direction of the sense layer 123b of the output unit 102b is in the + x direction that is substantially parallel to both magnetic fields because the two magnetic fields are generally intensified.
- the magnetization directions of the reference layer 121a and the sense layer 123a of the output unit 102a are parallel, and the MTJ of the output unit 102a has a low resistance.
- the magnetization directions of the reference layer 121b and the sense layer 123b of the output unit 102b are shifted from each other by 90 degrees, and the MTJ of the output unit 102b has a higher resistance than the parallel case.
- the output data when at least one of the two output units is not low resistance is set to “0”.
- the direction of magnetization of the sense layer 123a of the output unit 102a is + y direction of the easy axis direction because both magnetic fields almost cancel each other.
- a magnetic field having a ⁇ x direction component by the input unit 104 and a magnetic field having a + x direction component by the control unit 105 are applied to the sense layer 123b of the output unit 102b.
- the magnetization direction of the sense layer 123b of the output unit 102b is the + y direction of the easy axis direction because both magnetic fields cancel each other.
- the magnetization directions of the reference layer 121a and the sense layer 123a of the output unit 102a are parallel, and the MTJ of the output unit 102a has a low resistance.
- the magnetization directions of the reference layer 121b and the sense layer 123b of the output unit 102b are parallel to each other, and the MTJ of the output unit 102b has a low resistance.
- the output data when both the output sections are low resistance is set to “1”.
- the nonvolatile logic circuit 301 outputs the output data “0”, “0”, “0”, “1” with respect to the input data “00”, “01”, “10”, “11”, respectively. Is output. That is, when the control data “1” is set in the control unit 105, the nonvolatile logic circuit 101 can operate as an AND circuit.
- the nonvolatile logic circuit 101 in this embodiment can be used as a NOR circuit or an AND circuit by controlling the magnetization state of the magnetization switching region 155. Therefore, by configuring the NOR circuit and the AND circuit with the nonvolatile logic circuit 101 in this embodiment and combining them, another logic circuit can be assembled.
- Data input / output principle of the nonvolatile logic circuit according to the eighth embodiment of the present invention will be described with reference to FIGS. 33A and 33B.
- Data is input to the nonvolatile logic circuit 101 by writing data to the domain wall motion elements of the control unit 105 and the input units 103 and 104.
- data is output from the nonvolatile logic circuit 101 by reading data from the TMR elements of the output units 102a and 102b.
- Control data is written to the control unit 105 in advance before the operation of the nonvolatile logic circuit 101 (control data is input to the control unit 105). That is, the writing is performed by setting the domain wall motion element of the control unit 105 to, for example, the first magnetization state MS1 or the second magnetization state MS2 corresponding to “0” or “1” of the control data.
- the method for setting the first magnetization state MS1 or the second magnetization state MS2 is as described above.
- the nonvolatile logic circuit 101 can be set to one of a NOR circuit and an AND circuit.
- input data is written to the input unit 103 during the operation of the nonvolatile logic circuit 101 (input data is input to the input unit 103). That is, the writing is performed by setting the domain wall motion element of the input unit 103 to, for example, the first magnetization state MS1 or the second magnetization state MS2 corresponding to “0” or “1” of the input data.
- the method for setting the first magnetization state MS1 or the second magnetization state MS2 is as described above.
- input data is written to the input unit 104 during operation of the nonvolatile logic circuit 101 (input data is input to the input unit 104). That is, the writing is performed by setting the domain wall motion element of the input unit 104 to the first magnetization state MS1 or the second magnetization state MS2 corresponding to, for example, “0” or “1” of the input data.
- the method for setting the first magnetization state MS1 or the second magnetization state MS2 is as described above.
- data is input to the nonvolatile logic circuit 101.
- the control unit 105 and the input units 103 and 104 are in a desired magnetization state reflecting those data.
- output data is written to the output units 102a and 102b by the leakage magnetic field (synthetic magnetic field) from the control unit 105 and the input units 103 and 104.
- the control circuit 381 generates a write current IW having a magnitude and a direction corresponding to the control data in response to the supply of the control data as a prior setting operation of the nonvolatile logic circuit 101. Then, the signal is supplied to the path of the first control terminal 165 a, the control unit 105, and the second control terminal 165 b of the nonvolatile logic circuit 101 via the terminal Control and the terminal 392. Thereby, control data can be set in the control unit 105 (magnetization switching region 155). As a result, the nonvolatile logic circuit 101 can be set as a desired logic operation circuit (example: NOR circuit).
- the control circuit 381 first generates a write current IW1 having a magnitude and direction corresponding to the first input data in response to the supply of the first input data. Then, the signal is supplied to the path of the first input terminal 163a, the input unit 103, and the second input terminal 163b of the nonvolatile logic circuit 101 via the terminal IN1 and the terminal 392. Next, in response to the supply of the second input data, a write current IW2 having a magnitude and direction corresponding to the second input data is generated.
- the signal is supplied to the path of the first input terminal 164a, the input unit 104, and the second input terminal 164b of the nonvolatile logic circuit 101 via the terminal IN2 and the terminal 392.
- input data first input data, second input data
- the control circuit 381 generates a read current IR.
- the current flows through the terminal 391 and the terminal 392 through the path of the output terminal (not shown), the output unit 102a, the conductor layer 106, the output unit 102b, and another output terminal (not shown).
- a voltage (output voltage) corresponding to the MTJ resistance value of the output unit 102 a and the output unit 102 b is output from the terminal Out to the comparator 382.
- the comparator 382 compares the output voltage from the non-volatile logic circuit 101 with the reference voltage from the MTJ reference element 383, and outputs final output data. Thereby, the non-volatile logic circuit 101 can output output data indicating a desired logical operation result for the input data.
- the nonvolatile logic circuit 101 is set to a desired logic circuit, and input data is input to the nonvolatile logic circuit 101 and output data is output from the nonvolatile logic circuit 101. It becomes possible.
- the nonvolatile logic circuit 101 of this embodiment can reconfigure its logic by changing control data (configuration information) input to the control unit 105. That is, the non-volatile logic circuit 101 according to the present embodiment uses a read / write separation type domain wall motion element (control unit 105, input units 103, 104) and MTJ (output units 102a, 102b). A circuit can be realized.
- the nonvolatile logic circuit of the present embodiment stores configuration information (control data) in the control unit 105.
- the control unit 105 can be regarded as a nonvolatile memory using a domain wall motion element. By using this nonvolatile memory, it is not necessary to have an SRAM for holding configuration information when the power is turned off. Therefore, it is possible to solve the increase in area due to the non-volatile memory provided as a problem in the FPGA.
- the control unit 105, the storage units 103 and 104, and the output units 102a and 102b use magnetoresistive elements such as domain wall motion elements.
- magnetoresistive elements such as domain wall motion elements.
- they function as an element having both a logic element and a nonvolatile memory as a whole. Therefore, even if a magnetoresistive element is used, the size of the element can be kept small as a whole. Further, since the magnetoresistive element can operate at room temperature, the nonvolatile logic circuit of this embodiment can operate at room temperature.
- the present invention can provide a reconfigurable nonvolatile logic circuit element while suppressing an increase in the area of the element.
- the logic of the nonvolatile logic circuit 101 can be changed by changing the setting of the reference voltage level.
- FIG. 34A if the output of case ⁇ 4 is set to “0” and the outputs of the other cases ⁇ 1 to ⁇ 3 are set to “1”, what was originally NOR logic can be changed to NAND logic. In this case, “1” is set when the MTJ resistance value of the output units 102a and 102b is maximum, and “0” is set otherwise.
- FIG. 34B if the output of case ⁇ 1 is set to “0” and the outputs of other cases ⁇ 2 to ⁇ 4 are set to “1”, the original AND logic can be changed to OR logic. In this case, “1” is set when the MTJ resistance value of the output units 102a and 102b is maximum, and “0” is set otherwise.
- the control unit 105 is provided between the input unit 103 and the input unit 104.
- the arrangement order of the input units 103 and 104 and the control unit 105 is arbitrary.
- the output data is set to “1” when the magnetization directions of the output units 102a and 102b, such as case ⁇ 1 and case ⁇ 4, are both in the + y direction. This is because the output data is set to “0”.
- the relative positional relationship between the input units 103 and 104 and the control unit 105 is irrelevant.
- FIGS. 33A and 33B are schematic views showing modifications of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- the sense layers 123a and 123b of the output units 102a and 102b may overlap (overlap) the input units 103 and 104 and the control unit 105.
- the leakage magnetic field is maximized at the edges. Therefore, the sensitivity of the sense layers 123a and 123b can be further increased by overlapping (overlapping) the arrangement.
- the length of each sense layer in the x direction is larger than the interval between each input unit and the control unit.
- the overlapping (overlapping) portions may be only the sense layers 123a and 123b as shown in FIG. 35B or the entire output units 102a and 102b as shown in FIG. 35C. Good.
- the sense layers 123a and 123b of the output units 102a and 102b may be arranged in the + y direction with respect to the input units 103 and 104 and the control unit 105. Shifting each output unit in the + y direction has an advantage that the magnetization of the sense layer can be easily directed in the + y direction when the magnetizations of the left and right input units and the control unit are parallel to each other. Also in this case, the arrangement may overlap as shown in FIG. 35B or 35C.
- FIG. 36A to FIG. 36C are diagrams for explaining another modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- the sense layers of the output units 102a and 102b may be one large sense layer 123.
- the sense layer 123 has a multi-domain structure.
- “p” and “q” in FIG. 34A indicate the magnetization directions of magnetic domains corresponding to the respective positions of the output units 102a and 102b (indicated by broken lines), as shown in FIG.
- the output unit (entire MTJ) including the reference layer may be one large output unit 102.
- the sense layer 123 has a multi-domain structure as shown in FIG. 36B. By comprising in this way, manufacture of an output part can be made still easier. Even in these cases, two output terminals for supplying / extracting the read current to / from the output unit are provided at the same positions as in FIG. 33A.
- a magnetization fixed layer (hard layer) for initialization may be provided in each magnetization fixed region of the input units 103 and 104 and the control unit 105.
- FIG. 37A to FIG. 37B are diagrams for explaining still another modified example of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- each magnetization fixed layer is provided adjacent to the lower side ( ⁇ z direction) of each magnetization fixed region.
- the positions of the magnetization fixed layers are arbitrary as long as they are adjacent to each other.
- the magnetization fixed layer 148a and the magnetization fixed layer 148b of the input unit 104 preferably have different magnetic characteristics.
- each magnetization fixed layer may be provided adjacent to the upper side (+ z direction) of each magnetization fixed region. The upper side is easier to manufacture because of the direct magnetic coupling.
- FIG. 38 is a perspective view showing another modification of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention. As shown in FIG. 38, the vertical (z direction) relationship between the input units 103 and 104, the control unit 105, and the output units 102a and 102b may be reversed.
- the magnetization fixed layer (hard layer) shown in FIGS. 37A and 37B it is preferable in manufacturing that the nonvolatile logic circuit 101 is configured in the order as shown in FIG.
- FIG. 39 is a schematic diagram showing still another modified example of the configuration of the nonvolatile logic circuit according to the eighth embodiment of the present invention.
- input units 107 and 108 are added, and output units 102c and 102d are added.
- output units 102c and 102d are added.
- the diagram is As in 34A and FIG. 34B, a NOR operation, an AND operation, and the like can be performed.
- FIG. 40A is a perspective view showing a configuration of a nonvolatile logic circuit according to the ninth exemplary embodiment of the present invention.
- FIG. 40B is a plan view showing the configuration of the nonvolatile logic circuit according to Embodiment 9 of the present invention.
- the nonvolatile logic circuit 201 includes an input unit 203, an output unit 202, a control unit 205, and a conductor layer 206.
- the non-volatile logic circuit 201 is the same as the non-volatile logic circuit 101 except that the non-volatile logic circuit 101 (the eighth embodiment) has one less input unit and one output unit. Therefore, the description is omitted.
- the input unit 203 first magnetization fixed region 234a, magnetization switching region 235, second magnetization fixed region 234b
- output unit 202 reference layer 221, barrier layer 222, sense layer 223
- control unit 205 first magnetization
- the fixed region 254a, the magnetization switching region 255, the first magnetization fixed region 254b), and the conductor layer 206 are the input unit 103 (first magnetization fixed region 134a, magnetization switching region 135, second magnetization fixed region 134b) and output unit, respectively.
- 102a reference layer 121a, barrier layer 122a, sense layer 123a
- control unit 105 first magnetization fixed region 154a, magnetization switching region 155, second magnetization fixed region 154b
- conductor layer 106 conductor layer 106.
- 41A and 41B are tables showing the relationship between the magnetization switching region and the magnetization direction of the sense layer according to the ninth embodiment of the present invention.
- “A” indicates input data written to the input unit 203.
- “A” indicates the magnetization direction of the magnetization switching region 235.
- “L” indicates the magnetization direction of the magnetization switching region 255.
- “R” indicates the magnetization direction of the sense layer 223.
- “Out” indicates output data.
- a white circle indicates a magnetization in the ⁇ z direction. Black dots on the white circles indicate magnetization in the + z direction.
- An upward arrow indicates magnetization in the + y direction.
- a right-pointing arrow indicates magnetization in the + x direction.
- the left arrow indicates magnetization in the -x direction.
- the input data of the input unit 203 is set to “0”.
- the magnetization direction of the magnetization switching region 235 is the + z direction
- the input data of the input unit 203 is “1”.
- the control data of the control unit 205 is set to “0”.
- the magnetization direction of the magnetization switching region 255 is ⁇ z
- the control data of the control unit 205 is set to “1”.
- FIG. 41A shows a case where the magnetization direction of the magnetization switching region 255 of the control unit 205 is preset in the + z direction (control data “0”).
- the magnetization direction (“r”) of the sense layer 223 of the output unit 202 is in the ⁇ x direction substantially parallel to both magnetic fields because both magnetic fields strengthen each other.
- the magnetization directions of the reference layer 221 and the sense layer 223 of the output unit 202 are shifted from each other by 90 degrees, and the MTJ of the output unit 202 has a higher resistance than the parallel case.
- the output data (“out”) when the output unit 202 has a high resistance is set to “0”.
- the magnetization directions of the reference layer 221 and the sense layer 223 of the output unit 202 are parallel, and the MTJ of the output unit 202 has a low resistance.
- the output data when the output unit 202 has a low resistance is set to “1”.
- the nonvolatile logic circuit 201 outputs the output data “0” and “1” with respect to the input data “0” and “1”, respectively. That is, when the control data “0” is set in the control unit 205, the nonvolatile logic circuit 201 can operate as a Through circuit.
- FIG. 41B shows a case where the magnetization direction of the bias layer 253 of the control unit 205 is preset in the ⁇ z direction (control data “1”).
- the direction of magnetization (“r”) of the sense layer 223 of the output unit 202 is the + y direction, which is the direction of the easy axis of magnetization, because both magnetic fields almost cancel each other.
- the magnetization directions of the reference layer 221 and the sense layer 223 of the output unit 202 are parallel, and the MTJ of the output unit 202 has a low resistance.
- the output data (“out”) when the output unit 202 has a low resistance is set to “1”.
- the magnetization directions of the reference layer 221 and the sense layer 223 of the output unit 202 are shifted from each other by 90 degrees, and the MTJ of the output unit 202 has a higher resistance than the parallel case.
- the output data when the output unit 202 has a high resistance is set to “0”.
- the nonvolatile logic circuit 201 outputs the output data “1” and “0” with respect to the input data “0” and “1”, respectively. That is, when the control data “1” is set in the control unit 205, the nonvolatile logic circuit 201 can operate as a NOT circuit.
- the nonvolatile logic circuit 201 in this embodiment can be used as a Through circuit or a NOT circuit by controlling the magnetization state of the magnetization switching region 255. Therefore, by configuring the Through circuit and the NOT circuit with the nonvolatile logic circuit 201 in this embodiment and combining them, another logic circuit can be assembled. Note that if the “1” and “0” are reversed in the output data setting, the Through circuit and the NOT circuit can be reversed.
- Data input to the nonvolatile logic circuit 201 is performed by writing data to the domain wall motion elements of the control unit 205 and the input unit 203.
- data is output from the non-volatile logic circuit 201 by reading data from the TMR element of the output unit 202. Since writing and reading of the data in this data input / output principle are the same as those of the nonvolatile logic circuit 101 (eighth embodiment), the description thereof is omitted.
- the control circuit 481 generates a write current IW having a magnitude and a direction corresponding to the control data in response to the supply of the control data as a prior setting operation of the nonvolatile logic circuit 201. Then, the signal is supplied to the path of the first control terminal 265a, the control unit 205, and the second control terminal 265b of the nonvolatile logic circuit 201 through the terminal Control and the terminal 492. As a result, control data can be set in the control unit 205 (magnetization switching region 255). As a result, the non-volatile logic circuit 201 can be set to a desired logic operation circuit (example: NOT circuit).
- the control circuit 481 first generates a write current IW1 having a size and direction corresponding to the input data in response to the supply of the input data. Then, the signal is supplied to the path of the first input terminal 263a, the input unit 203, and the second input terminal 263b of the nonvolatile logic circuit 201 through the terminal IN1 and the terminal 492. Thereby, input data can be input to the input unit 203. Thereafter, the control circuit 481 generates a read current IR. Then, the current flows through the terminal 491 and the terminal 492 through an output terminal (not shown), the output unit 202, the conductor layer 206, and the first input terminal 236a.
- a voltage (output voltage) corresponding to the MTJ resistance value of the output unit 202 is output from the terminal Out to the comparator 482.
- the comparator 482 compares the output voltage from the non-volatile logic circuit 201 with the reference voltage from the MTJ reference element 483, and outputs final output data. Thereby, the non-volatile logic circuit 201 can output the output data which shows a desired logic operation result with respect to input data.
- the nonvolatile logic circuit 201 is set as a desired logic circuit, and input data is input to the nonvolatile logic circuit 201 and output data is output from the nonvolatile logic circuit 201. It becomes possible.
- nonvolatile logic circuit 201 of this embodiment the same effect as that of the nonvolatile logic circuit 101 of the eighth embodiment can be obtained.
- the configuration of the nonvolatile logic circuit 201 of the present embodiment can be modified in the same manner as the nonvolatile logic circuit 101 of the eighth embodiment as long as no technical contradiction occurs.
- FIG. 42 is a perspective view showing the configuration of the nonvolatile logic circuit according to the tenth embodiment of the present invention.
- the nonvolatile logic circuit 296 includes the nonvolatile logic circuit 101 according to the eighth embodiment, the nonvolatile logic circuit 201 according to the ninth embodiment, and a signal transmission circuit 297.
- the non-volatile logic circuit 296 is a circuit combining the non-volatile logic circuit 101 (eighth embodiment) and the non-volatile logic circuit 201 (ninth embodiment). That is, output data of the nonvolatile logic circuit 101 is used as input data of the nonvolatile logic circuit 201. Specifically, first, first input data is input to the input unit 103 of the nonvolatile logic circuit 101, and second input data is input to the input unit 104. Next, the signal transmission circuit 297 detects the magnetization states (output data) of the output units 102a and 102b that have changed according to the input data.
- the signal transmission circuit 297 detects the resistance values of the output units 102a and 102b, and determines whether the output data is “0” or “1”. Then, the signal transmission circuit 297 inputs the determined output data as input data to the input unit 203 of the nonvolatile logic circuit 201.
- the magnetization state (output data) of the output unit 202 changed by the input data is used as final output data of the nonvolatile logic circuit 296.
- Others are the same as those of the non-volatile logic circuits 101 and 201. Therefore, the description is omitted.
- 43A and 43B are tables showing the relationship between the magnetization switching region and the magnetization direction of the sense layer of each nonvolatile logic circuit according to the tenth embodiment of the present invention.
- “A” indicates input data written to the input unit 103 (magnetization switching region 135).
- “B” indicates input data written to the input unit 104 (magnetization switching region 145).
- “A” indicates the magnetization direction of the magnetization switching region 135.
- B” indicates the magnetization direction of the magnetization switching region 145.
- L1 indicates the magnetization direction of the magnetization switching region 155.
- P indicates the magnetization direction of the sense layer 123a.
- “Q” indicates the magnetization direction of the sense layer 123b.
- “O-1” is output data from the output units 102 a and 102 b and indicates input data written to the input unit 203.
- “O” indicates the magnetization direction of the magnetization switching region 235.
- “12” indicates the magnetization direction of the magnetization switching region 255.
- “R” indicates the magnetization direction of the sense layer 223.
- “O-2” indicates output data from the output unit 202, that is, output data of the nonvolatile logic circuit 296.
- a white circle indicates a magnetization in the ⁇ z direction. Black dots on the white circles indicate magnetization in the + z direction.
- An upward arrow indicates magnetization in the + y direction.
- a right-pointing arrow indicates magnetization in the + x direction. The left arrow indicates magnetization in the -x direction.
- the setting of “0” and “1” for each input data, each control data, and each output data is the same as that of the non-volatile logic circuits 101 and 201. Therefore, the description is omitted.
- FIG. 43A will be described.
- the magnetization direction of the magnetization switching region 155 of the control unit 105 is in the ⁇ z direction (control data “0”)
- the magnetization direction of the magnetization switching region 255 of the control unit 205 is in the + z direction (control data “0”).
- the non-volatile logic circuit 101 operates as a NOR circuit as shown in FIG. 34A.
- the non-volatile logic circuit 201 operates as a Through circuit as shown in FIG. 41A.
- the nonvolatile logic circuit 296 operates as a NOR circuit as a whole.
- the nonvolatile logic circuit 296 outputs the output data “1”, “0”, “0”, “0” with respect to the input data “00”, “01”, “10”, “11”, respectively. Is output. That is, when the control data “0” and “0” are set in the control units 105 and 205, respectively, the nonvolatile logic circuit 296 can operate as a NOR circuit.
- FIG. 43B Shows a case where it is set in advance.
- the non-volatile logic circuit 101 operates as an AND circuit as shown in FIG. 34B.
- the non-volatile logic circuit 201 operates as a NOT circuit as shown in FIG. 41B. That is, the nonvolatile logic circuit 296 operates as a NAND circuit as a whole.
- the non-volatile logic circuit 296 outputs the output data “1”, “1”, “1”, “0” with respect to the input data “00”, “01”, “10”, “11”, respectively. Is output. That is, when the control data “1” and “1” are set in the control units 105 and 205, the nonvolatile logic circuit 296 can operate as a NAND circuit.
- the nonvolatile logic circuit 296 in this embodiment can be used as a NOR circuit or a NAND circuit by controlling the magnetization states of the control units 105 and 205 of the nonvolatile logic circuits 101 and 201. Therefore, by forming a NOR circuit and a NAND circuit with the nonvolatile logic circuit 296 in this embodiment and combining them, another logic circuit can be assembled.
- the eighth embodiment using the nonvolatile logic circuit 101 is used.
- the logic gate 380 shown in FIG. 22) and the ninth embodiment can be executed, and the description thereof is omitted.
- the signal transmission circuit 297 can be configured by, for example, the comparator 382 in FIG. 22, the MTJ reference element 383, and a part that controls the comparator 382 and the MTJ reference element 383 in the control circuit 381.
- nonvolatile logic circuit 296 of the present embodiment the same effects as those of the nonvolatile logic circuit 101 of the eighth embodiment and the nonvolatile logic circuit 201 of the ninth embodiment can be obtained. Furthermore, since a NOR circuit and a NAND circuit can be configured, any logic circuit can be assembled by combining them. In addition, in the nonvolatile logic circuit 296 of the present embodiment, as long as no technical contradiction occurs, the nonvolatile logic circuit 101 of the eighth embodiment and the nonvolatile logic circuit 201 of the ninth embodiment are the same. The configuration can be modified.
- the nonvolatile logic circuit and the logic gate using the nonvolatile logic circuit in each embodiment of the present invention are appropriately selected and combined to be used for a semiconductor device (for example, a semiconductor integrated circuit) that performs a logical operation.
- a semiconductor device for example, a semiconductor integrated circuit
- the semiconductor device can be formed.
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Abstract
Description
図1は、本発明の実施の形態に係る不揮発ロジック回路の原理を示す模式図である。この不揮発ロジック回路は、複数の入力部と、コントロール部と、出力部とを具備している。複数の入力部(この図では2個の場合を例示)は、垂直磁気異方性を有し、磁化状態が変化可能な強磁性層を含む。コントロール部は、強磁性層を含む(この図では面内磁気異方性の場合を例示)。出力部は、複数の入力部及びコントロール部の近傍に設けられ、磁化状態が変化可能な磁気トンネル結合素子を含む。複数の入力部の各々の磁化状態は、入力データに対応して変化する。出力部の磁気トンネル結合素子の磁化状態は、複数の入力部及びコントロール部の磁化状態に対応して変化する。すなわち、出力部の磁気トンネル結合素子の磁化状態は、複数の入力部及びコントロール部の磁化状態に対応して変動する漏洩磁界(H1、H2、H0)により変化する。この磁化状態の変化した磁気トンネル結合の抵抗値を検知することで、入力データに対応した出力データを得ることができる。この場合、コントロール部、複数の入力部及び出力部が論理素子とメモリとを兼ね備えた素子を構成している。以下、本発明の不揮発ロジック回路の実施の形態について詳細に説明する。
1.不揮発ロジック回路の基本構成
以下、本発明の第1の実施の形態に係る不揮発ロジック回路の基本構成について説明する。図2Aは、本発明の第1の実施の形態に係る不揮発ロジック回路の構成を示す断面図である。不揮発ロジック回路1は、入力部3、4と、出力部2と、コントロール部5とを具備している。
中間層32は、ピン層31と記憶層A33との間に設けられた非磁性膜である。
バリア層22は、リファレンス層21とセンス層23との間に設けられた絶縁膜である。
次に、本発明の第1の実施の形態に係る不揮発ロジック回路の取り得る磁化状態について説明する。図3A~図3Hは、本発明の第1の実施の形態に係る不揮発ロジック回路の磁化状態の例を示す断面図である。まず、図3A~図3Dについて説明する。ただし、以下の説明において、図3A~図3Dに示す状態を、それぞれ状態α1~状態α4と呼ぶことにする。状態α1~状態α4は、コントロール部5のバイアス層53の磁化の向きが+x方向である。
次に、本発明の第1の実施の形態に係る不揮発ロジック回路の動作原理について説明する。
図5は、本発明の第1の実施の形態に係るセンス層の磁化のx成分と合成磁界のx方向成分との関係を示すグラフである。縦軸はセンス層23の磁化Mのx方向成分Mx、横軸は合成磁界Hsのx方向成分Hsxをそれぞれ示す。磁界±Hkは、センス層23の飽和磁界を示している。既述のように、合成磁界Hsに応じて、センス層23の磁化Mはx方向成分Mxを有するようになる。そのMxは、図に示されるように、合成磁界Hsのx方向成分Hsxが-Hk≦Hsx≦+Hkとなる範囲において、そのHsxに概ね正比例する。そして、Mxは、その範囲において、Mx0(=-Mx1)≦Hsx≦Mx1を取る。したがって、一つのHsxに対応して、一つのMxを割り当てることができる。すなわち、印加されるHsxに対応して、一つのデータをセンス層23に書き込むことができる。
MTJ抵抗=R1: Hsx<-Hk
MTJ抵抗=(R0-R1)・Hsx/2Hk+(R0+R1)/2: -Hk<Hsx<+Hk
MTJ抵抗=R0: Hsx>+Hk
したがって、Hsxを-Hk<Hsx<+Hkの範囲に設定することで、一つのHsxに対応して、一つMTJ抵抗を割り当てることができる。それにより、印加されるHsxに対応してセンス層23に書き込まれたデータを、MTJ抵抗の値として読み出すことができる。
Hsx=記憶層A33からの漏洩磁界Hst1
+記憶層B43からの漏洩磁界Hst2
+バイアス層53からの漏洩磁界Hcontrol
ここで、記憶層A33、記憶層B43からの漏洩磁界(x方向成分)の大きさをいずれもsとし、バイアス層53からの漏洩磁界(x方向成分)の大きさをbとする。そのとき、図3A~図3Dに示す状態α1~状態α4については、記憶層A及び記憶層B43の磁化方向と、バイアス層53の磁化方向と、合成磁界Hsxとの関係は図7Aに示すようになる。図3E~図3Hに示す状態β1~状態β4については図7Bのようになる。
次に、本発明の第1の実施の形態に係る不揮発ロジック回路1のデータ入出力原理について説明する。不揮発ロジック回路1に対するデータの入力は、コントロール部5、入力部3、4のGMR素子(又はTMR素子)に対してデータを書き込むことで行う。一方、不揮発ロジック回路1からのデータの出力は、出力部2のTMR素子のデータの読み出しにより行う。以下詳細に説明する。
図10は、本発明の第1の実施の形態におけるデータの書き込み原理を説明する断面図である。コントロール部5は、不揮発ロジック回路1の動作前に、事前に制御データが書き込まれる。その制御データが書き込まれることにより、不揮発ロジック回路1をNAND回路(図3A~図3D、図7A、図9A)及びNOR回路(図3E~図3H、図7B、図9B)のいずれか一方に設定することができる。一方、入力部3、4は、不揮発ロジック回路1の動作時に、それぞれ第1入力データ及び第2入力データを供給される。
図11は、本発明の第1の実施の形態におけるデータの読み出し原理を説明する断面図である。出力部2は、TMR素子である。図3A~図3Hで説明したように、出力部2は、入力部3、4及びコントロール部5からの漏洩磁界(合成磁界Hs)により、入力部3、4及びコントロール部5の磁化状態の組み合わせに対応した磁化状態に変化している。すなわち、出力部2のセンス層23の磁化は、制御データ、第1入力データ及び第2入力データの組み合わせに対応した向きに変化している。その結果、出力部2のMTJ抵抗は、制御データ、第1入力データ及び第2入力データの組み合わせに対応した値になっている。この状態において、共通端子(Com)66と出力端子(Out)67との間に読み出し電流IRを印加することにより、そのMTJ抵抗の値を読み出すことができる。読出し電流IRの向きは特に問わない。そのMTJ抵抗は、本不揮発ロジック回路1の出力データとなる。なお、図示されないが、出力端子(Out)67の先は、書込み電流IWの場合と読み出し電流IRの場合とで異なる。
続いて、不揮発ロジック回路を用いた論理ゲートについて説明する。
図12は、本発明の第1の実施の形態における論理ゲートの一例を示すブロック図である。論理ゲート80は、制御回路81、不揮発ロジック回路1、MTJ参照素子83、及び比較器82を備える。
次に、本発明の第1の実施の形態に係る不揮発ロジック回路の動作方法について説明する。
制御回路81は、不揮発ロジック回路1の動作前に、コントロール部5に制御データを書き込む(ステップS1)。すなわち、制御端子(Control)65と出力端子(Out)67との間に書き込み電流Iwを印加する。書き込み電流Iwは、書き込みたい制御データ(バイアス層53に磁化の向き)に対応した向きに流す。この動作により、不揮発ロジック回路1を所望の論理回路(例示:NAND回路、NOR回路)として設定することができる。
本発明の第2の実施の形態に係る不揮発ロジック回路について説明する。図14は、本発明の第2の実施の形態に係る不揮発ロジック回路の構成を示す断面図である。不揮発ロジック回路1は、入力部3、4と、出力部2と、コントロール部5とを具備している。この不揮発ロジック回路1は、メタル層6が入力部4と接続していない点で第1の実施の形態の不揮発ロジック回路1と異なる。それに伴い、入力部4用に、他のメタル層8及び共通端子(Com2)68が更に設けられている。
本発明の第3の実施の形態に係る不揮発ロジック回路について説明する。図15は、本発明の第3の実施の形態に係る不揮発ロジック回路の構成を示す斜視図である。不揮発ロジック回路1は、入力部3、4と、出力部2と、コントロール部5とを具備している。この不揮発ロジック回路1は、入力部3、4がy方向に延伸する磁壁移動型の磁気記録層で構成されている点で第1の実施の形態の不揮発ロジック回路1と異なる。
また、この場合も、第2の実施の形態と同様に、入力部3、4に電流を供給する端子が互いに独立している。すなわち、入力部3に第1入力データを書き込む動作と、入力部4に第2入力データを書き込む動作とを同時に行うことが出来る。それにより、その動作を高速にすることが出来る。
本発明の第4の実施の形態に係る不揮発ロジック回路について説明する。図18は、本発明の第4の実施の形態に係る不揮発ロジック回路の構成を示す斜視図である。不揮発ロジック回路1は、入力部3、4と、出力部2と、他の入力部5、9とを具備している。この不揮発ロジック回路1は、出力部2の上部に入力部5、9を有している点で、出力部2の上部にコントロール部5を有している第1の実施の形態と異なる。すなわち、本実施の形態の不揮発ロジック回路1は4入力である点で、第1の実施の形態の2入力の不揮発ロジック回路1と異なる。
1.不揮発ロジック回路の基本構成
以下、本発明の第5の実施の形態に係る不揮発ロジック回路の基本構成について説明する。図20Aは、本発明の第5の実施の形態に係る不揮発ロジック回路の構成を示す斜視図である。図20Bは、本発明の第5の実施の形態に係る不揮発ロジック回路の構成を示す断面図である。不揮発ロジック回路301は、入力部303、304と、出力部302a、302bと、コントロール部305と、導体層306と、プラグ308とを具備している。
次に、本発明の第5の実施の形態に係る不揮発ロジック回路の動作原理について説明する。
入力部303の入力データ(「A」)は「0」であり、記憶層A333の磁化の向き(「a」)は、-z方向である。入力部304の入力データ(「B」)は「0」であり、記憶層B343の磁化の向き(「b」)は、-z方向である。コントロール部305の制御データは「0」であり、バイアス層353の磁化の向き(「l」)は-z方向である。このとき、出力部302aのセンス層323aには、入力部303による-x方向成分を有する磁界(漏洩磁界)と、コントロール部305による+x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部302aのセンス層323aの磁化の向き(「p」)は、両磁界が概ね打ち消し合うため、磁化容易軸方向である+y方向になる。同様に、このとき、出力部302bのセンス層323bには、入力部304による+x方向成分を有する磁界(漏洩磁界)と、コントロール部305による-x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部302bのセンス層323bの磁化の向き(「q」)は、両磁界が概ね打ち消し合うため、磁化容易軸方向である+y方向になる。その結果、出力部302aのリファレンス層321aとセンス層323aの磁化方向は平行になり、出力部302aのMTJは低抵抗となる。同様に、出力部302bのリファレンス層321bとセンス層323bの磁化方向は平行になり、出力部302bのMTJは低抵抗となる。この両出力部が低抵抗である場合の出力データ(「out」)を「1」と設定する。
入力部303の入力データは「0」であり、記憶層A333の磁化の向きは、-z方向である。入力部304の入力データは「1」であり、記憶層B343の磁化の向きは、+z方向である。コントロール部305の制御データは「0」であり、バイアス層353の磁化の向きは-z方向である。このとき、出力部302aのセンス層323aには、入力部303による-x方向成分を有する磁界と、コントロール部305による+x方向成分を有する磁界とが印加される。その結果、出力部302aのセンス層323aの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向である+y方向になる。一方、このとき、出力部302bのセンス層323bには、入力部304による-x方向成分を有する磁界と、コントロール部305による-x方向成分を有する磁界とが印加される。その結果、出力部302bのセンス層323bの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な-x方向になる。その結果、出力部302aのリファレンス層321aとセンス層323aの磁化方向は平行になり、出力部302aのMTJは低抵抗となる。一方、出力部302bのリファレンス層321bとセンス層323bの磁化方向は互いに90度ずれた状態になり、出力部302bのMTJは平行な場合と比較して高抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データを「0」と設定する。
入力部303の入力データは「1」であり、記憶層A333の磁化の向きは、+z方向である。入力部304の入力データは「0」であり、記憶層B343の磁化の向きは、-z方向である。コントロール部305の制御データは「0」であり、バイアス層353の磁化の向きは-z方向である。このとき、出力部302aのセンス層323aには、入力部303による+x方向成分を有する磁界と、コントロール部305による+x方向成分を有する磁界とが印加される。その結果、出力部302aのセンス層323aの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な+x方向になる。一方、このとき、出力部302bのセンス層323bには、入力部304による+x方向成分を有する磁界と、コントロール部305による-x方向成分を有する磁界とが印加される。その結果、出力部302bのセンス層323bの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向である+y方向になる。その結果、出力部302aのリファレンス層321aとセンス層323aの磁化方向は互いに90度ずれた状態になり、出力部302aのMTJは平行な場合と比較して高抵抗となる。一方、出力部302bのリファレンス層321bとセンス層323bの磁化方向は平行になり、出力部302bのMTJは低抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データを「0」と設定する。
入力部303の入力データは「1」であり、記憶層A333の磁化の向きは、+z方向である。入力部304の入力データは「1」であり、記憶層B343の磁化の向きは、-z方向である。コントロール部305の制御データは「0」であり、バイアス層353の磁化の向きは-z方向である。このとき、出力部302aのセンス層323aには、入力部303による+x方向成分を有する磁界と、コントロール部305による+x方向成分を有する磁界とが印加される。その結果、出力部302aのセンス層323aの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な+x方向になる。同様に、このとき、出力部302bのセンス層323bには、入力部304による-x方向成分を有する磁界と、コントロール部305による-x方向成分を有する磁界とが印加される。その結果、出力部302bのセンス層323bの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な-x方向になる。その結果、出力部302aのリファレンス層321aとセンス層323aの磁化方向は互いに90度ずれた状態になり、出力部302aのMTJは平行な場合と比較して高抵抗となる。同様に、出力部302bのリファレンス層321bとセンス層323bの磁化方向は互いに90度ずれた状態になり、出力部302bのMTJは平行な場合と比較して高抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データを「0」と設定する。
入力部303の入力データ(「A」)は「0」であり、記憶層A333の磁化の向き(「a」)は、-z方向である。入力部304の入力データ(「B」)は「0」であり、記憶層B343の磁化の向き(「b」)は、-z方向である。コントロール部305の制御データは「1」であり、バイアス層353の磁化の向き(「l」)は+z方向である。このとき、出力部302aのセンス層323aには、入力部303による-x方向成分を有する磁界(漏洩磁界)と、コントロール部305による-x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部302aのセンス層323aの磁化の向き(「p」)は、両磁界が概ね強め合うため、両磁界と略平行な-x方向になる。同様に、このとき、出力部302bのセンス層323bには、入力部304による+x方向成分を有する磁界(漏洩磁界)と、コントロール部305による+x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部302bのセンス層323bの磁化の向き(「q」)は、両磁界が概ね強め合うため、両磁界と略平行な+x方向になる。その結果、出力部302aのリファレンス層321aとセンス層323aの磁化方向は互いに90度ずれた状態になり、出力部302aのMTJは平行な場合と比較して高抵抗となる。同様に、出力部302bのリファレンス層321bとセンス層323bの磁化方向は互いに90度ずれた状態になり、出力部302bのMTJは平行な場合と比較して高抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データ(「out」)を「0」と設定する。
入力部303の入力データは「0」であり、記憶層A333の磁化の向きは、-z方向である。入力部304の入力データは「1」であり、記憶層B343の磁化の向きは、+z方向である。コントロール部305の制御データは「1」であり、バイアス層353の磁化の向きは+z方向である。このとき、出力部302aのセンス層323aには、入力部303による-x方向成分を有する磁界と、コントロール部305による-x方向成分を有する磁界とが印加される。その結果、出力部302aのセンス層323aの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な-x方向になる。一方、このとき、出力部302bのセンス層323bには、入力部304による-x方向成分を有する磁界と、コントロール部305による+x方向成分を有する磁界とが印加される。その結果、出力部302bのセンス層323bの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向の+y方向になる。その結果、出力部302aのリファレンス層321aとセンス層323aの磁化方向は互いに90度ずれた状態になり、出力部302aのMTJは平行な場合と比較して高抵抗となる。一方、出力部302bのリファレンス層321bとセンス層323bの磁化方向は平行になり、出力部302bのMTJは低抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データを「0」と設定する。
入力部303の入力データは「1」であり、記憶層A333の磁化の向きは+z方向である。入力部304の入力データは「0」であり、記憶層B343の磁化の向きは、-z方向である。コントロール部305の制御データは「1」であり、バイアス層353の磁化の向きは+z方向である。このとき、出力部302aのセンス層323aには、入力部303による+x方向成分を有する磁界と、コントロール部305による-x方向成分を有する磁界とが印加される。その結果、出力部302aのセンス層323aの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向の+y方向になる。一方、このとき、出力部302bのセンス層323bには、入力部304による+x方向成分を有する磁界と、コントロール部305による+x方向成分を有する磁界とが印加される。その結果、出力部302bのセンス層323bの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な+x方向になる。その結果、出力部302aのリファレンス層321aとセンス層323aの磁化方向は平行になり、出力部302aのMTJは低抵抗となる。一方、出力部302bのリファレンス層321bとセンス層323bの磁化方向は互いに90度ずれた状態になり、出力部302bのMTJは平行な場合と比較して高抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データを「0」と設定する。
入力部303の入力データは「1」であり、記憶層A333の磁化の向きは+z方向である。入力部304の入力データは「1」であり、記憶層B343の磁化の向きは、+z方向である。コントロール部305の制御データは「1」であり、バイアス層353の磁化の向きは+z方向である。このとき、出力部302aのセンス層323aには、入力部303による+x方向成分を有する磁界と、コントロール部305による-x方向成分を有する磁界とが印加される。その結果、出力部302aのセンス層323aの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向の+y方向になる。同様に、このとき、出力部302bのセンス層323bには、入力部304による-x方向成分を有する磁界と、コントロール部305による+x方向成分を有する磁界とが印加される。その結果、出力部302bのセンス層323bの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向の+y方向になる。その結果、出力部302aのリファレンス層321aとセンス層323aの磁化方向は平行になり、出力部302aのMTJは低抵抗となる。同様に、出力部302bのリファレンス層321bとセンス層323bの磁化方向は平行になり、出力部302bのMTJは低抵抗となる。この両出力部が低抵抗である場合の出力データを「1」と設定する。
次に、本発明の第5の実施の形態に係る不揮発ロジック回路のデータ入出力原理について説明する。不揮発ロジック回路301に対するデータの入力は、コントロール部305、入力部303、304のGMR素子(又はTMR素子)に対してデータを書き込むことで行う。一方、不揮発ロジック回路301からのデータの出力は、出力部302a、302bのTMR素子のデータの読み出しにより行う。以下詳細に説明する。
続いて、本発明の第5の実施の形態に係る不揮発ロジック回路を用いた論理ゲートの構成及び動作について説明する。図22は、本発明の第5の実施の形態における論理ゲートの一例を示すブロック図である。論理ゲート380は、制御回路381、不揮発ロジック回路301、MTJ参照素子383、及び比較器382を備える。
以下、本発明の第6の実施の形態に係る不揮発ロジック回路について説明する。図27は、本発明の実施の形態に係る不揮発ロジック回路の原理を示す模式図である。この不揮発ロジック回路は、一つの入力部と、コントロール部と、出力部とを具備している。入力部及びコントロール部は、垂直磁気異方性を有し、磁化状態が変化可能な強磁性層を含む。出力部は、入力部及びコントロール部の近傍に設けられ、磁化状態が変化可能な磁気トンネル結合素子を含む。入力部の磁化状態は、入力データに対応して変化する。出力部の磁気トンネル結合素子の磁化状態は、入力部及びコントロール部の磁化状態に対応して変化する。すなわち、出力部の磁気トンネル結合素子の磁化状態は、入力部及びコントロール部の磁化状態に対応して変動する漏洩磁界(H1、H0)により変化する。この磁化状態の変化した磁気トンネル結合の抵抗値を検知することで、入力データに対応した出力データを得ることができる。この場合、コントロール部、入力部及び出力部が論理素子とメモリとを兼ね備えた素子を構成している。
以下、本発明の第6の実施の形態に係る不揮発ロジック回路の基本構成について説明する。図28Aは、本発明の第6の実施の形態に係る不揮発ロジック回路の構成を示す斜視図である。図28Bは、本発明の第6の実施の形態に係る不揮発ロジック回路の構成を示す断面図である。不揮発ロジック回路401は、入力部403と、出力部402と、コントロール部405と、導体層406と、プラグ408とを具備している。
次に、本発明の第6の実施の形態に係る不揮発ロジック回路の動作原理について説明する。
入力部403の入力データ(「A」)は「0」であり、記憶層A433の磁化の向き(「a」)は、-z方向である。コントロール部405の制御データは「0」であり、バイアス層453の磁化の向き(「l」)は+z方向である。このとき、出力部402のセンス層423には、入力部403による-x方向成分を有する磁界(漏洩磁界)と、コントロール部405による-x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部402のセンス層423の磁化の向き(「r」)は、両磁界が強め合うため、両磁界と略平行な-x方向になる。その結果、出力部402のリファレンス層421とセンス層423の磁化方向は互いに90度ずれた状態になり、出力部402のMTJは平行な場合と比較して高抵抗となる。この出力部402が高抵抗である場合の出力データ(「out」)を「0」と設定する。
入力部403の入力データは「1」であり、記憶層A433の磁化の向きは、+z方向である。コントロール部405の制御データは「0」であり、バイアス層453の磁化の向きは+z方向である。このとき、出力部402のセンス層423には、入力部403による+x方向成分を有する磁界と、コントロール部405による-x方向成分を有する磁界とが印加される。その結果、出力部402のセンス層423の磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向である+y方向になる。その結果、出力部402のリファレンス層421とセンス層423の磁化方向は平行になり、出力部402のMTJは低抵抗となる。この出力部402が低抵抗である場合の出力データを「1」と設定する。
入力部403の入力データ(「A」)は「0」であり、記憶層A433の磁化の向き(「a」)は、-z方向である。コントロール部405の制御データは「1」であり、バイアス層453の磁化の向き(「l」)は-z方向である。このとき、出力部402のセンス層423には、入力部403による-x方向成分を有する磁界(漏洩磁界)と、コントロール部405による+x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部402のセンス層423の磁化の向き(「r」)は、両磁界が概ね打ち消し合うため、磁化容易軸方向の+y方向になる。その結果、出力部402のリファレンス層421とセンス層423の磁化方向は平行になり、出力部402のMTJは低抵抗となる。この出力部402が低抵抗である場合の出力データ(「out」)を「1」と設定する。
入力部403の入力データは「1」であり、記憶層A433の磁化の向きは、+z方向である。コントロール部405の制御データは「1」であり、バイアス層453の磁化の向きは-z方向である。このとき、出力部402のセンス層423には、入力部403による+x方向成分を有する磁界と、コントロール部405による+x方向成分を有する磁界とが印加される。その結果、出力部402のセンス層423の磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な+x方向になる。その結果、出力部402のリファレンス層421とセンス層423の磁化方向は互いに90度ずれた状態になり、出力部402のMTJは平行な場合と比較して高抵抗となる。この出力部402が高抵抗である場合の出力データを「0」と設定する。
次に、本発明の第6の実施の形態に係る不揮発ロジック回路のデータ入出力原理について説明する。不揮発ロジック回路401に対するデータの入力は、コントロール部405、入力部403のGMR素子(又はTMR素子)に対してデータを書き込むことで行う。一方、不揮発ロジック回路401からのデータの出力は、出力部402のTMR素子のデータの読み出しにより行う。本データ入出力原理における、それらデータの書き込み及び読み出しについては、不揮発ロジック回路301(第5の実施の形態)と同様であるので、その説明を省略する。
続いて、本発明の第6の実施の形態に係る不揮発ロジック回路を用いた論理ゲートの構成及び動作について説明する。図30は、本発明の第6の実施の形態における論理ゲートの一例を示すブロック図である。論理ゲート480は、制御回路481、不揮発ロジック回路401、MTJ参照素子483、及び比較器482を備える。
1.不揮発ロジック回路の基本構成
以下、本発明の第7の実施の形態に係る不揮発ロジック回路の基本構成について説明する。図31は、本発明の第7の実施の形態に係る不揮発ロジック回路の構成を示す斜視図である。不揮発ロジック回路496は、第5の実施の形態に係る不揮発ロジック回路301と、第6の実施の形態に係る不揮発ロジック回路401と、信号伝達回路497とを具備している。
次に、本発明の第7の実施の形態に係る不揮発ロジック回路の動作原理について説明する。
入力部303の入力データ(「A」)は「0」、入力部304の入力データ(「B」)は「0」である。これは、図21Aにおけるケースγ1である。この場合、不揮発ロジック回路301の出力部302a、302bからの出力データは「1」である。従って、入力部403の入力データ(「O-1」)は「1」である。これは、図29Aにおけるケースε2である。従って、出力部402からの出力データ(「O-2」)は「1」である。
入力部303の入力データは「0」、入力部304の入力データは「1」である。これは、図21Aにおけるケースγ2である。この場合、不揮発ロジック回路301の出力部302a、302bからの出力データは「0」である。従って、入力部403の入力データは「0」である。これは、図29Aにおけるケースε1である。従って、出力部402からの出力データは「0」である。
入力部303の入力データは「1」、入力部304の入力データは「0」である。これは、図21Aにおけるケースγ3である。この場合、不揮発ロジック回路301の出力部302a、302bからの出力データは「0」である。従って、入力部403の入力データは「0」である。これは、図29Aにおけるケースε1である。従って、出力部402からの出力データは「0」である。
入力部303の入力データは「1」、入力部304の入力データは「1」である。これは、図21Aにおけるケースγ4である。この場合、不揮発ロジック回路301の出力部302a、302bからの出力データは「0」である。従って、入力部403の入力データは「0」である。これは、図29Aにおけるケースε1である。従って、出力部402からの出力データは「0」である。
入力部303の入力データ(「A」)は「0」、入力部304の入力データ(「B」)は「0」である。これは、図21Bにおけるケースδ1である。この場合、不揮発ロジック回路301の出力部302a、302bからの出力データは「0」である。従って、入力部403の入力データ(「O-1」)は「0」である。これは、図29Bにおけるケースζ1である。従って、出力部402からの出力データ(「O-2」)は「1」である。
入力部303の入力データは「0」、入力部304の入力データは「1」である。これは、図21Bにおけるケースδ2である。この場合、不揮発ロジック回路301の出力部302a、302bからの出力データは「0」である。従って、入力部403の入力データは「0」である。これは、図29Bにおけるケースζ1である。従って、出力部402からの出力データは「1」である。
入力部303の入力データは「1」、入力部304の入力データは「0」である。これは、図21Bにおけるケースδ3である。この場合、不揮発ロジック回路301の出力部302a、302bからの出力データは「0」である。従って、入力部403の入力データは「0」である。これは、図29Bにおけるケースζ1である。従って、出力部402からの出力データは「1」である。
入力部303の入力データは「1」、入力部304の入力データは「1」である。これは、図21Bにおけるケースδ4である。この場合、不揮発ロジック回路301の出力部302a、302bからの出力データは「1」である。従って、入力部403の入力データは「1」である。これは、図29Bにおけるケースζ2である。従って、出力部402からの出力データは「0」である。
次に、本発明の第7の実施の形態に係る不揮発ロジック回路のデータ入出力原理については、第5の実施の形態(不揮発ロジック回路301)及び第6の実施の形態(不揮発ロジック回路401)と同様であるので、その説明を省略する。
続いて、本発明の第7の実施の形態に係る不揮発ロジック回路を用いた論理ゲートの構成及び動作については、第5の実施の形態(不揮発ロジック回路301を用いた論理ゲート380:図22)と第6の実施の形態(不揮発ロジック回路401を用いた論理ゲート480:図30)とを組み合わせたもので実行可能であるので、その説明を省略する。ただし、信号伝達回路497は、例えば、図22における比較器382と、MTJ参照素子383と、制御回路381のうちの比較器382とMTJ参照素子383を制御する部分とで構成することができる。
1.不揮発ロジック回路の基本構成
以下、本発明の第8の実施の形態に係る不揮発ロジック回路の基本構成について説明する。図33Aは、本発明の第8の実施の形態に係る不揮発ロジック回路の構成を示す斜視図である。図33Bは、本発明の第8の実施の形態に係る不揮発ロジック回路の構成を示す平面図である。不揮発ロジック回路101は、入力部103、104と、出力部102a、102bと、コントロール部105と、導体層106とを具備している。
次に、本発明の第8の実施の形態に係る不揮発ロジック回路の動作原理について説明する。
入力部103の入力データ(「A」)は「0」であり、磁化反転領域135の磁化の向き(「a」)は、-z方向である。入力部104の入力データ(「B」)は「0」であり、磁化反転領域145の磁化の向き(「b」)は、-z方向である。コントロール部105の制御データは「0」であり、磁化反転領域155の磁化の向き(「l」)は-z方向である。このとき、出力部102aのセンス層123aには、入力部103による-x方向成分を有する磁界(漏洩磁界)と、コントロール部105による+x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部102aのセンス層123aの磁化の向き(「p」)は、両磁界が概ね打ち消し合うため、磁化容易軸方向である+y方向になる。同様に、このとき、出力部102bのセンス層123bには、入力部104による+x方向成分を有する磁界(漏洩磁界)と、コントロール部105による-x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部102bのセンス層123bの磁化の向き(「q」)は、両磁界が概ね打ち消し合うため、磁化容易軸方向である+y方向になる。その結果、出力部102aのリファレンス層121aとセンス層323aの磁化方向は平行になり、出力部102aのMTJは低抵抗となる。同様に、出力部102bのリファレンス層121bとセンス層323bの磁化方向は平行になり、出力部102bのMTJは低抵抗となる。この両出力部が低抵抗である場合の出力データ(「out」)を「1」と設定する。
入力部103の入力データは「0」であり、磁化反転領域135の磁化の向きは、-z方向である。入力部104の入力データは「1」であり、磁化反転領域145の磁化の向きは、+z方向である。コントロール部105の制御データは「0」であり、磁化反転領域155の磁化の向きは-z方向である。このとき、出力部102aのセンス層123aには、入力部103による-x方向成分を有する磁界と、コントロール部105による+x方向成分を有する磁界とが印加される。その結果、出力部102aのセンス層123aの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向である+y方向になる。一方、このとき、出力部102bのセンス層123bには、入力部104による-x方向成分を有する磁界と、コントロール部105による-x方向成分を有する磁界とが印加される。その結果、出力部102bのセンス層123bの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な-x方向になる。その結果、出力部102aのリファレンス層121aとセンス層123aの磁化方向は平行になり、出力部102aのMTJは低抵抗となる。一方、出力部102bのリファレンス層121bとセンス層123bの磁化方向は互いに90度ずれた状態になり、出力部102bのMTJは平行な場合と比較して高抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データを「0」と設定する。
入力部103の入力データは「1」であり、磁化反転領域135の磁化の向きは、+z方向である。入力部104の入力データは「0」であり、磁化反転領域145の磁化の向きは、-z方向である。コントロール部105の制御データは「0」であり、磁化反転領域155の磁化の向きは-z方向である。このとき、出力部102aのセンス層123aには、入力部103による+x方向成分を有する磁界と、コントロール部105による+x方向成分を有する磁界とが印加される。その結果、出力部102aのセンス層123aの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な+x方向になる。一方、このとき、出力部102bのセンス層123bには、入力部104による+x方向成分を有する磁界と、コントロール部105による-x方向成分を有する磁界とが印加される。その結果、出力部102bのセンス層123bの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向である+y方向になる。その結果、出力部102aのリファレンス層121aとセンス層123aの磁化方向は互いに90度ずれた状態になり、出力部102aのMTJは平行な場合と比較して高抵抗となる。一方、出力部102bのリファレンス層121bとセンス層123bの磁化方向は平行になり、出力部102bのMTJは低抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データを「0」と設定する。
入力部103の入力データは「1」であり、磁化反転領域135の磁化の向きは、+z方向である。入力部104の入力データは「1」であり、磁化反転領域145の磁化の向きは、-z方向である。コントロール部105の制御データは「0」であり、磁化反転領域155の磁化の向きは-z方向である。このとき、出力部102aのセンス層123aには、入力部103による+x方向成分を有する磁界と、コントロール部105による+x方向成分を有する磁界とが印加される。その結果、出力部102aのセンス層123aの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な+x方向になる。同様に、このとき、出力部102bのセンス層123bには、入力部104による-x方向成分を有する磁界と、コントロール部105による-x方向成分を有する磁界とが印加される。その結果、出力部102bのセンス層123bの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な-x方向になる。その結果、出力部102aのリファレンス層121aとセンス層123aの磁化方向は互いに90度ずれた状態になり、出力部102aのMTJは平行な場合と比較して高抵抗となる。同様に、出力部102bのリファレンス層121bとセンス層123bの磁化方向は互いに90度ずれた状態になり、出力部102bのMTJは平行な場合と比較して高抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データを「0」と設定する。
入力部103の入力データ(「A」)は「0」であり、磁化反転領域135の磁化の向き(「a」)は、-z方向である。入力部104の入力データ(「B」)は「0」であり、磁化反転領域145の磁化の向き(「b」)は、-z方向である。コントロール部105の制御データは「1」であり、磁化反転領域155の磁化の向き(「l」)は+z方向である。このとき、出力部102aのセンス層123aには、入力部103による-x方向成分を有する磁界(漏洩磁界)と、コントロール部105による-x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部102aのセンス層123aの磁化の向き(「p」)は、両磁界が概ね強め合うため、両磁界と略平行な-x方向になる。同様に、このとき、出力部102bのセンス層123bには、入力部104による+x方向成分を有する磁界(漏洩磁界)と、コントロール部105による+x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部102bのセンス層123bの磁化の向き(「q」)は、両磁界が概ね強め合うため、両磁界と略平行な+x方向になる。その結果、出力部102aのリファレンス層121aとセンス層123aの磁化方向は互いに90度ずれた状態になり、出力部102aのMTJは平行な場合と比較して高抵抗となる。同様に、出力部102bのリファレンス層121bとセンス層123bの磁化方向は互いに90度ずれた状態になり、出力部102bのMTJは平行な場合と比較して高抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データ(「out」)を「0」と設定する。
入力部103の入力データは「0」であり、磁化反転領域135の磁化の向きは、-z方向である。入力部104の入力データは「1」であり、磁化反転領域145の磁化の向きは、+z方向である。コントロール部105の制御データは「1」であり、磁化反転領域155の磁化の向きは+z方向である。このとき、出力部102aのセンス層123aには、入力部103による-x方向成分を有する磁界と、コントロール部105による-x方向成分を有する磁界とが印加される。その結果、出力部102aのセンス層123aの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な-x方向になる。一方、このとき、出力部102bのセンス層123bには、入力部104による-x方向成分を有する磁界と、コントロール部105による+x方向成分を有する磁界とが印加される。その結果、出力部102bのセンス層123bの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向の+y方向になる。その結果、出力部102aのリファレンス層121aとセンス層123aの磁化方向は互いに90度ずれた状態になり、出力部102aのMTJは平行な場合と比較して高抵抗となる。一方、出力部102bのリファレンス層121bとセンス層123bの磁化方向は平行になり、出力部102bのMTJは低抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データを「0」と設定する。
入力部103の入力データは「1」であり、磁化反転領域135の磁化の向きは+z方向である。入力部104の入力データは「0」であり、磁化反転領域145の磁化の向きは、-z方向である。コントロール部105の制御データは「1」であり、磁化反転領域155の磁化の向きは+z方向である。このとき、出力部102aのセンス層123aには、入力部103による+x方向成分を有する磁界と、コントロール部105による-x方向成分を有する磁界とが印加される。その結果、出力部102aのセンス層123aの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向の+y方向になる。一方、このとき、出力部102bのセンス層123bには、入力部104による+x方向成分を有する磁界と、コントロール部105による+x方向成分を有する磁界とが印加される。その結果、出力部102bのセンス層123bの磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な+x方向になる。その結果、出力部102aのリファレンス層121aとセンス層123aの磁化方向は平行になり、出力部102aのMTJは低抵抗となる。一方、出力部102bのリファレンス層121bとセンス層123bの磁化方向は互いに90度ずれた状態になり、出力部102bのMTJは平行な場合と比較して高抵抗となる。この両出力部の少なくとも一方が低抵抗でない場合の出力データを「0」と設定する。
入力部103の入力データは「1」であり、磁化反転領域135の磁化の向きは+z方向である。入力部104の入力データは「1」であり、磁化反転領域145の磁化の向きは、+z方向である。コントロール部105の制御データは「1」であり、磁化反転領域155の磁化の向きは+z方向である。このとき、出力部102aのセンス層123aには、入力部103による+x方向成分を有する磁界と、コントロール部105による-x方向成分を有する磁界とが印加される。その結果、出力部102aのセンス層123aの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向の+y方向になる。同様に、このとき、出力部102bのセンス層123bには、入力部104による-x方向成分を有する磁界と、コントロール部105による+x方向成分を有する磁界とが印加される。その結果、出力部102bのセンス層123bの磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向の+y方向になる。その結果、出力部102aのリファレンス層121aとセンス層123aの磁化方向は平行になり、出力部102aのMTJは低抵抗となる。同様に、出力部102bのリファレンス層121bとセンス層123bの磁化方向は平行になり、出力部102bのMTJは低抵抗となる。この両出力部が低抵抗である場合の出力データを「1」と設定する。
次に、本発明の第8の実施の形態に係る不揮発ロジック回路のデータ入出力原理について図33A、図33Bを参照して説明する。不揮発ロジック回路101に対するデータの入力は、コントロール部105、入力部103、104の磁壁移動素子に対してデータを書き込むことで行う。一方、不揮発ロジック回路101からのデータの出力は、出力部102a、102bのTMR素子のデータの読み出しにより行う。
続いて、本発明の第8の実施の形態に係る不揮発ロジック回路を用いた論理ゲートの構成及び動作について図22を参照して説明する。本実施の形態においても、不揮発ロジック回路101を用いた論理ゲートの一例として図22の構成を用いることができる。
1.不揮発ロジック回路の基本構成
以下、本発明の第9の実施の形態に係る不揮発ロジック回路の基本構成について説明する。図40Aは、本発明の第9の実施の形態に係る不揮発ロジック回路の構成を示す斜視図である。図40Bは、本発明の第9の実施の形態に係る不揮発ロジック回路の構成を示す平面図である。不揮発ロジック回路201は、入力部203と、出力部202と、コントロール部205と、導体層206とを具備している。
次に、本発明の第9の実施の形態に係る不揮発ロジック回路の動作原理について説明する。
入力部203の入力データ(「A」)は「0」であり、磁化反転領域235の磁化の向き(「a」)は、-z方向である。コントロール部205の制御データは「0」であり、磁化反転領域255の磁化の向き(「l」)は+z方向である。このとき、出力部202のセンス層223には、入力部203による-x方向成分を有する磁界(漏洩磁界)と、コントロール部205による-x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部202のセンス層223の磁化の向き(「r」)は、両磁界が強め合うため、両磁界と略平行な-x方向になる。その結果、出力部202のリファレンス層221とセンス層223の磁化方向は互いに90度ずれた状態になり、出力部202のMTJは平行な場合と比較して高抵抗となる。この出力部202が高抵抗である場合の出力データ(「out」)を「0」と設定する。
入力部203の入力データは「1」であり、磁化反転領域235の磁化の向きは、+z方向である。コントロール部205の制御データは「0」であり、磁化反転領域255の磁化の向きは+z方向である。このとき、出力部202のセンス層223には、入力部203による+x方向成分を有する磁界と、コントロール部205による-x方向成分を有する磁界とが印加される。その結果、出力部202のセンス層223の磁化の向きは、両磁界が概ね打ち消し合うため、磁化容易軸方向である+y方向になる。その結果、出力部202のリファレンス層221とセンス層223の磁化方向は平行になり、出力部202のMTJは低抵抗となる。この出力部202が低抵抗である場合の出力データを「1」と設定する。
入力部203の入力データ(「A」)は「0」であり、磁化反転領域235の磁化の向き(「a」)は、-z方向である。コントロール部205の制御データは「1」であり、磁化反転領域255の磁化の向き(「l」)は-z方向である。このとき、出力部202のセンス層223には、入力部203による-x方向成分を有する磁界(漏洩磁界)と、コントロール部205による+x方向成分を有する磁界(漏洩磁界)とが印加される。その結果、出力部202のセンス層223の磁化の向き(「r」)は、両磁界が概ね打ち消し合うため、磁化容易軸方向の+y方向になる。その結果、出力部202のリファレンス層221とセンス層223の磁化方向は平行になり、出力部202のMTJは低抵抗となる。この出力部202が低抵抗である場合の出力データ(「out」)を「1」と設定する。
入力部203の入力データは「1」であり、磁化反転領域235の磁化の向きは、+z方向である。コントロール部205の制御データは「1」であり、磁化反転領域255の磁化の向きは-z方向である。このとき、出力部202のセンス層223には、入力部203による+x方向成分を有する磁界と、コントロール部205による+x方向成分を有する磁界とが印加される。その結果、出力部202のセンス層223の磁化の向きは、両磁界が概ね強め合うため、両磁界と略平行な+x方向になる。その結果、出力部202のリファレンス層221とセンス層223の磁化方向は互いに90度ずれた状態になり、出力部202のMTJは平行な場合と比較して高抵抗となる。この出力部202が高抵抗である場合の出力データを「0」と設定する。
次に、本発明の第9の実施の形態に係る不揮発ロジック回路のデータ入出力原理について説明する。不揮発ロジック回路201に対するデータの入力は、コントロール部205、入力部203の磁壁移動素子に対してデータを書き込むことで行う。一方、不揮発ロジック回路201からのデータの出力は、出力部202のTMR素子のデータの読み出しにより行う。本データ入出力原理における、それらデータの書き込み及び読み出しについては、不揮発ロジック回路101(第8の実施の形態)と同様であるので、その説明を省略する。
続いて、本発明の第9の実施の形態に係る不揮発ロジック回路を用いた論理ゲートの構成及び動作について図30を用いて説明する。本実施の形態においても、不揮発ロジック回路201ヲ用いた論理ゲートの一例として図30の構成を用いることができる。
1.不揮発ロジック回路の基本構成
以下、本発明の第10の実施の形態に係る不揮発ロジック回路の基本構成について説明する。図42は、本発明の第10の実施の形態に係る不揮発ロジック回路の構成を示す斜視図である。不揮発ロジック回路296は、第8の実施の形態に係る不揮発ロジック回路101と、第9の実施の形態に係る不揮発ロジック回路201と、信号伝達回路297とを具備している。
次に、本発明の第10の実施の形態に係る不揮発ロジック回路の動作原理について説明する。
入力部103の入力データ(「A」)は「0」、入力部104の入力データ(「B」)は「0」である。これは、図34Aにおけるケースκ1である。この場合、不揮発ロジック回路101の出力部102a、102bからの出力データは「1」である。従って、入力部203の入力データ(「O-1」)は「1」である。これは、図41Aにおけるケースμ2である。従って、出力部202からの出力データ(「O-2」)は「1」である。
入力部103の入力データは「0」、入力部104の入力データは「1」である。これは、図34Aにおけるケースκ2である。この場合、不揮発ロジック回路101の出力部102a、102bからの出力データは「0」である。従って、入力部203の入力データは「0」である。これは、図41Aにおけるケースμ1である。従って、出力部202からの出力データは「0」である。
入力部103の入力データは「1」、入力部104の入力データは「0」である。これは、図34Aにおけるケースκ3である。この場合、不揮発ロジック回路101の出力部102a、102bからの出力データは「0」である。従って、入力部203の入力データは「0」である。これは、図41Aにおけるケースμ1である。従って、出力部202からの出力データは「0」である。
入力部103の入力データは「1」、入力部104の入力データは「1」である。これは、図34Aにおけるケースκ4である。この場合、不揮発ロジック回路301の出力部302a、302bからの出力データは「0」である。従って、入力部203の入力データは「0」である。これは、図41Aにおけるケースμ1である。従って、出力部202からの出力データは「0」である。
入力部103の入力データ(「A」)は「0」、入力部104の入力データ(「B」)は「0」である。これは、図34Bにおけるケースλ1である。この場合、不揮発ロジック回路101の出力部102a、102bからの出力データは「0」である。従って、入力部203の入力データ(「O-1」)は「0」である。これは、図41Bにおけるケースν1である。従って、出力部202からの出力データ(「O-2」)は「1」である。
入力部103の入力データは「0」、入力部104の入力データは「1」である。これは、図34Bにおけるケースλ2である。この場合、不揮発ロジック回路101の出力部102a、102bからの出力データは「0」である。従って、入力部203の入力データは「0」である。これは、図41Bにおけるケースν1である。従って、出力部202からの出力データは「1」である。
入力部103の入力データは「1」、入力部104の入力データは「0」である。これは、図34Bにおけるケースλ3である。この場合、不揮発ロジック回路101の出力部102a、102bからの出力データは「0」である。従って、入力部203の入力データは「0」である。これは、図41Bにおけるケースν1である。従って、出力部202からの出力データは「1」である。
入力部103の入力データは「1」、入力部104の入力データは「1」である。これは、図34Bにおけるケースλ4である。この場合、不揮発ロジック回路101の出力部102a、102bからの出力データは「1」である。従って、入力部203の入力データは「1」である。これは、図41Bにおけるケースν2である。従って、出力部202からの出力データは「0」である。
次に、本発明の第10の実施の形態に係る不揮発ロジック回路のデータ入出力原理については、第8の実施の形態(不揮発ロジック回路101)及び第9の実施の形態(不揮発ロジック回路201)と同様であるので、その説明を省略する。
続いて、本発明の第10の実施の形態に係る不揮発ロジック回路を用いた論理ゲートの構成及び動作については、第8の実施の形態(不揮発ロジック回路101を用いた論理ゲート380:図22)と第9の実施の形態(不揮発ロジック回路201を用いた論理ゲート480:図30)とを組み合わせたもので実行可能であるので、その説明を省略する。ただし、信号伝達回路297は、例えば、図22における比較器382と、MTJ参照素子383と、制御回路381のうちの比較器382とMTJ参照素子383を制御する部分とで構成することができる。
Claims (28)
- 垂直磁気異方性を有し、磁化状態が変化可能な強磁性層を含む入力部と、
強磁性層を含むコントロール部と、
前記入力部及び前記コントロール部の近傍に設けられ、磁化状態が変化可能な磁気トンネル結合素子を含む出力部と
を具備し、
前記入力部の磁化状態は、入力データに対応して変化し、
前記出力部の前記磁気トンネル結合素子の磁化状態は、前記入力部及び前記コントロール部の磁化状態に対応して変化する
不揮発ロジック回路。 - 請求項1に記載の不揮発ロジック回路であって、
前記出力部の前記磁気トンネル接合素子は、
反転可能な磁化を有し、面内磁気異方性を有する強磁性層であるセンス層と、
磁化の向きが固定され、面内磁気異方性を有する強磁性層であるリファレンス層と、
前記センス層と前記リファレンス層との間に設けられた絶縁層と
を備える
不揮発ロジック回路。 - 請求項2に記載の不揮発ロジック回路であって、
前記入力部は、
反転可能な磁化を有し、垂直磁気異方性を有する強磁性層であるフリー層と、
磁化の向きが固定され、垂直磁気異方性を有する強磁性層である固定層と、
前記フリー層と前記固定層との間に設けられた非磁性層と
を備える
不揮発ロジック回路。 - 請求項3に記載の不揮発ロジック回路であって、
前記入力部と前記出力部とを前記出力部の底面を含む平面へ射影したとき、前記入力部の射影の重心の位置は、前記出力部の重心の位置とずれている
不揮発ロジック回路。 - 請求項4に記載の不揮発ロジック回路であって、
前記コントロール部は、垂直磁気異方性を有し、
前記入力部は複数あり、
前記コントロール部と前記複数の入力部とは、直線状に並んで設けられている
不揮発ロジック回路。 - 請求項4に記載の不揮発ロジック回路であって、
前記センス層は、前記入力部と前記コントロール部とが並ぶ方向に対して垂直な方向の磁気異方性を有する
不揮発ロジック回路。 - 請求項6に記載の不揮発ロジック回路であって、
前記リファレンス層は、前記入力部と前記コントロール部とが並ぶ方向に対して垂直な方向に磁化が固定されている
不揮発ロジック回路。 - 請求項4に記載の不揮発ロジック回路であって、
前記コントロール部は、面内磁気異方性を有し、
前記コントロール部と前記出力部とを前記出力部の底面を含む平面へ射影したとき、前記コントロール部の前記射影の重心の位置は、前記出力部の重心の位置と重なる
不揮発ロジック回路。 - 請求項4に記載の不揮発ロジック回路であって、
前記コントロール部は、垂直磁気異方性を有し、
前記コントロール部と前記出力部とを前記出力部の底面を含む平面へ射影したとき、前記コントロール部の前記射影の重心の位置は、前記出力部の重心の位置とずれている
不揮発ロジック回路。 - 請求項4に記載の不揮発ロジック回路であって、
前記出力部の近傍に設けられた強磁性層を含む第2コントロール部を更に具備し、
前記コントロール部及び前記第2コントロール部は、垂直磁気異方性を有し、
前記コントロール部及び前記第2コントロール部と前記出力部とを前記出力部の底面を含む平面へ射影したとき、前記コントロール部及び前記第2コントロール部の前記射影の重心の位置は、前記出力部の重心の位置とずれている
不揮発ロジック回路。 - 請求項5に記載の不揮発ロジック回路であって、
単入力素子を更に具備し、
前記複数の入力部と、前記コントロール部と、前記出力部とは多入力素子を構成し、
前記単入力素子は、
垂直磁気異方性を有し、磁化状態が変化可能な強磁性層を含む第2入力部と、
強磁性層を含む第2コントロール部と、
前記第2入力部及び前記第2コントロール部の近傍に設けられ、磁化状態が変化可能な第2磁気トンネル結合素子を含む第2出力部と
を備え、
前記第2入力部の磁化状態は、前記出力部の出力に応じた伝達信号が入力され、前記伝達データに対応して変化し、
前記第2出力部の前記第2磁気トンネル結合素子の磁化状態は、前記第2入力部及び前記第2コントロール部の磁化状態に対応して変化する
不揮発ロジック回路。 - 請求項11に記載の不揮発ロジック回路であって、
前記出力部に電気的に接続され、前記出力部の出力に応じた前記伝達信号を前記第2入力部へ出力する信号伝達回路をさらに具備する
不揮発ロジック回路。 - 請求項2に記載の不揮発ロジック回路であって、
前記入力部は、
磁化の向きが第1方向に固定され、垂直磁気異方性を有する強磁性層である第1磁化固定領域と、
磁化の向きが前記第1方向と反対の第2方向に固定され、垂直磁気異方性を有する強磁性層である第2磁化固定領域と、
前記前記第1磁化固定領域と前記第2磁化固定領域との間に設けられ、反転可能な磁化を有し、垂直磁気異方性を有する強磁性層である磁化反転領域と
を備える
不揮発ロジック回路。 - 請求項13に記載の不揮発ロジック回路であって、
前記入力部は、
前記第1磁化固定領域の近傍に設けられ前記第1磁化固定領域の磁化を固定する第1ハード層、及び、前記第2磁化固定領域の近傍に設けられ前記第2磁化固定領域の磁化を固定する第2ハード層、の少なくとも一方をさらに備える
不揮発ロジック回路。 - 請求項13に記載の不揮発ロジック回路であって、
前記入力部と前記出力部とを前記出力部の底面を含む平面へ射影したとき、前記入力部の射影の重心の位置は、前記出力部の重心の位置とずれている
不揮発ロジック回路。 - 請求項15に記載の不揮発ロジック回路であって、
前記コントロール部が延在する方向と前記入力部が延在する方向とは平行である
不揮発ロジック回路。 - 請求項16に記載の不揮発ロジック回路であって、
前記入力部は複数あり、
前記複数の入力部が延在する方向は互いに平行である
不揮発ロジック回路。 - 請求項17に記載の不揮発ロジック回路であって、
前記コントロール部は、垂直磁気異方性を有し、
前記コントロール部と前記複数の入力部とは、直線状に並んで設けられている
不揮発ロジック回路。 - 請求項15に記載の不揮発ロジック回路であって、
前記センス層は、前記入力部と前記コントロール部とが並ぶ方向に対して垂直な方向の磁気異方性を有する
不揮発ロジック回路。 - 請求項19に記載の不揮発ロジック回路であって、
前記リファレンス層は、前記入力部と前記コントロール部とが並ぶ方向に対して垂直な方向に磁化が固定されている
不揮発ロジック回路。 - 請求項15に記載の不揮発ロジック回路であって、
前記センス層は、前記入力部と前記コントロール部とが並ぶ方向に対して平行な方向の磁気異方性を有する
不揮発ロジック回路。 - 請求項15に記載の不揮発ロジック回路であって、
前記コントロール部は、面内磁気異方性を有し、
前記コントロール部と前記出力部とを前記出力部の底面を含む平面へ射影したとき、前記コントロール部の前記射影の重心の位置は、前記出力部の重心の位置と重なる
不揮発ロジック回路。 - 請求項15に記載の不揮発ロジック回路であって、
前記コントロール部は、垂直磁気異方性を有し、
前記コントロール部と前記出力部とを前記出力部の底面を含む平面へ射影したとき、前記コントロール部の前記射影の重心の位置は、前記出力部の重心の位置とずれている
不揮発ロジック回路。 - 請求項15に記載の不揮発ロジック回路であって、
前記出力部の近傍に設けられた強磁性層を含む第2コントロール部を更に具備し、
前記コントロール部及び前記第2コントロール部は、垂直磁気異方性を有し、
前記コントロール部及び前記第2コントロール部と前記出力部とを前記出力部の底面をむ平面へ射影したとき、前記コントロール部及び前記第2コントロール部の前記射影の重心の位置は、前記出力部の重心の位置とずれている
不揮発ロジック回路。 - 請求項17に記載の不揮発ロジック回路であって、
単入力素子を更に具備し、
前記複数の入力部と、前記コントロール部と、前記出力部とは多入力素子を構成し、
前記単入力素子は、
垂直磁気異方性を有し、磁化状態が変化可能な強磁性層を含む第2入力部と、
強磁性層を含む第2コントロール部と、
前記第2入力部及び前記第2コントロール部の近傍に設けられ、磁化状態が変化可能な第2磁気トンネル結合素子を含む第2出力部と
を備え、
前記第2入力部の磁化状態は、前記出力部の出力に応じた伝達信号が入力され、前記伝達データに対応して変化し、
前記第2出力部の前記第2磁気トンネル結合素子の磁化状態は、前記第2入力部及び前記第2コントロール部の磁化状態に対応して変化する
不揮発ロジック回路。 - 請求項25に記載の不揮発ロジック回路であって、
前記出力部に電気的に接続され、前記出力部の出力に応じた前記伝達信号を前記第2入力部へ出力する信号伝達回路をさらに具備する
不揮発ロジック回路。 - 請求項1に記載の不揮発ロジック回路であって、
前記コントロール部は、コントロールデータを入力されて、前記コントロール部の強磁性層の磁化状態を前記コントロールデータに対応するように設定され、
前記入力部は、入力データを入力されて、前記入力部の強磁性層の磁化状態を前記入力データに対応するように設定され、
前記出力部の磁気トンネル結合素子は、前記コントロール部の強磁性体の磁化状態と前記入力部の強磁性体の磁化状態と基づいて変化した磁化状態が読み出される
不揮発ロジック回路。 - 不揮発ロジック回路の動作方法であって、
ここで、不揮発ロジック回路は、
垂直磁気異方性を有し、磁化状態が変化可能な強磁性層を含む入力部と、
強磁性層を含むコントロール部と、
前記入力部及び前記コントロール部の近傍に設けられ、磁化状態が変化可能な磁気トンネル結合素子を含む出力部と
を具備し、
前記不揮発ロジック回路の動作方法は、
前記コントロール部にコントロールデータを入力して、前記コントロール部の強磁性層の磁化状態を前記コントロールデータに対応するように設定するステップと、
前記入力部に入力データを入力して、前記入力部の強磁性層の磁化状態を前記入力データに対応するように設定するステップと、
前記コントロール部の強磁性体の磁化状態と前記入力部の強磁性体の磁化状態と基づいて変化した前記出力部の磁気トンネル結合素子の磁化状態を読み出すステップと
を具備する
不揮発ロジック回路の動作方法。
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