WO2010086949A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2010086949A1
WO2010086949A1 PCT/JP2009/007138 JP2009007138W WO2010086949A1 WO 2010086949 A1 WO2010086949 A1 WO 2010086949A1 JP 2009007138 W JP2009007138 W JP 2009007138W WO 2010086949 A1 WO2010086949 A1 WO 2010086949A1
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mosfet
terminal
voltage
semiconductor device
source
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PCT/JP2009/007138
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English (en)
French (fr)
Japanese (ja)
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高窪かをり
Hajime TAKAKUBO (高窪統)
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学校法人明治大学
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only

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  • the present invention relates to a semiconductor device, and more particularly to a reference voltage source configured on an integrated circuit using a semiconductor element that carries a diffusion current. More particularly, the present invention relates to a reference voltage source that is stable against fluctuations in power supply voltage, a PTAT reference voltage source that generates a voltage proportional to absolute temperature, and the use of this type of reference voltage source.
  • a proportional voltage source (PTAT: Proportional To Absolute Temperature) reference voltage source is an important analog circuit necessary for realizing a temperature sensor or a band gap reference voltage source on an integrated circuit.
  • PTAT reference voltage source there is Patent Document 1 as a semiconductor device using a MOSFET that operates in a weak inversion state.
  • Patent Document 1 shows a PTAT reference voltage source in which MOSFETs operated in a saturated state are connected by connecting a gate terminal and a drain terminal of a MOSFET operating in a weak inversion region to be diode-connected.
  • the PTAT reference voltage is proportional to a constant determined by the absolute temperature and the shape of the MOSFET, and exhibits a characteristic inversely proportional to the slope coefficient n in the exponential operation state.
  • the driving range of MOSFETs is further narrowed due to a decrease in threshold voltage in recent miniaturization processes, and it operates from a low power supply voltage of 0.5 V or less under a general-purpose process and generates a stable voltage against fluctuations in power supply voltage.
  • the minimum operating power supply voltage of the circuit is further increased. Further, the deterioration due to the variation of the slope coefficient n in the exponential operation state becomes a factor of reducing the reliability of the set voltage of the reference voltage source.
  • An object of the present invention is to provide a semiconductor device for generating a reference voltage that can be accurately designed on an integrated circuit according to the shape of a semiconductor element that operates with a diffusion current.
  • a semiconductor device comprising a first MOSFET and a second MOSFET, wherein a drain terminal of the first MOSFET and a source terminal of the second MOSFET are connected, and the drain terminal of the first MOSFET and the The output terminal is between the source terminal of the second MOSFET, the source terminal of the first MOSFET is a reference potential, a predetermined supply voltage is applied to the drain terminal of the second MOSFET, and the first MOSFET A gate terminal of the second MOSFET and a gate terminal of the second MOSFET, and a terminal between the gate terminal of the first MOSFET and the gate terminal of the second MOSFET is defined as a first gate terminal.
  • a substrate terminal of the MOSFET and a substrate terminal of the second MOSFET are connected, and the substrate terminal of the first MOSFET and the second MOSFET
  • the terminals of the substrate terminal of the MOSFET as a first substrate terminal, and the drain terminal of the first gate terminal and the second MOSFET can be achieved by not connected.
  • the proportionality coefficient can be designed accurately, and it is possible to generate a voltage on the integrated circuit that is proportional to the absolute temperature and insensitive to fluctuations in the power supply voltage. Since a fine semiconductor element is operated in a region modeled by a diffusion current, the minimum operating power supply voltage can be operated with a very low power supply voltage of about 0.2 V (output voltage +0.1 V), Power consumption is extremely small and the design area is extremely small. In addition, since the output voltage proportional to the temperature is determined by the ratio of the diffusion currents obtained by a plurality of semiconductor elements having different shape ratios, characteristics that do not depend on parameter variations in the manufacturing process are realized.
  • a PTAT circuit that can be integrated on-chip that can be driven by a weak power source such as a solar battery, and to an application circuit and a bias voltage circuit that are mounted on a general-purpose integrated circuit and perform temperature detection on-chip.
  • the effect is that it can be widely applied.
  • FIG. 1A is a circuit configuration diagram using an NMOSFET according to the present invention.
  • FIG. 1B is a circuit configuration diagram using a PMOSFET according to the present invention.
  • FIG. 2A is a circuit configuration diagram when the semiconductor device according to the first embodiment of the present invention shown in FIG. 1A is configured using bipolar transistors.
  • FIG. 2B is a circuit configuration diagram when the semiconductor device according to the first embodiment of the present invention shown in FIG. 1B is configured using bipolar transistors.
  • FIG. 3A is a schematic structural cross-sectional view of FIG. 1A.
  • FIG. 3B is a schematic structural cross-sectional view of FIG. 1B.
  • FIG. 3C is a schematic cross-sectional view of the structure when FIG. 1A is manufactured by an SOI process.
  • FIG. 1A is a circuit configuration diagram using an NMOSFET according to the present invention.
  • FIG. 1B is a circuit configuration diagram using a PMOSFET according to the present invention.
  • FIG. 3D is a schematic top view when FIG. 1A is manufactured by an SOI process.
  • FIG. 3E is a schematic cross-sectional view of the structure when FIG. 1B is manufactured by an SOI process.
  • FIG. 3F is a schematic structural cross-sectional view of the case where FIG. 2A is manufactured by a SOI process using a lateral bipolar transistor.
  • FIG. 3G is a schematic top view when FIG. 2A is manufactured by a SOI process using a lateral bipolar transistor.
  • FIG. 3H is a schematic cross-sectional view of the structure when FIG. 2B is manufactured by a SOI process using a lateral bipolar transistor.
  • FIG. 4 is a conceptual diagram showing an operation region of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a conceptual diagram showing an operation region of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 5A is an example of a circuit used for measurement when a DC voltage source is connected to a semiconductor device having an NMOSFET structure according to the first embodiment of the present invention corresponding to FIG. 1A.
  • FIG. 5B is an example of a circuit used for measurement when a DC voltage source is connected to a semiconductor device having a PMOSFET structure according to the first embodiment of the present invention corresponding to FIG. 1B.
  • FIG. 5B is a diagram showing the measurement result of the output potential difference VO ⁇ VS with respect to the potential difference VD ⁇ VS when the absolute temperature T is used as a parameter in the measurement circuit of the semiconductor device having the NMOSFET configuration according to the first embodiment of the present invention corresponding to FIG. 5A. is there.
  • FIG. 5A is an example of a circuit used for measurement when a DC voltage source is connected to a semiconductor device having an NMOSFET structure according to the first embodiment of the present invention corresponding to FIG. 1A.
  • FIG. 5B is an example of a circuit used for measurement when
  • FIG. 5B is a diagram showing a measurement result of consumption current ID with respect to potential difference VD ⁇ VS when absolute temperature T is used as a parameter in the measurement circuit of the semiconductor device having the NMOSFET configuration according to the first exemplary embodiment of the present invention corresponding to FIG. 5A.
  • FIG. 5B is a diagram showing theoretical characteristics and measurement results of an output potential difference VO ⁇ VS with respect to an absolute temperature T in the measurement circuit of the semiconductor device having the NMOSFET configuration according to the first example of the present invention corresponding to FIG. 5A.
  • FIG. 9B is a diagram showing theoretical characteristics and measurement results of an output potential difference VO ⁇ VS with respect to an absolute temperature T in a circuit configuration example of a semiconductor device having an NMOSFET configuration according to the first exemplary embodiment of the present invention corresponding to FIG. 9A.
  • FIG. 11A is a circuit configuration example for realizing a large positive temperature coefficient by cascading the semiconductor devices of the NMOSFET configuration according to the first embodiment of the present invention corresponding to FIG. 1A.
  • FIG. 11B is a circuit configuration example for realizing a large negative temperature coefficient by cascading the semiconductor devices having the PMOSFET configuration according to the first embodiment of the present invention corresponding to FIG. 1B.
  • the present invention operates two source-side MOSFETs and sink-side MOSFETs provided with the same structure, the same gate bias condition, and the same substrate bias condition connected in series in an operation region modeled by a diffusion current, and By biasing the gate terminal of the source side MOSFET without diode connection, a PTAT reference voltage source that can operate from a minute voltage to a wide power supply voltage range and is insensitive to fluctuations in the power supply voltage has been created.
  • two source-side MOSFETs and sink-side MOSFETs having the same structure are connected in series with the source terminal of the source-side MOSFET and the drain terminal of the sink-side MOSFET, and the gate terminals of the two MOSFETs connected in series are shared.
  • substrate terminals of two MOSFETs connected in series are connected in common.
  • the gate terminals connected in common in the two MOSFETs connected in series are configured to apply a potential independently of the drain terminal of the source-side MOSFET.
  • the operating region of the two MOSFETs is determined by the voltage between the gate terminal and the substrate terminal in the MOSFET, so the operating region is not limited to the threshold voltage of the MOSFET, Operation in an operation region based on the diffusion current model can be performed under a wide range of driving power supply voltages.
  • the bias condition of the gate terminal in the two MOSFETs connected in series is that the surface of the channel region immediately below the gate region of the MOSFET is biased within a voltage range that allows the diffusion current to flow from the flat band state to the operation region where no inversion layer occurs. To do.
  • the driving state of the present invention is achieved when the clock voltage satisfies the bias condition described above.
  • the bias condition of the substrate terminal in the two MOSFETs connected in series is within a voltage range for biasing the pn junction connected to the source terminal of the sink-side MOSFET from a weak forward bias to a reverse bias (including zero bias). Set. Furthermore, by adjusting the bias voltage of the substrate terminal, it is possible to adjust the current consumption of the semiconductor device and to control the operation speed of the semiconductor device.
  • the drain current characteristic of the MOSFET is an index determined by the voltages at the four terminals of the gate terminal, the source terminal, the drain terminal, and the substrate terminal without using the threshold voltage. It is expressed by a combination of characteristics.
  • the proportionality coefficient of the output voltage to the absolute temperature is k / q ⁇ ln (m + 1) when the channel shape ratio of the source side MOSFET to the channel shape ratio of the sink side MOSFET is m times.
  • k is a Boltzmann constant
  • q is an elementary electric quantity.
  • the proportional coefficient of the output voltage to the absolute temperature does not include the various parameters in the manufacturing process and the slope coefficient n in the exponential operation state, and is determined by the physical constant and the channel shape of the MOSFET. In addition, it is possible to design accurately by the channel shape of the MOSFET.
  • the reference voltage source of the present invention is a connection point between the drain terminal of the sink side MOSFET and the source terminal of the source side MOSFET with respect to the fluctuation of the voltage of the drain terminal of the source side MOSFET with respect to the source terminal of the sink side MOSFET. Therefore, the power supply voltage fluctuation rejection ratio is high.
  • FIG. 1 shows an embodiment of the present invention per drawing.
  • FIG. 1A is a circuit diagram of a PTAT reference voltage source of the present invention configured by using an NMOSFET in an operating state in which an inversion layer is not formed as a semiconductor element for passing a diffusion current.
  • a source-side NMOSFET (Mn2) and a sink-side NMOSFET (Mn1) having the same structure manufactured by setting the design parameters other than the channel shape ratio of the MOSFET and the manufacturing process parameters to be equal, the source terminal of Mn2, and the drain terminal of Mn1
  • the gate terminals of the two MOSFETs connected in series are connected in common, and the substrate terminals of the two MOSFETs connected in series are connected in common.
  • the source terminal of Mn2 and the n-type impurity semiconductor region constituting the drain terminal of Mn1 have the same impurity concentration, that is, have the same process parameters
  • the source terminal of Mn2 and Mn1 have the same impurity concentration, that is, have the same process parameters
  • the source terminal of Mn2 and Mn1 can be formed by sharing the drain terminal of each other.
  • the gate terminals connected in common in the two MOSFETs connected in series are configured to give a potential independently of the drain terminal of Mn2.
  • FIG. 3A is a schematic structural cross-sectional view when the PTAT reference voltage source shown in FIG. 1A is configured using a MOSFET.
  • the n-type high-concentration semiconductor region 2 connected to the output terminal 22 is shown as one n-type high-concentration semiconductor region 2 for convenience, but is divided into two n-type high-concentration semiconductor regions having the same concentration. It can also be configured.
  • FIG. 3B is a schematic structural cross-sectional view when the PTAT reference voltage source shown in FIG. 1B is configured by using a MOSFET.
  • FIG. 3C is a schematic cross-sectional view of the structure when the PTAT reference voltage source shown in FIG. 1A is configured on an SOI substrate using a MOSFET.
  • FIG. 3D is a schematic top view of FIG. 3C.
  • FIG. 3E is a schematic structural cross-sectional view when the PTAT reference voltage source shown in FIG. 1B is configured on an SOI substrate using a MOSFET.
  • a bipolar transistor is known as a semiconductor element for passing a diffusion current, as is the case with a MOSFET that does not form an inversion layer.
  • the semiconductor device shown in FIG. In a circuit using bipolar transistors as semiconductor elements as shown in FIG. 2A, a PTAT reference voltage source that operates with the same operation theory and generates the same output voltage can be configured. In this case, it does not have a gate terminal.
  • FIG. 1B can constitute a PTAT reference voltage source that operates on the same theory of operation and generates the same output voltage in a circuit that uses bipolar transistors as semiconductor elements as shown in FIG. 2B.
  • FIG. 3F is a schematic structural cross-sectional view when the PTAT reference voltage source shown in FIG. 1A is configured on an SOI substrate using a lateral bipolar transistor. In the case where a lateral bipolar transistor is used instead of the MOSFET for passing the diffusion current, the gate region 14 of the sink side semiconductor element, the gate region 15 of the source side semiconductor element, and the gate terminal 24 are not provided.
  • FIG. 3G is a schematic top view of FIG. 3F.
  • 3H is a schematic cross-sectional view of a structure in which the PTAT reference voltage source shown in FIG. 1A is configured on an SOI substrate using a lateral bipolar transistor. Similar to FIG. 3F, when a lateral bipolar transistor is used instead of a MOSFET for passing a diffusion current, the gate region 14 of the sink-side semiconductor element, the gate region 15 of the source-side semiconductor element, and the gate terminal 24 are not provided.
  • a voltage in a range in which the channel region immediately below the gate region of the MOSFET of Mn1 and Mn2 satisfies the operation region where the inversion layer is not formed from the flat band state is applied.
  • the substrate terminal (VB) of Mn1 and Mn2 has a substrate terminal in the voltage range (including zero bias) in which the source side pn junction of Mn1 is slightly operated in the forward-biased operation region. Apply voltage.
  • a potential difference VD ⁇ VS is applied between the source terminal (VS) of Mn1 and the drain terminal (VD) of Mn2 in a direction in which VD becomes positive with respect to VS.
  • the potential difference of VD with respect to VS is given about 0.1 V or more larger than the potential difference VO ⁇ VS of the output terminal (VO) connected to the drain terminal of Mn1 with reference to VS.
  • k is a Boltzmann constant
  • T is an absolute temperature
  • q is an elementary charge.
  • the operating characteristics of the PTAT circuit of the present invention will be described using a diffusion current model representing the drain current characteristics of a MOSFET in which an inversion layer is not formed.
  • r is a deterioration factor of the gate voltage that represents the rate at which the surface potential of the channel region of the MOSFET changes with respect to the voltage applied to the gate region.
  • I0 is expressed as A ⁇ q ⁇ Dn ⁇ np0 / L, A is an effective junction cross-sectional area of two pn junction side regions in contact with the MOSFET channel region, Dn is an electron diffusion coefficient, and np0 is an NMOSFET channel
  • L electron carrier density
  • the variation factor due to the substrate effect of the MOSFET in the drain current equation shown in the existing model of the MOSFET operating in the weak inversion region is based on the drain current in the MOSFET (4) and the voltage at the four terminals as the substrate potential.
  • the drain current of Mn1 can be expressed using equation (1).
  • In1 mn1 ⁇ I0 ⁇ EXP (q ⁇ (rVC + (1-r) VB) / kT) (EXP ( ⁇ q ⁇ VS / kT) ⁇ EXP ( ⁇ q ⁇ VO / kT)), (2)
  • the drain current of Mn2 can be expressed using equation (1).
  • In2 mn2 ⁇ I0 ⁇ EXP (q ⁇ (rVC + (1-r) VB) / kT) (EXP ( ⁇ q ⁇ VO / kT) ⁇ EXP ( ⁇ q ⁇ VD / kT)), (3)
  • In2 mn2 ⁇ I0 ⁇ EXP (q ⁇ (rVC + (1-r) VB) / kT) EXP ( ⁇ q ⁇ VO / kT), which can be rewritten as (4).
  • m represents the ratio of mn2 to mn1.
  • VO ⁇ VS kT / q ⁇ ln (m + 1)
  • the positive PTAT characteristic of (7) is derived.
  • the temperature coefficient for the absolute temperature T is accurately determined by the physical constants k, q and the ratio m of the channel shape ratio of Mn2 to Mn1.
  • Equation (3) a condition for the second term to be sufficiently smaller than the first term is considered.
  • ⁇ neg EXP ( ⁇ q (VD ⁇ VO) / kT)
  • ⁇ neg EXP ( ⁇ q ⁇ Vneg / kT)
  • Vneg is a converted voltage value of the error voltage that gives the maximum error ⁇ neg in equation (9).
  • Equation (3) the range of VD that Equation (3) can approximate to Equation (4) is VD ⁇ VO + Vneg, (11)
  • VD ⁇ VS + Vneg, (13) the condition of the equation (13) is included in the condition of the equation (11). Therefore, in order to obtain an approximation for deriving the equation (7), the voltage of VD is expressed by the equation (11). ).
  • the gate voltage VC-VB based on the substrate voltage VB of the two MOSFETs is: VC ⁇ VB ⁇ Vtn, (14) must be satisfied.
  • Vtn is a voltage at which an inversion layer is formed in the channel region of the NMOSFET.
  • VC ⁇ VB ⁇ Vfn is a voltage at which the channel region of the NMOSFET becomes a flat band state.
  • FIG. 4 shows the operation region of Mn2 with respect to the relationship between the drain voltage VD-VS of Mn2 based on the source terminal voltage VS of Mn1 and the output voltage VO-VS based on the source terminal voltage VS of Mn1.
  • the characteristic of the output voltage VO-VS with reference to the source terminal voltage VS of Mn1 is shown by a solid line.
  • the PTAT voltage Vpm at a certain absolute temperature increases to VpmH as the temperature increases, and decreases to VpmL as the temperature decreases.
  • VDmin The minimum potential difference VD ⁇ VS (referred to as VDmin) required to operate the PTAT circuit of the present invention is obtained as VDmin ⁇ VpmH + Vneg using the PTAT voltage VpmH at a high temperature from the equation (11).
  • VDmin ⁇ VpmH + Vneg the PTAT voltage VpmH at a high temperature from the equation (11).
  • the PTAT characteristic of Expression (7) is obtained in the same manner because it operates in accordance with the same principle as that of the case of using a MOSFET for passing a diffusion current.
  • the operating condition may satisfy Expression (11) in the same manner as in the case where the operating condition is configured using a MOSFET that allows a diffusion current to flow.
  • FIG. 6 shows the relationship between the drain voltage VD-VS of Mn2 based on the terminal voltage VS and the output voltage VO-VS based on the source terminal voltage VS of Mn1.
  • T the absolute temperature
  • the PTAT voltage Vpm moves in parallel at substantially equal intervals with respect to the change in absolute temperature.
  • FIG. 7 shows the current consumption ID for VD-VS in the measurement circuit of the PTAT circuit shown in FIG. 5A.
  • the measurement result agrees well with the calculation result, the output voltage is proportional to the absolute temperature T, and the semiconductor device of the present invention operates accurately as a PTAT reference voltage source.
  • FIG. 1B a circuit diagram of a PTAT reference voltage source configured using a PMOSFET is shown in FIG. 1B.
  • VO ⁇ VS ⁇ kT / q ⁇ ln (m + 1), (16)
  • a negative PTAT characteristic is derived.
  • a potential difference VD ⁇ VS is applied between the source terminal (VS) of Mn1 and the drain terminal (VD) of Mn2 in a direction in which VD becomes negative with respect to VS.
  • the conditions for the expression (16) to be satisfied are as follows.
  • FIG. 5B shows an example of DC voltage connection in a circuit having a PMOSFET configuration corresponding to FIG. 5A.
  • the PTAT characteristic of the equation (16) is obtained in the same manner because it operates according to the same principle as that of a case where a MOSFET for passing a diffusion current is used.
  • the operating condition may satisfy Expression (17) similarly to the case where the MOSFET is configured to flow a diffusion current.
  • a PTAT circuit having an NMOSFET structure that can be driven by only one external bias power supply by connecting VC and VS and connecting VB and VS is shown in FIG. 9A.
  • the PTAT voltage shown in equation (7) is generated.
  • the operating condition is determined only by equation (11).
  • VD 0.5 V
  • VS 0.0 V
  • Wn2 / Ln2 3 ⁇ m / 10 ⁇ m)
  • absolute temperatures T and Mn1 The relationship of the output voltage VO-VS with reference to the source terminal voltage VS is shown in FIG.
  • the measurement result agrees well with the calculation result, and the output voltage is proportional to the absolute temperature T.
  • FIG. 9B shows a PTAT circuit having a PMOSFET structure that can be driven by only one external bias power source by connecting VC and VS and connecting VB and VS.
  • the PTAT voltage shown in equation (16) is generated.
  • the operating condition is determined only by equation (17).
  • FIG. 9C shows a PTAT circuit having an NMOSFET structure that can be driven by only one external bias power source by connecting VC and VO and connecting VB and VS.
  • the PTAT voltage shown in equation (7) is generated.
  • the operating conditions are as follows: VO ⁇ VS ⁇ Vtn, determined by (20)
  • FIG. 9D shows a PTAT circuit having a PMOSFET structure that can be driven by only one external bias power source by connecting VC and VO and connecting VB and VS.
  • the PTAT voltage shown in equation (16) is generated.
  • the operating conditions are as follows: VO ⁇ VS ⁇ Vtp, determined by (21). These examples have the advantage that the PTAT voltage can be generated with a single power source.
  • a PTAT circuit having an NMOSFET configuration in which N-stage PTAT circuits are connected in cascade by connecting to the source terminal VS (k + 1) of the PTAT circuit, the first-stage source terminal VS1 is VS, and the N-stage output is VON is shown in FIG. Shown in m1 to m2N represent the channel shape ratios of the MOSFETs corresponding to Mn1 to Mn2N, respectively.
  • the operating conditions are VD ⁇ VON + Vneg, (23)
  • FIG. 11B shows a PTAT circuit having a PMOSFET configuration in which N-stage PTAT circuits are connected in cascade, the first-stage source terminal VS1 is VS, and the N-stage output is VON.
  • m1 to m2N represent the channel shape ratios of the MOSFETs corresponding to Mp1 to Mp2N, respectively.
  • the proportionality coefficient can be designed accurately and proportional to the absolute temperature, and a voltage insensitive to fluctuations in the power supply voltage can be generated on the integrated circuit. Since a fine MOSFET is operated in a region modeled by diffusion current, the minimum operating power supply voltage can be operated at a very low power supply voltage of about 0.2V, and the power consumption is extremely small, and the design area Is extremely small. In addition, since the output voltage proportional to the temperature is determined by the ratio of diffusion currents obtained by a plurality of MOSFETs having different shape ratios, characteristics that do not depend on variations in parameters in the manufacturing process are realized.
  • a PTAT circuit that can be integrated on-chip that can be driven by a weak and unstable power source such as a solar cell can be realized, and a wide range of application circuits and bias voltage circuits that are mounted on general-purpose integrated circuits and perform temperature detection on-chip. Adaptable. Furthermore, the PTAT voltage source of the present invention can be widely used in applications for obtaining a reference voltage source independent of temperature by combining with a circuit having different temperature dependency.
  • a voltage that can be driven with a low power supply voltage and is stable with respect to fluctuations in the power supply voltage is generated, and the temperature coefficient of the voltage is less affected by parameter fluctuations in the manufacturing process. Therefore, it can be used as a semiconductor device for generating a PTAT voltage that can be accurately designed on an integrated circuit.
  • the PTAT reference voltage source is used as an indispensable circuit for constituting an integrated reference voltage generating circuit, an integrated temperature detector, etc. capable of driving a low power supply voltage under the recent miniaturized CMOS process.
  • the semiconductor device of the present invention can be widely used as a minute bias voltage circuit that is insensitive to fluctuations in power supply voltage on an integrated circuit.

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JPH01205219A (ja) * 1987-10-05 1989-08-17 Matsushita Electric Ind Co Ltd 半導体集積回路
JP2003521113A (ja) * 2000-01-19 2003-07-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ バンドギャップ電圧の参照電圧源
JP2005134939A (ja) * 2003-10-06 2005-05-26 Ricoh Co Ltd 基準電圧発生回路及びそれを用いた電源装置
JP2005222301A (ja) * 2004-02-05 2005-08-18 Nec Electronics Corp 定電流回路
WO2009014042A1 (ja) * 2007-07-23 2009-01-29 National University Corporation Hokkaido University 基準電圧発生回路

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TWI402657B (zh) 2013-07-21

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