TW201113663A - Semiconductor device - Google Patents
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- TW201113663A TW201113663A TW099101220A TW99101220A TW201113663A TW 201113663 A TW201113663 A TW 201113663A TW 099101220 A TW099101220 A TW 099101220A TW 99101220 A TW99101220 A TW 99101220A TW 201113663 A TW201113663 A TW 201113663A
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- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
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201113663 六、發明說明： 【發明所屬之技術領域】 本發明關於半導體裝置，特別關於使用流通擴散電流 的半導體元件而於積體電路上被構成之基準電壓源。更詳 言之爲，對於電源電壓變動之穩定之基準電壓源，產生和 絕對溫度成比例之電壓的PTAT基準電壓源，以及該型之 基準電壓源之利用者》 【先前技術】 和絕對溫度成比例的（PTAT : Proportional To Absolute Temperature)基準電壓源，係在積體電路上實 現溫度感測器或能隙（band gap )基準電壓源時必要之重 要的類比電路。專利文獻1揭示利用在弱反轉狀態動作的 MOSFET之半導體裝置來作爲PTAT基準電壓源。專利文獻 1，係將弱反轉區域動作的Μ Ο S F E T之閘極端子與汲極端子 連接成爲二極體連接，將飽和狀態動作之MOSFET予以組 合而成PTAT基準電壓源。於專利文獻1之PTAT基準電壓源 ’ PTAT基準電壓，係呈現和依據絕對溫度及MOSFET之形 狀所決定之常數成比例，和指數動作狀態中之傾斜係數η 成反比例之特性。 但是，伴隨近年之類比電路之低電源電壓化之要求， 基準電壓不受積體電路製造參數影響的低電源電壓驅動之 PTAT基準電壓源成爲必要。專利文獻1揭示之將閘極端子 與汲極端子連接成爲二極體連接之MOSFET之中，伴隨汲 201113663 極電壓之變化閘極電壓亦隨之變化，因此Μ 0 S F E T之動作 狀態會受汲極電壓而變化。特別是，近年來之積體電路中 之低臨限値MOSFET之中，汲極電壓之設定範圍顯著受限 。另外，指數動作狀態中之傾斜係數η，乃積體電路之製 造參數及基於MOSFET之動作狀態而變動之參數，會使基 準電壓之特性劣化之同時，使設計時之設定電壓之信賴性 劣化。 專利文獻1 :公開特許公報特開昭5 5 - 5 7920號 【發明內容】 (發明所欲解決之課題） 近年來之微細化製程之臨限値電壓降低導致MOSFET 之驅動範圍變爲更窄，泛用製程基礎下於0.5V以下之低電 源電壓動作，對於電源電壓之變動可以產生穩定電壓之 PTAT基準電壓源還不存在。因此，無法實現可以太陽電 池等微弱、而且不穩定電源驅動之單晶片PTAT電路。另 外，需要串聯連接之電流源作爲外部電路時，電路之最低 動作電源電壓更進一步被提高。另外，指數動作狀態中之 傾斜係數η之變動引起之劣化，成爲降低基準電壓源之設 定電壓信賴性之主要原因。 ， 產受據 置以易依 裝可容可 體動不數 導變數係 半之係度 之壓度溫 用電溫之 生源之壓 產電壓電 壓於電準 電對準蕋 準且基， 基而，# 供、時影 提動同之 於驅之動 在壓壓變 的電電數 目源準參 明電基之 發低之中 本以定程 可穩製 其生到 -6 * 201113663 在擴散電流動作之半導體元件之形狀正確設計於積體電路 上。 (用以解決課題的手段） 藉由以下之半導體裝置來達成，具備第1MOSFET與第 2MOSFET :將上述第1MOSFET之汲極端子與上述第 2MOSFET之源極端子連接；以上述第1MOSFET之汲極端 子與上述第2MOSFET之源極端子之端子間作爲輸出端子； 以上述第1MOSFET之源極端子作爲基準電位；對上述第 2MOSFET之汲極端子施加特定之供給電壓·，將上述第 1MOSFET之閘極端子與上述第2MOSFET之閘極端子連接 ;以上述第1MOSFET之閘極端子與上述第2MOSFET之閘 極端子之端子間作爲第1閘極端子；將上述第1MOSFET之 基板端子與上述第2MOSFET之基板端子連接；以上述第 1MOSFET之基板端子與上述第2MOSFET之基板端子之端 子間作爲第1基板端子：上述第1閘極端子與上述第 2MOSFET之汲極端子未被連接。 (發明效果） 依據本發明之半導體裝置及其驅動方法，可以正確設 計比例係數，可於積體電路上產生和絕對溫度成比例之同 時’對於電源電壓之變動幾乎不受影響的電壓》另外，使 微細之半導體元件動作於以擴散電流模型化的區域，因此 最低動作電源電壓約0.2V (輸出電壓約+ 〇.IV)之極低電 201113663 源電壓的動作成爲可能，消費電力極小之同時，設計面積 亦極小。另外，藉由形狀比互異之複數個半導體元件所獲 得之擴散電流比，來決定和溫度成比例之輸出電壓，因此 可以實現不受製程參數之變動影響的特性。因此，可達成 之效果爲：能實現可以太陽電池等微弱電源驅動之單晶片 集積化之PT AT電路，同時可以搭載於泛用積體電路而廣 泛適用於以單晶片進行溫度檢測的應用電路及偏壓電路。 【實施方式】 說明本發明實施形態之半導體裝置及其驅動方法。本 發明，係使串聯連接之被賦予同一構造、同一閘極偏壓條 件、同一基板偏壓條件的2個供給側MOSFET ( Source side MOSFET )與汲入側 MOSFET ( Sink side MOSFET )，動作 於以擴散電流施予模型化的動作區域，而且供給側 MOSFET之閘極端子未被二極體連接而被施予偏壓，如此 而可於微小電壓至廣域電源電壓範圍內進行動作，而創作 出對於電源電壓之變動幾乎不受影響的PTAT基準電壓源 〇 更詳言之爲，針對具有同一構造的2個供給側MOSFET 與汲入側MOSFET，將供給側MOSFET之源極端子與汲入 側MOSFET之汲極端子予以串聯連接，將串聯連接之2個 Μ 0 S F E T之閘極端子予以共通連接之同時，將串聯連接之2 個MOSFET之基板端子予以共通連接。於串聯連接之2個 MOSFET被共通連接之閘極端子，係和供給側MOSFET之 201113663 汲極端子獨立地被供給電位而構成。即使供給側MO SFET 之汲極端子電壓有所變動之情況下，2個MOSFET之動作區 域’係由MOSFET中之閘極端子一基板端子間電壓來決定 ，因而動作區域不受限於MOSFET之臨限値電壓，可於廣 範圍驅動電源電壓下動作於擴散電流模型之動作區域。串 聯連接之2個MOSFET中之閘極端子之偏壓條件，係在使 MOSFET之閘極區域正下方之通道區域表面，滿足由平帶 (Flat Band)狀態成爲未產生反轉層之動作區域而流通擴 散電流的電壓之範圍內被施予偏壓。在串聯連接之2個 MOSFET中之閘極端子被輸入泛用CMOS電路之時脈時，在 滿足時脈電壓先行顯現之偏壓條件的時間內成爲本發明之 驅動狀態。串聯連接之2個MOSFET中之基板端子之偏壓條 件係設定在，使汲入側MOSFET之源極端子所連接的pn接 合，由弱的順向偏壓被偏壓成爲逆向偏壓（包含0偏壓） 之之電壓範圍內。另外，藉由基板端子之偏壓調整，可以 調整半導體裝置之消費電流之同時，可控制半導體裝置之 動作速度。在擴散電流模型之動作區域進行動作的 MOSFET之模型式，MOSFET之汲極電流特性，並非使用 臨限値電壓，而是依據閘極端子、源極端子、汲極端子、 基板端子之4端子電壓所決定之指數特性之組合予以呈現 。藉由本發明之半導體裝置及其驅動方法之適用擴散電流 模型予以解析，汲入側MOSFET之汲極端子與供給側 MOSFET之源極端子之連接點之電位，係以汲入側 MOSFET之源極電壓爲基準而成爲和絕對溫度成比例的輸 -9- 201113663 出電壓，此可由邏輯予以導出。另外，輸出電壓對於絕對 溫度之比例係數’在供給側MOSFET之通道形狀比對於汲 入側MOSFET之通道形狀比設爲m倍時，係成爲k/qxln ( m + 1)。其中’ k爲波爾兹曼常數（Boltzmann constant) ’ q爲電氣素量。輸出電壓對於絕對溫度之比例係數，並 不包含製程中之各種參數及指數動作狀態中之傾斜係數η ’而是由物理常數及MOSFET之通道形狀來決定，因此不 受製程中之各種參數之變動影響，而且可由MOSFET之通 道形狀正確地設計。另外，本發明之基準電壓源，相對於 以汲入側Μ Ο S F E T之源極端子爲基準的供給側μ Ο S F E T之 汲極端子之電壓變動，汲入側Μ Ο S F Ε Τ之汲極端子與供給 側MOSFET之源極端子間的連接點之電壓並未受其影響， 因此具有高的電源電壓變動去除比。 (實施形態） 圖面表示本發明之實施形態。圖1 A表示作爲流通擴散 電流的半導體元件，使用未形成有反轉層之動作狀態的 NMOSFET予以構成之本發明之PTAT基準電壓源之電路。 針對MOSFET之通道形狀比以外之設計參數及製程之參數 設爲相等製作而成之具有同一構造的供給（source )側 NMOSFET ( Mn2 )與汲入（sink) flj NMOSFET ( Mnl)， 將Mn2之源極端子與Mnl之汲極端子予以連接，將串聯連 接之2個MOSFET之閘極端子予以共通連接之同時，將串聯 連接之2個MOSFET之基板端子予以共通連接。構成Mn2之 -10- 201113663 源極端子的η型雜質半導體與構成Mnl之汲極端子的η型雜 質半導體區域具有同一雜質濃度時，亦即，具有同一製程 參數時，可以共有Μη2之源極端子與Mnl之汲極端子而以1 個η型雜質半導體區域構成。串聯連接之2個MOSFET之中 被共通連接之閘極端子，係構成爲和Mu2之汲極端子獨立 被供給電位。Mnl與Mn2之MOSFET之通道形狀比，係藉由 分別提供通道寬W與通道長L，針對Mill設計成爲Wnl / Lnl=mnl，針對Mn2設計成爲Wn2/Ln2=mn2之形狀比， 使mn2對於mnl之比成爲m而予以調整。另外，藉由將Mnl 與Mn2之通道長Lnl與Ln2設計成爲同一，可以減少通道長 相關之非線性要素。另外，m設爲整數時，將和Μη 1爲同 一形狀之MOSFET之m個予以並聯連接，藉由Μη2之 MOSFET並聯連接而成之m個MOSFET來設計，如此貝！J，可 以減低製程中之通道形狀加工誤差之影響，可以正確決定 m。 圖3A爲使用MOSFET構成圖1A之PTAT基準電壓源之 模式構造斷面圖。輸出端子22所連接之η型高濃度半導體 區域2，爲方便而表示以1個η型高濃度半導體區域2構成之 例，但是可以分割構成爲同濃度之2個η型高濃度半導體區 域。圖3Β爲使用MOSFET構成圖1Β之ΡΤΑΤ基準電壓源時之 模式構造斷面圖。輸出端子22所連接之p型高濃度半導體 區域12，爲方便而表示以1個p型高濃度半導體區域12構成 之例，但是可以分割構成爲同濃度之2個p型高濃度半導體 區域。圖3C爲使用MOSFET於SOI基板上構成圖1A之ptat -11 - 201113663 基準電壓源時之模式構造斷面圖。圖3D爲圖3C之模式上面 圖。圖3E爲使用MOSFET於SOI基板上構成圖1B之PTAT基 準電壓源時之模式構造斷面圖。 作爲流通擴散電流的半導體元件，雙極性電晶體係和 未形成有反轉層之M0SFET同樣爲習知者。分別使 MOSFET之源極端子對應於雙極性電晶體之射極端子、 MOSFET之汲極端子對應於雙極性電晶體之集極端子、 MOSFET之基板端子對應於雙極性電晶體之基極端子，則 圖1 A之半導體裝置可以構成爲PTAT基準電壓源，其係如 圖2 A所示，在以雙極性電晶體利用作爲半導體元件的電路 之中，以同一動作邏輯進行動作，產生同一輸出電壓。此 情況下，不具有閘極端子。同樣地，圖1 B之半導體裝置可 以構成爲PTAT基準電壓源，其係如圖2B所示，在以雙極 性電晶體利用作爲半導體元件的電路之中，以同一動作邏 輯進行動作，產生同一輸出電壓。圖3 F爲使用橫向雙極性 電晶體於S Ο I基板上構成圖1 A之P T A T基準電壓時之模式構 造斷面圖。取代流通擴散電流的MOSFET，改用橫向雙極 性電晶體時，不具備汲入側半導體元件之閘極區域1 4、供 給側半導體元件之閘極區域1 5、及閘極端子24。圖3G爲圖 3F之模式上面圖。圖3H爲使用橫向雙極性電晶體於SOI基 板上構成圖1A之PTAT基準電壓時之模式構造斷面圖。和 圖3F同樣，取代流通擴散電流的MOSFET改用橫向雙極性 電晶體時，不具備汲入側半導體元件之閘極區域1 4、供給 側半導體元件之閘極區域1 5、及閘極端子24。 -12- 201113663 其中，於Μ η 1與Μ η 2之閘極端子（V C )被施加之電壓 ，係滿足Mnl與Mn2之MOSFET之閘極區域正下方之通道區 域由平帶狀態變爲未被形成反轉層之動作區域之範圍之電 壓。於Mnl與Mn2之基板端子（VB)被施加基板端子電壓 ，其係使Μη 1之源極側pn接合由微小之順向偏壓之動作區 域成爲逆向偏壓之動作區域的電壓範圍（包含〇偏壓）。 Mnl之源極端子（VS)與Mn2之汲極端子（VD)之間，係 以VS爲基準使VD成爲正的方向而被提供電位差VD-VS。 以VS爲基準的VD之電位差，相較於以VS爲基準之Mnl之 汲極端子所連接之輸出端子（VO )之電位差VO — VS，係 被提供大0.1 V程度以上。結果，以VS爲基準之Mnl之汲極 端子所連接之輸出端子之電位差VO - VS，係和絕對溫度 成比例而成爲VO_VS=kT/qxln(m+l)。其中，k爲波 爾兹曼常數（Boltzmann constant) ，T爲絕對溫度，q爲 電氣素量。 以下使用呈現未形成有反轉層之MOSFET之汲極電流 特性的擴散電流模型，來說明本發明之PTAT電路之動作 特性。單體之4端子MOSFET動作於弱反轉區域時，汲極電 流，係以由閘極附近區域中之源極（source )端子pn接合 及汲極端pn接合之載子注入引起之擴散電流而被模型化， 使用4個端子之電壓VG、VB、VS、VD而如下表示， ID= I〇(EXP(q · (r(VG- VB)- (VS- VB))/kT)- EXP (q · (r(VG - VB) - (VD - VB))/ kT)) (1) 其中，r爲閘極電壓之劣化係數，用於表示MOSFET之 -13- 201113663 通道區域之表面電位相對於閘極區域之施加電壓之變化比 例，在泛用製程作成之MOSFET約爲具有0.5〜0.9之値。10 以A· q. Dn· npO/L表示，A爲和MOSFET之通道區域連 接的2個pn接合側面區域之有效接合面積，Dn爲電子之擴 散係數，ηρΟ爲構成NMOSFET之通道區域的p型基板之電 子之載子密度，L爲自通道區域之源極端ρη接合至汲極端 ρη接合爲止之長度，設爲短於電子之擴散長度。於弱反轉 區域動作的MOSFET之已知模型所示汲極電流式中之 MOSFET之基板效應弓|起之變動要素，於式（1 )之模型中 ，使用以基板電位爲基準的3對端子間電壓VG — VB、VS — VB、VD — VB來定義4端子之電壓，如此則，可以不使用 臨限値電壓而將MOSFET中之汲極電流予以模型化。Μη 1 之汲極電流，使用式（1 )可表示如下：BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a reference voltage source formed on an integrated circuit using a semiconductor element through which a diffusion current flows. More specifically, for a stable reference voltage source with a constant supply voltage variation, a PTAT reference voltage source that produces a voltage proportional to the absolute temperature, and a user of the reference voltage source of this type are used. [Prior Art] and absolute temperature The PTAT (Proportional To Absolute Temperature) reference voltage source is an important analog circuit necessary for implementing a temperature sensor or a band gap reference voltage on an integrated circuit. Patent Document 1 discloses a semiconductor device using a MOSFET operating in a weak inversion state as a PTAT reference voltage source. Patent Document 1 is a PTAT reference voltage source in which a gate electrode of a 弱 Ο S F E T and a 汲 terminal are connected in a weak polarity in a weak inversion region to form a diode connection. The PTAT reference voltage source ’ PTAT reference voltage of Patent Document 1 is proportional to the constant determined by the absolute temperature and the shape of the MOSFET, and inversely proportional to the tilt coefficient η in the exponential operating state. However, with the demand for low power supply voltage of analog circuits in recent years, it is necessary to drive the PTAT reference voltage source with a low power supply voltage whose reference voltage is not affected by the integrated circuit manufacturing parameters. According to Patent Document 1, a gate electrode in which a gate terminal and a 汲 terminal are connected to a diode is connected, and the gate voltage changes with the change of the pole voltage of 201113663. Therefore, the operation state of the Μ 0 SFET is subject to bungee jumping. The voltage changes. In particular, among the low-threshold MOSFETs in integrated circuits in recent years, the setting range of the drain voltage is significantly limited. Further, the inclination coefficient η in the exponential operation state is a parameter of the manufacturing circuit of the integrated circuit and a parameter which varies depending on the operating state of the MOSFET, which deteriorates the characteristics of the reference voltage and deteriorates the reliability of the set voltage at the time of design. [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei No. 5-5-5820 (Invention) [Resolution to the Invention] In recent years, the threshold of the miniaturization process has been lowered, and the driving range of the MOSFET has become narrower. Under the general-purpose process, the low-supply voltage operation below 0.5V does not exist for the PTAT reference voltage that can generate a stable voltage for the fluctuation of the power supply voltage. Therefore, a single-chip PTAT circuit that can be driven by a weak, unstable power source such as a solar cell cannot be realized. In addition, when a current source connected in series is required as an external circuit, the minimum operating power supply voltage of the circuit is further improved. Further, deterioration due to fluctuations in the inclination coefficient η in the index operation state is a factor that lowers the reliability of the set voltage of the reference voltage source. , the production is subject to the easy to install, can accommodate the body, the number of the derivative system is half of the degree of pressure, the temperature of the electric temperature, the voltage of the production voltage, the voltage is on the basis of the quasi-electrical alignment, and #供,时影影提动 The same as the driving force in the pressure change of the number of electric power source of the quasi-stationary electric base of the low, this can be stabilized by the fixed process to the -6 * 201113663 Diffusion current action of the semiconductor components The shape is correctly designed on the integrated circuit. (Means for Solving the Problem) The first MOSFET and the second MOSFET are provided by the following semiconductor device: a drain terminal of the first MOSFET is connected to a source terminal of the second MOSFET; and a first terminal of the first MOSFET is connected An output terminal is provided between the terminal of the source terminal of the second MOSFET; a source terminal of the first MOSFET is used as a reference potential; a specific supply voltage is applied to a drain terminal of the second MOSFET, and a gate terminal of the first MOSFET is applied a gate terminal connected to the second MOSFET; a first gate terminal between a gate terminal of the first MOSFET and a gate terminal of the second MOSFET; and a substrate terminal of the first MOSFET and a substrate terminal of the second MOSFET The first substrate terminal is connected between the substrate terminal of the first MOSFET and the terminal of the substrate terminal of the second MOSFET: the first gate terminal and the second terminal of the second MOSFET are not connected. (Effect of the Invention) According to the semiconductor device of the present invention and the driving method thereof, the proportional coefficient can be correctly designed, and a voltage which is almost unaffected by fluctuations in the power supply voltage can be generated on the integrated circuit while being proportional to the absolute temperature. The fine semiconductor element is operated in a region modeled by the diffusion current. Therefore, the lowest operating power supply voltage is about 0.2V (output voltage is about + 〇.IV). The operation of the source voltage is possible, and the power consumption is extremely small. The design area is also extremely small. Further, by determining the output voltage proportional to the temperature by the ratio of the diffusion current obtained by the plurality of semiconductor elements having different shapes, it is possible to achieve characteristics that are not affected by variations in the process parameters. Therefore, the achievable effect is that a PT AT circuit capable of integrating a single chip that can be driven by a weak power source such as a solar cell can be realized, and can be mounted on a general-purpose integrated circuit and widely applied to an application circuit for temperature detection using a single wafer. Bias circuit. [Embodiment] A semiconductor device and a method of driving the same according to an embodiment of the present invention will be described. According to the present invention, two supply-side MOSFETs (source side MOSFETs) and a sink-side MOSFET (Sink side MOSFET) having the same structure, the same gate bias condition, and the same substrate bias condition are connected in series, and The diffusion current is applied to the modeled action region, and the gate terminal of the supply side MOSFET is biased without being connected by the diode, so that it can operate from a small voltage to a wide-area supply voltage range, thereby creating The PTAT reference voltage source whose power supply voltage is almost unaffected is more specifically, for the supply side MOSFET and the sink side MOSFET having the same configuration, the source terminal and the sink side MOSFET of the supply side MOSFET are provided. The terminals are connected in series, and the gate terminals of the two S 0 SFETs connected in series are connected in common, and the substrate terminals of the two MOSFETs connected in series are connected in common. The gate terminals connected in common by the two MOSFETs connected in series are supplied with potentials independently of the 201113663 汲 terminal of the supply side MOSFET. Even if the voltage of the 汲 terminal of the supply side MO SFET is changed, the operating region of the two MOSFETs is determined by the voltage between the gate terminals of the MOSFET and the terminal of the substrate, so the operating region is not limited to the MOSFET. The limited voltage can be operated in the action region of the diffusion current model under a wide range of driving power supply voltages. The bias condition of the gate terminal of the two MOSFETs connected in series is such that the surface of the channel region directly under the gate region of the MOSFET satisfies the action region where the inversion layer is not generated by the Flat Band state. The voltage flowing through the diffusion current is biased. When the gate terminals of the two MOSFETs connected in series are input to the clock of the general-purpose CMOS circuit, the driving state of the present invention is achieved in a time period in which the bias voltage condition in which the clock voltage first appears is satisfied. The bias conditions of the substrate terminals of the two MOSFETs connected in series are set such that the pn junction to which the source terminal of the MOSFET is connected is biased by the weak forward bias to be reverse biased (including 0). Within the voltage range of the bias voltage). Further, by adjusting the bias voltage of the substrate terminal, the current consumption of the semiconductor device can be adjusted while controlling the operating speed of the semiconductor device. The model of the MOSFET operating in the action region of the diffusion current model, the drain current characteristic of the MOSFET is not based on the threshold voltage, but on the terminal voltage of the gate terminal, the source terminal, the 汲 terminal, and the substrate terminal. The combination of the determined index characteristics is presented. By analyzing the applicable diffusion current model of the semiconductor device and the driving method thereof, the potential of the connection point between the drain terminal of the input side MOSFET and the source terminal of the supply side MOSFET is the source voltage of the input side MOSFET. For the reference, it is the output voltage proportional to the absolute temperature, which can be derived from logic. Further, the ratio coefficient of the output voltage to the absolute temperature is k/qxln (m + 1) when the channel shape ratio of the supply side MOSFET is m times larger than the channel shape ratio of the input side MOSFET. Where 'k is the Boltzmann constant' q is the amount of electrification. The proportional coefficient of the output voltage to the absolute temperature does not include the various parameters in the process and the tilt coefficient η ' in the exponential operating state, but is determined by the physical constant and the channel shape of the MOSFET, and thus is not subject to variations in various parameters in the process. The effect can be correctly designed by the channel shape of the MOSFET. Further, the reference voltage source of the present invention has a voltage variation with respect to the 汲 terminal of the supply side μ Ο SFET based on the source terminal of the Μ Ο Ο SFET, and the 汲 terminal of the side Ο SF Ε Τ The voltage at the connection point with the source terminal of the supply side MOSFET is not affected by this, and therefore has a high power supply voltage variation removal ratio. (Embodiment) The drawings show an embodiment of the present invention. Fig. 1A shows a circuit of a PTAT reference voltage source of the present invention which is constituted by an NMOSFET in which an operation state of an inversion layer is not formed, as a semiconductor element through which a diffusion current flows. The source side NMOSFET (Mn2) and the sink flj NMOSFET (Mnl) having the same configuration for the channel shape ratio of the MOSFET are set equal to each other, and the source of Mn2 is used. The terminal is connected to the terminal of the Mnl, and the gate terminals of the two MOSFETs connected in series are connected in common, and the substrate terminals of the two MOSFETs connected in series are connected in common. When the n-type impurity semiconductor constituting the source terminal of -10-2, 201113663 has the same impurity concentration as the n-type impurity semiconductor region constituting the 汲 terminal of Mn1, that is, when having the same process parameter, the source terminal of Μη2 can be shared. It is composed of one n-type impurity semiconductor region with the Mn1 terminal. The gate terminals connected in common between the two MOSFETs connected in series are configured to be supplied with potential independently of the 汲 terminal of Mu2. The channel shape ratio of the MOSFETs of Mn1 and Mn2 is designed to be Wnl / Lnl = mnl for Mill and Wn2 / Ln2 = mn2 for Mn2 by providing channel width W and channel length L respectively, so that mn2 is for mnl The ratio is adjusted to m. In addition, by designing the channel lengths Lnl and Ln2 of Mn1 and Mn2 to be the same, the nonlinear elements related to the channel length can be reduced. Further, when m is an integer, m of MOSFETs having the same shape as Μη1 are connected in parallel, and m MOSFETs in which MOSFETs of Μn2 are connected in parallel are designed. J, can reduce the influence of the channel shape processing error in the process, and can correctly determine m. Fig. 3A is a schematic cross-sectional view showing the configuration of a PTAT reference voltage source of Fig. 1A using a MOSFET. The n-type high-concentration semiconductor region 2 to which the output terminal 22 is connected is an example in which one n-type high-concentration semiconductor region 2 is formed for convenience. However, two n-type high-concentration semiconductor regions having the same concentration can be divided. Fig. 3 is a schematic cross-sectional view showing the structure of the ΡΤΑΤ reference voltage source of Fig. 1 using a MOSFET. The p-type high-concentration semiconductor region 12 to which the output terminal 22 is connected is an example in which one p-type high-concentration semiconductor region 12 is formed for convenience. However, two p-type high-concentration semiconductor regions having the same concentration can be divided. 3C is a schematic structural cross-sectional view showing a ptat -11 - 201113663 reference voltage source of FIG. 1A formed on a SOI substrate using a MOSFET. Fig. 3D is a top view of the mode of Fig. 3C. Figure 3E is a schematic cross-sectional view showing the construction of the PTAT reference voltage source of Figure 1B on a SOI substrate using a MOSFET. As the semiconductor element through which the diffusion current flows, a bipolar transistor system and a MOSFET in which an inversion layer is not formed are also known. The source terminal of the MOSFET corresponds to the emitter terminal of the bipolar transistor, the 汲 terminal of the MOSFET corresponds to the collector terminal of the bipolar transistor, and the substrate terminal of the MOSFET corresponds to the base terminal of the bipolar transistor. The semiconductor device of FIG. 1A can be configured as a PTAT reference voltage source, and as shown in FIG. 2A, the same output voltage is generated by the same operation logic among the circuits using the bipolar transistor as the semiconductor element. In this case, there is no gate terminal. Similarly, the semiconductor device of FIG. 1B can be configured as a PTAT reference voltage source, and as shown in FIG. 2B, the same operation logic is used in the circuit using the bipolar transistor as the semiconductor element to generate the same output. Voltage. Figure 3F is a schematic cross-sectional view showing the configuration of the P T A T reference voltage of Figure 1A on a S Ο I substrate using a lateral bipolar transistor. When the MOSFET is used in the case of a laterally bipolar transistor, the gate region 14 of the semiconductor element is not provided, the gate region 15 of the supply side semiconductor element, and the gate terminal 24 are not provided. Fig. 3G is a top view of the mode of Fig. 3F. Figure 3H is a schematic cross-sectional view showing the construction of the PTAT reference voltage of Figure 1A on a SOI substrate using a lateral bipolar transistor. Similarly to FIG. 3F, when the MOSFET in which the diffusion current flows is changed to the lateral bipolar transistor, the gate region 14 of the semiconductor element on the side of the semiconductor element, the gate region 15 of the supply side semiconductor element, and the gate terminal 24 are not provided. . -12- 201113663 where the voltage applied to the gate terminal (VC) of Μ η 1 and η η 2 is such that the channel region immediately below the gate region of the MOSFET satisfying Mn1 and Mn2 is changed from the flat band state to the unrestricted state. The voltage that forms the range of the action region of the inversion layer. The substrate terminal voltage (VB) is applied to the substrate terminals (VB) of Mn1 and Mn2, and the source side pn of the Μn1 is connected to a voltage range in which the operation region of the forward bias is slightly reverse biased (including 〇 bias). Between the source terminal (VS) of Mnl and the 汲 terminal (VD) of Mn2, the potential difference VD-VS is supplied by making VD a positive direction with respect to VS. The potential difference of VD based on VS is greater than or equal to about 0.1 V in comparison with the potential difference VO - VS of the output terminal (VO) to which the NMOS terminal based on VS is connected. As a result, the potential difference VO - VS of the output terminal to which the drain terminal of Mn is referenced by VS is VO_VS = kT / qxln (m + 1) in proportion to the absolute temperature. Where k is the Boltzmann constant, T is the absolute temperature, and q is the electrical quantity. The operation characteristics of the PTAT circuit of the present invention will be described below using a diffusion current model which exhibits a drain current characteristic of a MOSFET in which an inversion layer is not formed. When the single 4-terminal MOSFET operates in the weak inversion region, the drain current is caused by the diffusion current caused by the source terminal pn junction and the 汲 terminal pn junction carrier injection in the region near the gate. Modeling, using the voltages of four terminals VG, VB, VS, VD as follows, ID = I〇(EXP(q · (r(VG- VB)-(VS- VB))))))) · (r(VG - VB) - (VD - VB)) / kT)) (1) where r is the degradation coefficient of the gate voltage and is used to indicate the surface potential of the MOSFET's -13-201113663 channel region relative to the gate The ratio of the applied voltage of the polar region is approximately 0.5 to 0.9 in the MOSFET of the general-purpose process. 10 is represented by A·q. Dn·npO/L, where A is the effective joint area of the two pn junction side regions connected to the channel region of the MOSFET, Dn is the diffusion coefficient of electrons, and ηρΟ is the p-type of the channel region constituting the NMOSFET. The electron carrier density of the substrate, L, is the length from the source terminal ρη junction to the 汲 extreme ρη junction of the channel region, and is shorter than the diffusion length of the electron. In the model of the formula (1), the three pairs of terminals based on the substrate potential are used in the model of the MOSFET of the MOSFET according to the known model of the MOSFET operating in the weak inversion region. The voltages VG — VB, VS — VB, VD — VB define the voltage at the 4 terminals. In this way, the gate current in the MOSFET can be modeled without using the threshold voltage. The drain current of Μη 1 can be expressed as follows using equation (1):
Inl=mnl · 10· EXP(q· (rVC+(l-r)VB)/kT)· EXP (_q. VS/ kT)- EXP(- q · VO/kT)) (2)Inl=mnl · 10· EXP(q·(rVC+(l-r)VB)/kT)· EXP (_q. VS/ kT)- EXP(- q · VO/kT)) (2)
Mn2之汲極電流可使用式（1)表示如下：The gate current of Mn2 can be expressed by the following formula (1):
In2 = mn2 · 10 . EXP(q · (r VC + (1 — r) VB) / kT). (EXP(- q * VO/kT)- EXP(- q · VD/kT)) (3) 於式（3 )，第1項相對於第2項變爲極小時，式（3 ) 可改寫爲·In2 = mn2 · 10 . EXP(q · (r VC + (1 — r) VB) / kT). (EXP(- q * VO/kT)- EXP(- q · VD/kT)) (3) Formula (3), the first term becomes extremely small with respect to the second term, and the formula (3) can be rewritten as
In2 = mn2 · 10 · EXP(q · (r VC + (1 — r) VB ) / kT) · exp(- q . v〇/ kT) (4) 其中，由輸出端子流出之電流極小時，成爲 (5)In2 = mn2 · 10 · EXP(q · (r VC + (1 — r) VB ) / kT) · exp(- q . v〇/ kT) (4) where the current flowing from the output terminal is extremely small, becoming (5)
In 1 = In2 -14- 201113663 式（2)及式（4)中之 Ι〇· EXP(q.(rVC+(l-r)VB) /kT)之項，係共通提供而被輸入至輸入Mill與Mn2之閘極 電壓VC及基板電壓VB，使Mnl與Mn2之製程中之參數一致 而持有同一構造，如此而成爲同一値予以設定。由式（2 )、式（4 )、式（5 )可知， (m+ 1)EXP( - q(V〇 - VS)/kT) = 1+ EXP( - q(VD-VS)/kT) (6) 其中，m表示mn2對於mnl之比，於式（6)之右邊， 當第2項相對於第1項變爲極小時， VO— VS=kT/q.ln(m+l) (7) 之正的PTAT特性被導出。對於絕對溫度T之溫度係數 ，可以藉由物理常數k、q與Mn2對於Mnl之通道形狀比之 比m予以正確決定。 於式（3 )，考慮第2項相對於第1項變爲極小之條件 。第2項對於第1項之相對誤差ε可表示如下， ε = EXP(- q(VD- VO)/kT) (8) 第2項對於第1項之相對誤差變爲極小而可以忽視時之 最大誤差設爲ε neg，ε neg可使用和式（8)同樣之函數 系而表示如下， eneg=EXP(— q.Vneg/kT) (9) 其中，Vneg爲式（9)之中提供最大誤差ε neg的誤差 電壓之換算電壓値。當第2項對於第1項之相對誤差變爲極 小而可以忽視時，滿足 ε ^ ε neg (10) -15- 201113663 即可。例如 ε neg=〇.〇2，T== 300K 時，Vneg 与 0.1V ( =? 4 · k T / q )。由式（8) 、 ( 9 ) 、 （10)可知，式（3 )可以近似式（4)之VD之範圍被提供爲 VD ^ VO + Vneg (11) 同樣地，式（6 )可以近似式（7 )之VD之範圍，於 ε = EXP(- q(VD- VS)/kT) (12) 藉由使用式（9) 、（10)而被提供爲 VD ^ VS + Vneg (13) 其中，VO大於VS，因此式（13)之條件內含於式（ 1 1 )之條件，欲使導出式（7 )用之近似成立時，只需VD 之電壓滿足式（11)即可。 以下考慮提案電路之動作區域。欲使MOSFET於弱反 轉區域動作時，以2個MOSFET之基板電壓VB爲基準的閘 極電壓VC - VB需要滿足 VC - VB ^ Vtn (14) 其中Vtn爲在NMOSFET之通道區域形成反轉層的電壓 。又，於弱反轉區域動作的Μ Ο S F Ε T，其之汲極電流可藉 由以基板電壓VB爲基準的閘極電壓VC _ VB來控制，因此 需要滿足 VC - VB^ Vfn (15) 其中，Vfn爲NMOSFET之通道區域成爲平帶狀態之電 壓。另外，作爲式（7 )成立之近似條件而需要滿足式（ 11)。如圖4所示爲Mn2之動作區域，係針對以Mnl之源極 端子電壓VS爲基準的Mn2之汲極電壓VD - VS與以Mnl之源 -16- 201113663 極端子電壓vs爲基準的輸出電壓VO - vs之關係者。以 Mnl之源極端子電壓VS爲基準的輸出電壓VO—VS之特性 以實線表示。某一絕對溫度中之PTAT電壓Vpm，係隨溫度 之上升而上升至VpmH，隨溫度之下降而下降至VpmL。欲 使本發明之PTAT電路動作必要之最小電位差VD — VS (稱 爲VDmin)，可由式（11)使用高溫時之PTAT電壓VpmH ，算出VDmin g VpmH + Vneg。使用具有充分長之通道長 的MOSFET時，對於VDmin以上之電壓VD，可以產生不受 電源電壓影響的PTAT電壓。消費電流，係如式（2 )、（ 4 )所示，藉由VC及VB，可以和式（7 )之關係獨立地進 行控制，可獲得穩定之PTAT電壓。 使用橫向雙極性電晶體作爲流通擴散電流之半導體元 件時，依據和使用流通擴散電流之MOSFET來構成時同樣 之原理動作，同樣可以獲得式（7 )之PTAT特性。動作條 件亦和使用流通擴散電流之MOSFET來構成時同樣滿足式 (1 1 )即可。In 1 = In2 -14- 201113663 式· EXP(q.(rVC+(lr)VB) /kT) in equations (2) and (4), which are commonly supplied and input to the inputs Mill and Mn2 The gate voltage VC and the substrate voltage VB have the same structure in accordance with the parameters in the process of Mn1 and Mn2, and thus are set to be the same. From equations (2), (4), and (5), (m + 1)EXP( - q(V〇- VS)/kT) = 1+ EXP( - q(VD-VS)/kT) ( 6) where m represents the ratio of mn2 to mnl, on the right side of equation (6), when the second term becomes extremely small with respect to the first term, VO_VS=kT/q.ln(m+l) (7 The positive PTAT feature is derived. The temperature coefficient of the absolute temperature T can be correctly determined by the physical constants k, q and Mn2 for the channel shape ratio Mn of Mnl. In equation (3), consider the condition that the second term becomes extremely small relative to the first term. The relative error ε of the second term for the first term can be expressed as follows, ε = EXP(- q(VD- VO)/kT) (8) The relative error of the second term for the first term becomes extremely small and can be ignored. The maximum error is set to ε neg, and ε neg can be expressed as follows using the same function system as equation (8), eneg=EXP(− q.Vneg/kT) (9) where Vneg provides the maximum among equations (9) The conversion voltage 値 of the error voltage of the error ε neg. When the relative error of the second term for the first term becomes extremely small and can be ignored, ε ^ ε neg (10) -15 - 201113663 is satisfied. For example, ε neg=〇.〇2, when T== 300K, Vneg and 0.1V (=? 4 · k T / q ). From equations (8), (9), and (10), equation (3) can approximate the range of VD of equation (4) as VD ^ VO + Vneg (11). Similarly, equation (6) can be approximated. (7) The range of VD is given as VD ^ VS + Vneg (13) by using equations (9) and (10) where ε = EXP(- q(VD- VS)/kT) (12) VO is greater than VS, so the condition of the formula (13) is contained in the condition of the formula (1 1 ). When the approximate expression (7) is to be established, the voltage of the VD only needs to satisfy the formula (11). Consider the action area of the proposed circuit below. When the MOSFET is to be operated in the weak inversion region, the gate voltage VC - VB based on the substrate voltage VB of the two MOSFETs needs to satisfy VC - VB ^ Vtn (14) where Vtn is an inversion layer formed in the channel region of the NMOSFET. Voltage. Further, the 汲 SF Ε T operating in the weak inversion region can be controlled by the gate voltage VC _ VB based on the substrate voltage VB, and therefore it is necessary to satisfy VC - VB^ Vfn (15) Wherein, Vfn is a voltage in which the channel region of the NMOSFET is in a flat state. Further, it is necessary to satisfy the equation (11) as an approximate condition for the equation (7). As shown in Fig. 4, the action region of Mn2 is the gate voltage VD - VS of Mn2 based on the source terminal voltage VS of Mn1 and the output voltage based on the source of the Mn1-16-201113663 terminal voltage vs. VO - vs relationship. The characteristics of the output voltage VO_VS based on the source terminal voltage VS of Mnl are indicated by solid lines. The PTAT voltage Vpm at an absolute temperature rises to VpmH as the temperature rises and decreases to VpmL as the temperature decreases. To minimize the potential difference VD - VS (referred to as VDmin) necessary for the operation of the PTAT circuit of the present invention, VDmin g VpmH + Vneg can be calculated from the PTAT voltage VpmH at a high temperature using Equation (11). When a MOSFET having a sufficiently long channel length is used, for a voltage VD of VDmin or more, a PTAT voltage which is not affected by the power supply voltage can be generated. The consumption current, as shown by equations (2) and (4), can be independently controlled by the relationship of equation (7) by VC and VB, and a stable PTAT voltage can be obtained. When a lateral bipolar transistor is used as the semiconductor element through which the diffusion current flows, the PTAT characteristic of the equation (7) can be obtained by the same principle operation as that of the MOSFET in which the diffusion current is used. The operating condition is also satisfied by the equation (1 1 ) when it is constructed using a MOSFET that uses a circulating diffusion current.
作爲圖1A所示PTAT電路之測定電路，說明於0.1 8μιηη —阱CMOS製程試做之圖1 Α所示PTAT電路連接如圖5Α所示 直流電源時之測定結果。於圖5A所示PTAT電路，被提供 VS = 0V、VB = 0V、VC = 0.2V、m = 10 ( Wnl/Lnl = 3μηι / 1 0 μ m、W η 2 / L η 2 = 3 0 μ m / 1 0 μ m )時，以 Μ η 1 之源極端 子電壓VS爲基準的Μη2之汲極電壓VD-VS與以Mnl之源極 端子電壓VS爲基準的輸出電壓VO — VS之關係，係如圖6所 示。以絕對溫度爲參數，測定絕對溫度27 8 K至400K。VC -17- 201113663 被提供滿足式（1〇與式（15)之條件的電壓。PTAT電 壓Vpm，對於絕對溫度之變化大略以等間隔平行移動。T =400K時之PTAT電壓VpmH成爲0.08 8V。使PTAT基準電 壓源動作之必要之最小電位差VDmin爲VDmin = 0.1 88 V。 在驅動電壓VD - VS爲0.2V至1.8V範圍內，不受VD—VS影 響平均上可獲得一定之輸出電壓，在T = 300K時，VD — VS 於1 V變動時，輸出電壓VO _ VS僅止於0.3mV之些微變動 ，由該値求出之電源電壓變動去除比爲- 7 OdB。可於微小 電源電壓範圍至寬廣電源電壓範圍動作，可於積體電路上 實現對於電源電壓之變動幾乎不受影響的偏壓電路。於圖 5A所示PTAT電路之測定電路中，消費電流ID對於VD-VS 之關係如圖7所示。絕對溫度T於27 8K至400K變化時，消 費電流於〗〇〇pA至8nA變化，可於低消費電流動作。於圖 5A 所示 PTAT 電路，被設定 VS=0V、VB=0V、VC=0.2V 、VD = 0.5V、m = 50、10、1時，絕對溫度與以Mnl之源極 端子電壓VS爲基準的輸出電壓v〇 一 VS之關係係如圖8所示 。將Mn2對於Mnl之通道形狀比之比m，設爲m = 50、m = 1 0、m = 1時之測定値分別以記號、▲記號、參記號表示 。另外’將Mn2對於Mnl之通道形狀比之比m，設爲m=50 、m = 1 0、m = 1時之式（7 )所對應之計算値分別以破折 線、實線、虛線表示。〇記號表示變更VB，設定VB = 0_2V之測定結果。τ= 300K (室溫）時之計算値，m= 50 時 VO — VS = 102mV，m:= 10 時 VO — VS = 62mV，m = 1 時 v0 一 VS=l8mV。測定結果和計算結果極爲一致，輸出電 -18 - 201113663 壓和絕對溫度τ成比例，本發明之半導體裝置可作爲PTAT 基準電壓源正確地動作。 作爲上述實施形態之變形例，使用PMOSFET構成之 PTAT基準電壓源之電路圖，係如圖1B所示。藉由進行和 使用NMOSFET之PTAT電路同樣之解析而成爲， VO-VS=-kT/q.ln(m+l) (16) 被導出負的PTAT特性。於使用PMOSFET之構成中， 係於Mnl之源極端子（VS)與Mn2之汲極端子（VD)之間 ，以VS爲基準使VD成爲負之方向而提供電位差VD-VS。 此時，式（16)成立之條件，藉由進行和NMOSFET同樣 之解析可以設爲 VD ^ VO - Vneg (17) 以下考慮動作區域。欲使MOSFET動作於弱反轉區域 時，以2個MOSFET之基板電壓VB爲基準的閘極電壓VC -VB，必須滿足 VC - VB ^ Vtp (18) 其中Vtp(Vtp<0)爲PMOSFET之通道區域未形成反 轉層之電壓。另外，欲使動作於弱反轉區域的MOSFET之 汲極電流，可以藉由以基板電壓VB爲基準的閘極電壓VC 一 VB加以控制時，必須滿足 VC-VBSVfp (19) 其中Vfp爲NMOSFET之通道區域成爲平帶狀態之電壓 。另外’作爲式（1 6 )成立之近似條件，必須滿足式（17 )。圖5A對應之PMOSFET構成之電路之直流電壓連接之 -19- 201113663 例，係如圖5 B所示。 使用橫向雙極性電晶體作爲流通擴散電流之半導體元 件時，依據和使用流通擴散電流之Μ Ο S F E T來構成時同樣 之原理動作，同樣可以獲得式（1 6 )之P T A Τ特性。動作 條件亦和使用流通擴散電流之MOSFET來構成時同樣滿足 式（1 7 )即可。 使用上述半導體裝置之驅動方法之一例，係藉由連接 VC與VS之同時，連接VB與VS，如圖9A所示之僅以1個外 部偏壓電源可以驅動的NMOSFET構成之PTAT電路。產生 式（7 )所示之PTAT電壓。動作條件可以僅由式（1 1 )予 以決定。關於圖9A所示PTAT電路，被提供VD=0.5V、VS :=0.0V、m - 1 ( Wnl / Lnl= 3μιη / ΙΟμιη、Wn2 / Ln2 = 3μιη/ ΙΟμιη )時，絕對溫度Τ與以Μ η 1之源極端子電壓V S 爲基準的輸出電壓VO - VS間之關係，係如圖10所示。將 Mn2對於Μη 1之通道形狀比之比m，設爲m = 1時之測定値 以•記號表示。另外，將Mn2對於Μη 1之通道形狀比之比m ，設爲m = 1時之式（7 )所對應之計算値以實線表示。測 定結果和計算結果極爲一致，輸出電壓和絕對溫度T成比 例。 其他驅動方法之一例，係藉由連接VC與VS之同時， 連接VB與VS，如圖9B所示之僅以1個外部偏壓電源可以驅 動的PMOSFET構成之PTAT電路。產生式（16)所示之 PTAT電壓。動作條件僅由式（1 7 )予以決定。其他驅動 方法之一例，係藉由連接VC與VO之同時，連接VB與VS ’ -20- 201113663 如圖9C所示之僅以ί個外部偏壓電源可以驅動的NMOSFET 構成之PTAT電路。產生式（7 )所示之PTAT電壓。動作條 件係由式（1 1 )及 VO - VS ^ Vtn (20) 予以決定。 作爲上述例之變形之驅動方法之一例，係藉由連接VC 與VO之同時，連接VB與VS，如圖9D所示之僅以1個外部 偏壓電源可以驅動的PMOSFET構成之PTAT電路。產生式 (1 6 )所示之PTAT電壓。動作條件係由式（1 7 )及 VO - VS ^ Vtp (2 1) 予以決定。於彼等例之中，具有可以1個電源產生 PTAT電壓之優點。 又，另一·變形例，係將N個PTAT電路之VD、VC、VB 分別共通連接，將k=l至k=N—l爲止之第k段PTAT電路 之輸出端子VOk連接於第k + 1段PTAT電路之源極端子VS (k+Ι) ’而將N段PTAT電路縱向連接，以初段之源極端 子VS1爲VS，以第N段之輸出爲VON，而成爲NMOSFET構 成之PTAT電路，如圖11A所示。ml〜m2N係分別表示和 Mnl〜Mn2N對應之MOSFET之通道形狀比。進行同樣解析 ’例如設計爲 m2=m4=· · ♦ · m2 ( N — 1 ) — 1 = m _ \ ，m2N=m+l、ml=m3=· . · · m2N — 1=1 > ] / m 時，被提供 VON— VS=N.kT/q.ln(m+l) (22) 欲實現N倍大之溫度係數時爲有效之構成。動作條件 -21 - 201113663 被提供爲 VD ^ VON + Vneg (23) 將N個PTAT電路之VD、VC' VB分別共通連接，將k =1至k=N_ 1爲止之第k段PTAT電路之輸出端子VOk連接 於第k+Ι段PTAT電路之VS(k+l)，將N段PTAT電路縱 向連接，以初段之源極端子VS1爲VS，以第N段之輸出爲 VON >而成爲PMOSFET構成之PTAT電路，如圖11B所示。 ml〜m2N係分別表示和Mpl〜Mp2N對應之MOSFET之通道 形狀比。進行同樣解析，例如設計爲m2 = m4 = ·... m2 ( N — 1) — 1 = m — 1 * m2N=m + 1 ' ml=m3= · . · • m2N — 1=1，mgl/m時，被提供 VON— VS=— N.kT/q*ln(m+l) (23) 欲實現N倍大之溫度係數時爲有效之構成。動作條件 被提供爲 VD ^ VON - Vneg (24) 如上述說明，依據本發明，可以正確設計比例係數， 可於積體電路上產生和絕對溫度成比例之同時，對於電源 電壓之變動幾乎不受影響的電壓。另外，使微細之 MOSFET動作於以擴散電流模型化的區域，因此最低動作 電源電壓約0.2V之極低電源電壓的動作成爲可能，消費電 力極小之同時，設計面積亦極小。另外，藉由形狀比互異 之複數個MOSFET所獲得之擴散電流比，來決定和溫度成 比例之輸出電壓，因此可以實現不受製程參數之變動影響 的特性。因此，可達成之效果爲：能實現可以太陽電池等 -22- 201113663 微弱、且不穩定電源驅動之單晶片集積化之PTAT電路， 同時’可以搭載於泛用積體電路而廣泛適用於以單晶片進 行溫度檢測的應用電路及偏壓電路。另外，本發明之 PT AT電壓源，藉由和溫度依存性不同之電路之組合，而 能廣泛利用於不受溫度影響的基準電壓源。 (產業上可利用性） 本發明’可以作爲以低電源電壓驅動、而且對於電源 電壓之變動可以產生穩定之電壓之同時，電壓之溫度係數 不容易受到製程中參數之變動影響，電壓之溫度係數可以 藉由MOSFET之形狀正確設計於積體電路上的pTAT電壓產 生用的半導體裝置予以使用。PT AT基準電壓源，係於近 年來之微細化CMOS製程基礎下，在構成可以低電源電壓 驅動的集積型基準電壓產生電路、集積型溫度檢測器等時 被利用作爲必要之電路。另外，本發明之半導體裝置，可 以廣泛利用作爲，在積體電路上不受電源電壓之變動影響 的微小偏壓電路。 【圖式簡單說明】 圖1A爲本發明之使用NMOSFET之電路構成，圖…爲 本發明之使用PMOSFET之電路構成。 圖2 A爲圖1 A所示本發明第1實施形態之半導體裝置以 雙極性電晶體予以構成時之電路構成圖，圖2B爲圖1B所示 本發明第1實施形態之半導體裝置以雙極性電晶體予以構 -23- 201113663 成時之電路構成圖。 圖3A爲圖1A之模式構造斷面圖，圖3B爲圖1B之模式 構造斷面圖，圖3C爲以SOI製程製造圖1 A時之模式構造斷 面圖，圖3D爲以SOI製程製造圖1 A時之模式上面圖，圖3E 爲以SOI製程製造圖1B時之模式構造斷面圖。圖3F爲使用 橫向雙極性電晶體以SOI製程製造圖2A時之模式構造斷面 S3。圖3G爲使用橫向雙極性電晶體以SOI製程製造圖2A時 之模式上面圖。圖3H爲使用橫向雙極性電晶體以SOI製程 製造圖2B時之模式構造斷面圖。 圖4爲本發明第1實施形態之半導體裝置之動作區域之 槪念圖。As a measurement circuit of the PTAT circuit shown in Fig. 1A, the measurement result of the PTAT circuit shown in Fig. 1A of the 0.1 8 μm η-well CMOS process is shown in Fig. 5A when the DC power supply is connected. The PTAT circuit shown in Figure 5A is supplied with VS = 0V, VB = 0V, VC = 0.2V, m = 10 (Wnl/Lnl = 3μηι / 1 0 μ m, W η 2 / L η 2 = 3 0 μ m / 1 0 μ m ), the relationship between the drain voltage VD-VS of Μη2 based on the source terminal voltage VS of Μ η 1 and the output voltage VO — VS based on the source terminal voltage VS of Mn1 is As shown in Figure 6. The absolute temperature is measured from the absolute temperature of 27 8 K to 400 K. VC -17- 201113663 is supplied with a voltage satisfying the condition of the equation (1〇 and equation (15). The PTAT voltage Vpm is moved in parallel at equal intervals for the change in absolute temperature. The PTAT voltage VpmH at T = 400K becomes 0.08 8V. The minimum potential difference VDmin necessary to operate the PTAT reference is VDmin = 0.1 88 V. In the range of the driving voltage VD - VS from 0.2 V to 1.8 V, a certain output voltage can be obtained on average without being affected by VD-VS. When T = 300K, when VD - VS changes at 1 V, the output voltage VO _ VS only slightly changes to 0.3 mV, and the power supply voltage variation removal ratio obtained by this 値 is - 7 OdB. It can be in the range of small power supply voltage. To a wide supply voltage range operation, a bias circuit that is almost unaffected by changes in the power supply voltage can be realized on the integrated circuit. In the measurement circuit of the PTAT circuit shown in FIG. 5A, the relationship of the consumption current ID to VD-VS As shown in Figure 7. When the absolute temperature T changes from 27 8K to 400K, the consumption current varies from 〇〇pA to 8nA, and can operate at low consumption current. In the PTAT circuit shown in Figure 5A, VS=0V, VB is set. =0V, VC=0.2V, VD = 0.5V, m = 50 At 10 and 1, the relationship between the absolute temperature and the output voltage v 〇 VS based on the source terminal voltage VS of Mn1 is as shown in Fig. 8. The ratio of the ratio of Mn2 to the channel shape of Mn1 is m, and is set to m = 50, m = 1 0, m = 1 when the measurement 値 is denoted by the symbol, ▲ mark, reference mark. In addition, 'the ratio of Mn2 to Mnl channel shape ratio m, set m = 50, m = 1 0, The calculation 对应 corresponding to the formula (7) at m = 1 is represented by a broken line, a solid line, and a broken line. The 〇 mark indicates that the VB is changed, and the measurement result of VB = 0_2V is set. τ = 300K (room temperature) calculation 値ν — VS = 102mV when m= 50, VO — VS = 62mV when m:= 10, v0 VS=l8mV when m = 1. The measurement results are in good agreement with the calculated results. Output -18 - 201113663 Pressure and absolute temperature The semiconductor device of the present invention can operate correctly as a PTAT reference voltage source in proportion to τ. As a modification of the above embodiment, a circuit diagram of a PTAT reference voltage source formed using a PMOSFET is shown in Fig. 1B. The PTAT circuit of NMOSFET is also parsed, and VO-VS=-kT/q.ln(m+l) (16) is derived. Negative PTAT characteristics. In the configuration using PMOSFET, it is between the source terminal (VS) of Mnl and the 汲 terminal (VD) of Mn2, and VD becomes negative in the direction of VS to provide potential difference VD-VS. . At this time, the condition that the equation (16) is established can be set to VD ^ VO - Vneg (17) by performing the same analysis as the NMOSFET. To operate the MOSFET in the weak inversion region, the gate voltage VC -VB based on the substrate voltage VB of the two MOSFETs must satisfy VC - VB ^ Vtp (18) where Vtp (Vtp < 0) is the channel of the PMOSFET The voltage of the inversion layer is not formed in the region. In addition, when the gate current of the MOSFET operating in the weak inversion region is controlled by the gate voltage VC_VB based on the substrate voltage VB, VC-VBSVfp (19) must be satisfied, where Vfp is the NMOSFET. The channel area becomes the voltage of the flat state. In addition, as an approximate condition for the establishment of the formula (16), the formula (17) must be satisfied. Figure 5A shows the DC voltage connection of the circuit formed by the PMOSFET, as shown in Figure 5B. When a lateral bipolar transistor is used as the semiconductor element through which the diffusion current flows, the P T A Τ characteristic of the equation (16) can be obtained in accordance with the same principle operation as that of the 扩散 F S F E T of the distributed diffusion current. The operation condition is also the same as the equation (1 7 ) when the MOSFET is configured to use a diffusion current. An example of the driving method using the above semiconductor device is to connect VB and VS while connecting VC and VS, and a PTAT circuit composed of an NMOSFET which can be driven by only one external bias power source as shown in Fig. 9A. The PTAT voltage shown in equation (7) is generated. The operating condition can be determined only by the formula (1 1 ). Regarding the PTAT circuit shown in FIG. 9A, when VD=0.5V, VS:=0.0V, m -1 (Wnl / Lnl=3μιη / ΙΟμιη, Wn2 / Ln2 = 3μιη / ΙΟμιη ) is provided, the absolute temperature Τ and Μ η The source terminal voltage VS of 1 is the relationship between the reference output voltage VO - VS, as shown in FIG. The ratio Mn2 to the channel shape ratio of Μη1 is m, and the measurement 値 is expressed by the ? mark. Further, the calculation 値 corresponding to the equation (7) when Mn2 is a ratio m of the channel shape ratio of Μη1 to m = 1 is indicated by a solid line. The measurement results are in good agreement with the calculated results, and the output voltage is proportional to the absolute temperature T. An example of another driving method is to connect VB and VS while connecting VC and VS, and a PTAT circuit composed of a PMOSFET which can be driven by only one external bias power source as shown in Fig. 9B. The PTAT voltage shown in equation (16) is generated. The operating conditions are determined only by equation (17). An example of another driving method is a PTAT circuit composed of an NMOSFET that can be driven by only one external bias power supply as shown in FIG. 9C by connecting VC and VO while connecting VB and VS'-20-201113663. The PTAT voltage shown in equation (7) is generated. The action conditions are determined by equations (1 1 ) and VO - VS ^ Vtn (20). As an example of the driving method of the above-described variant, a PTAT circuit composed of a PMOSFET which can be driven by only one external bias power supply as shown in Fig. 9D is connected by connecting VC and VO. The PTAT voltage shown in equation (16) is generated. The operating conditions are determined by equation (17) and VO-VS^Vtp (2 1). Among them, there is an advantage that a PTAT voltage can be generated by one power source. Further, in another modification, the VD, VC, and VB of the N PTAT circuits are connected in common, and the output terminal VOk of the k-th PTAT circuit from k=l to k=N-1 is connected to the k+th. The source terminal VS (k+Ι) of the 1-stage PTAT circuit is connected longitudinally, and the source terminal VS1 of the initial stage is VS, and the output of the Nth stage is VON, and becomes a PTAT circuit composed of NMOSFETs. As shown in Figure 11A. The ml~m2N system represents the channel shape ratio of the MOSFET corresponding to Mn1 to Mn2N, respectively. Perform the same analysis 'for example, design is m2=m4=·· ♦ · m2 ( N — 1 ) — 1 = m _ \ , m2N=m+l, ml=m3=· . · · m2N — 1=1 > / m is supplied with VON - VS = N.kT / q.ln (m + l) (22) It is effective to achieve N times the temperature coefficient. The operating condition -21 - 201113663 is provided as VD ^ VON + Vneg (23) The VD and VC' VB of the N PTAT circuits are connected in common, and the output of the k-th PTAT circuit from k = 1 to k = N_ 1 The terminal VOk is connected to the VS(k+l) of the k+th segment PTAT circuit, and the N-stage PTAT circuit is vertically connected, and the source terminal VS1 of the initial stage is VS, and the output of the Nth stage is VON > The PTAT circuit is constructed as shown in Fig. 11B. The ml~m2N system represents the channel shape ratio of the MOSFET corresponding to Mpl~Mp2N, respectively. Perform the same analysis, for example, design m2 = m4 = ·... m2 ( N — 1) — 1 = m — 1 * m2N=m + 1 ' ml=m3= · · · m2N — 1=1, mgl/ When m is supplied, VON is supplied - VS = - N.kT / q * ln (m + l) (23) It is effective to realize a temperature coefficient of N times larger. The operating condition is provided as VD ^ VON - Vneg (24) As explained above, according to the present invention, the proportional coefficient can be correctly designed to be proportional to the absolute temperature on the integrated circuit, and the variation of the power supply voltage is hardly affected. The voltage that is affected. Further, since the fine MOSFET is operated in a region modeled by the diffusion current, the operation of the extremely low power supply voltage with a minimum operating power supply voltage of about 0.2 V is possible, and the design power is extremely small, and the design area is extremely small. Further, by determining the output voltage proportional to the temperature by the ratio of the diffusion current obtained by the plurality of MOSFETs having different shapes, it is possible to achieve characteristics that are not affected by variations in the process parameters. Therefore, the achievable effect is that a PTAT circuit capable of integrating a single wafer with a weak and unstable power supply such as a solar cell can be realized, and can be mounted on a general-purpose integrated circuit and widely used for a single The application circuit and bias circuit for temperature detection of the wafer. Further, the PT AT voltage source of the present invention can be widely utilized as a reference voltage source which is not affected by temperature by a combination of circuits having different temperature dependence. (Industrial Applicability) The present invention can be driven as a low power supply voltage, and a stable voltage can be generated for variations in power supply voltage, and the temperature coefficient of the voltage is not easily affected by variations in parameters in the process, and the temperature coefficient of the voltage It can be used by a semiconductor device for generating pTAT voltage which is correctly designed on the integrated circuit by the shape of the MOSFET. The PT AT reference voltage source is used as a necessary circuit in the case of a condensed CMOS process in recent years, which constitutes an accumulation type reference voltage generating circuit and an accumulation type temperature detector which can be driven by a low power supply voltage. Further, the semiconductor device of the present invention can be widely used as a micro-bias circuit which is not affected by fluctuations in the power supply voltage in the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a circuit configuration using an NMOSFET according to the present invention, and is a circuit configuration using a PMOSFET of the present invention. 2A is a circuit configuration diagram of a semiconductor device according to a first embodiment of the present invention, which is configured as a bipolar transistor, and FIG. 2B is a bipolar device of the semiconductor device according to the first embodiment of the present invention shown in FIG. The transistor is constructed as a circuit diagram of -23-201113663. 3A is a schematic sectional view of the structure of FIG. 1A, FIG. 3B is a schematic structural sectional view of FIG. 1B, FIG. 3C is a schematic structural sectional view of the manufacturing process of FIG. 1A by the SOI process, and FIG. 3D is a manufacturing diagram of the SOI process. 1 A mode of the above figure, FIG. 3E is a schematic sectional view of the mode when the FIG. 1B is manufactured by the SOI process. Fig. 3F is a schematic structural section S3 when Fig. 2A is fabricated by a SOI process using a lateral bipolar transistor. Fig. 3G is a top view of the mode in which Fig. 2A is fabricated by a SOI process using a lateral bipolar transistor. Figure 3H is a schematic cross-sectional view showing the construction of Figure 2B in a SOI process using a lateral bipolar transistor. Fig. 4 is a view showing an operation region of the semiconductor device according to the first embodiment of the present invention.
圖5A爲在圖1A對應之本發明第1實施形態之NMOSFET 構成之半導體裝置連接直流電壓源予以驅動時之測定使用 的電路例。圖5 B爲在圖]B對應之本發明第1實施形態之 PMOSFET構成之半導體裝置連接直流電壓源予以驅動時之 測定使用的電路例。 圖6爲圖5 A對應之本發明第1實施形態之NMOSFET構 成之半導體裝置之測定電路之中，輸出電位差VO— VS對 於以絕對溫度T作爲參數時之電位差VD - VS之測定結果。 圖7爲圖5A對應之本發明第1實施形態之NMOSFET構 成之半導體裝置之測定電路之中，消費電流ID對於以絕對 溫度τ作爲參數時之電位差v D — V S之測定結果。 圖8爲圖5 A對應之本發明第1實施形態之NMOSFET構 成之半導體裝置之測定電路之中，輸出電位差VO _ VS對 -24- 201113663 於絕對溫度Τ之邏輯特性與測定結果》 圖9Α爲圖1Α對應之本發明第1實施形態之NMOSFET構 成之半導體裝置之中，設定VC=VB==VS時之電路構成例 。圖9B爲圖1B對應之本發明第1實施形態之PMOSFET構成 之半導體裝置之中，設定VC=VB=VS時之電路構成例。 圖9C爲圖1A對應之本發明第1實施形態之NMOSFET構成之 半導體裝置之中，設定VC=VO、VB=VS時之電路構成例 。圖9D爲圖1B對應之本發明第1實施形態之PMOSFET構成 之半導體裝置之中，設定VC=VO、VB=VS時之電路構成 例。 圖10爲圖9A對應之本發明第1實施形態之NMOSFET構 成之半導體裝置之電路構成例中，輸出電位差V〇—VS對 於絕對溫度T之邏輯特性與測定結果。 圖1 1 A爲將圖1 A對應之本發明第1實施形態之 NMOSFET構成之半導體裝置予以縱向連接而實現大的正 溫度係數的電路構成例。圖1 1 B爲將圖1 B對應之本發明第1 實施形態之PMOSFET構成之半導體裝置予以縱向連接而實 現大的負溫度係數的電路構成例。 1 明 說 號 符 件 元 要 主 1 : η型咼濃度半導體區域；2 : η型高濃度半導體區域 ;3 : η型高濃度半導體區域；6 : ρ型高濃度半導體區域； 7: ρ型高濃度半導體區域；8: ρ型半導體區域；9: ρ型半 導體區域；11 : ρ型高濃度半導體區域；12 : ρ型高濃度半 -25- 導體 體元 16 ： 18 ： 導體 件汲 ；2 7 201113663 區域：1 3 : p型高濃度半導體區域；1 件之閘極區域；1 5 :供給側半導體元f η型高濃度半導體區域；17 : η型高濃g η型半導體區域；19 : η型半導體區域； 裝置源極端子；22 :輸出端子；23 :哲 極端子；24 :閘極端子；25 :絕緣披| :基板端子；28 :絕緣層；29 :絕緣層 4 :汲入側半導 卜之閘極區域； £半導體區域； 2 1 :汲入側半 专給側半導體元 I ; 26 :絕緣層 -26-Fig. 5A is a circuit example used for measurement when a semiconductor device having an NMOSFET according to the first embodiment of the present invention corresponding to the first embodiment of the present invention is driven by a DC voltage source. Fig. 5B is a circuit example used for measurement when a semiconductor device composed of a PMOSFET according to the first embodiment of the present invention corresponding to Fig. B is driven by a DC voltage source. Fig. 6 is a measurement result of the potential difference VD - VS when the output potential difference VO - VS is measured with the absolute temperature T as a parameter in the measurement circuit of the semiconductor device of the NMOSFET according to the first embodiment of the present invention. Fig. 7 is a measurement result of the potential difference v D - V S when the consumption current ID is a parameter using the absolute temperature τ as a parameter in the measurement circuit of the semiconductor device of the NMOSFET according to the first embodiment of the present invention. Fig. 8 is a graph showing the logic characteristics and measurement results of the output potential difference VO _ VS versus -24-201113663 at an absolute temperature 测定 in the measurement circuit of the semiconductor device of the NMOSFET according to the first embodiment of the present invention, which corresponds to Fig. 5A. In the semiconductor device including the NMOSFET according to the first embodiment of the present invention, an example of the circuit configuration when VC = VB == VS is set. Fig. 9B is a circuit configuration example in the case where VC = VB = VS is set in the semiconductor device having the PMOSFET according to the first embodiment of the present invention, which corresponds to Fig. 1B. Fig. 9C is a circuit configuration example in the case where VC = VO and VB = VS are set in the semiconductor device of the NMOSFET according to the first embodiment of the present invention, which corresponds to Fig. 1A. Fig. 9D is a circuit configuration example in which VC = VO and VB = VS are set in the semiconductor device having the PMOSFET according to the first embodiment of the present invention, which corresponds to Fig. 1B. Fig. 10 is a graph showing the logical characteristics and measurement results of the output potential difference V 〇 - VS with respect to the absolute temperature T in the circuit configuration example of the semiconductor device of the NMOSFET according to the first embodiment of the present invention. Fig. 11 is a circuit configuration example in which a semiconductor device having an NMOSFET according to the first embodiment of the present invention corresponding to Fig. 1A is vertically connected to realize a large positive temperature coefficient. Fig. 1 is a circuit configuration example in which a semiconductor device having a PMOSFET according to the first embodiment of the present invention corresponding to Fig. 1B is vertically connected to realize a large negative temperature coefficient. 1 Ming said that the symbol element is the main 1: η type 咼 concentration semiconductor region; 2: η type high concentration semiconductor region; 3: η type high concentration semiconductor region; 6: ρ type high concentration semiconductor region; 7: ρ type high concentration Semiconductor region; 8: p-type semiconductor region; 9: p-type semiconductor region; 11: p-type high concentration semiconductor region; 12: p-type high concentration half-25-conductor element 16: 18: conductor piece 汲; 2 7 201113663 Area: 13: p-type high-concentration semiconductor region; 1 gate region; 1 5: supply-side semiconductor element f η-type high-concentration semiconductor region; 17: n-type high-concentration g η-type semiconductor region; 19: η-type Semiconductor region; device source terminal; 22: output terminal; 23: philosopher terminal; 24: gate terminal; 25: insulating lining |: substrate terminal; 28: insulating layer; 29: insulating layer 4: intrusion side semiconductor Gate region of the pad; £ semiconductor region; 2 1 : semi-special-side semiconductor element I on the intrusion side; 26: insulating layer -26-
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| JPS62239216A (en) * | 1986-04-10 | 1987-10-20 | Seiko Epson Corp | Constant current circuit |
| JPH01205219A (en) * | 1987-10-05 | 1989-08-17 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
| JPH02257317A (en) * | 1989-03-30 | 1990-10-18 | Sumitomo Electric Ind Ltd | Current source circuit |
| JPH11134049A (en) * | 1997-10-30 | 1999-05-21 | Dve:Kk | Reference voltage circuit |
| TW434992B (en) * | 1999-07-16 | 2001-05-16 | Ind Tech Res Inst | Current source apparatus with temperature compensation function |
| WO2001053903A1 (en) * | 2000-01-19 | 2001-07-26 | Koninklijke Philips Electronics N.V. | Bandgap voltage reference source |
| US6617836B1 (en) * | 2002-05-08 | 2003-09-09 | National Semiconductor Corporation | CMOS sub-bandgap reference with an operating supply voltage less than the bandgap |
| JP4397211B2 (en) * | 2003-10-06 | 2010-01-13 | 株式会社リコー | Reference voltage generation circuit and power supply device using the same |
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| GB2416210B (en) * | 2004-07-13 | 2008-02-20 | Christofer Toumazou | Ion sensitive field effect transistors |
| TWI317463B (en) * | 2006-03-20 | 2009-11-21 | Faraday Tech Corp | Low supply voltage bandgap reference circuit and negative temperature coefficient current generation unit thereof and method for supplying bandgap reference current |
| JP4919776B2 (en) * | 2006-11-17 | 2012-04-18 | 新日本無線株式会社 | Reference voltage circuit |
| JP5300085B2 (en) * | 2007-07-23 | 2013-09-25 | 国立大学法人北海道大学 | Reference voltage generation circuit |
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