JP4397211B2 - Reference voltage generation circuit and power supply device using the same - Google Patents

Description

  The present invention relates to a reference voltage generation circuit and a power supply device using the same.

  A reference voltage generation circuit using a depletion transistor having a gate and a source connected as a constant current source is known (see, for example, Patent Document 1). In such a reference voltage generating circuit, as shown in FIG. 10, the gate and the source of an NMOS (N-channel type metal oxide semiconductors) depletion transistor Q5 are connected and their constant current characteristics are utilized. Then, an NMOS enhancement transistor Q6 having a gate and a drain connected is connected in series so as to operate with the constant current of the transistor Q5, and a voltage generated in the transistor Q6 is taken out as a reference voltage Vref. As the reference voltage Vref, the difference between the threshold voltage Vt_d of the transistor Q5 and the threshold voltage Vt_e of the transistor Q6 is output.

  In Patent Document 1, as a method of changing the threshold voltage between the transistor Q5 and the transistor Q6, a method of changing the impurity concentration of the substrate or the impurity concentration of the channel is given as an example. As the method, it has been proposed to change the implantation amount at the time of ion implantation.

FIG. 11 shows the Vgs versus (Ids) ^1/2 waveform (where the drain voltage is a saturation condition) of the transistors Q5 and Q6. However, the conductance factors (K) of the transistors Q5 and Q6 are the same. Vgs is a voltage between the gate and the source, and Ids is a drain current.
Since the transistor Q5 is connected at Vgs of 0 V, a constant current of Iconst is passed from the waveform of Q5 in FIG. Therefore, Vgs of the transistor Q6 where Ids = Iconst is Vref. therefore,
Vref = Vt_e−Vt_d (1)
Thus, it can be seen that Vref is represented by the difference between the threshold voltages Vt_e and Vt_d of the two transistors Q5 and Q6.

The following points can be cited as advantages of Vref of this circuit configuration.
(1) Since the temperature characteristics of the two transistors Q5 and Q6 are substantially the same, the temperature dependence of Vref is small.
(2) Compared to a bandgap reference circuit or the like, since it can be configured with at least two transistors, it can be constructed relatively easily and with a small area. The band gap reference circuit is the polarity of the temperature characteristics of Vbe (voltage between base and emitter) and thermal voltage Vt (= kT / q) (k is Boltzmann constant, T is absolute temperature, q is unit charge) of PN junction. The reference voltage Vref having a very small temperature coefficient is taken out using the difference between the two.

In addition, there is an advantage that a low reference voltage can be generated by changing the connection method of the gate of the depletion transistor Q5 (see, for example, Patent Document 2). The circuit diagram is shown in FIG. The difference from FIG. 10 is that the gate of the depletion transistor Q1 is grounded.
Where Vref is
Vref = (Vt_e−Vt_d) / 2 (2)
Therefore, it is suitable for setting a low reference voltage.

Also, a method for stabilizing the output voltage using a feedback circuit in order to use the substrate bias effect of the depletion transistor is disclosed (for example, see Patent Document 3).
JP-A-56-108258 JP-A-8-335122 JP-A-4-295910

However, there are the following problems in order to realize higher-precision Vref with these circuit configurations.
(1) Since the threshold voltages Vt_d and Vt_e of the two transistors Q5 and Q6 are determined by separate ion implantation processes, the variations are independent, and the differences become large, resulting in variations in Vref. growing. FIG. 13 shows an example when the threshold voltage Vt_e of the transistor Q6 is increased. The broken line is the state before the change.

(2) Since the depletion transistor Q5 and the enhancement transistor Q6 have different conductivity types of impurities injected into the channel, the threshold voltage and mobility temperature characteristics are strictly different, and there is a limit to improving the temperature characteristics of Vref. FIG. 14 shows an example when the threshold voltage Vt_e and mobility of the transistor Q6 at high temperature change. The broken line is the state before the change, and the Vt_e and the slope of the transistor Q6 are changed.

  SUMMARY OF THE INVENTION In view of such problems, the present invention has an object to provide a reference voltage generation circuit that can generate a reference voltage that is less dependent on process variations and temperature changes and that has less variations, and a power supply device using the reference voltage generation circuit. To do.

A first aspect of the reference voltage generating circuit according to the present invention is configured by using an NMOS depletion transistor as a constant current source, and connecting an NMOS transistor having a threshold voltage different from that of the NMOS depletion transistor in series with the NMOS depletion transistor. The drain of the NMOS depletion transistor is connected to the power supply voltage, the gate and source are connected to the output voltage terminal, the substrate is connected to the GND potential, and the drain and gate of the NMOS transistor are connected to the output voltage terminal. Is connected to the GND potential, and the NMOS depletion transistor has a substrate bias coefficient that gives the threshold voltage a voltage change substantially equal to the voltage change of the output voltage terminal, and enhancement With the degree of the threshold voltage does not become.
Here, the NMOS transistor may be an enhancement type or a depression type as long as the threshold voltage is different from that of the NMOS depletion transistor. In the present invention, the voltage change having substantially the same magnitude as the voltage change at the output voltage terminal is preferably the same in magnitude as the voltage change at the output voltage terminal, but at most ± 50 The effect shown in this case can be expected if the voltage change is less than%.

In the first aspect of the reference voltage generating circuit of the present invention, an example in which the range of the output voltage is 0.5 to 1.5 V can be given.
Furthermore, an example in which the substrate depletion coefficient of the NMOS depletion transistor is ² to 3V ^1/2 can be given.
Further, an example in which the absolute value range of the threshold voltage of the NMOS depletion transistor when the substrate-source voltage Vbs = 0V is 1 to 2V can be given.

According to a second aspect of the reference voltage generating circuit of the present invention, a PMOS (P-channel MOS) depletion transistor is used as a constant current source, and a PMOS transistor having a threshold voltage different from that of the PMOS depletion transistor is connected in series to the PMOS depletion transistor. The drain of the PMOS depletion transistor is connected to the GND potential, the gate and source are connected to the output voltage terminal, the substrate is connected to the power supply voltage, and the drain and gate of the PMOS transistor are connected to the output voltage. The PMOS depletion transistor has a circuit configuration in which the source and the substrate are connected to the power supply voltage at the terminal, and the PMOS depletion transistor has a threshold voltage that is substantially the same size as the voltage change at the output voltage terminal and has the opposite polarity. Substrate bias for voltage The rice cake, and with the threshold voltage of the grade which is not an enhancement type.
Here, the PMOS transistor may be an enhancement type or a depression type as long as the threshold voltage is different from that of the PMOS depletion transistor.

In the second aspect of the reference voltage generation circuit of the present invention, an example in which the range of the voltage obtained by subtracting the output voltage from the power supply voltage is 0.5 to 1.5 V can be given.
Furthermore, an example in which the substrate depletion coefficient of the PMOS depletion transistor is ² to 3 V ^1/2 can be given.
Further, an example in which the absolute value range of the threshold voltage of the PMOS depletion transistor when the substrate-source voltage Vbs = 0 V is 1 to 2 V can be given.

  A first aspect of a power supply device according to the present invention includes a divided resistor circuit for dividing an input voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and a division from the divided resistor circuit A power supply device including a voltage detection circuit having a comparison circuit for comparing a voltage with a reference voltage from the reference voltage generation circuit, the power supply device including the reference voltage generation circuit of the present invention as the reference voltage generation circuit It is.

  A second aspect of the power supply device according to the present invention includes an output driver that controls output of an input voltage, a divided resistor circuit that divides the output voltage and supplies a divided voltage, and a reference voltage that supplies a reference voltage And a constant voltage generation circuit having a comparison circuit for comparing the divided voltage from the division resistance circuit with the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result. A power supply device provided with the reference voltage generation circuit of the present invention as the reference voltage generation circuit.

  According to a third aspect of the power supply device of the present invention, the capacitor is charged and discharged by charging and discharging the capacitor by the switching operation of the built-in switch based on the oscillation output from the oscillation circuit that operates based on the reference voltage from the reference voltage generation circuit. A power supply device including a flowing charge pump type DC / DC converter includes the reference voltage generation circuit of the present invention as the reference voltage generation circuit.

  According to the first aspect of the reference voltage generating circuit of the present invention, the substrate of the NMOS depletion transistor is connected to the GND potential, and the substrate bias of the output voltage is applied to the NMOS depletion transistor, so that the substrate of the NMOS depletion transistor is applied. By setting the bias coefficient so that the threshold voltage is given a voltage change that is substantially the same size as the voltage change at the output voltage terminal, for example, against a change in the output voltage due to process fluctuations, temperature changes, etc. This makes it possible to make the change in the threshold voltage of the NMOS depletion transistor almost linear, thus generating a reference voltage with small fluctuations in the output voltage (reference voltage) against external instability factors such as process fluctuations and temperature changes. A circuit can be obtained.

  In the first aspect of the reference voltage generation circuit, if the output voltage range is 0.5 to 1.5 V, the range of the practical power supply voltage and the variation in the threshold voltage of the transistor in the manufacturing process can be reduced. Thus, it is possible to obtain a reference voltage generating circuit with less fluctuations more efficiently.

Further, if the substrate bias coefficient is in the range of ² to 3 V ^1/2 , the change in the threshold voltage of the NMOS depletion transistor to which the substrate bias corresponding to the voltage value of the output voltage is applied with respect to the change in the output voltage. As a result, the reference voltage generating circuit with smaller variation can be obtained.

Further, if the absolute value range of the threshold voltage of the NMOS depletion transistor when the substrate-source voltage Vbs = 0 V is 1-2 V, for example, the substrate bias coefficient is in the range of 2-3 V ^1/2 . Even in the case of setting to, the NMOS depletion transistor does not become an enhancement type at the output voltage, and circuit malfunction can be prevented.

  In the second embodiment of the reference voltage generating circuit of the present invention, the substrate of the PMOS depletion transistor is connected to the power supply potential, and a voltage obtained by subtracting the output voltage from the power supply voltage to the PMOS depletion transistor (hereinafter referred to as differential voltage). By applying a substrate bias and setting the substrate bias coefficient of the PMOS depletion transistor to be substantially the same as the voltage change of the output voltage terminal and applying a reverse voltage change to the threshold voltage, for example, the process Since the change in the threshold voltage of the PMOS depletion transistor can be made almost linear with respect to the change in the differential voltage due to fluctuations and temperature changes, it is possible to deal with external instability factors such as process fluctuations and temperature changes. Therefore, it is possible to obtain a reference voltage generation circuit with small fluctuations in the output voltage (reference voltage). Can.

In the second aspect of the reference voltage generation circuit, if the range of the differential voltage is 0.5 to 1.5 V, the range of the practical power supply voltage and the variation in the threshold voltage of the transistor in the manufacturing process can be reduced. Thus, it is possible to obtain a reference voltage generating circuit with less variation more efficiently.
Further, if the substrate bias coefficient γ is in the range of ² to 3V ^1/2 , the change in the threshold voltage of the PMOS depletion transistor to which the substrate bias of the differential voltage is applied is linear with respect to the change in the differential voltage. As a result, it is possible to obtain a reference voltage generating circuit with less variation.
Further, if the range of the absolute value of the threshold voltage of the PMOS depletion transistor when the substrate-source voltage Vbs = 0 V is 1-2 V, the substrate bias coefficient is set within the range of 2-3 V ^1/2 . Even in the case of setting, the PMOS depletion transistor is not enhanced in the output voltage, and circuit malfunction can be prevented.

  In a first aspect of the power supply device according to the present invention, in the power supply device including a divided resistor circuit, a reference voltage generation circuit, and a voltage detection circuit having a comparison circuit for comparing the divided voltage and the reference voltage, the reference voltage Since the reference voltage generation circuit of the present invention is provided as a generation circuit, the reference voltage generation circuit of the present invention has a small variation in the reference voltage against external instability factors such as process variations and temperature variations. The detection capability can be stabilized and the accuracy can be improved.

  In the second aspect of the power supply device according to the present invention, the output driver, the divided resistor circuit, the reference voltage generating circuit, the divided voltage and the reference voltage are compared, and the operation of the output driver is controlled according to the comparison result. In the power supply apparatus having the constant voltage generation circuit having the comparison circuit of FIG. 5, the reference voltage generation circuit of the present invention is provided as the reference voltage generation circuit, so that external instability factors such as process fluctuations and temperature changes In contrast, the reference voltage generation circuit of the present invention in which the fluctuation of the reference voltage is small can stabilize the output voltage and improve the accuracy.

  According to a third aspect of the power supply device of the present invention, the capacitor is charged and discharged by charging and discharging the capacitor by the switching operation of the built-in switch based on the oscillation output from the oscillation circuit that operates based on the reference voltage from the reference voltage generation circuit. In the power supply device having the charge pump type DC / DC converter to be flown, the reference voltage generation circuit of the present invention is provided as the reference voltage generation circuit, so that external instability factors such as process variations and temperature changes In contrast, the reference voltage generation circuit of the present invention in which the fluctuation of the reference voltage is small can stabilize the output voltage and improve the accuracy.

FIG. 1 is a circuit diagram showing one embodiment of the first aspect of the reference voltage generating circuit of the present invention.
Q1 is an NMOS depletion transistor constituting a constant current source, and Q2 is an NMOS enhancement transistor. Transistors Q1 and Q2 are connected in series and have different threshold voltages.
The transistor Q1 has a drain connected to the power supply voltage 1, a gate and a source connected to the output voltage terminal 3, and a substrate connected to the GND potential 5.
The transistor Q 2 has a drain and a gate connected to the output voltage terminal 3, and a source and a substrate connected to the GND potential 5.

The calculation of the output voltage value of the reference voltage generating circuit of this embodiment is almost the same as that of the conventional reference voltage generating circuit shown in FIG. The difference is that the substrate bias is applied to the transistor Q1. If calculated from the above formula (1) for the reference voltage Vref,
Vref = Vt_e−Vt_d_Vsb (3)
Thus, the threshold voltage of the depletion transistor Q1 is replaced with that when the substrate bias is applied (Vt_d_Vsb) as compared with the equation (1).

FIG. 2 is a diagram showing a waveform of Vgs versus (Ids) ^1/2 for explaining the substrate bias effect of the depletion transistor Q1. The substrate bias effect is a change in the threshold voltage Vth when the substrate bias Vsb is applied.
When the substrate bias Vsb is applied, the threshold voltage Vth increases by ΔVth. As apparent from FIG. 1, the output voltage Vref itself corresponds to the substrate bias Vsb of the depletion transistor Q1. Considering this and Vref's expression (3), in the reference voltage generating circuit of the present invention, if the output voltage Vref is increased due to process variations or the like, the substrate bias Vsb of the depletion transistor Q1 increases. As a result, the threshold voltage Vth rises and negative feedback is applied, so that the output voltage Vref can be made constant.

By the way, the substrate bias effect in a practical output voltage range of about 0.5 V to 1.5 V is generally too small, and the effect of making Vref constant is small.
FIG. 3 shows a Vth vs. Vsb waveform of a depletion transistor having a threshold voltage Vth = −0.3V under the conditions of a substrate bias coefficient γ = 0.5V ^1/2 and a substrate bias Vsb = 0V.
It can be seen that the threshold voltage Vth increases as the substrate bias Vsb increases.
However, the change of the threshold voltage Vth when the substrate bias Vsb is changed in the range of 0.5V to 1.5V is about 0.2V. This indicates that there is only a 0.2V feedback effect when the output voltage changes by 1V. Therefore, in order to make the best use of the feedback effect, it is essential to optimally design the substrate bias effect of the depletion transistor Q1.

FIG. 4 shows a Vth vs. Vsb waveform when the substrate bias coefficient γ is set to 2.5 V ^1/2 .
When the substrate bias Vsb changes in the range of 0.5 V to 1.5 V, the change of the threshold voltage Vth is about 1 V, which has a substantially linear relationship, and feedback can be efficiently applied in this range.
However, it can be seen that when the substrate bias Vsb = 0V, the threshold voltage Vth = 1.5V, which is an enhancement.
This is a general Vth equation
Vth = 2φf + Vfb + γ (2φf + Vsb) (4)
As can be seen from the above, since the substrate bias coefficient γ also affects 2φf when the substrate bias Vsb = 0V, the threshold voltage Vth when the substrate bias Vsb = 0V is also increased. .

As a countermeasure, a method of setting the threshold voltage Vth when the substrate bias Vbs = 0V to be low by impurity implantation or the like can be considered. However, if the threshold voltage is too low, only the threshold voltage Vth of the depletion transistor Q1 exceeds the output voltage Vref of the reference voltage generating circuit, and the connected enhancement transistor Q2 cannot be inserted.
From the above, it can be seen that in the depletion transistor Q1 used in the present invention, it is necessary not only to optimize the substrate bias coefficient γ but also to optimize the threshold voltage Vth when the substrate bias Vsb = 0V.

For example, FIG. 5 shows a Vth vs. Vsb waveform of a depletion transistor in which the threshold voltage Vth when the substrate bias Vsb = 0 V is also optimized for a reference voltage generating circuit of 1 V output.
The depletion transistor Q1 has a threshold voltage Vth = -1.8V when the substrate bias Vsb = 0V, a substrate bias coefficient γ = 2.5V1 ^{/ 2} , and a threshold voltage Vth = when the substrate bias Vsb = 1V. Designed to -0.6V. By combining with the enhancement transistor Q2 with the threshold voltage Vth = 0.4V, a reference voltage with less variation of 1V output can be obtained.

A manufacturing method of the depletion transistor Q1 in which the threshold voltage Vth = -1.8V when the substrate bias Vsb = 0V and the substrate bias coefficient γ = 2.5V ^1/2 will be described.
Since the substrate bias coefficient γ can be controlled by the gate film thickness and the substrate concentration, these may be controlled so that the substrate bias coefficient γ becomes 2.5 V ^1/2 . For example
γ = (2qεNsub / Cox) ^1/2 (5)
Accordingly, the substrate bias coefficient γ = 2.5 V ^1/2 can be obtained by setting the gate film thickness to 60 nm and the substrate concentration (Nsub) = about 6 × 10 ¹⁶ cm ⁻³ .
For controlling the threshold voltage Vth, impurity implantation for threshold voltage correction, for example, phosphorus or arsenic is implanted in the case of an NMOS depletion transistor, and the threshold voltage Vth = −1 when the substrate bias Vsb = 0V. .8V can be obtained.

The reference voltage generation circuit according to the present invention is suitable for products for low power consumption such as cellular phones and PDAs (Personal Digital Assistance), in which case the range of practical power supply voltage and the threshold voltage variation of transistors in the manufacturing process are suitable. In view of the above, the output voltage is preferably about 0.5 to 1.5V. When the range of the output voltage is determined, γ = ² to 3V ^1/2 is obtained as the range of the substrate bias coefficient γ that can be efficiently fed back. When the substrate bias coefficient γ is controlled within this range, the optimum range of the absolute value of the threshold voltage Vth when the substrate bias Vbs = 0 V is that the depletion transistor is not enhanced and the threshold voltage at the output voltage is 1-2V is suitable so that the absolute value of Vth does not exceed the output voltage.

The reference voltage generating circuit of the present invention can be similarly configured with a PMOS transistor.
FIG. 6 shows a circuit diagram of an embodiment of the second aspect of the reference voltage generating circuit of the present invention.
Q3 is a PMOS enhancement transistor, and Q4 is a PMOS depletion transistor constituting a constant current source. Transistors Q3 and Q4 are connected in series and have different threshold voltages.
The transistor Q3 has a source and substrate connected to the power supply voltage 1, and a gate and drain connected to the output voltage terminal 3.
The transistor Q4 has a source and a gate connected to the output voltage terminal 3, a drain connected to the GND potential 5, and a substrate connected to the power supply voltage 1.
In this embodiment, since the voltage obtained by subtracting the output voltage from the power supply voltage corresponds to the reference voltage Vref when NMOS is used, it is suitable when the reference voltage is required based on the power supply voltage 1.

  In this embodiment, since the substrate of the PMOS depletion transistor Q4 is connected to the power supply voltage 1, a substrate bias of a voltage (differential voltage) obtained by subtracting the voltage of the output voltage terminal 3 from the power supply voltage 1 is applied to the PMOS depletion transistor Q4. . The substrate bias coefficient of the PMOS depletion transistor Q4 is set so as to give the threshold voltage a voltage change having substantially the same magnitude as the voltage change of the output voltage terminal 3 and having the opposite polarity.

For example, the PMOS depletion transistor Q4 has a threshold voltage Vth = 1.8V when the substrate-source voltage Vbs = 0V, a substrate bias coefficient γ = 2.5V ^1/2 , and a substrate bias of the differential voltage = −1V. In this case, the threshold voltage Vth is designed to be 0.6V.

In this embodiment, the differential voltage changes in voltage with the same magnitude and opposite polarity with respect to the voltage change at the output voltage terminal 3. Therefore, by setting the substrate bias coefficient of the PMOS depletion transistor Q4 to be substantially the same as the voltage change of the output voltage terminal 3 and having a reverse polarity to the threshold voltage, the difference voltage is set. The change of the threshold voltage of the PMOS depletion transistor Q4 with respect to the change of can be made almost linear.
For example, by combining with the PMOS enhancement transistor Q3 having the threshold voltage Vth = −0.4V, it is possible to obtain a reference voltage with less variation in (power supply voltage−1) V output.

When applying the reference voltage generation circuit of the present invention using a PMOS to a product for low power consumption such as a mobile phone or a PDA, considering the range of practical power supply voltage and the variation of the threshold voltage of the transistor in the manufacturing process, As in the case of the reference voltage generation circuit of the present invention using NMOS, the output voltage is preferably about 0.5 to 1.5V. When the range of the output voltage is determined, γ = ² to 3V ^1/2 is obtained as the range of the substrate bias coefficient γ that can be efficiently fed back. Further, when the substrate bias coefficient γ is controlled within this range, the optimum range of the absolute value of the threshold voltage Vth when the substrate-source voltage Vbs = 0V is 1-2V so that the depletion transistor does not become enhancement. Is suitable.

  The reference voltage generation circuit of the present invention can be applied to, for example, a power supply device. Hereinafter, embodiments of the power supply device including the reference voltage generation circuit of the present invention will be described. However, the use of the reference voltage generation circuit of the present invention is not limited to the power supply device.

FIG. 7 is a circuit diagram showing an embodiment of a power supply device having a constant voltage generating circuit.
A constant voltage generation circuit 11 is provided in order to stably supply power from the DC power supply 7 to the load 9. The constant voltage generation circuit 11 includes an input terminal (Vbat) 13 to which the DC power supply 7 is connected, a reference voltage generation circuit (Vref) 15, an operational amplifier (comparison circuit) 17, and a P-channel MOS transistor (hereinafter referred to as an output driver). 19 (abbreviated as PMOS) 19, divided resistance elements R 1 and R 2, and an output terminal (Vout) 21. The reference voltage generation circuit 15 includes the reference voltage generation circuit of the present invention.

In the operational amplifier 17 of the constant voltage generation circuit 11, the output terminal is connected to the gate electrode of the PMOS 19, the reference voltage Vref is applied from the reference voltage generation circuit 15 to the inverting input terminal (−), and the non-inverting input terminal (+) is applied. A voltage obtained by dividing the output voltage Vout by the resistance elements R1 and R2 is applied, and the division voltage of the resistance elements R1 and R2 is controlled to be equal to the reference voltage Vref.
In this embodiment, since the reference voltage generating circuit 15 of the present invention is provided as the reference voltage generating circuit 15, the reference voltage of the present invention is small in fluctuation of the reference voltage against external instability factors such as process fluctuation and temperature change. The generation circuit can stabilize the output voltage and improve the accuracy.

FIG. 8 is a circuit diagram showing an embodiment of a power supply device provided with a voltage detection circuit.
In the voltage detection circuit 23, reference numeral 17 denotes an operational amplifier. A reference voltage generation circuit 15 is connected to an inverting input terminal (−) of the operational amplifier, and a reference voltage Vref is applied. The voltage of the terminal to be measured input from the input terminal (Vsens) 25 is divided by the dividing resistance elements R1 and R2 and input to the non-inverting input terminal (+) of the operational amplifier 17. The output of the operational amplifier 17 is output to the outside through an output terminal (Vout) 27. The reference voltage generation circuit 15 includes the reference voltage generation circuit of the present invention.

In the voltage detection circuit 23, when the voltage of the terminal to be measured is high and the voltage divided by the dividing resistor elements R1 and R2 is higher than the reference voltage Vref, the output of the operational amplifier 17 is maintained at the H level and should be measured. When the voltage at the terminal drops and the voltage divided by the dividing resistor elements R1 and R2 becomes equal to or lower than the reference voltage Vref, the output of the operational amplifier 17 becomes L level.
In this embodiment, since the reference voltage generating circuit 15 of the present invention is provided as the reference voltage generating circuit 15, the reference voltage of the present invention is small in fluctuation of the reference voltage against external instability factors such as process fluctuation and temperature change. The generation circuit can stabilize the voltage detection capability and improve the accuracy.

FIG. 9 is a circuit diagram showing an embodiment of a power supply device including an inverting charge pump DC / DC converter.
The circuit includes an input terminal (Vin) 29, an output terminal (Vout, inverted output) 31, a GND terminal (GND) 33, a pump capacity positive terminal (CP +) 35, and a pump capacity negative terminal (CP-) 37. It has been. An external component capacitor (not shown) is connected between the pump capacity positive side terminal 35 and the pump capacity negative side terminal 37.

Inside, a PMOS transistor 39 and an NMOS transistor 41 are sequentially provided between the input terminal 29 and the GND terminal 33. A pump capacitor positive side terminal 35 is connected between the PMOS transistor 39 and the NMOS transistor 41. A ground potential 43 is connected between the NMOS transistor 41 and the GND terminal 33.
NMOS transistors 45 and 47 are sequentially connected between the GND potential 43 and the output terminal 31. A pump capacity negative terminal 37 is connected between the NMOS transistors 45 and 47.

  An oscillation circuit that alternately oscillates a voltage (Vin voltage) having the same magnitude as that of the input terminal 29 and a voltage (GND voltage) having the same magnitude as that of the GND terminal 33 based on the reference voltage from the reference voltage generation circuit (Vref) 49. (OSC) 51 is provided. The reference voltage generation circuit 15 includes the reference voltage generation circuit of the present invention. The output terminal of the oscillation circuit 51 is directly connected to the gate electrodes of the NMOS transistors 41 and 47, is connected to the gate electrode of the NMOS transistor 45 via the inverter 53, and the inverter 53 and the gate electrode of the PMOS transistor 39 are connected to each other. 55 is connected.

  This inverting charge pump DC / DC converter applies a voltage to the gate electrodes of the four transistors 39, 41, 45, 47 through the oscillation circuit 51 to switch them, and the pump capacity positive side terminal 35 and the pump capacity negative side terminal 37 are switched. Current is passed by charging and discharging the capacitors connected in between, and an inverted voltage of the input voltage 29 is output to the output terminal 31.

When the GND voltage is generated from the oscillation circuit 51, the PMOS transistor 39 and the NMOS transistor 45 are turned on, and the other two NMOS transistors 41 and 47 are turned off. At this time, a charge is accumulated in the capacitor connected between the pump capacity positive terminal 35 and the pump capacity negative terminal 37.
When the Vin voltage is generated from the oscillation circuit 51, the PMOS transistor 39 and the NMOS transistor 45 are turned off, and the other two NMOS transistors 41 and 47 are turned on. At this time, the capacitor storing the electric charge is discharged, but since the output terminal 31 is set at a lower potential than the GND terminal 33, an inverted voltage from the charge accumulated in the input voltage is output from the output terminal 31.
By repeating the above operation, current continues to flow at the inverted voltage of the input voltage.

  In this embodiment, since the reference voltage generating circuit 15 of the present invention is provided as the reference voltage generating circuit 15, the reference voltage variation is small with respect to external instability factors such as process variations and temperature changes. The reference voltage generating circuit can stabilize the output voltage and improve the accuracy.

Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and various modifications can be made within the scope of the present invention described in the claims.
For example, the embodiment shown in FIG. 1 includes one depletion transistor Q1 and one enhancement transistor Q2. However, the present invention is not limited to this, and the depletion transistor and enhancement transistor connected in series are not limited thereto. Any number may be used.

FIG. 3 is a circuit diagram showing an embodiment of a first aspect of a reference voltage generating circuit. It is a figure which shows the Vgs pair (Ids) ^1/2 waveform for demonstrating the substrate bias effect of the depletion transistor Q1. It is a figure which shows the Vth vs. Vsb waveform of a depletion transistor of threshold voltage Vth = -0.3V on the conditions of substrate bias coefficient (gamma) = 0.5 and substrate bias Vsb = 0V. It is a figure which shows the Vth vs. Vsb waveform of a depletion transistor at the time of raising a substrate bias coefficient (gamma) to 2.5. It is a figure which shows the Vth vs. Vsb waveform of the depletion transistor which also optimized the threshold voltage Vth when the substrate bias Vsb = 0V for the reference voltage generating circuit of 1V output. It is a circuit diagram of one Example of the 2nd aspect of the reference voltage generation circuit of this invention. It is a circuit diagram which shows one Example of a power supply device provided with the constant voltage generation circuit. It is a circuit diagram which shows one Example of a power supply device provided with the voltage detection circuit. It is a circuit diagram which shows one Example of the power supply device provided with the inverting type charge pump DC / DC converter. It is a circuit diagram which shows the prior art example of the reference voltage generation circuit which makes a depletion transistor a constant current. It is a figure which shows the Vgs vs. (Ids) ^1/2 waveform of transistors Q5 and Q6 whose drain voltage satisfies the saturation condition. It is a circuit diagram which shows the other conventional example of the reference voltage generation circuit which makes a depletion transistor a constant current. It is a figure which shows Vgs vs. (Ids) ^1/2 waveform when the threshold voltage of transistor Q6 changes. It is a figure which shows a Vgs pair (Ids) ^1/2 waveform when the threshold voltage and mobility of MOS transistor Q6 change at high temperature.

Explanation of symbols

1 power supply voltage 3 output voltage terminal 5 GND potential 7 DC power supply 9 load 11 constant voltage generation circuit 13 input terminal 15 reference voltage generation circuit 17 operational amplifier 19 P-channel MOS transistor 21 output terminal 23 voltage detection circuit 25 input terminal 27 output terminal 29 Input terminal 31 Output terminal 33 GND terminal 35 Pump capacity positive side terminal 37 Pump capacity negative side terminal 39 PMOS transistor 41, 45, 47 NMOS transistor 43 GND potential 49 Reference voltage generation circuit 51 Oscillation circuit 53, 55 Inverter Q1 NMOS depletion transistor Q2 NMOS enhancement transistor Q3 PMOS enhancement transistor Q4 PMOS depletion transistors R1, R2 Split resistance element

Claims (11)

An NMOS depletion transistor is used as a constant current source, and an NMOS transistor having a threshold voltage different from that of the NMOS depletion transistor is connected in series to the NMOS depletion transistor. The drain of the NMOS depletion transistor is connected to the power supply voltage, And the source is connected to the output voltage terminal, the substrate is connected to the GND potential, the drain and gate of the NMOS transistor are connected to the output voltage terminal, and the source and the substrate are connected to the GND potential,
The NMOS depletion transistor has a substrate bias coefficient that gives the threshold voltage a voltage change substantially equal to the voltage change of the output voltage terminal, and has a threshold voltage that does not become an enhancement type. Reference voltage generation circuit.   2. The reference voltage generating circuit according to claim 1, wherein the range of the output voltage is 0.5 to 1.5V. 3. The reference voltage generating circuit according to claim 1, wherein a substrate bias coefficient of the NMOS depletion transistor is ² to 3V1 ^/ 2.   4. The reference voltage generation circuit according to claim 1, wherein an absolute value range of a threshold voltage of the NMOS depletion transistor when the substrate-source voltage Vbs = 0 V is 1 to 2 V. 5. A PMOS depletion transistor is used as a constant current source, and a PMOS transistor having a threshold voltage different from that of the PMOS depletion transistor is connected in series to the PMOS depletion transistor. The drain of the PMOS depletion transistor is set to the GND potential. And the source is connected to the output voltage terminal, the substrate is connected to the power supply voltage, and the drain and gate of the PMOS transistor are connected to the output voltage terminal, and the source and substrate are connected to the power supply voltage.
The PMOS depletion transistor has a substrate bias coefficient that gives a voltage change of substantially the same magnitude as the voltage change of the output voltage terminal and a reverse polarity to the threshold voltage, and has a threshold that does not become an enhancement type. Reference voltage generation circuit with value voltage.   6. The reference voltage generating circuit according to claim 5, wherein a range of a voltage obtained by subtracting an output voltage from a power supply voltage is 0.5 to 1.5V. 7. The reference voltage generation circuit according to claim 5, wherein a substrate bias coefficient of the PMOS depletion transistor is ² to 3V1 ^{/ 2} .   8. The reference voltage generation circuit according to claim 5, wherein an absolute value range of a threshold voltage of the PMOS depletion transistor when a substrate-source voltage Vbs = 0 V is 1 to 2V. A divided resistor circuit for dividing the input voltage to supply a divided voltage, a reference voltage generating circuit for supplying a reference voltage, a divided voltage from the divided resistor circuit, and a reference voltage from the reference voltage generating circuit In a power supply device equipped with a voltage detection circuit having a comparison circuit for comparison,
A power supply apparatus comprising the reference voltage generation circuit according to claim 1 as the reference voltage generation circuit. An output driver for controlling the output of the input voltage, a divided resistor circuit for dividing the output voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and a divided voltage from the divided resistor circuit In a power supply device comprising a constant voltage generation circuit having a comparison circuit for comparing the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result,
A power supply apparatus comprising the reference voltage generation circuit according to claim 1 as the reference voltage generation circuit. A charge pump type DC / DC converter is provided that allows current to flow by charging / discharging a capacitor by switching operation of a built-in switch based on an oscillation output from an oscillation circuit that operates based on a reference voltage from a reference voltage generation circuit. In power supply,
A power supply apparatus comprising the reference voltage generation circuit according to claim 1 as the reference voltage generation circuit.

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