JPH02257317A - Current source circuit - Google Patents

Abstract

PURPOSE:To stably make output conductance small by composing the current source circuit of a 1st FET whose gate and source are connected mutually and a 2nd FET which has its gate connected to the gate of the 1st FET and its source connected to the drain of the 1st FET. CONSTITUTION:The 1st FET Q1 has its gate and source connected mutually; and the 2nd FET Q2 has its gate connected to the gate of the 1st FET Q1 and its threshold voltage is deeper than that of the 1st FEP Q1. When the drain potential of the 2nd FET Q2 is raised, the drain current increases correspondingly, the potential V3+V3 at the connection point between the source of the 2nd FET Q2 and the drain of the 1st FET Q1 raises, and the inter-gate-source voltage of the 2nd FET Q2 falls, so that the drain current decreases eventually. Thus, negative feedback is provided. Consequently, the output conductance g0 of the whole circuit is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a current source circuit suitable for use in an integrated circuit using a semiconductor.

[Conventional technology]

FIG. 2 shows a conventionally employed current source circuit. In the figure, the gate and source of an FET (field effect transistor) 10 are short-circuited to each other. External terminal 12 on the drain side of FETl0 configured in this way
When a voltage vDS is applied between the drain current ID and the external terminal 11 on the source side, the drain current ID is saturated as shown in FIG. 3, which is used as a current source.

Here, the slope of the ID-vDs characteristic curve shown in FIG. 3 is called the output conductance g, and g is g"'
d/avd' 17g-const.

is given by The smaller the output conductance g 2 is, the more constant the current is, so it can be said to be an excellent current source.

Further, when this circuit is used as a load of an amplifier circuit, there is an advantage that the smaller the output conductance g, the larger the gain can be obtained.

[Problem to be solved by the invention]

However, the above-described current source circuit has the following problems to be solved. First, the I of the FET.

-V. 8. In reality, due to the current flowing in the FET substrate, it is not nearly flat in the saturation region as shown in Figure 3, and the output conductance g is 5 m.
It can only be lowered to about S/wus.

In particular, when the gate length is shortened to increase the mutual conductance g of the FET, a phenomenon called the short channel effect appears, and as shown in Figure 4, the "D-
The slope of the vDS characteristic curve in the saturation region increases,
Output conductance g.

increases significantly.

Therefore, an object of the present invention is to provide a current source circuit in which the output conductance g stably takes a small value.

[Means to solve the problem]

The current source circuit according to the present invention includes a first FET whose gate and source are connected, the gate is connected to the gate of the first FET, and the source is connected to the drain of the first FET. and a second FET connected to each other, the threshold voltage of which is deeper than that of the first FET.

[Effect]

Since the current source circuit according to the present invention is configured as described above, when the potential of the drain of the second FET is increased, the drain current increases by a corresponding amount. As this current increases, the potential at the connection point between the source of the second FET and the drain of the first FET increases. This potential increase causes the gate-source voltage of the second FET to decrease, resulting in a decrease in drain current. By applying negative feedback in this manner, the output conductance g of the entire circuit can be reduced.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A current source circuit according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a configuration diagram of a current source circuit according to an embodiment of the present invention. In the figure, Q 1 and Q2 indicate FET T, both of which are depletion type. 1st F
The gate and source of ETQl are short-circuited, and the source is connected to external terminal 1. The gate of the first FETQ and the gate of the second FETQ2 are connected, and the gate of the first FETQ
The drain of TQl and the source of second FETQ2 are connected. The drain of the second FETQ2 is external terminal 2
It is connected to the.

Here, it is assumed that the threshold voltage of the second FET Q2 is deeper than that of the first FET Ql. In addition, in FET, the drain current is actually 0.1 to 1
A state in which the current decreases to 0 μA (value varies depending on the product) is determined to be zero, and the gate-to-source voltage at this time is called a threshold voltage vth.

The current flowing through the current source circuit configured as described above and the voltage at each part are expressed by symbols as shown in FIG. Here, uppercase letters indicate DC components, and lowercase letters indicate AC components. Then, it can be seen that the output conductance g of this current source circuit decreases based on the following principle.

l) Increase the voltage between external terminals 1.2 from v2 to v2+v. That is, a more positive voltage v2 is applied to the external terminal 2 from v2. A drain current i corresponding to this flows, and the drain current as a whole becomes I o +1 d.

11) Corresponding to the increase in drain current, the potential at the connection point 3 between the drain of the first FET Ql and the source of the second FET Q2 increases.

111) Due to the increase in the potential at connection point 3, the second F
As the gate-source voltage of ETQ2 decreases,
The drain current i, decreases.

Due to such negative feedback, the current value flowing into the current source circuit takes on a stable value, which indicates that the output conductance decreases.

The above action can be explained using a formula as follows.

It is assumed that the current source circuit of FIG. 1 is set to operate at a predetermined bias point. The first FET at this time
Q, the mutual conductance of the second FET Q2 is g g, and the output conductance ml' m2 is g g, respectively, then PO2 1-g (v -v) -gI12v3d
o2 2 3 "golv3 ... ■ From this formula 0, the output conductance g of the circuit in Figure 1 as a whole is g - (g'g) / (gIl12+go
1+go2) Ool o2 ■gol×(go2)/(g, 2+gol+go2)・
...■ becomes. Therefore, if g>gg, s2 o
1' o2 g is g. It can be seen that it is sufficiently small compared to l.

Here, conditions for the threshold voltage vth of the first FETQ and the second FETQ2 will be considered. Now, suppose that the threshold voltage vth is equal in the first FETQ and the second FETQ2, for example, -1v. Then, the connection point 3 in Fig. 1 is (V3-
) Since the first FET Q is biased at about 0.4 V and is not in the saturation region, go becomes large and the effect of lowering the output conductance g of the entire circuit is weakened.

Therefore, as the second FETQ2, the threshold voltage v
If th is selected to have a value on the deeper side than -2V and that of the first FETQ, the above connection point 3 is (V3-)1
．． Biased to about 0V, the first FETQ enters the saturation region, producing the effect of sufficiently reducing the output conductance g. That is, as a condition for placing the first FETQ1 in the saturation region before the second FETQ2 enters the saturation region, the threshold voltage th2 of the second FETQ2 is equal to the threshold voltage v of the first FETQl.
Choose something that is deeper than tht.

As a result, the first FETQt and the second FET
Both TQ2 are guaranteed to operate in the saturation region, and ■
In the formula, g>gg holds m2 o1'
o2. That is, the output conductance g can be reduced.

By the way, the threshold voltage of the first FETQ
If h2 is -1v and the ht threshold voltage V of the second FET Q2 is -1.8v, then g =0.8m/■m is obtained, which is about 1/6 of the normal (conventional) A current source circuit with an output conductance of is obtained.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, even if the type of FET is a junction type, a current source circuit with small output conductance can be realized by configuring the same as in the embodiment.

〔Effect of the invention〕

As described above in detail, according to the present invention, when the current increases, the potential at the connection point between the source of the second FET and the drain of the first FET increases, and eventually the gate of the FET at node 2 increases.・The output conductance can stably take a small value due to the effect of negative feedback, which lowers the source-to-source voltage and lowers the current.

It is a diagram showing 1-V, 8 characteristics.

1.2...External terminal, 3...Connection point, Ql...1st FET1Q2...2nd FET.

Claims (1)

[Claims] A first FET whose gate and source are connected; the gate is connected to the gate of this first FET, and the source is connected to the drain of this first FET, and its threshold voltage (drain current a second FET whose gate-source voltage value (which should be determined to be zero) is deeper than that of the first FET.