CN117492508A - LDO circuit - Google Patents
LDO circuit Download PDFInfo
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- CN117492508A CN117492508A CN202311444542.3A CN202311444542A CN117492508A CN 117492508 A CN117492508 A CN 117492508A CN 202311444542 A CN202311444542 A CN 202311444542A CN 117492508 A CN117492508 A CN 117492508A
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- 238000005070 sampling Methods 0.000 claims abstract description 45
- 230000003068 static effect Effects 0.000 abstract description 6
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention discloses an LDO circuit, comprising: the device comprises a first differential amplifier, a power tube, a first current mirror unit, an output tube, a voltage dividing unit, a current sampling mirror unit and a control unit; the control end of the power tube is connected with the output end of the first differential amplifier, the first current mirror unit is connected with the first end of the power tube, the current sampling mirror unit is connected with the control end of the output tube, and the control unit is connected with the first current mirror unit, the current sampling mirror unit, the control end of the power tube and the ground voltage. According to the LDO circuit disclosed by the invention, when the LDO circuit works in a Dropout area, the first current is controlled by comparing the second current generated by the first current mirror unit based on the first current flowing through the power tube with the third current which is duplicated and transmitted by the second current mirror unit and controlling the opening of the control unit through the signal generated by comparison, so that the condition that the static power consumption of the LDO circuit is larger when the LDO circuit works in the Dropout area is avoided, and meanwhile, the Linetran performance of the LDO circuit in the Dropout area is improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to an LDO circuit.
Background
Currently, SOC (system on chip) generally tends to be applied in low power consumption, and at the same time, the requirement on LDO static power consumption is higher and higher, for example, when the LDO circuit is in Dropout (deep linearity) region, the static power consumption needs to be as small as possible.
Fig. 1 shows a conventional LDO architecture, in which a closed-loop negative feedback circuit is formed by a resistor rf1 and a resistor rf2, so as to realize vout=vref (1+rf1/rf 2), when MOS transistor Mp0 and MOS transistor Mp1 are in a saturation region, we consider that the two are approximately in a current mirror relationship, so that the branch currents on MOS transistor Mn0 and MOS transistor Mp0 are in a linear relationship with the load current of the LDO circuit; when the LDO circuit is in the Dropout region, the closed loop stabilizing system of the LDO circuit is destroyed, the output of the amplifier EA is high, at the moment, the MOS tube Mn0 and the MOS tube MP0 can be considered to form a resistor+MOS tube structure, and the branch current is larger and is irrelevant to the load current of the LDO circuit.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
It is an object of the present invention to provide an LDO circuit that is capable of reducing static power consumption while facilitating an improvement in lineran performance of LDO circuits in Dropout regions.
To achieve the above object, an embodiment of the present invention provides an LDO circuit, including: the device comprises a first differential amplifier, a power tube, a first current mirror unit, an output tube, a voltage dividing unit, a current sampling mirror unit and a control unit;
the control end of the power tube is connected with the output end of the first differential amplifier, the first current mirror unit is connected with the first end of the power tube, the second end of the power tube is connected with the ground voltage, the first end of the voltage dividing unit is connected with the first end of the output tube to form the output end of the LDO circuit, the second end of the output tube is connected with the power voltage, the control end of the output tube is connected with the first current mirror unit, the current sampling mirror unit is connected with the control end of the output tube, the second end of the voltage dividing unit is connected with the ground voltage, and the control unit is connected with the first current mirror unit, the current sampling mirror unit, the control end of the power tube and the ground voltage;
the voltage dividing unit generates a voltage dividing signal based on the output voltage of the LDO circuit, and the first differential amplifier generates a control voltage based on the reference voltage and the voltage dividing signal to control the on and off of the power tube;
the first current mirror unit generates a second current based on a first current flowing through the power tube, the current sampling mirror unit samples a load current on the output tube and generates a third current, and the control unit controls on-off between a control end of the power tube and the ground voltage based on control of the second current and the third current.
In one or more embodiments of the present invention, the first current mirror unit includes a first MOS tube and a second MOS tube, a control end of the first MOS tube and a control end of the second MOS tube are connected to a control end of the output tube, a second end of the first MOS tube and a second end of the second MOS tube are connected to a power supply voltage, a first end of the first MOS tube is connected to a control end of the first MOS tube, a first end of the first MOS tube is connected to a first end of the power tube, and a first end of the second MOS tube is connected to the current sampling mirror unit and the control unit.
In one or more embodiments of the present invention, the ratio of the width to length ratio of the first MOS transistor to the second MOS transistor is k1:1.
in one or more embodiments of the present invention, the current sampling mirror unit includes a sampling unit for collecting a load current on the output pipe to generate a sampling current, and a second current mirror unit for mirroring the sampling current to generate a third current.
In one or more embodiments of the present invention, the sampling unit includes a third MOS transistor, a fourth MOS transistor, and a second differential amplifier, where a control end of the third MOS transistor is connected to a control end of the output pipe, a second end of the third MOS transistor is connected to a power supply voltage, a first end of the third MOS transistor is connected to a first input end of the second differential amplifier, a second input end of the second differential amplifier is connected to a first end of the output pipe, a second end of the fourth MOS transistor is connected to a first input end of the second differential amplifier, a control end of the fourth MOS transistor is connected to an output end of the second differential amplifier, and a first end of the fourth MOS transistor is connected to the second current mirror unit and outputs a sampling current.
In one or more embodiments of the present invention, the second current mirror unit includes a fifth MOS transistor and a sixth MOS transistor, where a first end of the fifth MOS transistor is connected to a control end of the fifth MOS transistor and the sampling unit to receive the sampling current, a control end of the sixth MOS transistor is connected to the control end of the fifth MOS transistor, a first end of the sixth MOS transistor is connected to the first current mirror unit and the control unit, and a second end of the fifth MOS transistor and a second end of the sixth MOS transistor are connected to a ground voltage.
In one or more embodiments of the present invention, the ratio of the width to length ratio of the third MOS transistor to the output transistor is k2:1.
in one or more embodiments of the present invention, the ratio of the width to length ratio of the first MOS transistor to the output transistor is 1: k3.
in one or more embodiments of the present invention, the control unit includes a switching tube, a first end of the switching tube is connected to a control end of the power tube, a second end of the switching tube is connected to a ground voltage, and the control end of the switching tube is connected to the first current mirror unit and the current sampling mirror unit.
In one or more embodiments of the present invention, the voltage dividing unit includes a first resistor and a second resistor, a first end of the first resistor is connected to a first end of the output pipe to form an output end of the LDO circuit, a second end of the first resistor is connected to a first end of the second resistor to output a voltage dividing signal, and a second end of the second resistor is connected to a ground voltage.
Compared with the prior art, according to the LDO circuit provided by the embodiment of the invention, when the LDO circuit works in a Dropout area, the first current mirror unit is compared with the second current generated by the first current flowing through the power tube and the third current which is duplicated and transmitted by the second current mirror unit, and the control unit is controlled to be started by the signal generated by the comparison, so that the first current is controlled, the condition of larger static power consumption of the LDO circuit when the LDO circuit works in the Dropout area is avoided, and meanwhile, the lineran performance of the LDO circuit in the Dropout area is improved.
Drawings
Fig. 1 is a circuit schematic of an LDO circuit according to the prior art.
Fig. 2 is a circuit schematic of an LDO circuit according to an embodiment of the invention.
FIG. 3 is a diagram illustrating a current waveform of an LDO circuit according to an embodiment of the present invention.
Detailed Description
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.
As shown in fig. 2, an LDO circuit includes: the first differential amplifier EA1, a power tube M0, a first current mirror unit 10, an output tube MT, a current sampling mirror unit, a voltage division unit 20 and a control unit 40.
The first differential amplifier EA1 has an output terminal, a first input terminal and a second input terminal, wherein the first input terminal of the first differential amplifier EA1 is configured to receive the reference voltage vref, and in one embodiment, the first input terminal is a positive input terminal, and the second input terminal is a negative input terminal.
The control end of the power tube M0 is connected with the output end of the first differential amplifier EA1, the first current mirror unit 10 is connected with the first end of the power tube M0, and the second end of the power tube M0 is connected with the ground voltage. The first end of the voltage dividing unit 20 is connected with the first end of the output tube MT to form an output end of the LDO circuit, the second end of the output tube MT is connected with the power voltage vdd, the control end of the output tube MT is connected with the first current mirror unit 10, the second end of the voltage dividing unit 20 is connected with the ground voltage, and the voltage dividing unit 20 generates a voltage dividing signal fb based on the output voltage of the LDO circuit. The second input terminal of the first differential amplifier EA1 is used for receiving the divided voltage signal fb, and the first differential amplifier EA1 generates a control voltage based on the reference voltage vref and the divided voltage signal fb to control the on and off of the power transistor M0. In one embodiment, the power tube M0 is an N-channel MOS tube, the first end of the power tube M0 is a drain electrode, the second end of the power tube M0 is a source electrode, and the control end of the power tube M0 is a gate electrode; the output tube MT is a P-channel MOS tube, the first end of the output tube MT is a drain electrode, the second end of the output tube MT is a source electrode, and the control end of the output tube MT is a grid electrode. In other embodiments, the power transistor M0 may be a P-channel MOS transistor, and the output transistor MT may be an N-channel MOS transistor.
The first current mirror unit 10 generates a second current ibuffer_sense based on the first current Ibuffer flowing through the power transistor M0. The current sampling mirror unit is connected with the control end of the output tube MT, and samples the load current Iload on the output tube and generates a third current Iload_sense. The control unit 40 is connected to the control terminal of the power tube M0, the ground voltage, the first current mirror unit 10, and the current sampling mirror unit, and the control unit 40 controls on/off between the control terminal of the power tube M0 and the ground voltage based on the control of the second current ibuffer_sense and the third current iload_sense.
As shown in fig. 2, the first current mirror unit 10 includes a first MOS transistor M1 and a second MOS transistor M2. The control end of the first MOS tube M1 and the control end of the second MOS tube M2 are connected with the control end of the output tube M0, the second end of the first MOS tube M1 and the second end of the second MOS tube M2 are connected with the power supply voltage vdd, and the first end of the first MOS tube M1 is connected with the control end of the first MOS tube M1.
The first end of the first MOS transistor M1 is connected to the first end of the power transistor M0, and the first end of the second MOS transistor M2 is connected to the current sampling mirror unit and the control unit 40. The second MOS transistor M2 is configured to generate a second current ibuffer_sense by mirroring according to a proportion, and in an embodiment, a ratio of width to length of the first MOS transistor M1 to a ratio of width to length of the second MOS transistor M2 is k1:1, the ratio of the width to length ratio of the first MOS tube M1 to the output tube MT is 1: k3.
in an embodiment, the first MOS transistor M1 and the second MOS transistor M2 are P-channel MOS transistors, the control end of the first MOS transistor M1 and the control end of the second MOS transistor M2 are gates, the first end of the first MOS transistor M1 and the first end of the second MOS transistor M2 are drains, and the second end of the first MOS transistor M1 and the second MOS transistor M2 are sources. In other embodiments, the first MOS transistor M1 and the second MOS transistor M2 may be N-channel MOS transistors.
As shown in fig. 2, the voltage dividing unit 20 includes a first resistor Rf1 and a second resistor Rf2, wherein a first end of the first resistor Rf1 is connected to the first current mirror unit 10 to form an output terminal vout of the LDO circuit, a second end of the first resistor Rf1 is connected to a first end of the second resistor Rf2 to output a voltage dividing signal fb, and a second end of the second resistor Rf2 is connected to a ground voltage. In one embodiment, the voltage output by the LDO circuit is divided by the first resistor Rf1 and the second resistor Rf2 to form a divided signal fb at the first end of the second resistor Rf2 and the divided signal fb is sent to the second input end of the first differential amplifier EA 1.
As shown in fig. 2, the current sampling mirror unit includes a sampling unit 31 and a second current mirror unit 32, the sampling unit 31 is connected to the control end of the output tube MT, the sampling unit 31 is used for collecting the load current on the output tube MT to generate a sampling current, the second current mirror unit 32 is connected to the sampling unit 31 and the first current mirror unit 10, and the second current mirror unit 32 is used for mirroring the sampling current to generate a third current iload_sense.
Specifically, the sampling unit 31 includes a third MOS transistor M3, a fourth MOS transistor M4, and a second differential amplifier EA2. The control end of the third MOS tube M3 is connected with the control end of the output tube MT, and the second end of the third MOS tube M3 is connected with the power supply voltage vdd. The first end of the third MOS transistor M3 is connected to the first input end of the second differential amplifier EA2, the second input end of the second differential amplifier EA2 is connected to the first end of the output tube MT, and the second end of the fourth MOS transistor M4 is connected to the first input end of the second differential amplifier EA2, in which, in an embodiment, the first input end of the second differential amplifier EA2 is a negative input end, and the second input end of the second differential amplifier EA2 is a positive input end. The control end of the fourth MOS transistor M4 is connected to the output end of the second differential amplifier EA2, and the first end of the fourth MOS transistor M4 is connected to the second current mirror unit 32 and outputs the sampling current. In one embodiment, the ratio of the width to length ratio of the third MOS transistor M3 to the output transistor MT is k2:1.
the second current mirror unit 32 includes a fifth MOS transistor M5 and a sixth MOS transistor M6. The control end of the fifth MOS transistor M5 is connected to the control end of the sixth MOS transistor M6, the first end of the fifth MOS transistor M5 is connected to the control end of the fifth MOS transistor M5 and to the first end of the fourth MOS transistor M4, and in an embodiment, the ratio of the width to length ratio of the fifth MOS transistor M5 to the sixth MOS transistor M6 is 1:1. the second ends of the fifth MOS transistor M5 and the sixth MOS transistor M6 are connected to the ground voltage, the first end of the sixth MOS transistor M6 is connected to the first end of the second MOS transistor M2 of the first current mirror unit 10 and the control unit 40, and the sixth MOS transistor M6 is configured to mirror the sampling current to generate a third current iload_sense.
In an embodiment, the third MOS transistor M3 and the fourth MOS transistor M4 are P-channel MOS transistors, the first end of the third MOS transistor M3 and the first end of the fourth MOS transistor M4 are drain electrodes, the second end of the third MOS transistor M3 and the second end of the fourth MOS transistor M4 are source electrodes, and the control end of the third MOS transistor M3 and the control end of the fourth MOS transistor M4 are gate electrodes. The fifth MOS tube M5 and the sixth MOS tube M6 are N-channel MOS tubes, the first end of the fifth MOS tube M5 and the first end of the sixth MOS tube M6 are drain electrodes, the second end of the fifth MOS tube M5 and the second end of the sixth MOS tube M6 are source electrodes, and the control end of the fifth MOS tube M5 and the control end of the sixth MOS tube M6 are grid electrodes. In other embodiments, the third MOS transistor M3 and the fourth MOS transistor M4 are N-channel MOS transistors, and the fifth MOS transistor M5 and the sixth MOS transistor M6 are P-channel MOS transistors.
As shown in fig. 2, the control unit 40 includes a switching tube M7, a first end of the switching tube M7 is connected to a control end of the power tube M0, a second end of the switching tube M7 is connected to a ground voltage, and a control end of the switching tube M7 is connected to a first end of the second MOS tube M2 of the first current mirror unit 10 and a first end of the sixth MOS tube M6 of the second current mirror unit 32. In one embodiment, the switching tube M7 is an N-channel MOS tube, the first end of the switching tube M7 is a drain electrode, the second end of the switching tube M7 is a source electrode, and the control end of the switching tube M7 is a gate electrode. In other embodiments, the switching transistor M7 may be a P-channel MOS transistor.
In this embodiment, the first MOS transistor M1 and the second MOS transistor M2 form a current mirror, and the fifth MOS transistor M5 and the sixth MOS transistor M6 form a current mirror. The first end of the second MOS tube M2 is connected with the first end of the sixth MOS tube M6 to form a current comparator, the switching tube M7 is controlled through a comparison result, when the current on the second MOS tube M2 is larger than the current on the sixth MOS tube M6, the switching tube M7 is turned on to pull down the output signal of the first differential amplifier EA1, and when the current on the second MOS tube M2 is smaller than the current on the sixth MOS tube M6, the switching tube M7 is turned off to not act on the output of the first differential amplifier EA1, so that the purpose that the current on the power tube M0 and the first MOS tube M1 is controllable is achieved.
As shown in fig. 3, if the LDO circuit is in the normal operation mode, the output tube MT is in the saturation region, the load current Iload on the output tube MT and the current Ibuffer on the first MOS tube M1 form a linear relationship of ibuffer=iload/k 3, the second current ibuffer_sense on the second MOS tube M2 and the current Ibuffer on the first MOS tube M1 are related as ibuffer_sense=iload/(k 1×k3), the third current iload_sense on the sixth MOS tube M6 and the load current Iload on the output tube MT are related as iload_sense=iload_k2, and when the third current iload_sense > the second current ibuffer_sense, the switch tube M7 is turned off.
If the LDO circuit is in the Dropout region, the output tube MT is in the linear region, and the second differential amplifier EA2 clamps the first end of the third MOS transistor M3 and the first end of the output tube MT, so that the output tube MT still can meet the requirements of iload_sense=iload k2 no matter in the saturation region or the linear region, but the ratio of the current Ibuffer on the first MOS transistor M1 to the load current Iload at this time is rapidly increased, i.e. the second current ibuffer_sense on the second MOS transistor M2 is rapidly increased, and when the second current ibuffer_sense on the second MOS transistor M2 is far greater than the third current iload_sense, the control terminal voltage of the switch tube M7 is raised, so that the control terminal of the power tube M0 is pulled down, and the power tube M0 is turned off, thereby fundamentally solving the problem that the first current Ibuffer is relatively large in the conventional architecture.
Therefore, the proportionality coefficients k1, k2 and k3 are reasonably set, the condition that the LDO circuit works in the Dropout area and has larger static power consumption can be avoided, and the Linetran performance of the LDO circuit in the Dropout area can be improved.
The invention also discloses a chip comprising the LDO circuit.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teachings or may be acquired from other forms, structures, arrangements, proportions, and with other components, materials and parts. The exemplary embodiments were chosen and described in order to explain the principles of the invention and its practical application to thereby enable others skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. An LDO circuit, comprising: the device comprises a first differential amplifier, a power tube, a first current mirror unit, an output tube, a voltage dividing unit, a current sampling mirror unit and a control unit;
the control end of the power tube is connected with the output end of the first differential amplifier, the first current mirror unit is connected with the first end of the power tube, the second end of the power tube is connected with the ground voltage, the first end of the voltage dividing unit is connected with the first end of the output tube to form the output end of the LDO circuit, the second end of the output tube is connected with the power voltage, the control end of the output tube is connected with the first current mirror unit, the current sampling mirror unit is connected with the control end of the output tube, the second end of the voltage dividing unit is connected with the ground voltage, and the control unit is connected with the first current mirror unit, the current sampling mirror unit, the control end of the power tube and the ground voltage;
the voltage dividing unit generates a voltage dividing signal based on the output voltage of the LDO circuit, and the first differential amplifier generates a control voltage based on the reference voltage and the voltage dividing signal to control the on and off of the power tube;
the first current mirror unit generates a second current based on a first current flowing through the power tube, the current sampling mirror unit samples a load current on the output tube and generates a third current, and the control unit controls on-off between a control end of the power tube and the ground voltage based on control of the second current and the third current.
2. The LDO circuit of claim 1, wherein the first current mirror unit comprises a first MOS tube and a second MOS tube, wherein the control end of the first MOS tube and the control end of the second MOS tube are connected with the control end of the output tube, the second end of the first MOS tube and the second end of the second MOS tube are connected with the supply voltage, the first end of the first MOS tube is connected with the control end of the first MOS tube, the first end of the first MOS tube is connected with the first end of the power tube, and the first end of the second MOS tube is connected with the current sampling mirror unit and the control unit.
3. The LDO circuit of claim 2, wherein a ratio of the aspect ratio of the first MOS transistor to the second MOS transistor is k1:1.
4. the LDO circuit of claim 1, wherein the current sampling mirror unit comprises a sampling unit for collecting a load current on the output pipe to generate a sampling current and a second current mirror unit for mirroring the sampling current to generate a third current.
5. The LDO circuit of claim 4, wherein the sampling unit comprises a third MOS transistor, a fourth MOS transistor, and a second differential amplifier, wherein a control end of the third MOS transistor is connected to a control end of the output tube, a second end of the third MOS transistor is connected to a power supply voltage, a first end of the third MOS transistor is connected to a first input end of the second differential amplifier, a second input end of the second differential amplifier is connected to a first end of the output tube, a second end of the fourth MOS transistor is connected to a first input end of the second differential amplifier, a control end of the fourth MOS transistor is connected to an output end of the second differential amplifier, and a first end of the fourth MOS transistor is connected to the second current mirror unit and outputs a sampling current.
6. The LDO circuit of claim 4, wherein the second current mirror unit comprises a fifth MOS transistor and a sixth MOS transistor, a first end of the fifth MOS transistor is connected to a control end of the fifth MOS transistor and the sampling unit to receive the sampling current, a control end of the sixth MOS transistor is connected to a control end of the fifth MOS transistor, a first end of the sixth MOS transistor is connected to the first current mirror unit and the control unit, and a second end of the fifth MOS transistor and a second end of the sixth MOS transistor are connected to a ground voltage.
7. The LDO circuit of claim 5, wherein the ratio of the width to length ratio of the third MOS transistor to the output transistor is k2:1.
8. the LDO circuit of claim 2, wherein a ratio of the width to length ratio of the first MOS transistor to the output transistor is 1: k3.
9. the LDO circuit of claim 1, wherein the control unit comprises a switching tube, a first end of the switching tube is connected to a control end of the power tube, a second end of the switching tube is connected to a ground voltage, and the control end of the switching tube is connected to the first current mirror unit and the current sampling mirror unit.
10. The LDO circuit of claim 1, wherein the voltage divider unit comprises a first resistor and a second resistor, the first end of the first resistor being coupled to the first end of the output tube to form an output terminal of the LDO circuit, the second end of the first resistor being coupled to the first end of the second resistor to output the divided voltage signal, the second end of the second resistor being coupled to the ground voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311444542.3A CN117492508A (en) | 2023-11-01 | 2023-11-01 | LDO circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311444542.3A CN117492508A (en) | 2023-11-01 | 2023-11-01 | LDO circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117492508A true CN117492508A (en) | 2024-02-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311444542.3A Pending CN117492508A (en) | 2023-11-01 | 2023-11-01 | LDO circuit |
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|---|---|
| CN (1) | CN117492508A (en) |
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- 2023-11-01 CN CN202311444542.3A patent/CN117492508A/en active Pending
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