JP2001118025A - Threshold detecting circuit, thershold adjusting circuit, and squaring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a threshold detecting circuit and a threshold adjusting circuit which is suitable to a squaring circuit which can obtain a high-precision multiplication result with a relatively low soursce voltage and the squaring circuit. SOLUTION: A 1st current corresponding to a reference voltage Vref is supplied to an NMOS transistor(TR) 113, a 2nd current which is higher than the 1st current by a level allowed as a detection error is supplied to a PMOS TR 114, and a current which is the difference between the 1st and 2nd currents is supplied to an NMOS TR 115, and the threshold of the NMOS TR 115 is detected and reference bias voltages of the NMOS TRs 115 and 132 are adjusted by an operational amplifier 121 so that the threshold becomes equal to the reference voltage Vref, thus obtaining the voltage which is the square of an input voltage Vin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a threshold detection circuit, a threshold adjustment circuit, and a squaring circuit.

[0002]

2. Description of the Related Art Conventionally, there has been known a multiplication circuit for inputting an analog signal and multiplying the input analog signal.

FIG. 4 is a circuit diagram of a conventional multiplication circuit.

[0004] A multiplication circuit 400 shown in FIG. 4 has an input terminal 411 to which an analog voltage vd on which a DC voltage Vd is superimposed is input, and two NMOS transistors 412 and 413 each having one end commonly connected to the input terminal 411. And input terminals 414, 415 connected to the gates of the NMOS transistors 412, 413. An analog voltage vg on which the DC voltage Vg is superimposed is input to the input terminal 414, and the DC voltage Vg is input to the input terminal 415.

The multiplying circuit 400 has current-voltage converting circuits 416 and 417 each having one input connected to the other end of each of the NMOS transistors 412 and 413, and the other of the current-voltage converting circuits 416 and 417. Is provided with an input terminal 418 that is commonly connected to the input side. The current-voltage conversion circuit 416 includes an operational amplification circuit 416a and a resistance element 416b.
7 comprises an operational amplifier circuit 417a and a resistance element 417b. The input terminal 418 has a DC voltage Vd
Is entered.

Further, the multiplying circuit 400 is provided with a subtraction circuit 419 whose input side is connected to the output side of the current-voltage conversion circuits 416 and 417, and an output terminal 420 connected to the output side of the subtraction circuit 419. I have.

In the multiplication circuit 400 configured as described above, when the analog voltage vg has a positive voltage value, the currents I ₁ and I ₂ flowing in the saturation region of the NMOS transistors 412 and 413 are expressed as follows.

I ₁ = β ₁ ｛(Vg + vg−Vd−Vt ₁ ) v
^{d + vd 2/2} I} 2 = β 2 {(Vg-Vd-Vt 2) vd + vd 2/2} where, β _1, β ₂ are constants determined by the process (channel width W, the channel length L and the carrier movement, etc.) , Vt ₁ and Vt ₂ are threshold values of the NMOS transistors 412 and 413.

Here, the current-voltage conversion circuits 416, 417
Constituting the resistance element 416b, when the 1Ω the value of 417b, voltages v1, v2 output from the current-voltage conversion circuit 416 and 417 becomes _{v1 = Vd-I 1 v2 =} Vd-I 2. Therefore, assuming that the gain of the subtraction circuit 419 is 1, β ₁ = β ₂ , and Vt ₁ = Vt ₂ , the voltage v0 at the output terminal 420 is v0 = β ₁ vgvd. Thus, the multiplication circuit 400 shown in FIG.
Then, the multiplication of the input analog voltage vg and analog voltage vd is performed. Here, when the values of the input analog voltage vg and analog voltage vd are the same, a squaring circuit is realized.

When the analog voltage vg is a negative voltage value, the multiplication of the input analog voltage vg and the analog voltage vd is performed in the same manner as in the case where the analog voltage vg is a positive voltage value. .

However, it is difficult to manufacture the two NMOS transistors 412 and 413 constituting the multiplying circuit 400 with the same characteristics such as transistor size representing the channel width W and channel length L and the threshold value. For this reason, β ₁ = β ₂ and Vt ₁ = Vt ₂ are not necessarily satisfied, and there is a problem that it is difficult to perform multiplication with high accuracy.

Therefore, Japanese Patent Publication No. 63-47474 proposes a multiplication circuit for multiplying an analog signal using one NMOS transistor.

FIG. 5 is a circuit diagram of a multiplication circuit proposed in Japanese Patent Publication No. 63-47474.

The same components as those of the multiplying circuit 400 shown in FIG. 4 are denoted by the same reference numerals.

The multiplication circuit 500 shown in FIG. 5 has the above-mentioned input terminals 411 and 418 and the NMOS transistor 41
2, a current-voltage conversion circuit 416, a subtraction circuit 419, and an output terminal 420, one end of which is commonly connected to the gate of the NMOS transistor 412, and the other end of which is connected to the DC voltage Vg.
Terminal 4 to which analog voltage vg on which is superimposed is input
14. Switches 511 and 512 connected to an input terminal 415 to which the DC voltage Vg is input are provided.

The multiplying circuit 500 has switches 513 and 514 each having one end commonly connected to the output side of the current-voltage conversion circuit 416, and an input side connected to the other ends of the switches 513 and 514 and an output side subtracting. Sample and hold circuits 515 and 516 connected to the input side of the circuit 419
Is provided.

In the multiplication circuit 500, first, the switches 511 and 512 are turned on and off by switch switching means (not shown), and the switches 513 and
514 is also turned on and off. Then NMO
Current-voltage conversion circuit 41 via S-transistor 412
The current I ₁ flows through the current 6, and the voltage v 1 obtained by current / voltage conversion by the current / voltage conversion circuit 416 is output. This voltage v
1 is a sample-and-hold circuit 5 via a switch 513.
15 is held. Next, the switches 511 and 512 are switched between the off state and the on state, and the switches 513 and 514 are also switched between the off state and the on state, so that the current I ₂ flows to the current-voltage conversion circuit 416 via the NMOS transistor 412. The current-voltage conversion circuit 4
16 outputs a voltage v2. This voltage v2 is held in the sample and hold circuit 516 via the switch 514. These voltages v1 and v2 are input to the subtraction circuit 419, and the voltage v0 (β ₁ vg) is output from the subtraction circuit 419 to the output terminal 420 in the same manner as described with reference to FIG.
vd) is output. This voltage v0 is one NMOS
Since this is obtained using the transistor 412,
The multiplication result can be obtained with higher accuracy than when two MOS transistors having different sizes and characteristics are used.

[0018]

However, in the multiplication circuit 500 described above, in order to improve the accuracy of the multiplication result, the NMO
There is a problem that it is necessary to secure a wide unsaturated region of the S transistor 412, and therefore a high power supply voltage is required.

In Japanese Patent Publication No. 50633/1992,
A multiplication circuit using a depletion-type MOS transistor has been proposed in order to avoid harmonic distortion generated due to the enhancement-type MOS transistor and the complexity of the configuration due to the application of a bias voltage. However, this multiplying circuit has a problem that many steps are required for manufacturing a depletion type MOS transistor.

Further, Japanese Patent Publication No. 1-59622 and Japanese Patent Publication No. 2-52307 disclose a resistance element which requires a relatively large area and power consumption for integration.
A multiplication circuit using a capacitor element has been proposed. However, in general, there is a problem that the capacitance accuracy of the capacitor element is low, and a special process is required to increase the capacitance accuracy of the capacitor element.

Further, Japanese Patent Publication No. 5-42033 and US Pat.
MO (Patent No. 4585961)
A squaring circuit using a saturation region of an S transistor has been proposed. However, in the technology proposed in these publications,
In the input stage, since three MOS transistors are connected in series between the power supply voltage and the ground,
There is a problem that a relatively high power supply voltage is required.

In view of the above circumstances, it is an object of the present invention to provide a threshold detecting circuit, a threshold adjusting circuit, and a square adjusting circuit suitable for a square circuit capable of obtaining a highly accurate multiplication result with a relatively low power supply voltage. With the goal.

[0023]

According to the present invention, there is provided a threshold value detecting circuit comprising: (1_1) a first constant current circuit for flowing a first current corresponding to a predetermined reference voltage; A second constant current circuit connected in series to the first constant current circuit and flowing a second current having a current value higher than the first current by an allowable level as a detection error in accordance with the reference voltage; 1_3) A first MOS transistor for threshold value detection, which is diode-connected in parallel with the first constant current circuit and flows a current having a difference between the second current and the first current, is provided. It is characterized by the following.

According to another aspect of the present invention, there is provided a threshold adjustment circuit comprising: (2_1) a first constant current circuit for flowing a first current according to a predetermined reference voltage; and (2_2) a first constant current circuit. A second constant current circuit connected in series with the current circuit and flowing a second current having a current value higher than the first current by an allowable level as a detection error in accordance with the reference voltage, (2_3) the second constant current circuit; A first MOS transistor which is diode-connected in parallel with the first constant current circuit and flows a current having a difference between the second current and the first current; (2_4) the first MOS transistor and the second MOS transistor; A substrate bias voltage adjusting circuit for adjusting a substrate bias voltage of the first MOS transistor so that a voltage of a node connected to the constant current circuit becomes equal to the reference voltage.

Further, the squaring circuit of the present invention that achieves the above object includes: (3_1) a first constant current circuit for flowing a first current corresponding to a predetermined reference voltage; and (3_2) a first constant current circuit. A second constant current circuit connected in series and flowing a second current having a current value higher by a level allowable as a detection error than the first current in accordance with the reference voltage, (3_3) the first constant current circuit; A first MOS transistor which is diode-connected in parallel with the current circuit and flows a current having a difference between the second current and the first current; (3_4) the first constant current circuit and the second constant current circuit And a substrate bias voltage adjusting circuit for adjusting the substrate bias voltage of the first MOS transistor so that the voltage of the node connected to the first MOS transistor becomes equal to the reference voltage. Flow Flip current, characterized by comprising a second MOS transistor which is adjusted to the same substrate bias voltage and the substrate bias voltage of the first MOS transistor by the substrate bias voltage adjustment circuit.

The present invention focuses on the current characteristics of a MOS transistor in the saturation region. For example, in the case of an NMOS transistor, the current I in the saturation region is I = β / 2 (Vgs−Vt). ² ... (A). Where β is a constant determined by the process, Vgs is the gate-source voltage of the NMOS transistor, and Vt is the threshold value of the NMOS transistor.
Here, when Vt is obtained by passing a small current through the NMOS transistor, and the obtained Vt is adjusted to, for example, 0, the above equation (A) becomes I∝Vgs ² ... (B). If such a current I is converted into a voltage, Vgs
A voltage proportional to ² is obtained.

The threshold detection circuit according to the present invention comprises a first MO
The configuration is such that a current of a difference between the second current and the first current as a level allowable as a detection error is supplied to the S transistor, and the current of the first MOS transistor is reduced by sufficiently reducing the difference current. A threshold can be determined.

Further, the threshold value adjusting circuit according to the present invention is arranged such that the voltage of the node connected to the first constant current circuit and the second constant current circuit in the substrate bias voltage adjusting circuit becomes equal to the reference voltage. Since the substrate bias voltage of the first MOS transistor is adjusted, the threshold value of the first MOS transistor can be adjusted by the reference voltage.

Further, in the squaring circuit of the present invention, the substrate bias voltage is adjusted to the same substrate bias voltage as the substrate bias voltage of the first MOS transistor by the substrate bias voltage adjusting circuit.
Since an input voltage is input to the gate of the second MOS transistor and a current corresponding to the input voltage flows therethrough, if the second MOS transistor is, for example, an NMOS transistor, its NM
The current I in the saturation region of the OS transistor can be expressed as I = β / 2 (Vin−Vref) ² (C). Here, Vin is an input voltage that is input to the gate of the NMOS transistor and replaces the gate-source voltage Vgs in the above-described equation (A). Vref is NMO in the above-described equation (A).
This is a reference voltage replacing the threshold value Vt of the S transistor. Here, if Vref is adjusted to, for example, 0, the above equation becomes I∝Vin ² . By converting the current I into a voltage, a voltage proportional to the square of the input voltage Vin is obtained.

[0030]

Embodiments of the present invention will be described below.

FIG. 1 is a circuit diagram of a threshold detection circuit according to a first embodiment of the present invention.

The threshold detection circuit 110 shown in FIG.
A PMOS transistor 111 and an NMOS transistor 112 connected in series between the power supply voltage Vdd and the ground GND, and an input terminal 116 connected to the gate of the NMOS transistor 112 and receiving a predetermined reference voltage Vref are provided.

The threshold detecting circuit 110 includes:
The gate is connected to the input terminal 116 and the input terminal 116
Current I ₁ according to the reference voltage Vref input to
NMOS transistor 113 (the first transistor according to the present invention)
).

Further, the threshold value detection circuit 110
The MOS transistor 113 is connected in series with the reference voltage V
Depending on the ref, the first current I ₁ level amount corresponding current values acceptable as detection error compared to shed high second current I ₂ PMOS transistor 114 (corresponding to a second constant current circuit according to this invention) Is provided. The gate of the PMOS transistor 114 is connected to the PMOS transistor 1
11 and the PMOS transistors 111 and N
It is connected to a connection point with the MOS transistor 112.

The threshold detection circuit 110 includes NM
The second current I ₂ , which is diode-connected in parallel with the OS transistor 113 and connected to the output terminal 117,
An NMOS transistor 115 (equivalent to the first MOS transistor according to the present invention) for detecting a threshold value, through which a current I _ds of a difference between the current and the first current I ₁ flows. Here, the transistor size ratio of the PMOS transistor 111, the NMOS transistors 112, 113 and 115, and the PMOS transistor 114 is 1: 1 + α.
(Α is about 1 to 10%).

The threshold value detecting circuit 1 configured as described above
A predetermined reference voltage Vref is input to ten input terminals 116. Then, the NMOS transistors 112 and 11
3 is turned on. Since the NMOS transistor 112 is turned on, the PMOS transistors 111, 11
4, the gate potential of the PMOS transistor 11 decreases.
1 and 114 are turned on, and a current corresponding to the size ratio of 1: 1 + α flows through the PMOS transistors 111 and 114. That is, the power supply voltage Vdd → the PMOS transistor 111 → N
A current I ₃ corresponding to a size ratio of 1 flows through a path from the MOS transistor 112 to the ground GND. Meanwhile, PMO
The S transistor 114 includes a current I ₁ flowing through the NMOS transistor 113 turned on by the reference voltage Vref input to the gate, and an NMOS transistor 115 connected in parallel to the NMOS transistor 113.
The current I ₂ flows in accordance with the size ratio (1 + α) which is the sum of the current I _ds flowing through the current I _ds .

Here, the output terminal 117 has its NMO due to the current I _ds flowing through the NMOS transistor 115.
A voltage Vgs between the gate and source in the saturation region of S transistor 115 is output. This voltage Vgs can be expressed as _{Vgs = Vt + (2I ds /} β) 1/2. Here, β is a constant determined by the process, and Vt is the threshold value of the NMOS transistor 115. Here, the current I _ds is a sufficiently small current of a level allowable as a detection error, and therefore, the voltage Vgs becomes Vgs ≒ Vt. Thus, the NMOS transistor 115
Is detected. Next, the threshold Vt
, A squaring circuit for squaring and outputting an input analog voltage will be described.

FIG. 2 is a circuit diagram of the squaring circuit according to the first embodiment of the present invention.

The squaring circuit 100 shown in FIG. 2 includes a threshold detecting circuit 110 shown in FIG.
10 and NMOS transistor 113 and PMOS
An operational amplifier 121 for adjusting the substrate bias voltage of the NMOS transistor 115 so that the voltage of the node connected to the transistor 114 becomes equal to the reference voltage Vref.
(Corresponding to the substrate bias voltage adjusting circuit according to the present invention). Note that a threshold adjustment circuit 120 is composed of the threshold detection circuit 110 and the operational amplifier 121.

The squaring circuit 100 has a reference voltage Vr
input terminal 1 to which an input voltage vin higher than ef is input
31 and a gate connected to its input terminal 131 to flow a current according to the input voltage vin input to the gate;
The NMOS transistor 132 (the second MO of the present invention) adjusted to the same substrate bias voltage as the substrate bias voltage of the NMOS transistor 115 by the operational amplifier 121.
S transistor).

Furthermore, the power supply voltage V
PM disposed between dd and the NMOS transistor 132
An OS transistor 133, a PMOS transistor 134 having a gate connected to the gate of the PMOS transistor 133 and connected to a connection point between the NMOS transistor 132 and the PMOS transistor 133;
A resistance element 135 disposed between the MOS transistor 134 and the ground GND;
Terminal 13 connected to the connection point between
6 are provided.

The reference voltage Vref and the input voltage v are applied to the input terminals 116 and 131 of the squaring circuit 100 thus configured.
in is input. Then, the voltage (threshold V) at the node to which the NMOS transistor 113 and the PMOS transistor 114 are connected is input to the positive-phase input of the operational amplifier 121.
t) is input, and the reference voltage Vref is input to the negative-phase input. In the operational amplifier 121, an adjustment voltage is output from the operational amplifier 121 to the back gate of the NMOS transistor 115 so that the voltage of the node becomes equal to the reference voltage Vref, and the substrate bias voltage of the NMOS transistor 115 is adjusted. .

The input voltage vin is input to the gate of the NMOS transistor 132.
The operational amplifier 12 is also provided on the back gate of the transistor 132.
The adjustment voltage from 1 is input, whereby the NMOS transistor 132 is turned on. Then, the potential at the connection point between the PMOS transistor 133 and the NMOS transistor 132 decreases, and the PMOS transistor 133 turns on, and the power supply voltage Vdd → the PMOS transistor 1
33 → NMOS transistor 132 → Ground GND
The current flows through the path. Also, the PMOS transistor 1
34 is also turned on, and a current flows through the path of the power supply voltage Vdd → the PMOS transistor 134 → the resistance element 135 → the ground GND. Here, the PMOS transistor 1
Assuming that the current flowing through I is I, this current I is expressed as I = β / 2 (vin−Vref) ² (1). Here, assuming that the value R of the resistance element 135 is 2 / β, the voltage vo at the output terminal 136 is expressed as v0 = (vin−Vref) ² (2). Further, if Vref = 0, equation (2) is represented as follows: v0 = (vin) ² ... (3) Thus, the voltage v0 obtained by squaring the input voltage vin is obtained.

As described above, the squaring circuit 1 of the present embodiment
At 00, the operational amplifier 121 adjusts the threshold voltage Vt in the saturation region of the NMOS transistor 115 to be equal to the reference voltage Vref to the substrate bias voltage of the NMOS transistor 115, and the input voltage vin.
Is also adjusted to its substrate bias voltage, and is expressed by the above equation (3).
Since a voltage v0 obtained by squaring the input voltage vin is obtained, a conventional technique for expanding a non-saturation region by applying a high power supply voltage in order to improve the accuracy of the multiplication result, and a power supply voltage and a ground in an input stage. Compared to the technique in which three MOS transistors are connected in series, a highly accurate multiplication result can be obtained with a relatively low power supply voltage.

FIG. 3 is a circuit diagram of a squaring circuit according to a second embodiment of the present invention.

In the squaring circuit 100 of the first embodiment, the example using the threshold value Vt of the NMOS transistor has been described. In the present embodiment, the example using the threshold value Vt of the PMOS transistor will be described. A threshold detection circuit 210 included in the squaring circuit 200 shown in FIG. 3 has a PMO connected in series between the power supply voltage Vdd and the ground GND.
S transistor 212 and NMOS transistor 21
1 and an input terminal 2 connected to the gate of the PMOS transistor 212 and receiving a predetermined reference voltage Vref
16 are provided. The gate is connected to the input terminal 216.
And the reference voltage V input to its input terminal 216
A PMOS transistor 213 (corresponding to a first constant current circuit according to the present invention) for flowing a _first current I1 according to ref is provided. Further, the PMOS transistor 2
13 in series with the first reference voltage Vref according to the reference voltage Vref.
The current I ₁ level amount corresponding current values acceptable as detection error compared to shed high second current I ₂ NMOS transistor 214 (corresponding to a second constant current circuit according to the present invention) is provided. The gate of the NMOS transistor 214 is connected to the gate of the NMOS transistor 211 and the PMOS transistor 212 and the NMOS transistor 2.
11 connection points. Further, in parallel to the diode-connected PMOS transistor 213, a second current I ₂ and flow difference of the current I _sd between the first current I _1, the PMOS transistor 215 (the present invention for threshold detection target (Corresponding to the first MOS transistor referred to above). Here, the PMOS transistors 212, 213,
215, the transistor size ratio between the NMOS transistor 211 and the NMOS transistor 214 is 1: 1+
α (α is about 1 to 10%).

Further, the squaring circuit 200 has a PMOS transistor 213 and a N
An operational amplifier 221 (corresponding to a substrate bias voltage adjusting circuit according to the present invention) that adjusts the substrate bias voltage of the PMOS transistor 215 so that the voltage of the node connected to the MOS transistor 214 becomes equal to the reference voltage Vref is provided. . Note that a threshold value adjusting circuit 220 is configured by the threshold value detecting circuit 210 and the operational amplifier 221.

Further, the reference voltage V
An input terminal 231 to which an input voltage vin lower than ref is input, and a gate connected to the input terminal 231 to flow a current corresponding to the input voltage vin input to the gate.
5, the PMOS transistor 232 (the second MOS transistor according to the present invention) adjusted to the same substrate bias voltage as the substrate bias voltage of the PMOS transistor 2
An NMOS transistor 233 is provided between the gate 32 and the ground GND.

In the squaring circuit 200, the gate is NM.
Connected to the gate of the OS transistor 233, the PMOS transistor 232 and the NMOS transistor 2
NMOS transistor 23 connected to the connection point 33
8, the NMOS transistor 238 and the power supply voltage Vd
There is provided a PMOS transistor 237 arranged between d. Further, the gate is a PMOS transistor 23
7, a PMOS transistor 234 connected to a connection point between the PMOS transistor 237 and the NMOS transistor 238, a resistance element 235 disposed between the PMOS transistor 234 and the ground GND, and a PMOS transistor 234 and a resistance element. 2
And an output terminal 236 connected to a connection point with the output terminal 235.

The input and output of the squaring circuit 200 thus configured
The reference voltage Vref and the input voltage v
in is input. Then, the PMOS transistor 21
2, 213 are turned on. PMOS transistor 2
12 is turned on, the NMOS transistor 21
The gate potentials of the transistors 1 and 214 rise and the NMOS transistors
The transistors 211 and 214 are turned on, and the NMOS transistors
The current I_ThreeFlows. On the other hand, NMOS transistors
The reference voltage Vre input to the gate is
PMOS transistor 213 turned on by f
Current I flowing through ₁And its PMOS transistor 213
To the PMOS transistor 215 connected in parallel to
Current I_sdCurrent I which is the sum of_TwoFlows. Where
Style I_sdIs small enough to be acceptable as a detection error.
Therefore, the threshold current shown in FIG.
As in the case of the output circuit 110, the PMOS transistor
The threshold value Vt of the data 215 is detected.

The threshold value Vt is input to the positive phase input of the operational amplifier 221. Further, a reference voltage Vref is input to an opposite-phase input of the operational amplifier 221. In the operational amplifier 221, an adjustment voltage is input from the operational amplifier 221 to the back gate of the PMOS transistor 215 so that the threshold value Vt becomes equal to the reference voltage Vref.
Thereby, the substrate bias voltage of the PMOS transistor 215 is adjusted.

The input voltage vin is input to the gate of the PMOS transistor 232,
The operational amplifier 22 is connected to the back gate of the transistor 232.
The adjustment voltage from 1 is input, whereby the PMOS transistor 232 is turned on. Then, the potential of the connection point between the NMOS transistors 233 and 238 rises, and the NMOS transistors 233 and 238 are turned on, and accordingly, the PMOS transistors 237 and 234
Is also turned on, so that the power supply voltage Vdd → the PMOS transistor 234 → the resistance element 235 → the ground GND
The current I flows through the path. As in the case of the squaring circuit 100 shown in FIG. 2, the voltage vo = (vin) ² based on the current I, that is, the voltage v0 obtained by squaring the input voltage vin is output to the output terminal 236. You.

As described above, the squaring circuit 200 of the second embodiment
Then, the threshold voltage Vt in the saturation region of the PMOS transistor 215 is adjusted to the substrate bias voltage of the PMOS transistor 215 by the operational amplifier 221 so that the threshold voltage Vt becomes equal to the reference voltage Vref. Since the voltage v0 is obtained by squaring the input voltage vin by adjusting to the substrate bias voltage, a highly accurate multiplication result can also be obtained with a relatively low power supply voltage.

[0054]

As described above, according to the present invention,
A threshold detection circuit, a threshold adjustment circuit, and a threshold circuit suitable for a squaring circuit that can obtain a highly accurate multiplication result at a relatively low power supply voltage.
And its squaring circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a threshold detection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a squaring circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a squaring circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional multiplication circuit.

FIG. 5 is a circuit diagram of a multiplication circuit proposed in Japanese Patent Publication No. 63-46474.

[Explanation of symbols]

100, 200 Square circuit 110, 210 Threshold value detection circuit 111, 114, 133, 134, 212, 213, 2
15, 232, 234, 237 PMOS transistors 112, 113, 115, 132, 211, 214, 2
33,238 NMOS transistor 116,131,216,231 Input terminal 117,136,236 Output terminal 120,220 Threshold adjustment circuit 121,221 Operational amplifier 135,235 Resistance element

Claims (3)

[Claims] A first constant current circuit for supplying a first current according to a predetermined reference voltage; a first constant current circuit connected in series to the first constant current circuit and the first current according to the reference voltage; A second constant current circuit for flowing a second current having a current value higher by a level allowable as a detection error than that of the second constant current circuit, and a diode connected in parallel to the first constant current circuit; A current of a difference from the current of 1
A threshold value detection circuit comprising: a first MOS transistor for detecting a threshold value. 2. A first constant current circuit for flowing a first current according to a predetermined reference voltage, and the first current connected in series to the first constant current circuit and according to the reference voltage. A second constant current circuit for flowing a second current having a current value higher by a level allowable as a detection error than that of the second constant current circuit, and a diode connected in parallel to the first constant current circuit; A first MOS transistor through which a current different from the first current flows, and a voltage at a node connected to the first constant current circuit and the second constant current circuit being equal to the reference voltage. A threshold adjustment circuit for adjusting a substrate bias voltage of the first MOS transistor. 3. A first constant current circuit for flowing a first current according to a predetermined reference voltage, and the first current connected in series to the first constant current circuit and according to the reference voltage. A second constant current circuit for flowing a second current having a current value higher by a level allowable as a detection error than that of the second constant current circuit, and a diode connected in parallel to the first constant current circuit; A first MOS transistor through which a current different from the first current flows, and a voltage at a node connected to the first constant current circuit and the second constant current circuit being equal to the reference voltage. A substrate bias voltage adjusting circuit for adjusting a substrate bias voltage of the first MOS transistor; an input voltage being input to a gate and flowing a current corresponding to the input voltage; Base Squaring circuit which is characterized in that a second MOS transistor which is adjusted to the same substrate bias voltage and the bias voltage.