TW434992B - Current source apparatus with temperature compensation function - Google Patents

Current source apparatus with temperature compensation function Download PDF

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TW434992B
TW434992B TW88112040A TW88112040A TW434992B TW 434992 B TW434992 B TW 434992B TW 88112040 A TW88112040 A TW 88112040A TW 88112040 A TW88112040 A TW 88112040A TW 434992 B TW434992 B TW 434992B
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current
transistor
current source
source unit
item
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Chinese (zh)
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Jaw-Juinn Horng
Hsueh-Kun Liao
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Ind Tech Res Inst
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Abstract

A kind of current source apparatus having temperature compensation function can be used for any fabricating process that includes CMOS, BJT, HBT, GaAs, ..., and so on. By using simple devices, such as Schottky diode, resistor, and depletion type FET transistor, to match the special symmetrical-circuit structure, the compensation of temperature variation can be performed in order to decrease the influence of temperature on current such that the product yield of total fabricating process is improved.

Description

4349924. 五、發明說明(1) 本發明係有關於 具有溫度補償功能之電流源裝置。 'Λ ;89Ji./t4' :!: 種電流源1^ 一置,特別是有關於一種 第1圖顯示一具有溫度正變化之電流源。第1圖上端兩 個PMOS電晶體(PI、P2)構成一電流源,其左右兩邊所輸出 之電流相等(1,12),故連帶使得NMOS電晶體Q1和Q2之閘極 -源極間電壓(Vgs )相等,如此則A點電壓等於B點電壓。針 對電流部分對第1圖之線路作分析,可得下列之式子β ¢1) I〆=VeB4 - Veb3 IL ξ Is3 exp(VEB3/VT) (2) I2 s Is4 exp(VEB4/VT) (3) llR Ξ VT^n(I2/Is4) -νΊίη{ΙλΙ1ί2) 且 I[ = :I2 .,. ^ ^ VT/R ^n(N) (4) 其中,N表示BJT電晶體Q3和Q4之尺寸比值。 由上述式子(4 )可知,第1圖電流源之電流值I 1和I 2僅 與B J T電晶體Q1和Q 2之尺寸大比值和電阻值R相關;由於VT 之值隨溫度昇高而增加,所以電流值I丨和12亦隨溫度之昇 高而增加,故而呈現正變化之關係,此即稱為PTAT電流 源。將此電流源經由re f_C以電流鏡之方式供給至工作電 路的話,則整個工作電路即呈現溫度正變化之情形。 以上述之製程而言,需提供PMOS、NMOS、BJT電晶 體、電阻器等之元件。然而在GaAs製程中,由於成本和實 作上之考量,一般僅只提供若干基本之元件,例如空乏型_4349924. V. Description of the invention (1) The present invention relates to a current source device having a temperature compensation function. 'Λ; 89Ji./t4':!: A current source 1 ^ is set, especially for a type. Figure 1 shows a current source with a positive temperature change. The two PMOS transistors (PI, P2) at the top of Figure 1 constitute a current source, and the currents on the left and right sides are equal (1, 12). Therefore, the gate-source voltage of the NMOS transistors Q1 and Q2 is jointly (Vgs) are equal, so the voltage at point A is equal to the voltage at point B. For the analysis of the line in Figure 1 for the current part, we can get the following formula β ¢ 1) I〆 = VeB4-Veb3 IL ξ Is3 exp (VEB3 / VT) (2) I2 s Is4 exp (VEB4 / VT) ( 3) llR Ξ VT ^ n (I2 / Is4) -νΊίη {ΙλΙ1ί2) and I [=: I2.,. ^ VT / R ^ n (N) (4) where N is the BJT transistor Q3 and Q4 Size ratio. From the above formula (4), it can be known that the current values I 1 and I 2 of the current source in FIG. 1 are only related to the size ratio of the BJT transistors Q1 and Q 2 and the resistance value R; because the value of VT increases with temperature Increased, so the current values I 丨 and 12 also increase with the increase in temperature, so they show a positive change, which is called the PTAT current source. If this current source is supplied to the working circuit in the form of a current mirror via re f_C, the entire working circuit will show a positive temperature change. In terms of the above process, components such as PMOS, NMOS, BJT transistors and resistors need to be provided. However, in the GaAs process, due to cost and implementation considerations, generally only only a few basic components are provided, such as empty type_

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资正 4 3 ^.9 9 2^ 五、發明說明(2) I ¢1 ^t:| (depletion type) MOS ί^ΤΤ"!;晶體、Schottky 二極體、電 阻器,而且空之型(depletion type) M0SFET電晶體僅提 供N型,所以第1圖之架構電流源,可能無法由GaAs製程來 實施。此外,第1圖架構之電流源,係使用兩個BJT電晶體 (Q3、Q4)之尺寸比值,來調整電流I和12之大小。此一調 整方式並不通用在GaAs製程,又BJT電晶體相當耗費電路 之面積,連帶使得設計之效率降低。 有鑑於此,本發明之目的係為了改善上述問題而提出 一種具有溫度補償功能之電流源裝置,其可適用於任何製 程,包括CMOS、B JT、HBT、GaAs …等,利用簡單之元件 如Schottky 二極體、電阻器、和電晶體,配合特殊之對 稱電路架構,使其能夠對溫度變化進行補償,以降低溫度 對電流之影響,進而改善整體製程之良品率,以及電路之 面積。 為達到上述目的,本發明提出之具有溫度補償功能之 電流源裝置,其架構包括下列單元。 一第一電流源單元,提供一具有定電流值之第一電 流 一第二電流源單元,提供一第二電流,其電流值隨溫 度昇高而增加。其中,上述第二電流源單元,至少包括: 一第一電晶體、一第 上述第二電流;一第 二極體,構成一第一電流路徑流通 電晶體、一第二二極體,構成一第 二電流路徑流通上述第二電流;上述第二電流之值取決於 上述第一二極體和第二二極體兩者間之尺寸比例。Zi Zheng 4 3 ^ .9 9 2 ^ V. Description of the invention (2) I ¢ 1 ^ t: | (depletion type) MOS ί ^ ΤΤ "!; Crystal, Schottky diode, resistor, and empty type ( The depletion type) M0SFET transistor only provides N type, so the current source of the architecture shown in Figure 1 may not be implemented by the GaAs process. In addition, the current source shown in Figure 1 uses the size ratio of two BJT transistors (Q3, Q4) to adjust the currents I and 12. This adjustment method is not commonly used in the GaAs process, and the BJT transistor consumes a considerable amount of circuit area, which also reduces the design efficiency. In view of this, the object of the present invention is to propose a current source device with a temperature compensation function in order to improve the above problems, which can be applied to any process, including CMOS, B JT, HBT, GaAs, etc., using simple components such as Schottky Diodes, resistors, and transistors, combined with a special symmetrical circuit architecture, make it possible to compensate for temperature changes to reduce the effect of temperature on current, thereby improving the yield of the overall process and the area of the circuit. In order to achieve the above-mentioned object, the structure of the current source device with temperature compensation function provided by the present invention includes the following units. A first current source unit provides a first current with a constant current value and a second current source unit provides a second current, the current value of which increases with increasing temperature. The second current source unit includes at least: a first transistor, a first second current; a second electrode, which constitutes a first current path through the transistor, and a second diode, which constitutes a The second current path passes the second current; the value of the second current depends on the size ratio between the first diode and the second diode.

43Λ9 92;4_ 五、發明說明(3) ' 一第三電流源單元,提供一第三電流,其值為上述第 —電流和第二電流兩者之差值;其中,上述第一電流源單 元串接上述第二電流源單元,而上述第三電源單元並連上 述第三電源單元。 圖式之簡單說明: 為讓本發明之上述目的、特徵、和優點能更明顯易 懂,下文特舉一較佳實施例,並配合所附圖式,做詳細說 明如下: 第1圖顯示一具有溫度正變化之電流源; 第2圖顯示一可能之GsAs製程之電流源; 第3圖顯示二極體和GaAs電晶體負載線之電流-電壓對 應圖; 第4圖顯示使用電流鏡(current mirror)之方式,將 電流耦合給複數級電路使用之架構示意圖; 第5圖顯示依據GaAs製程、搭配隨溫度呈正變化之 PTAT電流源而得之電流源示意圖; 第6圖顯示本發明一實施例之電路架構示意圖; 第7圖顯示本發明一實施例之詳細電路圖; 第8圖顯示將本發明實施例裝置產生之電流予以耦合 輸出之應用圖; 第9圖顯示將第8圖之E和F部分合併成一個電流源之示 意圖; 第10圖顯示應用本發明架構,在只有NM0S與二極體的 情形下,所設計的之不隨溫度變化之電壓源電路;43Λ9 92; 4_ V. Description of the invention (3) 'A third current source unit provides a third current whose value is the difference between the first current and the second current; wherein the first current source unit The second current source unit is connected in series, and the third power source unit is connected in parallel to the third power source unit. Brief description of the drawings: In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: FIG. 1 shows a Current source with positive temperature change; Figure 2 shows a current source for a possible GsAs process; Figure 3 shows the current-voltage map of the diode and the load line of the GaAs transistor; Figure 4 shows the use of a current mirror (current Mirror), a schematic diagram of the architecture for coupling current to a complex stage circuit; Figure 5 shows a schematic diagram of a current source based on a GaAs process and a PTAT current source that changes positively with temperature; Figure 6 shows an embodiment of the present invention Schematic diagram of the circuit architecture; FIG. 7 shows a detailed circuit diagram of an embodiment of the present invention; FIG. 8 shows an application diagram for coupling output of the current generated by the device of the embodiment of the present invention; and FIG. 9 shows the E and F of FIG. 8 Partially combined into a current source; Figure 10 shows the application of the structure of the present invention, in the case of only NMOS and diode, a voltage source that does not change with temperature Road;

434B924 五'發明說明(4) ; 第1 1圖係為第1 0圖中的BB部分電路,其電流對溫度之 實驗模擬數據; 第1 2圖係為第1 0圖中的BB部分電路,其電流對電壓 Vcc之實驗數據;其中,當二極體比值為2:1時,電流對電 壓關係為A曲線,當二極體比值為8 : 1時,電流對電壓關係 為B曲線; 第1 3圖則顯示一般電流源,其電流對溫度變化之實驗 數據圖;以及 第14圖顯示將第10圖中之BB部分與第1 3圖電路合併成 一個電流源時(如第9圖中之E、F部分),其電流對溫度變 化之實驗數據圖。 符號說明:434B924 Five 'invention description (4); Figure 11 is the experimental simulation data of the BB circuit in Figure 10 and its current vs. temperature; Figure 12 is the BB circuit in Figure 10, The experimental data of its current vs. voltage Vcc; among them, when the diode ratio is 2: 1, the current versus voltage relationship is A curve, and when the diode ratio is 8: 1, the current versus voltage relationship is B curve; Figure 13 shows the experimental data graph of the general current source and its current versus temperature change; and Figure 14 shows when the BB part in Figure 10 and the circuit in Figure 13 are combined into a current source (as shown in Figure 9) Part E, F), the experimental data chart of its current versus temperature change. Symbol Description:

Vcc〜電壓源;P卜P2〜PMOS電晶體,CU-Q2、Q5-Q6~FET 電晶體;Q3-Q4〜BJT電晶體;R〜電阻器;D1-D2〜二極體; 1 u — 1 ts〜電流源;A卜第一電流源單元;A 2〜第二電流源單 元;A3〜第三電流源單元;Pa-Pb〜電流路徑;第一電流 路徑;P2〜第二電流路徑;P3〜第三電流路徑;P4 ~第四電流 路徑;IaI- Ia2~定電流;Ibl-Ib2〜隨溫度呈正變化之電流;Vcc ~ voltage source; P2 P2 ~ PMOS transistor, CU-Q2, Q5-Q6 ~ FET transistor; Q3-Q4 ~ BJT transistor; R ~ resistor; D1-D2 ~ diode; 1 u — 1 ts ~ current source; A1 first current source unit; A2 ~ second current source unit; A3 ~ third current source unit; Pa-Pb ~ current path; first current path; P2 ~ second current path; P3 ~ The third current path; P4 ~ the fourth current path; IaI- Ia2 ~ constant current; Ibl-Ib2 ~ current that changes positively with temperature;

Ici 一 Ic2〜電流;Ma、Mb、Ml、M2、M3、M4 〜(空乏型)N-1 ype FET電晶體;E、F〜耦合電流源。 實施例: _ 請參照第2圖之電路,其為一使用GsAs製程之定電流 源,主要由空乏型FET電晶體(Q5、Q6)、Schottky二極體— (D1、D2)、電阻器R所構成。第2圖所示之電流源為自偏壓Ici-Ic2 ~ current; Ma, Mb, Ml, M2, M3, M4 ~ (empty type) N-1 ype FET transistor; E, F ~ coupling current source. Example: _ Please refer to the circuit in Figure 2. It is a constant current source using GsAs process. It is mainly composed of empty FET transistors (Q5, Q6), Schottky diodes (D1, D2), resistor R. Made up. The current source shown in Figure 2 is self-biased

434992^ 五、發明說明(5) (self-bias)之架構,利用二極體D1 (D2)墊高Q5 (Q6)源 極之電壓,且將Q5之閘極接地。在此不使用電阻器而用二 極體,乃因在相同電流之須下,二極體所佔用之面積遠小 於電阻器所佔用之面積。另外,由第3圖之負載圖可知, 由電晶體Q5 (Q6)和二極體D1 (D2)組成之工作點(iD、 VD)’在電壓源Vcc有很大之變動時,工作點電流之變化並 不大。 由於Q5 = Q6,D1=D2且兩邊閘極為等電位,所以為了使 Q5和Q6之閘極-源極間電壓(Vgs)相等,所以須Ιι = 〗2。 除了將此電流源之電流12供其他電路(負載)使用外 (如第2圖所示);亦可以使用電流鏡(Clirrent mirror)之 方式’將電流耦合給複數級電路使用,如第4圖所示。第4 圖(a)(b)中’係將I!電流耦合給(n-i)級電路使用,其 中’每個電晶體Q2〜Qn之尺寸均等於Q1,則二極體Dt之總 面積等於原電流源中二極體D1面積之η倍。另外,若是耦 合(η-1)倍L電流供其他電路使用,則電晶體Qn之面積須 為Q1之(n-1)倍’而二極體Dn之面積亦須為D1之(n-1)倍, 如第4圖(c)所示。上述之電流源可應用到一般的訊差級 (di fferential pair)以提昇其CMRR(同模拒絕比)和 PSRIi(電源拒絕比)。 將上述所提之電流源(依據GaAs製程)、搭配隨溫度呈-正變化之PTAT電流源而予以變形,而得到如第5圖所示之 電路。第5圖中,電晶體Q3和Q4之尺寸相同,二極體D3之 面積為D4之η倍。另外,Q3和Q4之閘極不再接地,以避免434992 ^ V. Description of the invention (5) (self-bias) The structure uses diode D1 (D2) to raise the voltage of Q5 (Q6) source and ground the gate of Q5. The diode is not used here because the area occupied by the diode is much smaller than the area occupied by the resistor under the same current. In addition, from the load diagram in Fig. 3, it can be seen that the operating point current (iD, VD) 'composed of the transistor Q5 (Q6) and the diode D1 (D2) is the operating point current when the voltage source Vcc varies greatly. The change is not large. Since Q5 = Q6, D1 = D2, and the gates on both sides are equipotential, in order to make the gate-source voltage (Vgs) of Q5 and Q6 equal, it must be ι = 〖2. In addition to using the current 12 of this current source for other circuits (loads) (as shown in Figure 2); you can also use a current mirror (Clirrent mirror) method to 'couple current to a complex stage circuit, as shown in Figure 4 As shown. In Figure 4 (a) and (b), 'I! Current is coupled to the (ni) stage circuit, where' the size of each transistor Q2 ~ Qn is equal to Q1, then the total area of the diode Dt is equal to the original Η times the area of diode D1 in the current source. In addition, if coupling (η-1) times L current for other circuits, the area of transistor Qn must be (n-1) times Q1 'and the area of diode Dn must also be (n-1 ) Times, as shown in Figure 4 (c). The above current sources can be applied to general differential pairs to improve their CMRR (same mode rejection ratio) and PSRIi (power supply rejection ratio). The current source mentioned above (according to the GaAs process) is matched with a PTAT current source that changes in a positive direction with temperature and deformed to obtain the circuit shown in Figure 5. In Fig. 5, transistors Q3 and Q4 have the same size, and the area of diode D3 is η times that of D4. In addition, the gates of Q3 and Q4 are no longer grounded to avoid

4 349 9 2¾ 五、發明說明(6) 電流被Q 3和Q 4所限制。 又113^ 0所以 首先,藉由電路之機制使電流源k =〖u, Q3和Q4之VgS均相同,因此下列式子得以成立4 349 9 2¾ 5. Description of the invention (6) The current is limited by Q 3 and Q 4. 113 ^ 0 So first, the current source k = [u is made by the mechanism of the circuit, VgS of Q3 and Q4 are the same, so the following formula can be established

VD4 J1R ' V〇3 = 〇 => I,R = V,, - V 1 D4 ν 且 h ^ ID3 exp(VD3/VT) I2 = ID4 eXP(VD4^VT)VD4 J1R 'V〇3 = 〇 => I, R = V ,,-V 1 D4 ν and h ^ ID3 exp (VD3 / VT) I2 = ID4 eXP (VD4 ^ VT)

IiR = VT^n(I2/ID4) - VT^n(I1/ID3)IiR = VT ^ n (I2 / ID4)-VT ^ n (I1 / ID3)

Ij ^ vT/R ^n(n) 至此可知’第5圖所示之電流源電路中,其電流值i i和12僅 與二極體D3和D4之尺寸大比值和電阻值R相關;且由於ντ 之值隨溫度昇高而增加’所以電流值1〖和12亦隨溫度之昇 高而增加,故而呈現正變化之關係,此即稱為PTAT電流 源。所以,只要能夠製作一個不用P型電晶體之電流源Itl 和It2,如此即可達到利用GaAs製程實作具有溫度補償功能 電流源(亦即其電流具有狀η ( η)特性)之目的。 然而,參照第5圖,若電流源Iu和It2為定電流源的 話,則如第2圖,電流Iti (=^) = 1 = 12。如此,I,和12電流值 係由定流源Itl (和It2)所決定,而不會受二極體D3和D4尺 寸比值之影響。所以,電流源1ti和1不可使用習知之定電 流源電路。 ~ 第6圖顯示本發明之具有溫度補償功能之電流源裝置— 之架構圖。在此實施例中,使用GaAs電晶體來作介紹;其Ij ^ vT / R ^ n (n) So far, it can be known that in the current source circuit shown in Fig. 5, the current values ii and 12 are only related to the size ratio of the diodes D3 and D4 and the resistance value R; and The value of ντ increases with increasing temperature, so the current values 1 and 12 also increase with increasing temperature, and therefore show a positive change. This is called a PTAT current source. Therefore, as long as it is possible to make current sources Itl and It2 that do not use P-type transistors, the purpose of implementing a current source with temperature compensation function (that is, its current has a shape of η (η)) using the GaAs process can be achieved. However, referring to Fig. 5, if the current sources Iu and It2 are constant current sources, then as in Fig. 2, the current Iti (= ^) = 1 = 12. In this way, the current values of I, and 12 are determined by the constant current sources Itl (and It2), and are not affected by the size ratio of the diodes D3 and D4. Therefore, the current sources 1ti and 1 cannot use the conventional constant current source circuit. ~ Figure 6 shows the structure diagram of the current source device with temperature compensation function of the present invention. In this embodiment, a GaAs transistor is used for introduction;

434992^_ 五、發明說明(7) · 中電晶體均為空乏型N-type FET電晶體,而二極體則均為 高能障之Schott ky二極體。但是本發明並不限定於只能 GaAs製程,而是可以應用至各種可能之半導體製程。 參照第6圖,本發明提出具有溫度補償功能之電流源 裝置,包括下列單元。 一第一電流源單元(A1)’提供兩條電流路徑(p a、434992 ^ _ V. Description of the invention (7) · The CTCs are all empty N-type FET transistors, and the diodes are Schottky diodes with high energy barriers. However, the present invention is not limited to the GaAs process, but can be applied to various possible semiconductor processes. Referring to Fig. 6, the present invention proposes a current source device having a temperature compensation function, which includes the following units. A first current source unit (A1) 'provides two current paths (p a,

Pb) ’分別流通具有定電流值之電流匕和l。 一第—電流源單元(A2 ),提供電流(ibl和ib2) ’其電流 值隨溫度昇高而增加。其中,上述第二電流源單元(A2), 至少包括:一第一電晶體(Ml)、一第一二極體(D1),構成 一第一電流路徑(P1)流通上述電流(Ibl); —第二電晶體 (M2)、一第二二極體(D2) ’構成一第二電流路徑(P2)流通 上述電流(Ib2)。 上述第一電晶體(Ml )和上述第二電晶體(M2)之偏壓極 (閘極)耦接一起,上述電流(Ibl = Ib2)之值取決於上述第一 二極體(D1)和第二二極體(D2)兩者間之尺寸比例。在此實 施例中,上述第一電晶體(Ml)和上述第二電晶體(M2)均可 為N-type FET電晶體。 一第三電流源單元(A3),提供一第三電流路徑(p3)和 一第四電流路徑(P 4) ’分別流通電流(Icl和1。2)。 其中,上述第一電流源單元中電流路徑之一(pa)搞接 上述第一電流路徑(P1)和上述第三電流路徑(P3),上述第 一電流源單元(A1)中另一電流路徑(Pb)輕接上述第二電流 路徑(P2)和上述第四電流路徑(P4),上述第三電流之值為Pb) 'respectively circulates current k and l having a constant current value. A first-current source unit (A2), which provides current (ibl and ib2) ', and its current value increases as the temperature increases. Wherein, the second current source unit (A2) at least includes: a first transistor (M1), a first diode (D1), constituting a first current path (P1) to flow the current (Ibl); -The second transistor (M2) and a second diode (D2) 'constitute a second current path (P2) through which the above-mentioned current (Ib2) flows. The bias transistor (gate) of the first transistor (M1) and the second transistor (M2) are coupled together, and the value of the current (Ibl = Ib2) depends on the first diode (D1) and The size ratio between the second diode (D2). In this embodiment, both the first transistor (M1) and the second transistor (M2) may be N-type FET transistors. A third current source unit (A3) provides a third current path (p3) and a fourth current path (P4) 'to flow currents (Icl and 1.2), respectively. One of the current paths (pa) in the first current source unit connects the first current path (P1) and the third current path (P3), and the other current path in the first current source unit (A1). (Pb) Lightly connect the second current path (P2) and the fourth current path (P4), and the value of the third current is

第10頁 434992^ 五、發明說明(8) · 上述第一電流和第二電流兩者之差值(Ici = Iai„Ibi ; [^ -ib2)。 a 如上所述,利用電路之機制使第一電流源單元(A1 )為 定電流源時,其路徑pa和pb上之電流丨a不會因X和γ點上電 壓之變動而變化’此時若沒有第三電流源單元(A3)之搭 配’則第二電流源單元(A2)中,路徑P1和P2上之電流Ibi和 I ^將被第一電流源單元(A1 )所主宰。如此一來,電流(I μ 和込2)將不會是由二極體D1和D2之比值(η)來決定,亦即不 會有正比於VT/R€ η(η)之特性。所以,在本發明中,第三 電流源單元(A3)之目的主要係作為電流槽(current sink) 之用’使定電流之第一電流源單元(A1)可以應用至本發 明’而且讓第二電流源單元(A2)之電流(ibi*Ib2)仍由二極 體D1和D2之比值(η)來決定’且具有隨溫度呈現正變化之 特性,即呈現Ibl = Ib2 = VT/R€ η(η)之關係式。另外,第三電 流源單元(A3 )之電流(Icl和I。2)並不是定電流源,而是隨著 X、Y點位置電壓之變化而變動。 第12圖係為第6圖所示電流源電路架構使用njjos時之 實驗模擬數據。在第12圖中,當兩個二極體比值(n : 1:) 由2 : 1變成8 : 1時’其餘元件值也可隨之改變之情形 下’電流I之曲線由A變成B ^故電流I之電流值大小仍係取 決於兩個二極體之比值《另外,由比較曲線A、β可知,元 件和電壓源Vcc之變動對電流值之影響並不大,所以可以 有效增加良品率Page 10 434992 ^ V. Description of the invention (8) · The difference between the above first current and second current (Ici = Iai „Ibi; [^ -ib2). A As mentioned above, the circuit When a current source unit (A1) is a constant current source, the currents on its paths pa and pb 丨 a will not change due to changes in voltage at points X and γ. 'If there is no third current source unit (A3) With 'the second current source unit (A2), the currents Ibi and I ^ on paths P1 and P2 will be dominated by the first current source unit (A1). In this way, the currents (I μ and 込 2) will be It will not be determined by the ratio (η) of the diodes D1 and D2, that is, it will not have a characteristic proportional to VT / R € η (η). Therefore, in the present invention, the third current source unit (A3 The purpose of) is mainly to be used as a current sink. “The first current source unit (A1) of constant current can be applied to the present invention” and the current of the second current source unit (A2) (ibi * Ib2) It is still determined by the ratio (η) of diodes D1 and D2, and has the characteristic of positive change with temperature, that is, the relationship of Ibl = Ib2 = VT / R € η (η) In addition, the current (Icl and I.2) of the third current source unit (A3) is not a constant current source, but changes with the change in the voltage at the X and Y points. Figure 12 is shown in Figure 6. The experimental simulation data when the current source circuit architecture uses njjos. In Figure 12, when the ratio of the two diodes (n: 1: :) is changed from 2: 1 to 8: 1, the values of the remaining components can be changed accordingly. Under the circumstances, the curve of the current I changes from A to B ^ Therefore, the current value of the current I still depends on the ratio of the two diodes. In addition, it can be seen from the comparison of the curves A and β that the changes in the component and voltage source Vcc affect the current. The effect of the value is not large, so it can effectively increase the yield

第11頁 4 349 92'^ 五、發明說明(9) 第7圖顯示本發明在使用GaAs FET下之具有溫度補償 功能之電流源裝置之一實施例之電路圖。 上述第一電流源單元(A 1)中之兩條電流路徑Pa、Pb, 均係由一空乏型NMOS電晶體(Ma) _接一二極體(Da)所構 成’且上述二極體(Da)之陰極耦接上述電晶體(Ma)之閘極 (偏壓極);上述電晶體Ma之一端耦接至一電壓源(Vcc), 上述兩條電流路徑中之兩個二極體Da之陰極分別耦接至上 述第一電晶體(Μ 1)和第二電晶體(M2 )之汲極,如第7圖所 示0 上述第二電流源單元(Α2)中之第一電流路徑pi,係由 上述第一 Ν-type FET電晶體Ml、電阻器R、和第一二極體 D1彼此串接而成;第二電流路徑P2,係由上述第二N_type FET電晶體M2、和第二二極體D2彼此串接而成,如第7圖所 示。 上述第二電流源單元A2更包括一偏壓裝置BA1 (參照 第6圖),用以對上述第一電晶體(M1)和第二電晶體M2進行 偏壓。 參”’、第7圖’上述偏壓裝置(bai)至少包括:一第一偏 f電晶體Mbl串連一電壓位準移位裝置,(透過電阻器Rb)設 置於f述電壓源Vcc和上述電晶體M1和心之閘極間;以 L Φ Γ Ϊ壓電晶體^2 ’設置於上述電晶體M1和112偏壓-極和電壓參考點(GND)之間。而且,上Page 11 4 349 92 '^ 5. Description of the invention (9) Figure 7 shows a circuit diagram of an embodiment of a current source device with temperature compensation function in the present invention using a GaAs FET. The two current paths Pa and Pb in the first current source unit (A 1) are both composed of an empty NMOS transistor (Ma) _ connected to a diode (Da), and the diode ( The cathode of Da) is coupled to the gate (bias) of the transistor (Ma); one terminal of the transistor Ma is coupled to a voltage source (Vcc), and the two diodes Da in the two current paths are The cathodes are respectively coupled to the drains of the first transistor (M 1) and the second transistor (M2), as shown in FIG. 7. 0 The first current path pi in the second current source unit (A2). Is formed by connecting the first N-type FET transistor M1, the resistor R, and the first diode D1 in series with each other; and the second current path P2 is by the second N_type FET transistor M2 and the first The two diodes D2 are connected in series with each other, as shown in FIG. 7. The second current source unit A2 further includes a biasing device BA1 (refer to FIG. 6) for biasing the first transistor (M1) and the second transistor M2. See "", Fig. 7 'The above biasing device (bai) includes at least: a first biasing transistor Mbl connected in series with a voltage level shifting device (through a resistor Rb) disposed at the voltage source Vcc and The above-mentioned transistor M1 and the gate of the heart; L Φ Γ Ϊ piezoelectric crystal ^ 2 'is provided between the above-mentioned transistors M1 and 112 bias-pole and voltage reference point (GND).

Mbl之偏壓極轉接至上述镇_ 广保澄策晶篮 上攻第一電日日體M2和上述第一電流源單 α路fe ( Pb)之連接點;上述第二偏壓電晶體、The bias pole of Mbl is transferred to the above town _ Guangbao Chengce crystal basket to attack the connection point of the first electric solar element M2 and the first current source single alpha channel fe (Pb); the second bias transistor ,

第12頁 434992^ 五、發明說明~ 之閘極叙接至上述電壓參考點。 在此實施例中’上述電壓位準移位裝置係由2個二極 體(Dbll、Dbl2)串接而成;上述第二偏壓電晶體l更串接— 二極體(DbZ1)再耦接至上述電壓參考點,如第7圓所示。在 此,對於Ml和M2閘極之偏壓,本發明使用位準移位(level shift)之方式,而不使用電阻分壓,係為了減低電流之漏 失’期能使流向Ml和M2閘極之電流儘可能接近零。 上述第三電流源單元(A3)中之第三電流路徑p3,係由 一 N-type FET電晶體M3、和二極體D3彼此串接而成;第四 電流路徑P4 ’係由一N-type FET電晶體M4、和二極體D4 彼此串接而成;且上述電晶體M3和M4之汲極分別耦接至X 點和Y點;如第7圖所示。而為了使流過電流路徑p 3和p 4之 電流相同,亦即1^ = 1。’故讓電晶體M3和[^4之尺寸相同, 以及讓二極體D3和D4之尺寸相同。 上述第三電流源單元A3更包括一偏壓裝置“2 (第6圖 中未圖示),用以對上述電晶體M3和M2互相連接之閘極進 行偏壓。在此實施例中,偏壓裝置BA2之構成和配置與BA1 相同,如第7圖所示。 第11圖係為第7圖所示電流源電路(亦即第1 〇圖中的 BB部分電路)在電晶體只有使用NM0S的情形下之實驗模擬 數據’電流I之值與先前推導之結果相同,係隨著溫度昇 高而增加。 第8圖顯示將本發明實施例裝置產生之電流予以耦合 輸出之應用圖。由上述可知,由F部分供給電路TA使用之Page 12 434992 ^ V. Description of the invention-The gate electrode is connected to the above voltage reference point. In this embodiment, the above-mentioned voltage level shifting device is formed by connecting two diodes (Dbll, Dbl2) in series; the second bias transistor l is further connected in series-the diode (DbZ1) recoupling Connect to the voltage reference point as shown in circle 7. Here, for the bias of the M1 and M2 gates, the present invention uses a level shift method instead of a resistor divider, which is to reduce the current leakage period of the current to the M1 and M2 gates. The current is as close to zero as possible. The third current path p3 in the third current source unit (A3) is formed by connecting an N-type FET transistor M3 and a diode D3 in series; the fourth current path P4 'is formed by an N- The type FET transistor M4 and the diode D4 are connected in series with each other; and the drains of the transistors M3 and M4 are coupled to the X point and the Y point, respectively, as shown in FIG. 7. In order to make the currents flowing in the current paths p 3 and p 4 the same, that is, 1 ^ = 1. Therefore, the sizes of the transistors M3 and [^ 4 are the same, and the sizes of the diodes D3 and D4 are the same. The third current source unit A3 further includes a biasing device "2 (not shown in Fig. 6) for biasing the gates of the transistors M3 and M2 connected to each other. In this embodiment, the bias The structure and configuration of the voltage device BA2 is the same as that of BA1, as shown in Fig. 7. Fig. 11 is the current source circuit shown in Fig. 7 (that is, part of the BB circuit in Fig. 10). Only NMOS is used in the transistor. In the case of the experimental simulation data, the value of the current I is the same as the result of the previous derivation, and it increases with the increase of temperature. Fig. 8 shows an application diagram for coupling and outputting the current generated by the device of the embodiment of the present invention. It can be seen that the part F is supplied to the circuit TA for use.

第13頁 434992^ 五'發明說明(11) ^ 電流ITA(=m X D係為隨溫度呈正變化。由上述可知,二極 體之位能障(barrier height)隨溫度昇高而降低,故通過 之電流隨溫度昇高而增加;又,電晶體隨溫度昇高,電淹 反而減少’故而定電流部分,即A丨,受溫度之影響較小。 但是因為F部分,為隨溫度呈正變化,故而E部分供給電路 TB使用之電流ITB( = k X lb2)則相反,並成為隨溫度呈負變 化。 若將E和F部分合併成一個電流源,如第9圖所示,可 藉由調整E和F部分之比例,而使得供給至電路T c之電流Γ 儘可能地不隨溫度變化而變動’或是將溫度對電流Ief之^ 響降側最低。倘若電路TC僅為一電阻器,則由電阻器所輸 出之電壓即不受溫度變化影響之定電壓。 第1 4圖顯示將Ε和F部分合併成一個電流源時,其電流 對溫度變化之實驗數據圖。第1 3圖則顯示一般電流源,其 電流對溫度變化之實驗數據圖。由第1 3圖可知,一般電流 源在零下40t時之電流約為440 ν A ;當溫度昇高至80 t 時,電流降低約至408私A,電流之變動達到32 " A。由第 14圖可知’由E和F部分所合併成之電流源,在零下4〇 時 之電流約為4 6 8. 7仁A ;當溫度昇高約至5 0 °C時,電流降低 約至4 6 2 //A,當溫度昇高至80 時,電流則昇高約至4 64 //A ;其間電流之最大變動僅為6.7yA,遠小於一般之電. 流源。因此,由E和F部分所合併成之電流源,確實已經將 溫度對電流IEF之影響降低到最低之程度,幾乎已經不隨溫 度變化而變動。Page 13 434992 ^ Five 'description of the invention (11) ^ The current ITA (= m XD is a positive change with temperature. From the above, we can see that the barrier height of the diode decreases with increasing temperature, so it passes The current increases with increasing temperature; and the transistor decreases with increasing temperature. Therefore, the current portion, that is, A 丨, is less affected by temperature. However, because the F portion changes positively with temperature, Therefore, the current ITB (= k X lb2) used by the E supply circuit TB is the opposite and becomes a negative change with temperature. If the E and F parts are combined into a current source, as shown in Figure 9, it can be adjusted by The proportion of parts E and F, so that the current Γ supplied to the circuit T c does not change with temperature as much as possible 'or minimizes the effect of temperature on the current Ief ^. If the circuit TC is only a resistor, The voltage output by the resistor is a constant voltage that is not affected by temperature changes. Figure 14 shows the experimental data diagram of current versus temperature changes when E and F are combined into a current source. Figure 13 shows Shows the general current source, whose current changes with temperature The experimental data chart. From Figure 13 it can be seen that the current of the general current source is about 440 ν A at minus 40t; when the temperature rises to 80 t, the current is reduced to about 408 A, and the current variation reaches 32. A. As can be seen from Figure 14, 'the current source formed by combining parts E and F, the current at minus 40 is about 4 6 8. 7 Ren A; when the temperature rises to about 50 ° C, The current decreases to approximately 4 6 2 // A. When the temperature rises to 80, the current increases to approximately 4 64 // A; the maximum change in current during this time is only 6.7yA, which is far less than the average electricity. Current source. Therefore, the current source combined by parts E and F has indeed reduced the effect of temperature on the current IEF to a minimum, and has almost no change with temperature changes.

第14頁 4 349 9 2^ _ 五、發明說明(12) 第10圖顯示應用本發明架構,在只有NMOS與二極體的 情形下,所設計的之不隨溫度變化之電壓源電路。 另外,將F部分接成如第10圖所示之電路,由上 述可知,IF電流大約等於(VT/R) X βη(η) X m,則Cout 點的電壓 Vout 為 Vcc-IrxRF-VDr。Mu,v〇ut = Vcc- {(mVTRr/R)x€n(n) + VDr}。已知[(mVTRF/R)x/n(n)]係 隨溫度呈現正變化,而VEF (二極體電壓)伤隨溫度呈現 負變化3故而只要適當調整(mRr/H)之值,即可以得到 一不隨溫度變化之輸出電壓。 由上述可知’本發明所提出具有溫度補償功能之電流 源裝置之各種電路,其整個架構均使用了元件對稱比例之 觀念’所以使用本發明所提出之架構,不僅可以使用在溫 度補償電路上’輸出之電流亦使用對稱比例來決定,故可 以使用在相關之電路上。因此,電路效能表現 (performance)將不會受到製程本身之影響,使得藉由 GaAs…等製程所製作之電路之良品率提昇。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明’任何熟悉本項技藝者,在不脫離本發明之精 神和範圍内,當可做些許之更動和潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 1^1 HHra 第15頁Page 14 4 349 9 2 ^ _ V. Description of the invention (12) Figure 10 shows the voltage source circuit that is designed not to change with temperature when the structure of the present invention is applied. In the case of only NMOS and diodes. In addition, by connecting part F into a circuit as shown in Fig. 10, it can be known from the above that the IF current is approximately equal to (VT / R) X βη (η) X m, then the voltage Vout at the Cout point is Vcc-IrxRF-VDr. Mu, v〇ut = Vcc- {(mVTRr / R) x € n (n) + VDr}. It is known that [(mVTRF / R) x / n (n)] shows a positive change with temperature, and VEF (diode voltage) damage shows a negative change with temperature. Therefore, as long as the value of (mRr / H) is adjusted appropriately, that is, An output voltage that does not change with temperature can be obtained. From the above, it can be known that the entire architecture of the current source device with temperature compensation function proposed by the present invention uses the concept of symmetrical proportions of components. Therefore, using the proposed structure of the present invention can not only be used in temperature compensation circuits. The output current is also determined using a symmetrical ratio, so it can be used in related circuits. Therefore, the performance of the circuit will not be affected by the process itself, so that the yield of circuits produced by processes such as GaAs ... will be improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 1 ^ 1 HHra p. 15

Claims (1)

4 349 92^ 六、申請專利範圍 1 - ^·種具有溫度補償功能之電流源裝置,包括: 一第一電流源單元,提供兩條電流路徑,分別流通具 有定電流值之第一電流; 一第二電流源單元,提供一第二電流,其電流值隨溫 度昇高而增加;其中,上述第二電流源單元,至少包括: 一第一電晶體、一第一二極體,構成—第—電流路徑流通 上述第二電流;一第二電晶體、一第二二極體,構成一第 二電流路徑流通上述第二電流;上述第二電流之值取決於 上述第一二極體和第二二極體兩者間之尺寸比例; 一第三電流源單元,提供一第三電流路徑和一第四電 流路徑,分別流通一第三電流; 其中,上述第一電流源單元中電流路徑之一耦接上述 第一電流路徑和上述第三電流路徑,上述第一電流源單元 中另一電流路徑耦接上述第二電流路徑和上述第四電流路 徑’上述第二電流之值為上述第一電流和第二電流兩者 差值。 2.如申請專利範圍第1項所述之裝置,其中,上述第 一電流源單元中之兩條電流路徑,均係由一電晶體串接一 二極體所構成,且上述二極體之陰極耦接上述電晶 壓極;上述電晶體之-端_接至—電壓源,上述 路徑中之兩個二極體之陰極分別耦接至上述 、電瀹 3.如申請專利範圍第1項所述之裝置,其中, 一電晶體之一端耦接上述第一電流源單 —上述第 电 '峨路徑,4 349 92 ^ VI. Patent application scope 1-^ · Current source device with temperature compensation function, including: a first current source unit, providing two current paths, respectively, a first current with a constant current value; The second current source unit provides a second current whose current value increases as the temperature increases; wherein the second current source unit includes at least: a first transistor, a first diode, and a first component. A current path passes the second current; a second transistor and a second diode constitute a second current path to pass the second current; the value of the second current depends on the first diode and the first A size ratio between the two diodes; a third current source unit providing a third current path and a fourth current path, respectively, passing a third current; wherein the current path in the first current source unit is One is coupled to the first current path and the third current path, and another current path in the first current source unit is coupled to the second current path and the fourth current path. The first current and the second current value is the difference of the two second current. 2. The device according to item 1 of the scope of the patent application, wherein the two current paths in the first current source unit are each composed of a transistor connected in series with a diode, and the diode The cathode is coupled to the transistor; the-terminal of the transistor is connected to a voltage source; the cathodes of the two diodes in the above path are respectively coupled to the above-mentioned, electric voltage. In the device, one terminal of a transistor is coupled to the first current source unit-the second electric source path, 434992 六、申請專利範圍 上述第一一極體之陽極耦接上述第—電晶體之另一端,其 陰極搞接至一電壓參考點;上述第二電晶體之一端耦接丄 述第一電流源單元之另一電流路徑,上述第二二極體之陽 極柄接上述第二電晶體之另一端,其陰極耦接至上述電壓 參考點’上述第一和第二電晶體兩者之偏壓極互相連接。 4·如申凊專利範圍第3項所述之裝置,其中,上述第 一電晶體之一端和上述第一二極體陽極之間更耦接 阻器。 电 5. 如申請專利範圍第2項或第3 上述第二電流源單元更包括—偏負:辻之裝置,其中’ 電晶體和第二電晶體進行偏壓。I * ’用以對上述第- 6. 如申請專利範圍第5項所述 壓裝置至少包括一第一偏壓雷曰之裝置,其中,上述偏 裝置,設置於上述電壓源和上述Z串連-電壓位準移位 極之間;以及’一第二偏壓電晶〜(或第二)電晶體偏壓 第二)電晶體偏壓極和上述電壓參’設置於上述第一(或 壓電晶體之偏壓極耦接至上述第—點之間;上述第一偏 源單元之另一電流路徑之連接點了電晶體和上述第一電流 偏壓極耦接至上述電壓參考點。上述第二偏壓電晶體之 7·如申請專利範圍第6項所述 壓位準移位裝置係由複數二極體·〈敦置’其广,上述電 構成;上述第二偏壓電晶體更串 、或由單一二極體所 電壓參考點。 一極體再輕接至上述 8.如申請專利範圍第丨項所述 之裝置’其中,上述第434992 VI. Scope of patent application: The anode of the first monopolar body is coupled to the other end of the first transistor, and the cathode is connected to a voltage reference point; one end of the second transistor is coupled to the first current source. In another current path of the unit, the anode handle of the second diode is connected to the other end of the second transistor, and the cathode is coupled to the voltage reference point, the bias electrode of both the first and second transistors. Connected to each other. 4. The device according to item 3 of the patent claim, wherein a resistor is further coupled between one end of the first transistor and the anode of the first diode. 5. The second current source unit according to item 2 or 3 of the scope of patent application further includes a device that is biased-negative: 辻, wherein the transistor and the second transistor are biased. I * 'is used for the above-mentioned 6.-The voltage device described in item 5 of the scope of patent application includes at least one device with a first bias voltage, wherein the above-mentioned bias device is disposed between the voltage source and the Z series. -A voltage level shifting electrode; and 'a second bias transistor ~ (or a second) transistor bias second) the transistor bias electrode and the voltage reference' are set at the first (or voltage) The bias electrode of the transistor is coupled between the first point; the connection point of the other current path of the first bias source unit is the transistor and the first current bias electrode are coupled to the voltage reference point. The second bias transistor 7. The voltage level shifting device as described in item 6 of the scope of the patent application is composed of a plurality of diodes. The voltage reference point is more stringed, or by a single diode. A pole is then lightly connected to the above 8. The device described in item 丨 of the scope of patent application 'wherein, the above $ 17頁 4 3 49 9? 六、申請專利範圍 三電流源單元* 體,構成上述第 曰曰 體、一第四 二電流,上述第 9.如_請專 二電晶體之一端 上述第三二極體 陰極耦接至一電 述第一電流源單 極耦接上述第二 參考點。 至少包 ζ電流 極體, 三和第 利範圍 1¾接上 之陽極 壓參考 元之另 電晶體 括:一第 電 曰a 體、一第三二極 路徑流通上述第三電流 構成上述第四電流路徑流 四電晶體兩者之偏壓極互 第8項所述之裝置,其中 述第一電流源單元之一電 耦接上述第三電晶體之另 點;上述第四電晶體之一 一電流路徑’上述第四二 之另一端’其陰極耦(接至 一第四電 通上述第 相連接。 ,上述第 流路徑, 一端,其 端耦接上 極體之陽 上述電壓 10.如申請專利範圍第9項所述之裝置,其 二電流源單元更包括一偏壓裝置,用以對上述 二 曰 和第四電晶體進行偏壓。 二電晶體 11. 如申請專利範圍第10項所述之裝置,其中, 偏壓裝置至少包括:一第三偏壓電晶體串連一電墨’位 位裝置’設置於上述電壓源和上述第三(或第四)電晶體t 壓極之間;以及,一第四偏壓電晶體,設置於上述第二 (或第四)電晶體偏壓極和上述電壓參考點之間;上述第_ 偏壓電晶體之偏壓極耦接至上述第一電晶體和上述第—二 流源單元之另一電流路徑之連接點;上述第四偏壓電晶體 之偏壓極耦接至上述電壓參考點。 曰 12. 如申請專利範圍第11項所述之裝置,其中,上述.. 電壓位準移位裝置係由複數二極體串接、或由單—二拼$ 17Page 4 3 49 9? VI. Patent application scope Three current source unit * body, which constitutes the above-mentioned first body and a forty-two current, as mentioned above. The cathode of the electrode body is coupled to a first electrode of the first current source and the second reference point is coupled to the above-mentioned second reference point. At least the zeta current pole body, and the other transistor of the anode voltage reference element connected to the third and second range include: a first electric body and a third dipole path. The third current passes through to form the fourth current path. The device according to item 8 in which the bias voltages of the two current-transistor transistors are mutually interchanged, wherein one of said first current source units is electrically coupled to another point of said third transistor; a current path of one of said fourth transistor 'The other end of the aforementioned fourth two' has a cathode coupling (connected to a fourth electrical connection of the above-mentioned first phase connection.) In the above-mentioned current flow path, one end, its end is coupled to the anode of the upper pole and the above-mentioned voltage 10. The device according to item 9, the second current source unit further includes a biasing device for biasing the second transistor and the fourth transistor. The second transistor 11. The device according to item 10 of the scope of patent application Wherein, the biasing device includes at least: a third biasing transistor connected in series with an electro-ink 'position device' disposed between the voltage source and the third (or fourth) transistor t voltage electrode; and, A fourth bias transistor , Set between the second (or fourth) transistor bias electrode and the voltage reference point; the bias electrode of the first bias transistor is coupled to the first transistor and the second-second source unit The connection point of the other current path; the bias electrode of the fourth bias transistor is coupled to the voltage reference point. 12. The device according to item 11 of the scope of patent application, wherein the above .. voltage level The quasi-shifting device is connected by a plurality of diodes in series or by single-two spelling. 第18頁 4 349 92 六、申請專利範圍 . 所構成;上述第二偏壓電晶體更串接一二極體再耦接至上 述電壓參考點。 ^ 13.如申請專利範圍第8項所述之裝置,其中,上述第 三電流源單元之第三和第四電晶體具有相同之尺寸大小, 上述第三和第四二極體具有相同之尺寸大小。 1 4.如申請專利範圍第1項所述之裝置,其t,上述所 有電晶體均為空乏型FET電晶體。 1 5 .如申請專利範圍第1項所述之裝置,其中,上述所 有二極體均為高能障二極體、或是Shottky二極體。 16. 如申請專利範圍第1項所述之裝置,更由上述第二 電流源單元中,將流通於上述第二電流路徑中之電流,以 電流鏡方式耦接出來,作為第四電流源β 17. 如申請專利範圍第16項所述之裝置,其中,上述 第四電流源再串接一電阻器、一二極體,以便將第四電流 源轉換作為一電壓源。 18. 如申請專利範圍第1項所述之裝置,其中,更由上 述第二電流源單元中,將流通於上述第二電流路徑中之電 流,以電流鏡方式耦接出來,作為第五電流源;以及,由 上述第三電流源單元中,將流通於上述第三電流路徑中之 電流,以電流鏡方式耦接出來,作為第六電流源;再將上 述第五和第六電流源合併成一第七電流源。 . 1 9. 一種具有溫度補償功能之電流源裝置,包括: 一第一電流源單元,提供一具有定電流值之第一電 流;Page 18 4 349 92 6. Application scope of patent. The above-mentioned second bias transistor is further connected in series with a diode and then coupled to the above voltage reference point. ^ 13. The device according to item 8 of the scope of patent application, wherein the third and fourth transistors of the third current source unit have the same size, and the third and fourth diodes have the same size size. 1 4. The device according to item 1 of the scope of patent application, wherein t, all the transistors mentioned above are empty FET transistors. 15. The device according to item 1 of the scope of patent application, wherein all the diodes mentioned above are high energy barrier diodes or Shottky diodes. 16. According to the device described in the first item of the scope of patent application, the second current source unit further couples the current flowing in the second current path in a current mirror manner as a fourth current source β. 17. The device according to item 16 of the scope of patent application, wherein the fourth current source is further connected in series with a resistor and a diode in order to convert the fourth current source into a voltage source. 18. The device according to item 1 of the scope of patent application, wherein the second current source unit further couples the current flowing in the second current path in a current mirror manner as a fifth current. And the third current source unit couples the current flowing in the third current path in a current mirror manner as a sixth current source; and then combines the fifth and sixth current sources Into a seventh current source. 1 9. A current source device having a temperature compensation function, comprising: a first current source unit for providing a first current having a constant current value; 第19頁 六、申請專利範圍 一第二電流源單元,提供一第二電流,其電流值隨溫 度昇高而增加;其中,上述第二電流源單元,至少包括i 一第一電晶體、一第一二極體,構成一第一電流路徑流通 上述第二電流;一第二電晶體、一第二二極體,構成一第 二電流路徑流通上述第二電流;上述第二電流之值取決於 上述第一二極體和第二二極體兩者間之尺寸比例; 一第三電流源單元,提供一第三電流,其值為上述第 一電流和第二電流兩者之差值: 其中,上述第一電流源單元串接上述第二電流源單 元,而上述第三電源單元並連上述第三電源單元。 20. 如申請專利範圍第19項所述之裝置,其中,上述 第二電流源單元更包括一偏壓裝置,用以對上述第一電晶 體和第二電晶體進行偏壓。 21. 如申請專利範圍第19項所述之裝置,其中,上述 第一電流源單元至少包括兩條電流路徑,分別流通上述第 一電流、以及串接至上述第二電流單元之第一電晶體和第 二電晶體。 22. 如申請專利範圍第21項所述之裝置,其中,每一 上述第一電流源單元中之電流路徑,均係由一電晶體串接 一二極體所構成,且上述電晶體之偏壓極耦接至上述二極 體之陰極。 23. 如申請專利範圍第19項所述之裝置,其中,上述 第三電流單元,至少包括:一第三電晶體、一第三二極 體,構成一第三電流路徑流通上述第三電流;一第四電晶Page 19 VI. Patent application scope A second current source unit provides a second current whose current value increases with increasing temperature; wherein the second current source unit includes at least i a first transistor, a The first diode constitutes a first current path through which the second current flows; a second transistor and a second diode constitute a second current path through which the second current flows; the value of the second current depends on A size ratio between the first diode and the second diode; a third current source unit for providing a third current, the value of which is the difference between the first current and the second current: The first current source unit is connected in series with the second current source unit, and the third power source unit is connected in parallel with the third power source unit. 20. The device according to item 19 of the application, wherein the second current source unit further includes a biasing device for biasing the first transistor and the second transistor. 21. The device according to item 19 in the scope of patent application, wherein the first current source unit includes at least two current paths, respectively, through which the first current flows, and a first transistor connected in series to the second current unit. And a second transistor. 22. The device according to item 21 of the scope of patent application, wherein the current path in each of the first current source units is composed of a transistor connected in series with a diode, and the bias of the transistor is The voltage pole is coupled to the cathode of the diode. 23. The device according to item 19 of the scope of patent application, wherein the third current unit includes at least: a third transistor and a third diode, forming a third current path to flow the third current; A fourth transistor 第20頁 六、申請專利範圍 體、一第四二極體,構成一第四電流路徑流通上述第三電 流。 24. 如申請專利範圍第23項所述之裝置,其中,上述 第三電流源單元更包括一偏壓裝置,用以對上述第三電晶 體和第四電晶體進行偏壓。 25. 如申請專利範圍第23項所述之裝置,其中,上述 第三電流源單元之第三和第四電晶體具有相同之尺寸大 小,上述第三和第四二極體具有相同之尺寸大小。 26. 如申請專利範圍第19項所述之裝置,更由上述第 二電流源單元中,將流通於上述第二電流路徑中之電流, 以電流鏡方式耦接出來,作為第四電流源。 27. 如申請專利範圍第26項所述之裝置,其中,上述 第四電流源再串接一電阻器、一二極體,以便將第四電流 源轉換作為一電塵源。 28. 如申請專利範圍第19項所述之裝置,其中,更由 上述第二電流源單元中,將流通於上述第二電流路徑中之 電流,以電流鏡方式耦接出來,作為第五電流源;以及, 由上述第三電流源單元甲,將流通於上述第三電流路徑中 之電流,以電流鏡方式耦接出來,作為第六電流源;再將 上述第五和第六電流源合併成一第七電流源。Page 20 6. The scope of patent application, a fourth diode, constitutes a fourth current path to flow the third current. 24. The device described in claim 23, wherein the third current source unit further includes a biasing device for biasing the third transistor and the fourth transistor. 25. The device according to item 23 of the scope of patent application, wherein the third and fourth transistors of the third current source unit have the same size, and the third and fourth diodes have the same size . 26. The device described in item 19 of the scope of the patent application, further comprises the second current source unit coupling the current flowing in the second current path in a current mirror manner as a fourth current source. 27. The device according to item 26 of the scope of the patent application, wherein the fourth current source is further connected in series with a resistor and a diode in order to convert the fourth current source into an electric dust source. 28. The device according to item 19 of the scope of patent application, wherein the second current source unit further couples the current flowing in the second current path in a current mirror manner as a fifth current. And the third current source unit A couples the current flowing in the third current path in a current mirror manner as a sixth current source; and then combines the fifth and sixth current sources Into a seventh current source. 第21頁Page 21
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI392219B (en) * 2008-12-01 2013-04-01 Silicon Motion Inc Low noise reference circuit of improving frequency variation of ring oscillator
TWI402657B (en) * 2009-01-28 2013-07-21 Univ Meiji Semiconductor device
TWI549406B (en) * 2015-11-20 2016-09-11 明緯(廣州)電子有限公司 Novel feedback circuit with temperature compensation function

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI392219B (en) * 2008-12-01 2013-04-01 Silicon Motion Inc Low noise reference circuit of improving frequency variation of ring oscillator
TWI402657B (en) * 2009-01-28 2013-07-21 Univ Meiji Semiconductor device
TWI549406B (en) * 2015-11-20 2016-09-11 明緯(廣州)電子有限公司 Novel feedback circuit with temperature compensation function

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