JPH01227520A - Power semiconductor device - Google Patents

Abstract

PURPOSE:To set a detecting voltage to be sufficiently large without deteriorating a current detecting accuracy by electric-connecting the output terminal of an arithmetic amplifier through a resistance for detecting a load current to the negative side input terminal. CONSTITUTION:The negative side input terminal of an arithmetic amplifier 5 is connected to a connecting point (c) of the source electrode of a DMOS 2 and a resistance 6 for detecting a load current, further, the output terminal is electric-connected through the resistance 6 to the negative side input terminal, and the output voltage of the arithmetic amplifier 5 is returned to the input side. At present, when the load current to flow to a load 4 is made into an excessive current, the current to divide-flow to the double diffusion type MOS transistor (DMOS) 2 is also made large, and a both- terminal voltage VS of the resistance is made large. However, the potentials at the connecting point (c) and a connecting point (d) are made equal by the negative feedback action of the arithmetic amplifier 5, and the voltages between the gates and sources of a DMOS 1 and the DMOS 2 are set to be equal. Thus, the detecting accuracy of the load current cannot be deteriorated by the degree of the both-terminal voltage VS of the resistance 6, and the voltage can be set at a value to be sufficiently large.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power semiconductor device, and particularly to a circuit configuration aimed at improving the detection accuracy of a load current flowing through a load.

[Conventional technology]

In recent years, power semiconductor devices use double-diffused MO3 transistors (hereinafter referred to as rDMs) for power parts.

The mainstream is the development of multi-functional devices in which power device protection circuits, other processing circuits, etc. are built into the same semiconductor substrate.

Among these protection circuits, the circuit that detects the load current flowing through the load and protects the power element, load, etc. from destruction due to overcurrent uses a portion of the cells of DMO3 for current detection.
For example, the circuit configuration is shown in FIG.

That is, DMO3IO0 and 101 are formed in the same semiconductor substrate, and among them, DMO3100 is configured as a power element that mainly controls the load current of load 102, and some
MO3l 01 is used for current detection, and those DMO
A resistor 103 for load current detection is inserted between the source (S) electrode of DMO3I01 and DMO3I01, and the state of the load current is determined by detecting the voltage across this resistor 103. Based on the voltage value, DMO3IO0, The gate voltage of the circuit 101 is controlled, which in turn controls the load current.

[Problem to be solved by the invention]

However, in the above circuit configuration, when using DMO3 as a power element for load current control, D
Since the drain (D) which is the substrate potential of MO3100 and DMO3101 is common, the potential difference generated in the resistor 103 is 8, and the gate (G)-source (S) threshold voltage of DMO3100 is 6,1 and that of DMO3101. A potential difference is generated between the gate and the source voltage vasz, which causes deterioration in detection accuracy. In addition, in order to improve detection accuracy, the detection voltage due to the voltage across the resistor 103, that is, the potential difference V, must be made as small as possible. There is a problem in that high-performance circuits are required, and the circuits become more complex.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is intended to improve the accuracy of current detection in a circuit configuration in which some of the cells of the power element for controlling load current are used for current detection as described above. It is an object of the present invention to provide a power semiconductor device that can provide a sufficiently large detection voltage without causing any deterioration.

[Means to solve the problem]

In order to achieve the above object, the power semiconductor device of the present invention includes a first voltage supply terminal, a second voltage supply terminal set to a lower potential than this terminal, and a first voltage supply terminal and a second voltage supply terminal. a first half-integral element that is electrically connected with a load between voltage supply terminals and mainly controls the load current flowing to the load; and a first half-integral element that is formed within the same semiconductor substrate as the first semiconductor element;
a second semiconductor element that shares a substrate potential with the first semiconductor element; a resistor electrically connected to the second semiconductor element; a positive input terminal thereof electrically connected to the first semiconductor element; and a negative input terminal thereof; an operational amplifier whose terminal is electrically connected between the second semiconductor element and the resistor, and whose output terminal is electrically connected to the negative input terminal via the resistor; detecting both life pressures of the resistor; The present invention is characterized in that it includes a control unit i that controls the load current by controlling the operating state layers of the first semiconductor element and the second semiconductor element based on the voltage value.

Furthermore, in such a power semiconductor device, the first semiconductor element and the second semiconductor element may be configured as double-diffused MOS transistors that share their drain potential; The semiconductor element may be configured as a high-side switch that is electrically connected closer to the first voltage supply terminal than the load, and further, the substrate potential is set to be the same potential as the potential of the first voltage supply terminal. You can.

Alternatively, the first semiconductor element may be configured as a load side switch that is electrically connected closer to the second voltage supply terminal than the load.

[Effect]

Therefore, according to the present invention, the first semiconductor element and the second semiconductor element are electrically connected to the positive input terminal and the negative input terminal of the operational amplifier, respectively, and the output terminal of the operational amplifier is connected to the load current detection resistor. Since the configuration is such that the operational amplifier is electrically connected to its negative input terminal, the connection point between the operational amplifier, the first semiconductor element, and the second semiconductor element is not affected by the potential difference due to resistance due to the negative chip feed bank operation of the operational amplifier. They have the same potential without being affected.

Therefore, the detection voltage set by the voltage across the resistor can be set to a sufficiently large value since load current detection accuracy is not deteriorated in any way depending on the magnitude of the voltage value.

〔Example〕

Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.

FIG. 1 is an electrical circuit diagram showing the configuration of a first embodiment of the present invention, and is an example in which an N-channel DMO 3 is used as a power element for controlling a load current, and the DMO 3 is used as a high-side switch.

In the figure, DMO3I and 0MO of N-type channel 71/
32 are formed in the same semiconductor substrate in the same manufacturing process,
They share a drain electrode (that is, a substrate potential), and a power supply voltage V is supplied to the drain potential from the first voltage supply terminal a.

Further, the ratio of the number of cells of DMO3I and DMOS2 is set to, for example, 3000 to 4000:1,
A current mirror circuit is configured to divide the current flowing from the first voltage supply terminal a according to the ratio of the number of cells. The gates of the DMO 31 and the 0MO 32 are electrically connected in common to the gate drive circuit 3, and when a high level signal is supplied from the gate drive circuit 3, they are turned on.

The source electrode of the DMO 3I is electrically connected to the load 4, and the load current flowing through the load 4 is mainly controlled by the operating state of the DMO 31. Further, the other terminal of the load 4 is connected to a ground line (GND) corresponding to the second voltage supply terminal according to the present invention.
) is electrically connected to. 0M031 source electrode and load 4
The connection point with is electrically connected to the positive input terminal of an operational amplifier (op-amp) 5.

Further, the negative input terminal of the operational amplifier 5 is electrically connected to the connection point C between the source electrode of the 0MO32 and the resistor 6 for detecting load current, and the output terminal is connected to the negative input terminal via the resistor 6. It is electrically connected and sends the output voltage of the operational amplifier 5 back to the input side.

The voltage across the resistor 6, ie, the voltage between the connection points c and d, is taken into the voltage control circuit 7, and the control circuit 7 outputs a control signal according to the detected voltage value to the gate drive circuit 3.

In the circuit configuration as described above, if the load current flowing to the load 4 becomes excessive due to some factor, the current shunted to the 0MO32 will also inevitably become thicker.
Therefore, the voltage across the resistor 6 increases. Then, when the control circuit 7 detects the voltage value and determines that it is an abnormal voltage value,
A control signal corresponding to the voltage value is output to the gate drive circuit 3.

Upon receiving a control signal from the gate drive circuit 31, DMO3I and 0MO32 (7) ON-OF are activated based on the control signal.
F control is performed to reduce the load current.

However, according to this embodiment, due to the negative feedback operation of the operational amplifier 5, the potentials at the connection point C and the connection point d become the same potential, and the gate-source voltage VG of the DMO3I
The gate-source voltages ves□ of MO31 and MO32 are set to be equal. Therefore, the problem of the prior art in which the magnitude of the voltage s across the resistor 6 affects the load current detection accuracy is solved, and in this embodiment, the magnitude of the voltage V across the resistor 6 is approximately equal to the power supply voltage . Since it can be freely set within the range of , the value Vs can be made sufficiently large, and the control circuit 7 that detects the value v3
The configuration can be made relatively simple.

Figure 2 shows the load current of the power semiconductor device according to this embodiment.
Detection voltage characteristics are shown, and FIG. 3 shows load current-detection voltage characteristics of the conventional power semiconductor device shown in FIG. 6. still,
This measurement result shows the gate-source voltage Vr of DMO3,
5=10V, junction temperature T.

= 25°C. In this way, according to this embodiment, even if the size of the resistor 6 is about R(6)=IKΩ,
While sufficient linearity can be obtained in the characteristics and the value of the detection voltage V can be set to a sufficiently large value, in the conventional example, when considering load current detection accuracy, temperature characteristics of the detected value, etc. The limit value of the size is approximately R(103) =
100Ω, and in that case, the limit of the detection voltage ■, is vs
=200 to 300IIlv. Comparing using specific values, the resistance for load current detection (103,
6) If the voltage across both ends (detection voltage VS) is received using a comparator, then the offset voltage is 10 mV.
Then, in the conventional example, when the detection voltage Vs=200mV,
The influence of offset voltage reaches as much as 5%. On the other hand, in this embodiment, when the power supply voltage is IOV, the detection voltage V can be set to approximately IOV, so the influence of the offset voltage can be reduced to only about 0.1%, compared to the conventional The detection accuracy can be significantly improved compared to the example.

Furthermore, in this embodiment, since the positive input terminal of the operational amplifier 5 is electrically connected to the connection point between the DMO 3I and the load 4, the voltage applied to the first voltage supply terminal a and the operational amplifier 5 are connected electrically. The voltage applied to power supply terminal e has the same voltage value (■.

Even in D), the detection voltage v3 can be set. Furthermore, DMO3I.

When DMost, 2 is in the ON state, the potential of the connection points S and C is set to approximately the power supply voltage v0, but even in that case, DMost, 2 is
In order to maintain the ON state, a booster circuit will be required in the gate drive circuit 3.

The voltage applied to the power supply terminal e of the operational amplifier 5 is particularly high when the potentials at points b and c fall within the input operating voltage.
Voltage V applied to voltage supply terminal a.

does not need to be equal to .

Next, the configuration of a second embodiment of the present invention will be explained using the electric circuit diagram shown in FIG. This second embodiment uses a P-type channel DMO3 as a power element for controlling load current,
This is an example in which the DMO3 is used as a high side switch. Note that the same components as in the first embodiment are given the same reference numerals.

In the figure, a configuration different from that of the first embodiment will be explained.

First, the P-type channel DMO310 and DMO3II share a drain electrode, and the load 4 is electrically connected to the drain electrode. In addition, the first voltage supply terminal a and the DMO
The positive input terminal of the operational amplifier 5 is electrically connected to the connection point f with the source electrode of the operational amplifier 5 .

Also in the second embodiment with the circuit configured in this way, D
Both the potentials of the connection points f and c electrically connected to the source electrode of MO3I0.11 can be made the same potential, and
The magnitude of the detection voltage V is the difference between the voltage VCC applied to the highest potential terminal e of the power supply of the operational amplifier 5 and the voltage VDII applied to the first voltage supply terminal a, that is, vcc Vf
It can be set freely within the range of ltl, and the value can be made sufficiently large.

In addition, in this embodiment, since a P-type channel is used as the DMO3 on the high side, the DMO310
A booster circuit is not required in the configuration of a gate drive circuit that gate-controls and 11. However, since the positive input terminal of the operational amplifier 5 is electrically connected between the first voltage supply terminal a and the DMO 310, Vα>vIID is the condition for setting the detection voltage V3, and therefore the power supply voltage (2) A circuit is required to set CC+v0 for each.

Next, the configuration of a third embodiment of the present invention will be explained using the electric circuit diagram shown in FIG. This third embodiment is an example in which an N-type channel DMO3 is used as a power element for controlling load current, and the DMO3 is used as a low side switch. Note that the same components as in the first embodiment are given the same reference numerals.

In the figure, a configuration different from that of the first embodiment will be explained.

First, the DMO 3I and DMO 32 connected between the first voltage supply terminal a and the ground line are electrically connected to the ground side, ie, the low side, of the load 4. Further, the positive input terminal of the operational amplifier 5 is electrically connected to the connection point g between the DMO 3I and the ground line.

Also in the third embodiment configured in this way, the DM
connection points g connected to the source electrodes of O3I,2, respectively;
The same potential of c can be made the same potential, and the detection voltage V
, is the difference between the negative voltage VSS applied to the lowest potential terminal of the power supply of the operational amplifier 5 and the ground potential, that is, 1V.
It can be set freely within the range of ssl, and the value can be set to a sufficiently large value.

In this embodiment, since an N-type channel DMO 3 is used on the low side, a booster circuit is not required in the configuration of the gate drive circuit for controlling the gates of the DMOs 3I and 12. However, since the positive input terminal of the operational amplifier 5 is electrically connected between the DMO 3l and the ground line, the ground potential G
The condition is ND>Vss, and therefore a circuit for setting the negative voltage VSS is required.

The present invention has been explained above using the first to third embodiments, but
The present invention is not limited thereto, and can be modified in various ways, for example as shown below, without departing from the spirit thereof.

■P-type channel D as a power element for load current control
A circuit configuration using MO3 as a low-side switch may also be used.

■The first semiconductor element and the second semiconductor element referred to in the present invention are semiconductor elements that have a current path in the vertical direction (thickness direction of the semiconductor substrate) in addition to the above-mentioned DMO3, and that share the substrate potential. Anything is fine (for example, VMO
3, or an insulated gate bipolar transistor that shares an anode potential can be used.

(2) The potential of the second voltage supply terminal in the present invention does not necessarily have to be the ground potential.

■As a gate drive circuit, set the gate potential of DMO3 to D
Possible options include utility control, fixed price control, etc. Further, as a method of controlling the operating state of the DMO 3, the power supply voltage supplied to the DMO 3 may be made variable.

〔Effect of the invention〕

As described above, according to the power semiconductor device of the present invention, the first semiconductor element and the second semiconductor element are electrically connected to the positive input terminal and the negative input terminal of the operational amplifier, respectively, and the output of the operational amplifier is Since the terminal is electrically connected to its negative input terminal via a resistor for detecting load current, current detection accuracy is not deteriorated (the detection voltage can be set sufficiently large, and This has the excellent effect of simplifying the subsequent circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram representing a first embodiment of the present invention, FIG. 2 is a load current-detected voltage characteristic diagram of the embodiment in FIG. 1,
FIG. 3 is a load current-detection voltage characteristic diagram of the conventional example in FIG. 6, and FIG. 4 is an electric circuit diagram showing the second embodiment of the present invention.
FIG. 5 is an electric circuit diagram showing a third embodiment of the present invention, and FIG. 6 is an electric circuit diagram showing a conventional example. 1.2...DMO3,3...gate drive circuit, 4.
...Load, 5...Operation amplifier, 6...Resistance, 7...
・Control circuit. Representative Patent Attorney Takashi Okabe 1.2. , DMOS 4--Ao5 ;1! Increase? ! 6 6-Ji pit (Example of 1st grade grass) Fig. 1 Negative 7 current (A) Fig. 2 AatI flow (A) (Conventional example) Fig. 3

Claims (6)

[Claims] (1) A first voltage supply terminal and a second voltage supply terminal set to a lower potential than this terminal, and electrically connected together with a load between the first voltage supply terminal and the second voltage supply terminal, and the current flows to the load. a first semiconductor element that mainly controls a load current; a second semiconductor element that is formed in the same semiconductor substrate as the first semiconductor element and shares a substrate potential with the first semiconductor element; A resistor to be electrically connected, its positive input terminal electrically connected to the first semiconductor element, its negative input terminal electrically connected between the second semiconductor element and the resistor, and its output terminal electrically connected to the resistor. an operational amplifier electrically connected to the negative input terminal via the resistor; A power semiconductor device comprising a control means for controlling load current. (2) The first semiconductor element and the second semiconductor element are
2. The power semiconductor device according to claim 1, which is a double-diffused MOS transistor that shares a drain potential. (3) The first semiconductor element and the second semiconductor element are
2. The power semiconductor device according to claim 1, which is an insulated gate bipolar transistor that shares an anode potential. (4) The first semiconductor element is lower than the load.
4. The power semiconductor device according to claim 1, wherein the power semiconductor device is electrically connected to the voltage supply terminal side. (5) The power semiconductor device according to claim 4, wherein the substrate potential is set to be the same potential as the potential of the first voltage supply terminal. (6) The first semiconductor element is lower than the second semiconductor element than the load.
4. The power semiconductor device according to claim 1, wherein the power semiconductor device is electrically connected to the voltage supply terminal side.