EP0609009A2

EP0609009A2 - Dual gate JFET circuit to control threshold voltage

Info

Publication number: EP0609009A2
Application number: EP94300383A
Authority: EP
Inventors: Doug R. Farrenkopf
Original assignee: National Semiconductor Corp
Current assignee: National Semiconductor Corp
Priority date: 1993-01-28
Filing date: 1994-01-19
Publication date: 1994-08-03
Also published as: EP0609009A3; JPH06303118A

Abstract

A monolithic integrated circuit includes a plurality of dual gate junction field effect transistors. One is selected as a standard transistor and its current is passed through a first resistor. A reference current is passed through a second resistor. The two resistors are coupled to the inputs of an op-amp, the output of which is coupled to one gate of the standard transistor. The other gate of the standard transistor is supplied with a bias voltage selected to operate the transistor in the conducting mode. Thus, the standard transistor forms a negative feedback loop around the op-amp. As a result, the standard transistor will pass a current related to the reference current in a ratio determined by the ratio of the resistor values. The op-amp output can then be coupled to the other gates in all of the other transistors in the integrated circuit. Accordingly, all of the transistors will have their operating currents the same as that of the standard transistor at the same operating bias. This means that all of the transistors display the same effective threshold voltage.

Description

Background of the Invention

The invention relates to junction field effect transistor (JFET) devices and, in particular, to dual gate devices. Such transistors have a pair of gate terminals along with the source and drain elements. JFET devices are common in integrated circuit (IC) structures where both field effect and bipolar transistors are fabricated into a single IC chip. One such series of devices has been trademarked as BIFET® operational amplifiers (op amps).
A JFET device has a property known as the threshold voltage (V_T), which is the gate voltage at which source-drain conduction starts. This voltage is a function of the device geometry and the nature of the associated semiconductor regions. Thus, it is extremely process sensitive.
Clearly, when turned on, the amount of JFET conduction will also be a process related variable because the current flowing in a JFET is proportional to the square root of the difference between the gate bias and V_T. Because of processing variations, V_T varies, and so does the amount of conduction at a particular gate bias.
Thus, it would be desirable to control the conduction of a JFET at a particular gate bias thereby, in effect, to control V_T.
A JFET can have more than one gate and such devices are known as plural-gate devices. In the well known BIFET® op-amps, a subsurface channel has a PN junction gate electrode facing it. The gate itself acts to locate the channel below the semiconductor surface. The opposite face of the channel encounters what is known as the "back gate". In IC fabrication, both the gate and the back gate connections can be made available at the IC surface so that a dual gate structure is present.
While BIFET® IC op-amp construction is preferred, it is to be understood that the gate itself can be fabricated as a two-element device. A pair of gates together span one face of the channel region and operate in concert to control the JFET conduction. This effectively produces a pair of series-connected JFET elements. The opposite side of the channel faces a semiconductor region to form a back gate that is typically connected to the transistor source. In operation each gate electrode has its own V_T and both of the individual JFET gates must be biased above V_T for conduction to occur.
In the discussion to follow, where a dual-gate JFET is described, the first gate can be of either a top or front gate with respect to a second bottom or back gate, as in the BIFET® op amp IC construction, or it can be a more conventional JFET having a succession of individual gates facing a common channel, where there is a common backgate opposite to the individual gates.

Summary of the Invention

It is an object of the invention to employ a plurality of dual gate JFETs in an IC and to connect one into a reference circuit which biases it into a controlled state of conduction and the reference circuit can be used to bias all of the other JFETs to control their threshold voltage.
It is a further object of the invention to employ a dual gate JFET, having a first gate biased above V_T and the second gate biased by a diff-amp which is coupled to both a reference current and the JFET current so that the bias on the second gate is forced to a voltage which provides for the JFET current proportional to the reference current and the resultant voltage coupled to the equivalent gates on all of the other JFET devices in the IC.
These and other objects are achieved as follows. A plurality of dual-gate JFETs are incorporated on an IC chip. These devices can be of the conventional side by side gate construction where the two gates together span the channel region. In the preferred embodiment, the devices can be of conventional gate construction wherein the gate forms a PN junction with the channel and spans the channel length. The reverse side of the channel faces the semiconductor material into which the JFET is fabricated and which forms a back gate electrode that is electrically isolated from the front gate. One such dual-gate transistor is selected out of the plurality and it can be assumed that this selected transistor is representative of all of the JFETs on the IC chip. This is a reasonable assumption because the process variables, which give rise to altered electrical characteristics, will apply equally to all of the devices on the IC chip. The source of the selected transistor is returned to a first terminal of a suitable operating power supply. The selected transistor has a predetermined potential applied to the front, or the first, of the two gates. This potential is selected to produce a gate turn-on condition in the transistor.
The selected transistor drain is returned to the second operating power supply terminal by a first resistor. A second resistor is connected between the second operating power supply terminal and a constant current supply that is coupled to the source potential. The two resistors are connected to the inputs of an op-amp, the output of which is connected to the back or second gate of the selected transistor. The selected transistor drain is connected to the op-amp inverting input so that a negative feedback loop is present. Thus, the op-amp output will drive the selected transistor second gate until the op-amp inputs are equal. If the two resistors are of equal value the selected transistor will be forced to conduct a channel current that equals the current in the constant current source connected to the second resistor. If the second or back gates of all of the dual-gate JFETs on the IC chip are connected to the op-amp output all of the JFETs will have the same V_T and will all conduct substantially the same current when turned on by an equal bias applied to their first gates. Since the JFET gates draw substantially zero current, a relatively large number of them can be simultaneously driven from a single op-amp.

Brief Description of the Drawing

Figure 1 is a block-schematic diagram of the circuit of the invention using dual gate P channel transistors.
Figure 2 is a partial schematic diagram showing of a dual-gate N channel transistor.

Description of the Invention

With reference to figure 1, a circuit is shown operated by a V_DD power supply connected + to terminal 10 and - to ground terminal 11. JFET 12 is a dual gate p channel transistor with its source connected to the +V_DD rail. It has its first gate connected to terminal 13 which is typically supplied with a positive V_BIAS potential. V_BIAS is selected so that the first gate is biased below the gate threshold (V_T). In figure 1, a p-channel JFET is shown. In this case, when V_BIAS is below V_T, there is conduction, while when V_BIAS is above V_T, the device is cut off. A constant current source 16, which is connected to + V_DD, is coupled to resistor 15, which acts as a ground return, and, therefore, I₂ will flow in resistor 15. Op-amp 17 has its input terminals connected to resistors 14 and 15 and its output connected to the back or second gate of JFET 12. Since the drain of JFET 12 is connected to the op-amp noninverting input, a negative feedback loop is present. Op-amp 17 will drive the second gate of JFET 12 until the potentials across resistors 14 and 15 are equal. If resistors 14 and 15 are matched I₁ will be equal to I₂. Thus, I₂ can be selected to produce the desired value of I₁.
A second p-channel JFET is shown in dashed outline at 18 and it passes I₃. This device is intended to represent one or a plurality of other JFETs on an IC chip. When V_IN equals V_BIAS, each of these devices will pass I₃ which is determined by I₂. Since all of the JFETs on a chip are subjected to the same fabrication conditions any fabrication-induced parameters, such as V_T, will be substantially the same. As a result, all of the transistors on the chip will be forced to conduct a current proportional to I₁ when their first gates are biased at the potential of V_BIAS. Since a JFET current is proportional to the square root of the difference between the applied bias and V_T, the V_T values of the JFETs will be controlled to match.
Since op-amp 17 can produce a substantial output current and since the JFETs connected thereto draw essentially zero current, as many JFETs as desired can be controlled by a single op-amp. Accordingly, the circuit shown requires only a single op-amp on the IC chip.
It is to be understood that while resistors 14 and 15 are described as matched, this is convenience, not a necessity. These resistors can be ratioed, in which case I₁ and I₂ will have the same ratio.
Figure 2 is a partial schematic showing an N channel dual gate transistor 12'. Its source is connected to a negative supply potential. (The power supply has a reverse polarity from that of figure 1.) The drain of transistor 12' is connected to a resistor 14 which acts as a ground return to the positive power supply terminal. Thus, electrons from the - V_DD supply flow as I₁ in resistor 14.

Example

By way of example, a circuit was constructed, as shown in figure 1, wherein resistors 14 and 15 were made to have values of 100K ohms and current source 16 operated at 10 micro-amperes. V_BIAS was set at a level of two volts below + V_DD. A 10 microampere current flowed in transistor 12. Therefore, a 10 microampere current would flow in any similar JFET (such as 18) that has its first gate biased at the V_BIAS level. The result is that all of the JFETs having their second gates connected to op-amp 17, as shown, have the same V_T values for their first gates.
The invention has been described and a preferred embodiment detailed. Alternatives have also been described. When a person skilled in the art reads the foregoing description, other alternatives and equivalents, within the spirit and intent of the invention, will be apparent. Accordingly, it is intended that the scope of the invention be limited only by the claims that follow.

Claims

An integrated circuit that includes a first junction field effect transistor (12) and at least one other junction field effect transistor (18), each such transistor being constructed to have first and second gates which, in combination, determine the transistor's conduction, characterised by: means (17) for comparing current flow through the second gate of the first transistor with a reference to develop an error signal which is coupled to the first gate of the first transistor whereby to force the first transistor to conduct a current related in value to the reference and means for connecting the second gate of each other transistor to receive the said error signal so that the said transistors all conduct currents related to the reference.
An integrated circuit that includes a plurality of junction field effect transistors are incorporated into a single chip and are constructed to have first and second gates which, in combination, determine the transistor conduction, characterised by:
first and second resistors (14,15), a first of the said transistors (12) being connected to pass its current through said first resistor;
means (13) for applying a bias to said first gate on said first transistor which produces a turn-on bias greater than the transistor threshold voltage on an N-channel JFET, or less than the transistor threshold voltage in the case of a P-channel JFET;
means (16) for passing a reference current through said second resistor;
an operational amplifier (17) having inverting and non-inverting inputs and an output coupled to said second gate of said standard transistor;
means connecting one each of the inputs of the operational amplifier to the said resistors, whereby said first transistor is forced to conduct a current related to said reference current; and
means for connecting the second gates of other transistors on said chip to said operational amplifier whereby said other transistors have their first gate threshold voltages the same as that of said first transistor.
A circuit according to claim 1 or 2 wherein said junction field effect transistors are formed to have first and second gates spaced along one face of a channel and a common back gate spanning the opposite face of said channel.
A circuit according to claim 1 or 2 said junction field effect transistors are formed to have said first gate spanning one face of a channel and said second gate spanning the opposite face of said channel.
A circuit according to claim 2 wherein said first and second resistors are matched and said other transistors pass a current equal to said first transistor's current when their first gates are biased at the level of said first transistor's first gate.
A circuit according to claim 2 wherein said first and second resistors are ratioed and said other transistors have their currents proportional to said first transistor's current multiplied by said ratio when said first gates are biased at the level of said first transistor's first gate.