EP0609009A2 - Doppelgate-JFET Schaltung zur Steuerung von Schwellspannungen - Google Patents

Doppelgate-JFET Schaltung zur Steuerung von Schwellspannungen Download PDF

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Publication number
EP0609009A2
EP0609009A2 EP94300383A EP94300383A EP0609009A2 EP 0609009 A2 EP0609009 A2 EP 0609009A2 EP 94300383 A EP94300383 A EP 94300383A EP 94300383 A EP94300383 A EP 94300383A EP 0609009 A2 EP0609009 A2 EP 0609009A2
Authority
EP
European Patent Office
Prior art keywords
transistor
gate
transistors
current
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94300383A
Other languages
English (en)
French (fr)
Other versions
EP0609009A3 (de
Inventor
Doug R. Farrenkopf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of EP0609009A2 publication Critical patent/EP0609009A2/de
Publication of EP0609009A3 publication Critical patent/EP0609009A3/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only

Definitions

  • JFET junction field effect transistor
  • op amps BIFET® operational amplifiers
  • V T threshold voltage
  • the amount of JFET conduction will also be a process related variable because the current flowing in a JFET is proportional to the square root of the difference between the gate bias and V T . Because of processing variations, V T varies, and so does the amount of conduction at a particular gate bias.
  • a JFET can have more than one gate and such devices are known as plural-gate devices.
  • a subsurface channel has a PN junction gate electrode facing it.
  • the gate itself acts to locate the channel below the semiconductor surface.
  • the opposite face of the channel encounters what is known as the "back gate”.
  • both the gate and the back gate connections can be made available at the IC surface so that a dual gate structure is present.
  • each gate electrode has its own V T and both of the individual JFET gates must be biased above V T for conduction to occur.
  • the first gate can be of either a top or front gate with respect to a second bottom or back gate, as in the BIFET® op amp IC construction, or it can be a more conventional JFET having a succession of individual gates facing a common channel, where there is a common backgate opposite to the individual gates.
  • a plurality of dual-gate JFETs are incorporated on an IC chip. These devices can be of the conventional side by side gate construction where the two gates together span the channel region. In the preferred embodiment, the devices can be of conventional gate construction wherein the gate forms a PN junction with the channel and spans the channel length. The reverse side of the channel faces the semiconductor material into which the JFET is fabricated and which forms a back gate electrode that is electrically isolated from the front gate.
  • One such dual-gate transistor is selected out of the plurality and it can be assumed that this selected transistor is representative of all of the JFETs on the IC chip. This is a reasonable assumption because the process variables, which give rise to altered electrical characteristics, will apply equally to all of the devices on the IC chip.
  • the source of the selected transistor is returned to a first terminal of a suitable operating power supply.
  • the selected transistor has a predetermined potential applied to the front, or the first, of the two gates. This potential is selected to produce a gate turn-on condition in the transistor.
  • the selected transistor drain is returned to the second operating power supply terminal by a first resistor.
  • a second resistor is connected between the second operating power supply terminal and a constant current supply that is coupled to the source potential.
  • the two resistors are connected to the inputs of an op-amp, the output of which is connected to the back or second gate of the selected transistor.
  • the selected transistor drain is connected to the op-amp inverting input so that a negative feedback loop is present. Thus, the op-amp output will drive the selected transistor second gate until the op-amp inputs are equal. If the two resistors are of equal value the selected transistor will be forced to conduct a channel current that equals the current in the constant current source connected to the second resistor.
  • Figure 1 is a block-schematic diagram of the circuit of the invention using dual gate P channel transistors.
  • Figure 2 is a partial schematic diagram showing of a dual-gate N channel transistor.
  • JFET 12 is a dual gate p channel transistor with its source connected to the +V DD rail. It has its first gate connected to terminal 13 which is typically supplied with a positive V BIAS potential. V BIAS is selected so that the first gate is biased below the gate threshold (V T ).
  • V T gate threshold
  • a p-channel JFET is shown. In this case, when V BIAS is below V T , there is conduction, while when V BIAS is above V T , the device is cut off.
  • a constant current source 16 which is connected to + V DD , is coupled to resistor 15, which acts as a ground return, and, therefore, I2 will flow in resistor 15.
  • Op-amp 17 has its input terminals connected to resistors 14 and 15 and its output connected to the back or second gate of JFET 12. Since the drain of JFET 12 is connected to the op-amp noninverting input, a negative feedback loop is present. Op-amp 17 will drive the second gate of JFET 12 until the potentials across resistors 14 and 15 are equal. If resistors 14 and 15 are matched I1 will be equal to I2. Thus, I2 can be selected to produce the desired value of I1.
  • a second p-channel JFET is shown in dashed outline at 18 and it passes I3.
  • This device is intended to represent one or a plurality of other JFETs on an IC chip.
  • V IN equals V BIAS
  • each of these devices will pass I3 which is determined by I2. Since all of the JFETs on a chip are subjected to the same fabrication conditions any fabrication-induced parameters, such as V T , will be substantially the same. As a result, all of the transistors on the chip will be forced to conduct a current proportional to I1 when their first gates are biased at the potential of V BIAS . Since a JFET current is proportional to the square root of the difference between the applied bias and V T , the V T values of the JFETs will be controlled to match.
  • op-amp 17 can produce a substantial output current and since the JFETs connected thereto draw essentially zero current, as many JFETs as desired can be controlled by a single op-amp. Accordingly, the circuit shown requires only a single op-amp on the IC chip.
  • resistors 14 and 15 are described as matched, this is convenience, not a necessity. These resistors can be ratioed, in which case I1 and I2 will have the same ratio.
  • Figure 2 is a partial schematic showing an N channel dual gate transistor 12'. Its source is connected to a negative supply potential. (The power supply has a reverse polarity from that of figure 1.)
  • the drain of transistor 12' is connected to a resistor 14 which acts as a ground return to the positive power supply terminal. Thus, electrons from the - V DD supply flow as I1 in resistor 14.
  • a circuit was constructed, as shown in figure 1, wherein resistors 14 and 15 were made to have values of 100K ohms and current source 16 operated at 10 micro-amperes.
  • V BIAS was set at a level of two volts below + V DD .
  • a 10 microampere current flowed in transistor 12. Therefore, a 10 microampere current would flow in any similar JFET (such as 18) that has its first gate biased at the V BIAS level.
  • JFET such as 18

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electronic Switches (AREA)
EP9494300383A 1993-01-28 1994-01-19 Doppelgate-JFET Schaltung zur Steuerung von Schwellspannungen. Withdrawn EP0609009A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1038093A 1993-01-28 1993-01-28
US10380 1993-01-28

Publications (2)

Publication Number Publication Date
EP0609009A2 true EP0609009A2 (de) 1994-08-03
EP0609009A3 EP0609009A3 (de) 1994-11-02

Family

ID=21745505

Family Applications (1)

Application Number Title Priority Date Filing Date
EP9494300383A Withdrawn EP0609009A3 (de) 1993-01-28 1994-01-19 Doppelgate-JFET Schaltung zur Steuerung von Schwellspannungen.

Country Status (2)

Country Link
EP (1) EP0609009A3 (de)
JP (1) JPH06303118A (de)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7808415B1 (en) 2009-03-25 2010-10-05 Acco Semiconductor, Inc. Sigma-delta modulator including truncation and applications thereof
US8008731B2 (en) 2005-10-12 2011-08-30 Acco IGFET device having a RF capability
US8334178B2 (en) 2008-02-13 2012-12-18 Acco Semiconductor, Inc. High breakdown voltage double-gate semiconductor device
US8928410B2 (en) 2008-02-13 2015-01-06 Acco Semiconductor, Inc. Electronic circuits including a MOSFET and a dual-gate JFET
US9240402B2 (en) 2008-02-13 2016-01-19 Acco Semiconductor, Inc. Electronic circuits including a MOSFET and a dual-gate JFET

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0375124A1 (de) * 1988-12-20 1990-06-27 Tektronix Inc. Vorspannungsgenerator für Komparator CMOS
EP0446595A2 (de) * 1990-03-12 1991-09-18 Texas Instruments Incorporated Pufferschaltung
EP0531101A2 (de) * 1991-09-05 1993-03-10 TriQuint Semiconductor, Inc. Geräuscharme Vorspannungschaltung für Mehrfachstromquelle

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0375124A1 (de) * 1988-12-20 1990-06-27 Tektronix Inc. Vorspannungsgenerator für Komparator CMOS
EP0446595A2 (de) * 1990-03-12 1991-09-18 Texas Instruments Incorporated Pufferschaltung
EP0531101A2 (de) * 1991-09-05 1993-03-10 TriQuint Semiconductor, Inc. Geräuscharme Vorspannungschaltung für Mehrfachstromquelle

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8008731B2 (en) 2005-10-12 2011-08-30 Acco IGFET device having a RF capability
US8334178B2 (en) 2008-02-13 2012-12-18 Acco Semiconductor, Inc. High breakdown voltage double-gate semiconductor device
US8928410B2 (en) 2008-02-13 2015-01-06 Acco Semiconductor, Inc. Electronic circuits including a MOSFET and a dual-gate JFET
US9240402B2 (en) 2008-02-13 2016-01-19 Acco Semiconductor, Inc. Electronic circuits including a MOSFET and a dual-gate JFET
US7808415B1 (en) 2009-03-25 2010-10-05 Acco Semiconductor, Inc. Sigma-delta modulator including truncation and applications thereof

Also Published As

Publication number Publication date
EP0609009A3 (de) 1994-11-02
JPH06303118A (ja) 1994-10-28

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