KR20000075637A - Current-limit circuit - Google Patents

Abstract

The present invention relates to a current limiter circuit for a controlled semiconductor power element 60, in particular a current limiter circuit for a power transistor independent of voltage supply. This is controlled semiconductor power including a detection resistor 20 connected in series with the main current path of the controlled semiconductor power element 60 to generate a voltage drop indicative of a current flowing through the controlled semiconductor power element 60. Element 60, in particular a current limiter circuit for the power transistor. The current limiter circuit also generates a first current source device 31 for generating a first current between the first and second reference potentials, a second current between the control potential of the gate terminal of the semiconductor power element and the third reference potential. And a current balancing circuit device 30 having a second current source device 32 to make it. The current limiter circuit also has a first and first response in response to the voltage drop of the detection resistor, in order to limit the current flowing through the semiconductor power element by increasing the second current to lower the control potential if the voltage drop is greater than the predetermined value. A current source coupling circuit 33 for coupling the two current source devices 31, 32.

Description

Current limiter circuit {CURRENT-LIMIT CIRCUIT}

Integrated circuits must be effectively protected from current overloads, but are not destroyed by heat in the event of a short circuit.

Although the present invention and the problems it is based on can be applied basically to all controlled semiconductor power devices, reference is made to power integrated circuits of a mixed technology provided with bipolar devices and CMOS devices in addition to MOS power transistors.

A common basic principle of such a current limiter circuit is that a part of the total current causes a voltage drop in a resistor (called a shunt resistor) by the total current flowing through the power transistor or the sense cell principle.

When the voltage drop exceeds a predetermined maximum value, the control signal of the power transistor is provided to the current limiter circuit, so that the output current of the power transistor, which can be determined by the output characteristic curve field from the control signal, is kept below the allowable limit.

A series of methods for circuit technically implementing the basic principle are known in the prior art.

In general, a current control limiter circuit and a voltage control limiter circuit are distinguished.

Current control limiter circuits generally require a filter to mask the connection peaks. The voltage control limiter circuit requires a temperature compensation circuit. In addition, both types of known circuits require complex short-circuit connection itself.

Examples of such prior art are B. Murari, F. Bertotti and G.A. Vignola, "Smart Power ICs-Techologies and Applications", pages 328, 400, 426, Springer Verlag, Berlin-Heidelberg-New York, 1996.

The present invention relates to a controlled current limiter circuit for semiconductor power devices, in particular a current limiter circuit for power transistors.

1 is a blow circuit diagram of a current limiter circuit according to the present invention;

2 is a circuit diagram of a first embodiment of a current limiter circuit according to the present invention;

3 is a circuit diagram of a second embodiment of a current limiter circuit according to the present invention;

4 is a circuit diagram of a third embodiment of a current limiter circuit according to the present invention;

5 is a circuit diagram of a conventional reference current source circuit as an output point for the present invention.

It is an object of the present invention to provide a current limiter circuit that can be simply implemented and preferably operates independently of its voltage supply.

The object according to the present invention

A detection resistor connected in series with the main current path of the controlled semiconductor power element to generate a voltage drop indicative of a current flowing through the controlled semiconductor power element; And

a) a first current source device for generating a first current between the first and second reference potentials;

b) a second current source device for generating a second current between the control potential of the control terminal of the semiconductor power element and the third reference potential; And

c) if the voltage drop is greater than the predetermined value, the first and second current source devices in response to the voltage drop of the detection resistor, in order to limit the current flowing through the semiconductor power element by increasing the second current to lower the control potential. Current source coupling circuit for coupling

It is achieved by a current limiter circuit for a controlled semiconductor power element, in particular for a power transistor, characterized in that it comprises a current balancing circuit arrangement with.

Preferred embodiments are presented in the dependent claims.

According to a preferred embodiment, the first current source device comprises first and second bipolar transistors wired such that collector currents are proportional to each other; The second current source device includes third and fourth bipolar transistors. The third bipolar transistor applies a current that is proportional to the collector current of the fourth bipolar transistor; The emitter-base voltage of the fourth bipolar transistor is the voltage component, the voltage drop in the detection resistor, the emitter-base voltage of the second and third bipolar transistors with a positive sign and the emitter- of the first bipolar transistor with a negative sign. It includes the base voltage.

According to a preferred embodiment at least one of the four bipolar transistors has a different emitter surface than the other bipolar transistors.

According to another preferred embodiment, the emitter-base voltage of the fourth bipolar transistor comprises an additional constant voltage component, the value of the voltage component being the emitter-base of the additional bipolar transistor operating at a different emitter current density. Is obtained from the difference in voltage.

According to another preferred embodiment, the current balancing circuit device

First and second bipolar transistors connected in series between a first reference potential and a terminal of a detection resistor connected to a source terminal of the semiconductor power element with one current source, and

Third and fourth bipolar transistors connected in series between the control potential and the third reference potential,

The collector and base of the first bipolar transistor are connected together, the base of the first and third bipolar transistors are connected together,

The base of the second bipolar transistor is connected to a node lying between the emitter of the third bipolar transistor and the collector of the fourth bipolar transistor,

The base of the fourth bipolar transistor is connected to a node lying between the emitter of the first bipolar transistor and the collector of the second bipolar transistor.

According to another preferred embodiment, the current balancing circuit device

First and second bipolar transistors connected in series between a first reference potential and a terminal of a detection resistor connected to a source terminal of the semiconductor power element with one current source, and

Third and fourth bipolar transistors connected in series between the control potential and the third reference potential,

The collector and base of the first bipolar transistor are connected together and the base of the first and third bipolar transistor are connected together,

A fifth and sixth bipolar transistor connected in series with an associated current source between the first and second reference potentials,

The base of the second bipolar transistor is connected to a node lying between the emitter of the fifth bipolar transistor and a corresponding current source and the base of the fifth bipolar transistor lies between the emitter of the third bipolar transistor and the collector of the fourth bipolar transistor. Connected to the node,

The base of the fourth bipolar transistor is connected to a node connected between the emitter of the sixth bipolar transistor and the corresponding current source, and the base of the sixth bipolar transistor is between the emitter of the first bipolar transistor and the collector of the second bipolar transistor. It is connected to the connected node.

In this embodiment, the sensitivity of the current limiter circuit according to the present invention is increased.

According to another preferred embodiment, the current sources of the fifth and sixth bipolar transistors are each one resistor.

According to another preferred embodiment, the current sources of the fifth and sixth bipolar transistors are each NMOS transistors.

According to another preferred embodiment, the common gate potential of the NMOS transistors is the potential of the common base terminal of the first and third bipolar transistors.

According to a preferred embodiment, the current balancing circuit arrangement

A first current balance circuit, consisting of first and second PNP bipolar transistors, having a emitter connected to a control potential of the semiconductor power element,

A second current balancing circuit, consisting of third and fourth PNP bipolar transistors, having an emitter connected to the control potential of the semiconductor power element,

A third current balancing circuit, consisting of first and second MOS transistors, having a source connected to a reference potential,

A fourth current balancing circuit, consisting of third and fourth MOS transistors, having a source connected to a reference potential,

A first NPN-bipolar transistor having an emitter connected to the drain of the third MOS transistor,

A second NPN bipolar transistor connected between the collector of the fourth PNP bipolar transistor and the terminal of the detection resistor connected to the semiconductor power element,

A third NPN bipolar transistor having an emitter connected to the drain of the second MOS transistor,

A fourth NPN bipolar transistor connected between the collector of the first PNP bipolar transistor and the terminal of the detection resistor connected to the load output terminal,

The base terminals of the first and third NPN bipolar transistors are connected together and the collector terminals of the first and third NPN bipolar transistors are connected via a diode to the control potential of the semiconductor power element in the flow direction,

The emitter of the first NPN bipolar transistor is connected to the base of the fourth NPN bipolar transistor and the emitter of the third NPN bipolar transistor is connected to the base of the second NPN bipolar transistor,

A fifth and sixth MOS transistor connected in series between the reference potential of the fourth current balancing circuit and the terminals of the semiconductor power element connected to the supply potential,

The gate of the fifth MOS transistor is connected to the collector of the third PNP bipolar transistor, the gate of the sixth MOS transistor is connected to the control potential of the semiconductor power element,

A node between the fifth and sixth MOS transistors is connected to a common base of the first and third NPN bipolar transistors.

This embodiment is particularly suitable for highside switches.

Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings.

In the drawings, the same parts or the same parts have the same reference numerals.

The current limiter circuit according to the present invention assumes the conventional reference current source circuit shown in FIG.

5 shows NPN bipolar transistors 51, 52, 53, 54. Transistors 52, 54, 51, and 53 are connected in series and define the first and second main current paths 501 or 502, respectively.

The first main current path 501 is connected between the positive battery potential V _B and the negative battery potential (ground) and includes a constant current source 56.

The emitter surfaces of transistors 52 and 51 have a ratio of m: 1, and the emitter surfaces of transistors 54 and 53 have a ratio of 1: n. Ignoring all base currents, the collector current of transistors 54 and 52 and the collector current of transistors 53 and 51 are equal.

Independent of the current in paths 501 and 502, with an exponential relationship of collector current to emitter base voltage, typical for bipolar transistors from cross coupling of transistors 54 and 53

U _R = ln (m · n) · kT / e

The difference between the emitter potentials of the transistors 53 and 54 is shown.

The difference in emitter potential U _R is at the same time the voltage drop U _R at the resistor 55 placed in the current path 502. Accordingly, the resistance value of the resistor 55 determines the current I _{ref that} can be drawn at the output regardless of the current of the current source 56.

1 is a block diagram of a current limiter circuit according to the present invention.

A current limiter circuit for a controlled semiconductor power element, according to the present invention, shown in FIG. 1, is provided in a MOS power transistor 60.

The detection resistor 20 is connected in series with the main current path of the MOS power transistor 60 to generate a voltage drop representing the current flowing through the MOS power transistor 60.

The current balancing circuit arrangement 30 generates a first current between the first reference potential and the second reference potential, here between the positive battery voltage V _B and the negative battery voltage (ground), by the detection resistor 20. And a first current source device 31 for the purpose.

The current balancing circuit device 30 also includes a second current source device 32 for generating a second current between the control potential V _G of the control terminal of the MOS power transistor 60 and the third reference potential (here, ground). ).

Finally, the current balancing circuit device 30 is provided with a current source coupling circuit 33 for coupling the first and second current source devices 31, 32 in response to the voltage drop of the detection resistor. The current source coupling circuit 33 operates so that the current flowing through the semiconductor power element is limited by increasing the second current for lowering the control potential if the voltage drop is greater than the predetermined value.

2 shows a circuit diagram of a first embodiment of a current limiter circuit according to the present invention.

2 shows NPN bipolar transistors 51 ', 52', 53 'and 54'. Transistors 52 ', 54' and 51 ', 53' are respectively connected in series and define first and second main current paths 501 'and 502'.

The first main current path 501 'is connected between the positive battery potential V _B and the negative battery potential (ground) and includes a constant current source 56' and a resistor 55 '.

The second main current path 502 'is connected between the control terminal of the MOS power transistor 60 and the negative battery potential (ground). Current I _A is applied to a control signal source that supplies a control potential V _G via a second main current path 502 ′.

The emitter surfaces of transistors 52 'and 51' have a ratio of 1: m, and the emitter surfaces of transistors 54 'and 53' have a ratio of n: 1.

Applying the equation applied to the circuit similarly to the current source circuit according to FIG. 5 described above, the transistors 54 'and 53' are independent of the current ratios in the paths 501 'and 502'. About difference of emitter potential

U _R '= ln (m · n) kT / e

Is obtained.

The difference in emitter voltage is applied to the detection resistor 55 'as a voltage drop U _R '.

If the voltage drop U _R ′ is not ln (m · n) · kT / e, the currents in the paths 501 'and 502' may differ from each other so that the base current can no longer be ignored. .

If (U _R ′) is smaller than ln (m · n) · kT / e, the current at branch 502 'has a value that is one to two orders of magnitude smaller than the current given previously at branch 501'.

If the voltage U _R ′ is greater than ln (m · n) · kT / e, the current in the path 502 'increases in units of tens of millivolts within the voltage fluctuation range.

The present invention utilizes the above characteristics so that the current in the path 502 'is used to reduce the control potential of the semiconductor power switch so that an accurate and delay-free current limit is achieved.

A resistor 55 'connected between transistor 54' and ground is connected in series with the main current path of controlled MOS power transistor 60, resulting in a voltage drop indicative of the current flowing through it.

2 shows that the resistor 55 'is provided as a shunt resistor instead of the resistor 55 according to FIG. 5, and that the load current flows through the resistor and the reference current source circuit shown in FIG. different. The resistor acts like a voltage source that depends on the load current due to the lower order resistance value. In addition, the emitter ratio is different from that of FIG. 5.

Due to the internal coupling of the two current paths 501 'and 502', if the voltage drop U _R 'at the resistor 55' is less than ln (m * n) kT / e, The output current I _A flowing through the two current paths 502 'is much smaller than the input current flowing through the first current path 501'.

On the other hand, if the voltage drop at the resistor 55 'is greater than ln (m) n kT / e, then the output current I _A flowing through the second current path 502' is the first current path 501. Much greater than the input current flowing through ').

In the range of voltage drop with the value of ln (m · n) · kT / e, the output current increases by several tens of units within the range of voltage drop variation of several millivolts.

Therefore, if the input current is correctly selected according to the order and the output current I _A is branched from the control terminal of the MOS power transistor 60, a predetermined current limit can be achieved.

3 shows a second embodiment of a current limiter circuit according to the invention.

The second embodiment is an extension of the first embodiment shown in FIG. 2 and additionally includes NPN bipolar transistors 59 'and 60' and current sources 57 'and 58'.

The additional device is used for the modified coupling of the first and second current paths 501 'and 502'.

In particular, in the second embodiment, the base of the second transistor 54 'is connected between the emitter of the third transistor 51' and the collector of the fourth transistor 53 'as in the first embodiment. An additional current conversion stage consisting of a transistor 60 'and a current source 58' is connected between them.

Similarly, in the second embodiment the node of the fourth transistor 54 'is connected between the emitter of the first transistor 52' and the collector of the second transistor 54 'as in the first embodiment. An additional current conversion stage consisting of a transistor 59 'and a current source 57' is connected between them.

The emitter surface ratio between the current conversion stage consisting of transistor 60 'and current source 58' and the current conversion stage consisting of transistor 59 'and current source 57' is 1: 1. The ratio of the currents generated by the current sources 58 'and 57' is 1: k.

According to the second embodiment of the present invention, the circuit shown in FIG. 3 enables the sudden rise of the output current I _A in the range of voltage drop with the value of ln (m · n · k · l) · kT / e. This is because the two current conversion stages introduce third and fourth factors into the log, which allows for a larger voltage drop U _R ′ in the resistor 55 ′.

Additional current conversion stages can continuously increase the relative accuracy of the circuit.

Current sources 58 'and 57' with emitter ratio 1: k can be formed as resistors in the simplest case, preferably NMOS transistors. As the common gate potential of the NMOS transistor, the common base terminals of the transistors 52 'and 51' are used.

4 is a circuit diagram of a third embodiment of a current limiter circuit according to the present invention.

The above-mentioned first and second embodiments are preferably used for a lowside-switch, while the third embodiment described below relates in particular to a highside-switch.

In the high side switch, no potential is supplied to the source terminal of the MOS power transistor 60 connected to the control signal and the load of the MOS power transistor 60. Therefore, in such a high-side switch, the control potential and the source potential become negative when the inductive load is interrupted, so that the base of the collector and the lateral PNP transistor of the NPN transistor is connected to the source or gate of the MOS power transistor 60. It should not be.

The third embodiment according to the present invention, shown in FIG. 4, satisfies the above prerequisites.

4, NPN bipolar transistors 61, 62, 63 and 64 and PNP bipolar transistors 65, 66, 67 and 68 are shown.

Also shown are MOS transistors 71, 72, 73 and 74 and 76 and 78.

Drain supply potential V _D and gate control potential V _{G of} diode 75, MOS power transistor 60 are shown.

The first current balancing circuit consists of first and second PNP bipolar transistors 65 and 67, the emitter of which is connected to the control potential of the semiconductor power element 60.

The second current balancing circuit consists of third and fourth PNP bipolar transistors 66 and 68, whose emitter is connected to the control potential of the semiconductor power element 60.

The third current balancing circuit consists of first and second MOS transistors 71 and 73, the source of which is connected to the terminal of the detection resistor 55 'connected to the reference potential, preferably the load output terminal. do.

The fourth current balancing circuit consists of third and fourth MOS transistors 72 and 74, the source of which is connected to a terminal of the detection resistor 55 'connected to a reference potential, preferably the load output terminal. do.

The emitter of the first NPN bipolar transistor 62 is connected to the drain of the third MOS transistor 72.

The second NPN bipolar transistor 64 is connected between the collector of the fourth PNP bipolar transistor 68 and the terminal of the detection resistor 55 ′ connected to the semiconductor power element 60.

The emitter of the third NPN bipolar transistor 61 is connected to the drain of the second MOS transistor 73.

The fourth NPN bipolar transistor 63 is connected between the collector of the first PNP bipolar transistor 65 and the terminal of the detection resistor 55 'connected to the load output terminal.

Base terminals of the first and third NPN bipolar transistors 62 and 61 are connected together, and collector terminals of the first and third NPN bipolar transistors 62 and 61 are flowed through the diode 75 in a flow direction. To the control potential V _G of the semiconductor power element 60.

The emitter of the first NPN bipolar transistor 62 is connected to the base of the fourth NPN bipolar transistor 63, and the emitter of the third NPN bipolar transistor 61 is connected to the base of the second NPN bipolar transistor 64.

The fifth and sixth MOS transistors 76 and 78 have a reference potential, that is, a terminal of a detection resistor 55 'connected to a load output terminal, and a semiconductor power element 60 connected to a supply potential V _D. Is connected in series between the terminals.

The gate of the fifth MOS transistor 76 is connected to the collector of the third PNP bipolar transistor 66, and the gate of the sixth MOS transistor 78 is connected to the control potential of the semiconductor power element 60.

Finally, the node between the fifth and sixth MOS transistors 76, 78 is not connected to the common base of the first and third NPN transistors 62, 61.

Thus, unlike the first and second embodiments described above, four NPN bipolar transistors 61, 62, 63, and 64 are no longer connected in series in pairs, and the PNP bipolar transistor 65 And two current balancing circuits consisting of (66), (67) and (68) and MOS transistors (71), (72), (73) and (74) of the lower NPN bipolar transistors (63), (64). The collector current is received and supplied back to the upper NPN bipolar transistors 61 and 62.

Thus, the collector of the NPN transistor is connected to the source terminal of the MOS power transistor 60 via a PN-junction having polarity in the flow direction.

The invention is not limited to the embodiment described above. In particular, a current balancing circuit with a corresponding current ratio can be inserted into the circuit to increase the sensitivity.

Claims (10)

A current limiter circuit for a controlled semiconductor power element 60 comprising a detection resistor 55 'connected in series to the main current path of the controlled semiconductor power element 60, A first connected in series between the first supply voltage terminal V _B and the terminal of the detection resistor 55 ′ connected to the source terminal of the semiconductor power element 60 together with the load section and current source 56 ′; Second bipolar transistors 52 ', 54', and Third and fourth bipolar transistors 51 ', 53' connected in series between the control terminal and the second supply voltage terminal (ground) with a load section, The collector and base of the first bipolar transistor 52 'are connected to the base of the third bipolar transistor 52', The base of the second bipolar transistor 54 'is coupled to a node connected between the emitter of the third bipolar transistor 54' and the collector of the fourth bipolar transistor 53 ', The base of the fourth bipolar transistor (53 ') is coupled to a node connected between the emitter of the first bipolar transistor (52') and the collector of the second bipolar transistor (54 '). The method of claim 1, The first current source device 31 comprises first and second bipolar transistors 52 ', 54'; 62, 64 wired such that the collector currents are proportional to each other, The second current source device 32 comprises third and fourth bipolar transistors 51 ', 53'; 61, 63, the third bipolar transistor 51 '; 61 having a fourth bipolar transistor in its emitter; A current proportional to the collector current of 53 '; The emitter-base voltage of the fourth bipolar transistors 53 '; 63 is the voltage component of the second and third bipolar transistors 54', 51 '; A current limiter circuit comprising an emitter-base voltage and an emitter-base voltage of a first bipolar transistor (52 ', 62) having a negative sign. 3. Current limiter circuit according to claim 2, characterized in that at least one of the four bipolar transistors (51 '-54'; 61-64) has an emitter surface different from the other bipolar transistors. 3. An additional bipolar transistor according to claim 2, wherein the emitter-base voltage of the fourth bipolar transistor (53 ') 63 comprises an additional constant voltage component, the value of said voltage component operating at different emitter current densities. And a current limiter circuit obtained from the difference of the emitter-base voltages of the circuit. 4. A device according to any one of the preceding claims, wherein the current balancing circuit device 30 A first and a second connected in series between a first reference potential V _B with one current source 56 ′ and a terminal of the detection resistor 55 ′ connected to the source terminal of the semiconductor power element 60. Bipolar transistors 52 ', 54', and Third and fourth bipolar transistors 51 ', 53' connected in series between the control potential V _G and the third reference potential (ground), The collector and base of the first bipolar transistor 52 'are connected together and the base of the first and third bipolar transistors 52', 51 'are connected together, The base of the second bipolar transistor 54 'is connected to a node lying between the emitter of the third bipolar transistor 54' and the collector of the fourth bipolar transistor 53 ', The base of the fourth bipolar transistor (53 ') is connected to a node lying between the emitter of the first bipolar transistor (52') and the collector of the second bipolar transistor (54 '). 5. The device of claim 1, wherein the current balancing circuit arrangement A first and a second connected in series between the first reference potential V _B with one current source 56 ′ and the terminal of the detection resistor 55 ′ connected to the source terminal of the semiconductor power element 60. 2 bipolar transistors 52 ', 54', and Third and fourth bipolar transistors 51 ', 53' connected in series between the control potential V _G and a third reference potential (ground), The collector and base of the first bipolar transistor 52 'are connected together and the base of the first and third bipolar transistors 52', 51 'are connected together, A fifth and sixth bipolar transistor 60 ', 59' connected in series to the associated current source 57 ', 58' between the first and second reference potentials VB, ground, The base of the second bipolar transistor 54 'is connected to a node lying between the emitter of the fifth bipolar transistor 60' and the corresponding current source 58 'and the base of the fifth bipolar transistor 59' Connected to a node lying between the emitter of the third bipolar transistor 51 'and the collector of the fourth bipolar transistor 53', The base of the fourth bipolar transistor 53 'is connected to a node connected between the emitter of the sixth bipolar transistor 59' and the corresponding current source 57 ', and the base of the sixth bipolar transistor 59'. Is connected to a node connected between the emitter of the first bipolar transistor (51 ') and the collector of the second bipolar transistor (54'). 7. Current limiter circuit according to claim 6, characterized in that the current sources (57 ', 58') of the fifth and sixth bipolar transistors (60 ', 59') are each one resistor. 7. Current limiter circuit according to claim 6, characterized in that the current sources (57 ', 58) of the fifth and sixth bipolar transistors (60', 59) are NMOS transistors, respectively. 9. The current limiter circuit according to claim 8, wherein a common gate potential of the NMOS transistor is a potential of a common base terminal of the first and third bipolar transistors (52 ', 51'). The device of claim 1, wherein the current balancing circuit device 30 is A first current balance circuit consisting of first and second PNP bipolar transistors 65, 67 and having an emitter connected to the control potential V _G of the semiconductor power element 60, A second current balancing circuit consisting of third and fourth PNP bipolar transistors 66, 68 and having an emitter connected to the control potential V _G of the semiconductor power element 60, A third current balancing circuit, consisting of first and second MOS transistors 71 and 73, having a source connected to a reference potential, A fourth current balancing circuit, consisting of third and fourth MOS transistors 72 and 74, having a source connected to a reference potential, A first NPN-bipolar transistor 62 having an emitter connected to the drain of the third MOS transistor 72, A second NPN bipolar transistor 64 connected between the collector of the fourth PNP bipolar transistor 68 and the terminal of the detection resistor 55 'connected to the semiconductor power element 60, A third NPN bipolar transistor 61 having an emitter connected to the drain of the second MOS transistor 73, A fourth NPN bipolar transistor 63 connected between the collector of the first PNP bipolar transistor 65 and the terminal of the detection resistor 55 'connected to the load output terminal, The base terminals of the first and third NPN bipolar transistors 62, 61 are connected together and the collector terminals of the first and third NPN bipolar transistors 62, 61 are connected in a flow direction through the diode 75 in the semiconductor power element. Connected to the control potential V _G of 60, The emitter of the first NPN bipolar transistor 62 is connected to the base of the fourth NPN bipolar transistor 63 and the emitter of the third NPN bipolar transistor 61 is connected to the base of the second NPN bipolar transistor 64. Become, A fifth MOS transistor 76 and a sixth MOS transistor 78 connected in series between the reference potential of the fourth current balancing circuit and the terminals of the semiconductor power element 60 connected to the supply potential V _D. , The gate of the fifth MOS transistor 76 is connected to the collector of the third PNP bipolar transistor 66 and the gate of the sixth MOS transistor 78 is connected to the control potential V _G of the semiconductor power element 60. , A node between the fifth and sixth MOS transistors (76, 78) is connected to a common base of the first and third NPN bipolar transistors (62, 61).