JP2016133414A

JP2016133414A - Switching element drive device

Info

Publication number: JP2016133414A
Application number: JP2015008567A
Authority: JP
Inventors: 将嗣入江; Masatsugu Irie; 昌弘山本; Masahiro Yamamoto; 丹羽　章雅; Akimasa Niwa; 章雅丹羽
Original assignee: Denso Corp
Current assignee: Denso Corp
Priority date: 2015-01-20
Filing date: 2015-01-20
Publication date: 2016-07-25
Anticipated expiration: 2035-01-20
Also published as: JP6476890B2

Abstract

PROBLEM TO BE SOLVED: To provide a switching element drive device with which it is possible to detect a bipolar electric current with high accuracy while suppressing the consumption of electric power.SOLUTION: One terminal of a current detection resistor 18 is connected to the source of a sense FET 6, the positive terminal of a first power supply circuit 17 is connected to a battery 8, and a voltage output terminal is connected to a terminal PGND, with a negative voltage outputted to a negative terminal. The non-inverted input terminal of an op-amp 23 is connected to the source of the sense FET 6, and the inverted input terminal is connected to a terminal PGND. A second power supply circuit 20 generates a power supply as a negative terminal is connected to a terminal ICGND. A series circuit of FETs 21 and 22 is connected in parallel to the second power supply circuit 20, and the common connection point of the series circuit is connected to the other terminal of the resistor 18, whereby the electricity-conducting state of the FETs 21 and 22 is reciprocally controlled in accordance with a change in the level of an output signal of the op-amp 23. An A/D converter 19 detects a current flowing in the resistor 18 on the basis of the voltage of the common connection point.SELECTED DRAWING: Figure 1

Description

本発明は、駆動用スイッチング素子と、この駆動用スイッチング素子に流れる電流を所定の分流比で流す電流検出用スイッチング素子とを駆動する駆動装置に関する。 The present invention relates to a drive device that drives a drive switching element and a current detection switching element that causes a current flowing through the drive switching element to flow at a predetermined diversion ratio.

例えばパワーＭＯＳＦＥＴを駆動する装置には、パワーＭＯＳＦＥＴに流れるドレイン電流を検出するため、そのドレイン電流を小さい電流比で流す電流検出用のＭＯＳＦＥＴ（センスＭＯＳＦＥＴ）を併せて形成しておき、そのセンスＭＯＳＦＥＴのドレイン電流を検出する回路を備えるものがある。この場合、センスＭＯＳＦＥＴのソースに接続した抵抗素子の端子電圧を検出する。ところが、このような構成を採用するとセンスＭＯＳＦＥＴのソース電位が上昇し、パワーＭＯＳＦＥＴとセンスＭＯＳＦＥＴとでゲート−ソース間電圧が異なる状態となり、電流検出精度が低下するという問題がある。 For example, in a device for driving a power MOSFET, in order to detect a drain current flowing in the power MOSFET, a current detection MOSFET (sense MOSFET) that flows the drain current at a small current ratio is also formed. Some have a circuit for detecting the drain current. In this case, the terminal voltage of the resistance element connected to the source of the sense MOSFET is detected. However, when such a configuration is adopted, the source potential of the sense MOSFET rises, and there is a problem that the voltage between the gate and the source differs between the power MOSFET and the sense MOSFET, and the current detection accuracy decreases.

この問題に対処するため、例えば特許文献１には、パワーＭＯＳＦＥＴ及びセンスＭＯＳＦＥＴのソースを、それぞれオペアンプの入力端子に接続することで仮想接地して、電流検出精度を向上させる構成が開示されている。 In order to deal with this problem, for example, Patent Document 1 discloses a configuration in which the sources of the power MOSFET and the sense MOSFET are virtually grounded by connecting the sources of the power MOSFET and the sense MOSFET to the input terminal of the operational amplifier, thereby improving the current detection accuracy. .

特開２００３−２０２３５５号公報JP 2003-202355 A

しかしながら、特許文献１の構成では、検出電流が抵抗素子を介して負電源に流れ込むようになっている。すると負電源電圧が低下するので、その電圧低下を補償するために電力を消費してしまうという問題がある。また、特許文献１の構成では、正極性の電流だけが検出対象となっている。 However, in the configuration of Patent Document 1, the detection current flows into the negative power source through the resistance element. Then, since the negative power supply voltage is lowered, there is a problem that power is consumed to compensate for the voltage drop. In the configuration of Patent Document 1, only a positive current is a detection target.

本発明は上記事情に鑑みてなされたものであり、その目的は、電力の消費を抑制しつつ、両極性の電流を高い精度で検出可能なスイッチング素子の駆動装置を提供することにある。 The present invention has been made in view of the above circumstances, and an object thereof is to provide a driving device for a switching element capable of detecting a bipolar current with high accuracy while suppressing power consumption.

請求項１記載のスイッチング素子の駆動装置によれば、電流検出用抵抗の一端を、電流検出用スイッチング素子の電位基準側導通端子に接続する。また、第１電源回路は、正側端子を入力電源に接続し、電圧出力端子を基準グランドに接続することで負側端子に負電圧を出力する。また、オペアンプの非反転入力端子を電流検出用スイッチング素子の電位基準側導通端子に接続し、反転入力端子を基準グランド，すなわち駆動用スイッチング素子の電位基準側導通端子に接続する。 According to the switching element drive device of the first aspect, one end of the current detection resistor is connected to the potential reference side conduction terminal of the current detection switching element. The first power supply circuit outputs a negative voltage to the negative terminal by connecting the positive terminal to the input power supply and connecting the voltage output terminal to the reference ground. The non-inverting input terminal of the operational amplifier is connected to the potential reference side conduction terminal of the current detection switching element, and the inverting input terminal is connected to the reference ground, that is, the potential reference side conduction terminal of the driving switching element.

更に、第２電源回路は、その負側端子を入力電源の負側端子である回路グランドに接続することで電源を生成する。そして、電源側及びグランド側スイッチング素子の直列回路を第２電源回路に並列に接続し、且つ前記直列回路の共通接続点を電流検出用抵抗の他端に接続して、電源側及びグランド側スイッチング素子の導通状態を、前記オペアンプの出力信号のレベル変化に応じて相反的に制御する。電流検出回路は、前記共通接続点の電圧に基づいて電流検出用抵抗に流れる電流を検出する。 Further, the second power supply circuit generates a power supply by connecting its negative terminal to a circuit ground which is a negative terminal of the input power supply. A series circuit of the power supply side and ground side switching elements is connected in parallel to the second power supply circuit, and a common connection point of the series circuit is connected to the other end of the current detection resistor, so that the power supply side and ground side switching are performed. The conduction state of the element is reciprocally controlled according to the level change of the output signal of the operational amplifier. The current detection circuit detects a current flowing through the current detection resistor based on the voltage at the common connection point.

ここで、電源側及びグランド側スイッチング素子がオンした際に流れる電流を正極性，オフした際にダイオードを介して流れる電流（還流電流）を負極性と定義する。上記のように構成すれば、正電流は、負荷→電流検出用スイッチング素子→電流検出用抵抗→グランド側スイッチング素子→回路グランド→第１電源回路→基準グランドの経路で流れる。一方、負電流は、基準グランド→第１電源回路→回路グランド→第２電源回路→電源側スイッチング素子→電流検出用抵抗→電流検出用スイッチング素子のダイオードの経路で流れる。したがって、駆動用スイッチング素子と電流検出用スイッチング素子との電位基準側導通端子をオペアンプにより仮想接地した状態で、正負両極性の電流を高精度に検出できる。 Here, the current that flows when the power supply side and ground side switching elements are turned on is defined as positive polarity, and the current that flows through the diode when it is turned off (return current) is defined as negative polarity. If comprised as mentioned above, a positive current will flow through the path | route of load-> current detection switching element-> current detection resistance-> ground side switching element-> circuit ground-> 1st power supply circuit-> reference ground. On the other hand, the negative current flows through a diode path of reference ground → first power supply circuit → circuit ground → second power supply circuit → power supply side switching element → current detection resistor → current detection switching element. Therefore, it is possible to detect the positive and negative currents with high accuracy in a state where the potential reference side conduction terminals of the driving switching element and the current detection switching element are virtually grounded by the operational amplifier.

そして、正電流と負電流とが第２電源回路を互いに逆方向に流れて経由するので、正負の電流により第１電源回路内部の容量成分を各極性で充電する電荷の収支はゼロになり、第１電源回路が回路グランドに出力している負電圧を変動させることがない。したがって、電流の検出動作に伴い第１電源回路が電力を余分に消費することが無くなる。 Since the positive current and the negative current flow through the second power supply circuit in opposite directions, the balance of charges for charging the capacitance component in the first power supply circuit with each polarity by the positive and negative currents becomes zero. The negative voltage output from the first power supply circuit to the circuit ground is not changed. Therefore, the first power supply circuit does not consume extra power due to the current detection operation.

請求項２記載のスイッチング素子の駆動装置によれば、第１電源回路を、入力電源に並列に接続される定電圧レギュレータと、基準グランドと回路グランドとの間に接続されるコンデンサとで構成するので、正電流と負電流とが前記コンデンサを各極性で充電する電荷の収支がゼロになる。 According to the switching element drive device according to claim 2, the first power supply circuit is constituted by a constant voltage regulator connected in parallel to the input power supply, and a capacitor connected between the reference ground and the circuit ground. Therefore, the balance of charges for charging the capacitor with each polarity by the positive current and the negative current becomes zero.

第１実施形態であり、インバータ回路の下アーム側ＦＥＴを駆動する駆動装置の構成と、センスＦＥＴを介して流れる正電流の経路とを示す図The figure which is 1st Embodiment and shows the structure of the drive device which drives lower arm side FET of an inverter circuit, and the path | route of the positive current which flows through a sense FET 同構成と、センスＦＥＴの寄生ダイオードを介して流れる負電流の経路とを示す図The figure which shows the same structure and the path | route of the negative current which flows through the parasitic diode of sense FET ゲート電圧波形，並びにＦＥＴ及びセンスＦＥＴを介して流れる電流波形を示す図The figure which shows the current waveform which flows through a gate voltage waveform and FET and sense FET 第２実施形態であり、駆動装置の構成を示す図The figure which is 2nd Embodiment and shows the structure of a drive device 図３に示すゲート電圧波形の一部を拡大して示す図The figure which expands and shows a part of gate voltage waveform shown in FIG. 図５の区間１に流れるゲート充電電流の経路を示す図The figure which shows the path | route of the gate charge current which flows into the area 1 of FIG. 図５の区間２に流れるゲート放電電流の経路を示す図The figure which shows the path | route of the gate discharge current which flows into the area 2 of FIG. センスＦＥＴを介して流れる正電流の経路を示す図Diagram showing the path of positive current flowing through the sense FET センスＦＥＴの寄生ダイオードを介して流れる負電流の経路を示す図Diagram showing the path of the negative current that flows through the parasitic diode of the sense FET 第３実施形態であり、駆動装置の構成を示す図The figure which is 3rd Embodiment and shows the structure of a drive device 図５の区間０に流れるゲート充電電流の経路を示す図The figure which shows the path | route of the gate charge current which flows into the area 0 of FIG. 図５の区間１に流れるゲート充電電流の経路を示す図The figure which shows the path | route of the gate charge current which flows into the area 1 of FIG. 図５の区間２に流れるゲート放電電流の経路を示す図The figure which shows the path | route of the gate discharge current which flows into the area 2 of FIG. 図３に示すゲート電圧波形の一部を拡大して示す図The figure which expands and shows a part of gate voltage waveform shown in FIG. 第４実施形態であり、駆動装置の構成を示す図The figure which is 4th Embodiment and shows the structure of a drive device 図５の区間０に流れるゲート充電電流の経路を示す図The figure which shows the path | route of the gate charge current which flows into the area 0 of FIG. 図５の区間１に流れるゲート充電電流の経路を示す図The figure which shows the path | route of the gate charge current which flows into the area 1 of FIG. 図５の区間２に流れるゲート放電電流の経路を示す図The figure which shows the path | route of the gate discharge current which flows into the area 2 of FIG. センスＦＥＴを介して流れる正電流の経路を示す図Diagram showing the path of positive current flowing through the sense FET センスＦＥＴの寄生ダイオードを介して流れる負電流の経路を示す図Diagram showing the path of the negative current that flows through the parasitic diode of the sense FET 第５実施形態であり、駆動装置の構成を示す図The figure which is 5th Embodiment and shows the structure of a drive device 負電流が流れるＰＷＭキャリアのオン期間に、スイッチ回路のオンオフを繰り返す状態を示す図The figure which shows the state which repeats ON / OFF of the switch circuit in the ON period of the PWM carrier in which a negative current flows スイッチ回路のオフ時に負電流が流れる経路を示す図Diagram showing the path through which a negative current flows when the switch circuit is off スイッチ回路のオン時に負電流が流れる経路を示す図Diagram showing the path through which negative current flows when the switch circuit is on 第６実施形態であり、駆動装置の構成を示す図The figure which is 6th Embodiment and shows the structure of a drive device 正電流が流れる期間に、各ＦＥＴのオンオフ状態を示す図The figure which shows the ON / OFF state of each FET during the period when the positive current flows 負電流が流れる期間に、各ＦＥＴのオンオフ状態を示す図The figure which shows the on / off state of each FET during the period when the negative current flows 第７実施形態であり、駆動装置の構成及び正電流が流れる経路を示す図The figure which is 7th Embodiment and shows the structure of a drive device, and the path | route through which a positive current flows 同負電流が流れる経路を示す図Diagram showing the path through which the negative current flows 第８実施形態であり、駆動装置の構成を示す図The figure which is 8th Embodiment and shows the structure of a drive device 充放電電流波形とコンデンサの端子電圧波形とを示す図Diagram showing charge / discharge current waveform and capacitor terminal voltage waveform

（第１実施形態）
図１に示すように、インバータ回路１は、６個のＮチャネルＭＯＳＦＥＴ２（Ｕ，Ｖ，Ｗ／Ｘ，Ｙ，Ｚ）を３相ブリッジ接続して構成されている。インバータ回路１の正側電源線３（＋），負側電源線３（−）には、高圧直流電源であるバッテリ４の正側端子，負側端子がそれぞれ接続されている。 (First embodiment)
As shown in FIG. 1, the inverter circuit 1 is configured by connecting six N-channel MOSFETs 2 (U, V, W / X, Y, Z) in a three-phase bridge connection. A positive terminal and a negative terminal of a battery 4 that is a high-voltage DC power supply are connected to the positive power line 3 (+) and the negative power line 3 (−) of the inverter circuit 1, respectively.

インバータ回路１の各相出力端子は、スター結線されている３相モータの固定子巻線５Ｕ，５Ｖ，５Ｗの一端にそれぞれ接続されている。図中では、Ｕ相アームのグランド側に配置されているＦＥＴ２Ｘのみについて示しているが、ＦＥＴ２Ｘ（駆動用スイッチング素子）のドレイン（非電位基準側導通端子）には、電流検出用のＮチャネルＭＯＳＦＥＴ６（電流検出用スイッチング素子）のドレインが接続されている（以下では、センスＦＥＴ６と称する）。センスＦＥＴ６は、ＦＥＴ２Ｘに流れるドレイン電流を小さな電流比（例えば１００：１など）で自身のドレイン電流として流すように形成されている。 Each phase output terminal of the inverter circuit 1 is connected to one end of a stator winding 5U, 5V, 5W of a three-phase motor that is star-connected. In the figure, only the FET 2X arranged on the ground side of the U-phase arm is shown, but an N-channel MOSFET 6 for current detection is connected to the drain (non-potential reference side conduction terminal) of the FET 2X (driving switching element). The drain of (current detection switching element) is connected (hereinafter referred to as sense FET 6). The sense FET 6 is formed so that the drain current flowing through the FET 2X flows as its own drain current with a small current ratio (for example, 100: 1).

駆動装置７の電源端子＋Ｂ，−Ｂには、低圧直流電源であるバッテリ８の正側端子，負側端子がそれぞれ接続されている。駆動装置７は、ＦＥＴ２Ｘ及びセンスＦＥＴ６のゲート（導通制御端子）にゲート信号を出力する駆動回路９を内蔵している。駆動装置７の端子ＰＧＮＤはグランド（基準グランド）及びインバータ回路１の負側電源線３（−）に接続されている。また、駆動装置７の端子ＩＣＧＮＤは電源端子−Ｂ（回路グランド）に接続されていると共に、コンデンサ１０を介して端子ＰＧＮＤに接続されている。 The positive terminal and the negative terminal of the battery 8 that is a low-voltage DC power supply are connected to the power supply terminals + B and −B of the driving device 7, respectively. The driving device 7 includes a driving circuit 9 that outputs a gate signal to the gates (conduction control terminals) of the FET 2X and the sense FET 6. The terminal PGND of the driving device 7 is connected to the ground (reference ground) and the negative power supply line 3 (−) of the inverter circuit 1. Further, the terminal ICGND of the driving device 7 is connected to the power supply terminal -B (circuit ground) and is connected to the terminal PGND via the capacitor 10.

電源端子＋Ｂと端子ＩＣＧＮＤとの間には、ＰチャネルＭＯＳＦＥＴ１１及びＮチャネルＭＯＳＦＥＴ１２の直列回路が接続されており、ＦＥＴ１１，１２のゲートには、図示しない制御回路からの駆動制御信号がそれぞれゲートドライバ１３，１４を介して与えられる。これらが駆動回路９を構成している。そして、ＦＥＴ１１及び１２の共通接続点は、端子Ｇ及びゲート抵抗１５を介してＦＥＴ２Ｘ及びセンスＦＥＴ６のゲートに接続されている。 A series circuit of a P-channel MOSFET 11 and an N-channel MOSFET 12 is connected between the power supply terminal + B and the terminal ICGND, and a drive control signal from a control circuit (not shown) is connected to the gates of the FETs 11 and 12, respectively. , 14. These constitute the drive circuit 9. The common connection point of the FETs 11 and 12 is connected to the gates of the FET 2X and the sense FET 6 via the terminal G and the gate resistor 15.

電源端子＋Ｂと端子ＩＣＧＮＤとの間には定電圧レギュレータ１６が接続されており、定電圧レギュレータ１６の電源出力端子は端子ＰＧＮＤに接続されている。外付けのコンデンサ１０と定電圧レギュレータ１６とが第１電源回路１７を構成している。 A constant voltage regulator 16 is connected between the power supply terminal + B and the terminal ICGND, and a power supply output terminal of the constant voltage regulator 16 is connected to the terminal PGND. The external capacitor 10 and the constant voltage regulator 16 constitute a first power supply circuit 17.

センスＦＥＴ６のソース（電位基準側導通端子）は、端子ＳＥ及び電流検出抵抗１８を介してＡ／Ｄコンバータ１９（電流検出回路）の入力端子に接続されている。電源端子＋Ｂ，−Ｂ間には降圧型レギュレータで構成される第２電源回路２０が接続されており、第２電源回路２０の電源出力端子と電源端子−Ｂとの間には、ＰチャネルＭＯＳＦＥＴ２１（電源側スイッチング素子）及びＮチャネルＭＯＳＦＥＴ２２（グランド側スイッチング素子）の直列回路が接続されている。ＦＥＴ２１及び２２の共通接続点は、Ａ／Ｄコンバータ１９の入力端子に接続されている。 A source (potential reference side conduction terminal) of the sense FET 6 is connected to an input terminal of an A / D converter 19 (current detection circuit) via a terminal SE and a current detection resistor 18. A second power supply circuit 20 composed of a step-down regulator is connected between the power supply terminals + B and −B, and a P-channel MOSFET 21 is provided between the power supply output terminal of the second power supply circuit 20 and the power supply terminal −B. A series circuit of (power supply side switching element) and N-channel MOSFET 22 (ground side switching element) is connected. A common connection point of the FETs 21 and 22 is connected to an input terminal of the A / D converter 19.

オペアンプ２３の非反転入力端子は端子ＳＥに接続されており、反転入力端子は端子ＰＧＮＤに接続されている。そして、オペアンプ２３の出力端子はＦＥＴ２１及び２２のゲートに接続されている。これにより、ＦＥＴ２Ｘ及びセンスＦＥＴ６のソースは仮想接地状態となっている。 The non-inverting input terminal of the operational amplifier 23 is connected to the terminal SE, and the inverting input terminal is connected to the terminal PGND. The output terminal of the operational amplifier 23 is connected to the gates of the FETs 21 and 22. Thereby, the sources of the FET 2X and the sense FET 6 are in a virtual ground state.

次に、本実施形態の作用について説明する。図１に示すように、インバータ回路１のＦＥＴ２Ｖ，２Ｘがオンすることで、バッテリ４からの電流が、インバータ回路１では図中に実線で示すようにＶ相（＋）→Ｕ相（−）に流れる。この時、センスＦＥＴ６もオンしているので、電流は図中に破線で示すように、固定子巻線５ＵよりセンスＦＥＴ６を介して端子ＳＥより電流検出抵抗１８の方向に流れる（正極性）。図３に示すように、ＦＥＴ２Ｘ及びセンスＦＥＴ６がＰＷＭ制御により正弦波通電されている場合に、波形の正半波期間に流れる電流である。 Next, the operation of this embodiment will be described. As shown in FIG. 1, when the FETs 2V and 2X of the inverter circuit 1 are turned on, the current from the battery 4 is changed from the V phase (+) to the U phase (−) in the inverter circuit 1 as shown by the solid line in the figure. Flowing into. At this time, since the sense FET 6 is also turned on, current flows from the stator winding 5U through the sense FET 6 to the current detection resistor 18 through the sense FET 6 (positive polarity) as indicated by a broken line in the drawing (positive polarity). As shown in FIG. 3, when the FET 2X and the sense FET 6 are energized with a sine wave by PWM control, the current flows during the positive half-wave period of the waveform.

そして、オペアンプ２３は、端子ＳＥの電位を端子ＰＧＮＤの電位に等しくするように出力端子の電圧を上昇させる。これによりＦＥＴ２２側がオンする。したがって正電流は、センスＦＥＴ６→端子ＳＥ→電流検出抵抗１８→ＦＥＴ２２
→コンデンサ１０→負側電源線３（−）
の経路で流れる。よって、Ａ／Ｄコンバータ１９は、端子ＳＥの仮想接地電位（０Ｖ）を基準とする電流検出抵抗１８による電圧降下量を、正電流の値としてＡ／Ｄ変換できる。 The operational amplifier 23 increases the voltage at the output terminal so that the potential at the terminal SE is equal to the potential at the terminal PGND. This turns on the FET 22 side. Therefore, the positive current is sense FET 6 → terminal SE → current detection resistor 18 → FET 22
→ Capacitor 10 → Negative power line 3 (-)
It flows in the route. Therefore, the A / D converter 19 can A / D convert the voltage drop amount by the current detection resistor 18 with the virtual ground potential (0 V) of the terminal SE as a reference as a positive current value.

一方、インバータ回路１のＦＥＴ２Ｕ，２Ｙがオンした後（Ｕ相（＋）→Ｖ相（−））図２に示すようにＦＥＴ２Ｕがオフすると、インバータ回路１では還流電流が固定子巻線５Ｕ及び５Ｖ→ＦＥＴ２Ｙ→ＦＥＴ２Ｘの寄生ダイオード２ＸＤの経路で流れる。この時、センスＦＥＴ６もオフしており、電流は、負側電源線３（−）からコンデンサ１０を介して端子ＩＣＧＮＤの方向に流れる（負極性）。図３に示すように、波形の負半波期間に流れる電流である。この時ＦＥＴ２Ｘ及び６のゲート電位は負電位になり、ＦＥＴ２Ｘの閾値電圧が低い場合でもターンオフを確実に行うことができる。 On the other hand, after the FETs 2U and 2Y of the inverter circuit 1 are turned on (U phase (+) → V phase (−)), when the FET 2U is turned off as shown in FIG. The current flows through the path of the parasitic diode 2XD of 5V → FET2Y → FET2X. At this time, the sense FET 6 is also turned off, and the current flows from the negative power supply line 3 (−) to the terminal ICGND via the capacitor 10 (negative polarity). As shown in FIG. 3, the current flows during the negative half-wave period of the waveform. At this time, the gate potential of the FETs 2X and 6 becomes a negative potential, and even when the threshold voltage of the FET 2X is low, the turn-off can be reliably performed.

この時オペアンプ２３は、同じく端子ＳＥの電位を端子ＰＧＮＤの電位に等しくするように出力端子の電圧を低下させる。これによりＦＥＴ２１側がオンする。したがって負電流は、
コンデンサ１０→端子ＩＣＧＮＤ→バッテリ８→レギュレータ２０
→ＦＥＴ２１→電流検出抵抗１８→センスＦＥＴ６の寄生ダイオード６Ｄ
の経路で流れる。よって、Ａ／Ｄコンバータ１９は、端子ＳＥの仮想接地電位を基準とする電流検出抵抗１８による電圧上昇量を負電流の値としてＡ／Ｄ変換できる。尚、Ａ／Ｄコンバータ１９がＡ／Ｄ変換した電流のデータは、図示しない上位の制御装置に対して、例えばシリアル通信などにより送信される。 At this time, the operational amplifier 23 similarly reduces the voltage at the output terminal so that the potential at the terminal SE is equal to the potential at the terminal PGND. This turns on the FET 21 side. Therefore, the negative current is
Capacitor 10 → terminal ICGND → battery 8 → regulator 20
→ FET 21 → current detection resistor 18 → parasitic diode 6D of the sense FET 6
It flows in the route. Therefore, the A / D converter 19 can A / D convert the amount of voltage increase by the current detection resistor 18 with respect to the virtual ground potential of the terminal SE as a negative current value. The current data A / D converted by the A / D converter 19 is transmitted to a higher-level control device (not shown) by, for example, serial communication.

以上のように本実施形態によれば、駆動装置７において、電流検出用抵抗１８の一端をセンスＦＥＴ６のソースに接続し、第１電源回路１７の正側端子をバッテリ８に接続し、電圧出力端子を端子ＰＧＮＤに接続することで負側端子に負電圧を出力する。また、オペアンプ２３の非反転入力端子をセンスＦＥＴ６のソースに接続し、反転入力端子を端子ＰＧＮＤに接続する。第２電源回路２０は、負側端子を端子ＩＣＧＮＤに接続することで電源を生成する。 As described above, according to the present embodiment, in the driving device 7, one end of the current detection resistor 18 is connected to the source of the sense FET 6, the positive terminal of the first power supply circuit 17 is connected to the battery 8, and voltage output By connecting the terminal to the terminal PGND, a negative voltage is output to the negative terminal. Further, the non-inverting input terminal of the operational amplifier 23 is connected to the source of the sense FET 6 and the inverting input terminal is connected to the terminal PGND. The second power supply circuit 20 generates power by connecting the negative terminal to the terminal ICGND.

ＦＥＴ２１及び２２の直列回路を第２電源回路２０に並列に接続し、且つ前記直列回路の共通接続点を電流検出用抵抗１８の他端に接続して、ＦＥＴ２１及び２２の導通状態をオペアンプ２３の出力信号のレベル変化に応じて相反的に制御する。そして、Ａ／Ｄコンバータ１９は、前記共通接続点の電圧に基づいて電流検出用抵抗１８に流れる電流を検出する。したがって、ＦＥＴ２ＸとセンスＦＥＴ６とのソースをオペアンプ２３により仮想接地した状態で、正負両極性の電流を高精度に検出できる。 The series circuit of the FETs 21 and 22 is connected in parallel to the second power supply circuit 20, and the common connection point of the series circuit is connected to the other end of the current detection resistor 18, and the conduction state of the FETs 21 and 22 is changed to that of the operational amplifier 23. The reciprocal control is performed according to the level change of the output signal. The A / D converter 19 detects the current flowing through the current detection resistor 18 based on the voltage at the common connection point. Therefore, the positive and negative currents can be detected with high accuracy in a state where the sources of the FET 2X and the sense FET 6 are virtually grounded by the operational amplifier 23.

また、第１電源回路１７を、入力電源に並列に接続される定電圧レギュレータ１６と、端子ＰＧＮＤ，ＩＣＧＮＤ間に接続されるコンデンサ１０とで構成したので、正負の電流によりコンデンサ１０を交互に各極性で充電する電荷の収支はゼロになり、第１電源回路１７が端子ＩＣＧＮＤに出力している負電圧を変動させることがない。したがって、電流の検出動作に伴い第１電源回路１７が電力を余分に消費することが無くなる。尚、ＦＥＴ２Ｘをターンオン，ターンオフさせる際にゲートを充放電する電流によって、コンデンサ１０を充放電する電荷の収支もゼロになることは勿論である。 Further, since the first power supply circuit 17 is constituted by the constant voltage regulator 16 connected in parallel to the input power supply and the capacitor 10 connected between the terminals PGND and ICGND, the capacitor 10 is alternately switched by positive and negative currents. The balance of charges charged with polarity becomes zero, and the negative voltage output from the first power supply circuit 17 to the terminal ICGND is not changed. Accordingly, the first power supply circuit 17 does not consume extra power due to the current detection operation. It goes without saying that the balance of charge for charging and discharging the capacitor 10 is also zero due to the current for charging and discharging the gate when the FET 2X is turned on and off.

（第２実施形態）
以下、第１実施形態と同一部分には同一符号を付して説明を省略し、異なる部分について説明する。図４に示すように、第２実施形態の駆動装置３１では、降圧型レギュレータで構成されていた第２電源回路２０が削除されており、それに替わる第２電源回路３２が配置されている。また、駆動装置３１は端子ＶＣＰを備えており、ＦＥＴ２１のソースはその端子ＶＣＰに接続されている。 (Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different parts will be described. As shown in FIG. 4, in the driving device 31 of the second embodiment, the second power supply circuit 20 configured by the step-down regulator is deleted, and a second power supply circuit 32 is arranged instead. The driving device 31 includes a terminal VCP, and the source of the FET 21 is connected to the terminal VCP.

第２電源回路３２は、端子Ｇ，ＶＣＰ間に接続されているスイッチ回路３３（スイッチ手段）と、端子ＶＣＰ，ＩＣＧＮＤ間に外付けで接続されているコンデンサ３４とで構成されている。スイッチ回路３３は、例えばアナログスイッチなどで構成される。また、スイッチ回路３３のオンオフ制御は、例えば、駆動回路９がゲート駆動信号を出力するための信号に同期して制御信号を生成し出力する図示しない制御回路等によって行われる。 The second power supply circuit 32 includes a switch circuit 33 (switch means) connected between the terminals G and VCP and a capacitor 34 connected externally between the terminals VCP and ICGND. The switch circuit 33 is composed of, for example, an analog switch. The on / off control of the switch circuit 33 is performed by, for example, a control circuit (not shown) that generates and outputs a control signal in synchronization with a signal for the drive circuit 9 to output a gate drive signal.

次に、第２実施形態の作用について説明する。図５に示すように、ＦＥＴ２Ｘをターンオフさせる際にゲート電圧が立下りを開始してから、コンデンサ３４及び１０の直列接続で決まる容量に、ＦＥＴ２Ｘのゲート容量に蓄えられた電荷を並列接続することで決定される電圧に到達するまでの区間１において、図６に示すようにスイッチ回路３３をオンすると、ＦＥＴ２Ｘのゲートより流出する放電電流は、
スイッチ回路３３→コンデンサ３４及び１０→ＦＥＴ２Ｘのソース
の経路で流れる。したがって、上記放電電流によってコンデンサ３４が充電され、電荷として回収される。 Next, the operation of the second embodiment will be described. As shown in FIG. 5, the charge stored in the gate capacitance of the FET 2X is connected in parallel to the capacitance determined by the series connection of the capacitors 34 and 10 after the gate voltage starts falling when the FET 2X is turned off. When the switch circuit 33 is turned on as shown in FIG. 6 in the section 1 until reaching the voltage determined by, the discharge current flowing out from the gate of the FET 2X is
It flows in the path of the source of the switch circuit 33 → the capacitor 34 and 10 → the FET 2X. Therefore, the capacitor 34 is charged by the discharge current and collected as electric charge.

そして、図５に示すゲート電圧が負電位になる区間２では、図７に示すようにスイッチ回路３３をオフする。これにより、放電電流は、
端子Ｇ→ＦＥＴ１２→端子ＩＣＧＮＤ→コンデンサ１０→ＦＥＴ２Ｘのソース
の経路で流れるので、ゲート電圧が負電位になる。 Then, in the section 2 in which the gate voltage shown in FIG. 5 is a negative potential, the switch circuit 33 is turned off as shown in FIG. As a result, the discharge current is
Since the current flows from the terminal G → the FET 12 → the terminal ICGND → the capacitor 10 → the source of the FET 2X, the gate voltage becomes a negative potential.

図８に示すように、センスＦＥＴ６がオンしている期間の正電流は、第１実施形態と同様の経路で流れる。一方、図９に示すように、センスＦＥＴ６がオフしている期間の負電流は、
コンデンサ１０及び３４→ＦＥＴ２１→電流検出抵抗１８→寄生ダイオード６Ｄ
の経路で流れる。この時、区間２において充電されたコンデンサ３４の電荷が、ＦＥＴ２１のソースに電源として供給されている。 As shown in FIG. 8, the positive current while the sense FET 6 is on flows through the same path as in the first embodiment. On the other hand, as shown in FIG. 9, the negative current during the period when the sense FET 6 is off is
Capacitors 10 and 34 → FET 21 → current detection resistor 18 → parasitic diode 6D
It flows in the route. At this time, the charge of the capacitor 34 charged in the section 2 is supplied to the source of the FET 21 as a power source.

以上のように第２実施形態によれば、第２電源回路３２を、端子Ｇ，ＶＣＰ間に接続さるスイッチ回路３３と、端子ＶＣＰ，ＩＣＧＮＤ間に外付けで接続されるコンデンサ３４とで構成した。したがって、コンデンサ３４の充電電荷をＦＥＴ２１の駆動用電源として利用でき、第１実施形態のように降圧型レギュレータを用いる必要が無く、駆動装置３１を低コストで構成できる。 As described above, according to the second embodiment, the second power supply circuit 32 includes the switch circuit 33 connected between the terminals G and VCP and the capacitor 34 connected externally between the terminals VCP and ICGND. . Therefore, the charge of the capacitor 34 can be used as a power source for driving the FET 21, and it is not necessary to use a step-down regulator as in the first embodiment, and the drive device 31 can be configured at low cost.

（第３実施形態）
図１０に示すように、第３実施形態の駆動装置４１は、第１実施形態の第２電源回路２０を備えている。また、端子Ｇ，ＰＧＮＤ間にはスイッチ回路４２（スイッチ手段）が接続されている。次に、第３実施形態の作用について説明する。図５に示すゲート電圧波形がハイレベルとなる区間０においてＦＥＴ２Ｘがオンしている際には、ＦＥＴ２Ｘ（及びセンスＦＥＴ６）のゲートは、図１１に示すように
バッテリ８（＋）→ＦＥＴ１１→ＦＥＴ２Ｘのゲート及びソース
→コンデンサ１０→バッテリ８（−）
の経路で流れる電流によって充電される。 (Third embodiment)
As shown in FIG. 10, the drive device 41 of the third embodiment includes the second power supply circuit 20 of the first embodiment. A switch circuit 42 (switch means) is connected between the terminals G and PGND. Next, the operation of the third embodiment will be described. When the FET 2X is ON in the period 0 in which the gate voltage waveform shown in FIG. 5 is at a high level, the gate of the FET 2X (and the sense FET 6) is connected to the battery 8 (+) → FET 11 → FET 2X as shown in FIG. Gate and source → capacitor 10 → battery 8 (-)
It is charged by the current flowing through the path.

続く区間１では、図１２に示すようにスイッチ回路４２をオンすることで、ＦＥＴ２Ｘのゲートより流出する放電電流は、
スイッチ回路４２→端子ＰＧＮＤ→ＦＥＴ２Ｘのソース
の経路で流れる。したがって、ＦＥＴ２Ｘのゲート電位は０Ｖまで低下する（図１４参照）。 In the subsequent section 1, by turning on the switch circuit 42 as shown in FIG. 12, the discharge current flowing out from the gate of the FET 2X is
It flows in the path of the source of the switch circuit 42 → terminal PGND → FET 2X. Therefore, the gate potential of the FET 2X decreases to 0V (see FIG. 14).

そして、区間２では、図１３に示すようにスイッチ回路４２をオフすることで、放電電流は、
ＦＥＴ１２→端子ＩＣＧＮＤ→コンデンサ１０→ＦＥＴ２Ｘのソース
の経路で流れるので、ゲート電圧が負電位になる。 In section 2, by turning off the switch circuit 42 as shown in FIG.
Since the current flows through the path of FET12 → terminal ICGND → capacitor 10 → FET2X, the gate voltage becomes a negative potential.

すなわち、区間１においてゲート放電電流をグランドに流すことで、区間２においてコンデンサ１０が放電される電荷が減少する。つまり、
（区間０での充電量）＞（区間２での放電量）
という関係になる。そして、センスＦＥＴ６のオン期間にコンデンサ１０を放電させる電荷と、センスＦＥＴ６のオフ期間にコンデンサ１０を充電する電荷との収支は第１実施形態と同様にゼロである。 That is, by causing the gate discharge current to flow to the ground in the section 1, the charge discharged from the capacitor 10 in the section 2 is reduced. That means
(Charge amount in section 0)> (Discharge amount in section 2)
It becomes the relationship. The balance between the charge for discharging the capacitor 10 during the ON period of the sense FET 6 and the charge for charging the capacitor 10 during the OFF period of the sense FET 6 is zero, as in the first embodiment.

以上のように第３実施形態によれば、端子Ｇ，ＰＧＮＤ間に接続されるスイッチ回路４２を備えるので、ＦＥＴ２Ｘをターンオンさせる際にコンデンサ１０を充電する電荷によって端子ＩＣＧＮＤを負電位に維持することができる。 As described above, according to the third embodiment, since the switch circuit 42 connected between the terminals G and PGND is provided, the terminal ICGND is maintained at a negative potential by the charge for charging the capacitor 10 when the FET 2X is turned on. Can do.

（第４実施形態）
図１５に示すように、第４実施形態の駆動装置５１は、第３実施形態の駆動装置４１より第２電源回路２０及びスイッチ回路４２を削除し、第２電源回路５２及び端子ＶＣＮを配置した構成である。第２電源回路５２は、端子Ｇ，ＶＣＰ間に接続されるスイッチ回路５３（第１スイッチ手段）と、端子ＶＣＰ，ＶＣＮ間に接続されるコンデンサ５４と、端子ＶＣＮ，ＰＧＮＤ間に接続されるスイッチ回路５５（第２スイッチ手段）と、端子ＶＣＮ，ＩＣＧＮＤ間に接続されるスイッチ回路５６（第３スイッチ手段）とで構成されている。 (Fourth embodiment)
As shown in FIG. 15, in the driving device 51 of the fourth embodiment, the second power supply circuit 20 and the switch circuit 42 are deleted from the driving device 41 of the third embodiment, and the second power supply circuit 52 and the terminal VCN are arranged. It is a configuration. The second power supply circuit 52 includes a switch circuit 53 (first switch means) connected between the terminals G and VCP, a capacitor 54 connected between the terminals VCP and VCN, and a switch connected between the terminals VCN and PGND. The circuit 55 (second switch means) and the switch circuit 56 (third switch means) connected between the terminals VCN and ICGND are constituted.

次に、第４実施形態の作用について説明する。第３実施形態と同様の区間０では、図１６に示すように、スイッチ回路５３，５５及び５６を全てオフにすると、ＦＥＴ２Ｘのゲートを充電する電流は第３実施形態と同様の経路で流れる。続く区間１では、図１７に示すようにスイッチ回路５３及び５５をオンにすると、ＦＥＴ２Ｘのゲートを放電する電流は、
スイッチ回路５３→コンデンサ５４→スイッチ回路５５→ＦＥＴ２Ｘのソース
の経路で流れるので、ゲート電位はＦＥＴ２Ｘのゲート容量に蓄えられた電荷と、コンデンサ５４に蓄えられた電荷とで決定される電圧まで低下する。この時、コンデンサ５４が充電される（放電電流が電荷として回収される）。 Next, the operation of the fourth embodiment will be described. In the same section 0 as in the third embodiment, as shown in FIG. 16, when all the switch circuits 53, 55 and 56 are turned off, the current for charging the gate of the FET 2X flows through the same path as in the third embodiment. In the subsequent section 1, when the switch circuits 53 and 55 are turned on as shown in FIG. 17, the current for discharging the gate of the FET 2X is
Since it flows through the source path of the switch circuit 53 → the capacitor 54 → the switch circuit 55 → the FET 2X, the gate potential is reduced to a voltage determined by the charge stored in the gate capacitance of the FET 2X and the charge stored in the capacitor 54. . At this time, the capacitor 54 is charged (discharge current is recovered as electric charge).

そして、区間２では、図１８に示すように、再びスイッチ回路５３，５５及び５６を全てオフにすると、放電電流は、
ＦＥＴ１２→端子ＩＣＧＮＤ→コンデンサ１０→ＦＥＴ２Ｘのソース
の経路で流れるので、ゲート電圧が負電位になる。すなわち、区間１においてコンデンサ５４を充電した分だけ、区間２においてコンデンサ１０が放電される電荷が減少する。つまり、第３実施形態と同様に、
（区間０での充電量）＞（区間２での放電量）
となる。 In section 2, as shown in FIG. 18, when all the switch circuits 53, 55 and 56 are turned off again, the discharge current is
Since the current flows through the path of FET12 → terminal ICGND → capacitor 10 → FET2X, the gate voltage becomes a negative potential. That is, the amount of charge discharged from the capacitor 10 in the section 2 is reduced by the amount that the capacitor 54 is charged in the section 1. That is, as in the third embodiment,
(Charge amount in section 0)> (Discharge amount in section 2)
It becomes.

図１９に示すように、センスＦＥＴ６のオン期間にはスイッチ回路５３，５５及び５６を全てオフにすることで、正電流が流れる経路は第１実施形態と同じになる。一方、センスＦＥＴ６のオフ期間は、図２０に示すようにスイッチ回路５６をオンすることで、負電流は、
コンデンサ１０→スイッチ回路５６→コンデンサ５４
→ＦＥＴ２１→電流検出抵抗１８→寄生ダイオード６Ｄ
の経路で流れる。この時、コンデンサ５４に充電された電荷が利用される。 As shown in FIG. 19, by turning off all of the switch circuits 53, 55 and 56 during the on period of the sense FET 6, the path through which the positive current flows is the same as in the first embodiment. On the other hand, when the sense FET 6 is off, the switch circuit 56 is turned on as shown in FIG.
Capacitor 10 → Switch circuit 56 → Capacitor 54
→ FET21 → current detection resistor 18 → parasitic diode 6D
It flows in the route. At this time, the electric charge charged in the capacitor 54 is used.

以上のように第４実施形態によれば、電源回路５２を、スイッチ回路５３と、コンデンサ５４と、スイッチ回路５５及び５６とで構成した。これにより、寄生ダイオード６Ｄを介して負電流が流れる際に、ＦＥＴ２Ｘのターンオフ時にコンデンサ５４に回収された電荷を利用できるので、消費電力を低減できる。 As described above, according to the fourth embodiment, the power supply circuit 52 includes the switch circuit 53, the capacitor 54, and the switch circuits 55 and 56. Thereby, when a negative current flows through the parasitic diode 6D, the charge collected in the capacitor 54 when the FET 2X is turned off can be used, so that power consumption can be reduced.

（第５実施形態）
図２１に示すように、第５実施形態の駆動装置６１は、第１実施形態の駆動装置７において端子ＳＥ，ＰＧＮＤ間にスイッチ回路６２（スイッチ手段）を加えたものである。次に、第５実施形態の作用について説明する。センスＦＥＴ６がオンした際の正電流は、スイッチ回路６２をオフすることで第１実施形態と同じ経路で流れる。そして、スイッチ回路６２を、図２２に示すように、負電流が流れる期間においてＰＷＭキャリアのオン期間よりも短い周期でオンオフを繰り返すように制御する。 (Fifth embodiment)
As shown in FIG. 21, the drive device 61 of the fifth embodiment is obtained by adding a switch circuit 62 (switch means) between the terminals SE and PGND in the drive device 7 of the first embodiment. Next, the operation of the fifth embodiment will be described. The positive current when the sense FET 6 is turned on flows through the same path as in the first embodiment by turning off the switch circuit 62. Then, as shown in FIG. 22, the switch circuit 62 is controlled so as to be repeatedly turned on and off at a cycle shorter than the on-period of the PWM carrier in the period in which the negative current flows.

これにより、図２３に示すようにスイッチ回路６２をオフしている間は、負電流が第１実施形態と同じ経路で電流検出抵抗１８に流れる。一方、図２４に示すようにスイッチ回路６２をオンしている間は、負電流は
端子ＰＧＮＤ→スイッチ回路６２→寄生ダイオード６Ｄ
の経路で流れるので、電流検出抵抗１８には流れなくなる。 Thus, as shown in FIG. 23, while the switch circuit 62 is turned off, a negative current flows through the current detection resistor 18 through the same path as that of the first embodiment. On the other hand, as shown in FIG. 24, while the switch circuit 62 is on, the negative current is changed to the terminal PGND → switch circuit 62 → parasitic diode 6D.
Therefore, the current does not flow through the current detection resistor 18.

すなわち、負電流は、第１実施形態のようにＰＷＭキャリアのオン期間に連続して流れることはなく、スイッチ回路６２をオフしている間のみ流れる。つまり、負電流をＡ／Ｄコンバータ１９により検出するタイミングに合わせてスイッチ回路６２をオフすれば良く、電流検出抵抗１８により消費される電力に加えて、バッテリ８から供給され定電圧レギュレータ１６で降圧する際の電力損失を低減できる。 That is, the negative current does not flow continuously during the on period of the PWM carrier as in the first embodiment, but flows only while the switch circuit 62 is turned off. That is, it is only necessary to turn off the switch circuit 62 in accordance with the timing at which the negative current is detected by the A / D converter 19. In addition to the power consumed by the current detection resistor 18, the voltage is supplied from the battery 8 and reduced by the constant voltage regulator 16. Can reduce power loss.

（第６実施形態）
図２５に示すように、第６実施形態の駆動装置７１は、第１実施形態の駆動装置７において、第２電源回路２０の電源出力端子と端子ＩＣＧＮＤとの間に、定電流源７２（第２定電流源）及びＮチャネルＭＯＳＦＥＴ７３（第２補助スイッチング素子）の直列回路と、ＰチャネルＭＯＳＦＥＴ７４（第１補助スイッチング素子）及び定電流源７５（第１定電流源）の直列回路とを接続した構成である。そして、オペアンプ２３の出力端子はＦＥＴ７３及び７４のゲートに接続されており、ＦＥＴ２１のゲートはＦＥＴ７４のドレインに、ＦＥＴ２２のゲートはＦＥＴ７３のドレインにそれぞれ接続されている。 (Sixth embodiment)
As shown in FIG. 25, the driving device 71 of the sixth embodiment is the same as that of the driving device 7 of the first embodiment, between the power output terminal of the second power supply circuit 20 and the terminal ICGND. 2 constant current sources) and an N-channel MOSFET 73 (second auxiliary switching element) connected in series with a P-channel MOSFET 74 (first auxiliary switching element) and a series circuit of constant current source 75 (first constant current source). It is a configuration. The output terminal of the operational amplifier 23 is connected to the gates of the FETs 73 and 74, the gate of the FET 21 is connected to the drain of the FET 74, and the gate of the FET 22 is connected to the drain of the FET 73.

次に、第６実施形態の作用について説明する。図２６に示すように、センスＦＥＴ６がオンして正電流が流れる期間に、オペアンプ２３の出力電圧は０Ｖを下回る負電位となるが、端子ＩＣＧＮＤの電位よりも高くなる。これにより、ＦＥＴ７４はフルオンするのでＦＥＴ２１が完全にオフ状態になる。一方、ＦＥＴ７３は半オン状態となってＦＥＴ２２をフルオン状態にする。したがって、ＦＥＴ２１及び２２を介して貫通電流が流れることが抑止される。 Next, the operation of the sixth embodiment will be described. As shown in FIG. 26, during the period in which the sense FET 6 is turned on and a positive current flows, the output voltage of the operational amplifier 23 is a negative potential lower than 0 V, but is higher than the potential of the terminal ICGND. As a result, the FET 74 is fully turned on, so that the FET 21 is completely turned off. On the other hand, the FET 73 is in a half-on state, and the FET 22 is in a full-on state. Therefore, the through current is prevented from flowing through the FETs 21 and 22.

また、図２７に示すように、センスＦＥＴ６がオフし、寄生ダイオード６Ｄを介して負電流が流れる期間に、オペアンプ２３の出力電圧は０Ｖを上回る正電位となる。これにより、ＦＥＴ７３はフルオンするのでＦＥＴ２２が完全にオフ状態になる。一方、ＦＥＴ７４は半オン状態となってＦＥＴ２１をフルオン状態にする。したがってこの場合も、ＦＥＴ２１及び２２を介して貫通電流が流れることが抑止される。 Further, as shown in FIG. 27, the output voltage of the operational amplifier 23 becomes a positive potential exceeding 0 V during a period in which the sense FET 6 is turned off and a negative current flows through the parasitic diode 6D. As a result, the FET 73 is fully turned on, so that the FET 22 is completely turned off. On the other hand, the FET 74 is in a half-on state, and the FET 21 is in a full-on state. Therefore, in this case as well, the through current is prevented from flowing through the FETs 21 and 22.

以上のように第６実施形態によれば、第２電源回路２０の電源出力端子とＦＥＴ２１のゲートとの間に接続されるＦＥＴ７４と、このＦＥＴ７４と端子ＩＣＧＮＤとの間に接続される定電流源７５と、前記電源出力端子とＦＥＴ２２のゲートとの間に接続される定電流源７２と、前記ゲートと端子ＩＣＧＮＤとの間に接続されるＦＥＴ７３とを備え、ＦＥＴ７３及び７４のゲートをオペアンプ２３の出力端子に接続した。これにより、ＦＥＴ２１及び２２を介して貫通電流が流れることが抑止される。 As described above, according to the sixth embodiment, the FET 74 connected between the power output terminal of the second power supply circuit 20 and the gate of the FET 21, and the constant current source connected between the FET 74 and the terminal ICGND. 75, a constant current source 72 connected between the power supply output terminal and the gate of the FET 22, and an FET 73 connected between the gate and the terminal ICGND. The gates of the FETs 73 and 74 are connected to the operational amplifier 23. Connected to the output terminal. Thereby, it is suppressed that a through current flows through the FETs 21 and 22.

（第７実施形態）
図２８及び図２９に示すように、第７実施形態の駆動装置７Ａは、駆動装置７においてＦＥＴ１２のソースを、端子ＩＣＧＮＤに替えて端子ＰＧＮＤに接続した構成である。このように構成すれば、ＦＥＴ２Ｘをターンオフさせる際のゲート電位は０Ｖになる。したがって、ゲートを負電位にせずともターンオフが可能なＦＥＴであれば適用できる。 (Seventh embodiment)
As shown in FIGS. 28 and 29, the driving device 7A of the seventh embodiment has a configuration in which the source of the FET 12 in the driving device 7 is connected to the terminal PGND instead of the terminal ICGND. If comprised in this way, the gate potential at the time of turning off FET2X will be set to 0V. Therefore, any FET that can be turned off without setting the gate to a negative potential can be applied.

（第８実施形態）
図３０に示すように、第８実施形態の駆動装置７Ｂは、定電圧レギュレータ１６Ｂが外部より入力される制御信号（起動信号）がアクティブとなる期間のみ動作するように構成されている。これにより、駆動装置７Ｂを起動する際に定電圧レギュレータ１６Ｂを一定期間だけ動作させて、コンデンサ１０をαＶに充電してから（図３１参照）ＦＥＴ２Ｘ及び６の駆動制御を開始させるようにする。すると、以降の通常動作においてコンデンサ１０に対する充放電電圧が±βＶ（β＜α）で変化しても、端子ＩＣＧＮＤは負電位を維持するようになる（コンデンサ１０の容量を、そのように設定する）。またその後、コンデンサ１０の端子電圧が（α±β）Ｖの範囲を超えて変化したことを検知した際に、定電圧レギュレータ１６Ｂを一定期間だけ動作させるようにしても良い。 (Eighth embodiment)
As shown in FIG. 30, the driving device 7B of the eighth embodiment is configured such that the constant voltage regulator 16B operates only during a period in which a control signal (start signal) input from the outside is active. Thus, when starting the driving device 7B, the constant voltage regulator 16B is operated for a certain period, and the capacitor 10 is charged to αV (see FIG. 31), so that the drive control of the FETs 2X and 6 is started. Then, even if the charging / discharging voltage with respect to the capacitor 10 changes by ± βV (β <α) in the subsequent normal operation, the terminal ICGND maintains a negative potential (the capacitance of the capacitor 10 is set as such. ). After that, when it is detected that the terminal voltage of the capacitor 10 has changed beyond the range of (α ± β) V, the constant voltage regulator 16B may be operated for a certain period.

本発明は上記した、又は図面に記載した実施形態にのみ限定されるものではなく、以下のような変形又は拡張が可能である。
スイッチング素子はＭＯＳＦＥＴに限ることはない。例えば駆動用スイッチング素子については、電圧駆動型のスイッチング素子であれば良い。したがって、寄生ダイオードを有する素子に限らず、還流電流を通電させるためのダイオードは素子に外付けされていても良い。 The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The switching element is not limited to a MOSFET. For example, the driving switching element may be a voltage-driven switching element. Therefore, not only the element having a parasitic diode, but also a diode for energizing the return current may be externally attached to the element.

図面中、２ＸはＮチャネルＭＯＳＦＥＴ（駆動用スイッチング素子）、６はＮチャネルＭＯＳＦＥＴ（電流検出用スイッチング素子）、９は駆動回路、１０はコンデンサ、１７は第１電源回路、１８は電流検出抵抗、１９はＡ／Ｄコンバータ（電流検出回路）、２０は第２電源回路（定電圧レギュレータ）、２１はＰチャネルＭＯＳＦＥＴ（電源側スイッチング素子）、２２はＮチャネルＭＯＳＦＥＴ（グランド側スイッチング素子）、２３はオペアンプを示す。 In the drawing, 2X is an N-channel MOSFET (switching element for driving), 6 is an N-channel MOSFET (switching element for current detection), 9 is a drive circuit, 10 is a capacitor, 17 is a first power supply circuit, 18 is a current detection resistor, 19 is an A / D converter (current detection circuit), 20 is a second power supply circuit (constant voltage regulator), 21 is a P-channel MOSFET (power-supply side switching element), 22 is an N-channel MOSFET (ground side switching element), and 23 is Indicates an operational amplifier.

Claims

A driving switching element (2X) having a diode for energizing a reflux current between the conduction terminals, and a non-potential reference side conduction terminal are connected in common with the driving switching element, and a current flowing through the driving switching element is obtained. A drive circuit (9) for outputting a drive signal to the current detection switching element (6) flowing at a predetermined diversion ratio;
A current detection resistor (18) having one end connected to the potential reference side conduction terminal of the current detection switching element;
A first power supply circuit (17) for outputting a negative voltage to a negative terminal by connecting a positive terminal to an input power supply and connecting a voltage output terminal to the reference ground;
An operational amplifier (23) having a non-inverting input terminal connected to the potential reference-side conduction terminal of the current detection switching element and an inverting input terminal connected to the reference ground;
A second power supply circuit (20, 32, 52) for generating a power supply by connecting a negative terminal to a negative terminal (hereinafter referred to as circuit ground) of the input power supply;
A power supply connected in parallel to the second power supply circuit and having a common connection point connected to the other end of the current detection resistor, and the conduction state is reciprocally controlled in accordance with the level change of the output signal of the operational amplifier. A series circuit of a side switching element (21) and a ground side switching element (22);
A switching element drive device comprising: a current detection circuit (19) that detects a current flowing through the current detection resistor based on a voltage at the common connection point.

The first power supply circuit includes a constant voltage regulator (16, 16B) connected in parallel to the input power supply, and a capacitor (10) connected between the reference ground and the circuit ground. The driving device for a switching element according to claim 1.

3. The switching element driving device according to claim 2, wherein the constant voltage regulator (16B) is configured to operate only during a period in which a start signal is input and to charge the capacitor to a predetermined potential. .

4. The switching element drive device according to claim 1, wherein the second power supply circuit is constituted by a step-down regulator. 5.

The second power supply circuit (32) includes a capacitor (34) connected in parallel to a series circuit of the power supply side and ground side switching elements;
The switch means (33) connected between the output terminal of the said drive circuit and the power supply side conduction | electrical_connection terminal of the said power supply side switching element is comprised in any one of Claim 1 to 4 characterized by the above-mentioned. The switching element drive device according to claim 1.

The second power supply circuit (52) includes first switch means (53) connected between an output terminal of the drive circuit and a power supply side conduction terminal of the power supply side switching element,
A series circuit of a capacitor (54) and a second switch means (55) connected between the power supply side conduction terminal and the reference ground;
5. The switching element drive according to claim 1, further comprising third switch means connected between a common connection point of the series circuit and the circuit ground. 6. apparatus.

The switching element driving device according to any one of claims 1 to 4, further comprising switch means (42) connected between an output terminal of the driving circuit and the reference ground.

The switching element according to any one of claims 1 to 4, further comprising a switch means (62) connected between a potential reference side conduction terminal of the current detection switching element and the reference ground. Drive device.

A first auxiliary switching element (74) of the same conductivity type connected between a power supply output terminal of the second power supply circuit and a conduction control terminal of the power supply side switching element;
A first constant current source (75) connected between the first auxiliary switching element and the circuit ground;
A second constant current source (72) connected between a power supply output terminal of the second power supply circuit and a conduction control terminal of the ground side switching element; a conduction control terminal of the ground side switching element; and the circuit ground. A second auxiliary switching element (73) of the same conductivity type connected in between,
9. The switching element driving device according to claim 1, wherein conduction control terminals of the first and second auxiliary switching elements are connected to an output terminal of the operational amplifier. 10.