JP5500356B2 - Inductive element drive circuit - Google Patents

Description

  The present invention relates to a drive circuit effective for a high voltage DC-DC converter or a high voltage switching regulator for driving an inductive element.

  FIG. 3 shows a power supply circuit including a high-voltage inductive element driving circuit for driving a conventional inductive element (inductor) L1. This power supply circuit has an input terminal 110 for inputting a pulse width modulation (PWM) signal, a PMOS high voltage transistor M0 whose source is connected to a first power supply terminal (15 V in this example), and a source connected to a ground terminal. The drain is provided at the connection point of the first NMOS high voltage transistor M1 having the drain connected to the drain of the PMOS high voltage transistor M0, the drain of the PMOS high voltage transistor M0, and the drain of the first NMOS high voltage transistor M1. The first NMOS high withstand voltage after detecting the potential change of the output terminal (LX) 111 for outputting a signal for driving the induction element (inductor) L1 and the output terminal (LX) 111 and turning off the PMOS high withstand voltage transistor M0. And a voltage detection circuit 109 configured to turn on the transistor M1.

The voltage detection circuit 109 includes a source follower circuit including a second NMOS high withstand voltage transistor M2 and a first resistor R1, a low withstand voltage NMOS transistor M3, and a second resistor R2. The drain of the second NMOS high breakdown voltage transistor M2 is connected to the output terminal (LX) 111, the source is connected to one end of the first resistor R1, the other end of the first resistor R1 is grounded, and the low breakdown voltage NMOS The gate of the transistor M3 is connected to the source of the second NMOS high voltage transistor M2, the source is grounded, the drain is connected to one end of the second resistor R2, and the other end of the second resistor R2 is the second power source. It is connected to a terminal (5V in this example). The drain of the NMOS transistor M3 is connected to the second delay circuit 105 via the NOT circuit 112 and the latch circuit 108.
The gate voltage generation circuit of the PMOS high voltage transistor M0 has an OR circuit 102 formed between the input terminal 110 and the gate of the PMOS high voltage transistor M0, and the OR circuit 102 has an input at the first input terminal. The PWM signal is input from the terminal 110, the second input terminal is connected to the gate of the first NMOS high voltage transistor M1 via the first delay circuit 101, and the output terminal of the OR circuit 102 is the level shift circuit 103. Are connected to the gate of the PMOS high voltage transistor M0 through the buffer circuit 104.

The gate voltage generation circuit of the first NMOS high voltage transistor M1 includes an AND circuit 106 formed between the input terminal 110 and the gate of the first NMOS high voltage transistor M1. The second delay circuit 105 is connected to the input terminal of the first input terminal, the PWM signal from the input terminal 110 is input to the second input terminal, and the output terminal is connected to the first NMOS high voltage transistor through the buffer circuit 107. It is connected to the gate of M1.
The conventional inductive element driving circuit clamps the LX terminal voltage with the second NMOS high withstand voltage transistor M2, detects the potential drop at the connection point of the output high withstand voltage transistors M0 and M1 with the NMOS transistor M3 and the resistor R2, and outputs After the PMOS high voltage transistor M0 constituting the high voltage transistor is turned off, the first NMOS high voltage transistor M1 is controlled to be turned on, and the conduction period of the PMOS high voltage transistor M0 and the first NMOS high voltage transistor M1 is controlled. It is characterized by controlling so as not to overlap.

The operation of the voltage detection circuit formed in the conventional inductive element driving circuit will be specifically described.
(1) First, a high level signal is input to the gate (PGATE) of the PMOS high voltage transistor M0, and the PMOS high voltage transistor M0 is turned off.
(2) By the operation of (1), the terminal voltage of the output terminal (LX) 111 decreases from 15V to −0.6V, and the source terminal voltage (VS) (5-VTH) of the source of the second NMOS high voltage transistor M2. (Threshold voltage)) also decreases to -0.6V.
(3) When the terminal voltage (VS) of the source of the second NMOS high withstand voltage transistor M2 drops to −0.6 V, this voltage is applied to the gate of the NMOS transistor M3 to turn off the NMOS transistor M3.
(4) Due to the parasitic capacitance at the drain node of the second resistor R2 and the NMOS transistor M3, the drain is changed from 0V to 5V (High) by their time constant.
(5) Since the NOT circuit 112 is inserted between the drain of the NMOS transistor M3 and the latch circuit 108, the output from the drain of the NMOS transistor M3 is inverted and the input of the latch circuit 108 is 0V (Low). become.

Japanese Patent No. 3637904 discloses a power supply circuit in which a through current is reduced in a synchronous rectification type power supply circuit or the like. The disclosed power supply circuit has a high-order transistor and a low-order transistor connected in series between a power supply voltage and a reference potential, and each of the transistors is turned on and off by each PWM signal, and a DC output subjected to PWM control as an output A logic circuit including a DC-DC conversion circuit for obtaining a voltage and a level shifter connected to an intermediate node of a connection point between the upper transistor and the lower transistor, and the intermediate node potential is set to a predetermined value after the upper transistor is turned off. PWM means having detection means for outputting a signal for turning on the lower-order transistor when it is detected that the potential is equal to or lower than the first potential. When the upper transistor is turned off, the intermediate node potential decreases, and when the intermediate node potential falls below a predetermined potential, the lower transistor is turned on. The transistor can be turned on, and when the upper transistor is turned off, no through current flows between the upper transistor and the lower transistor.

In the inductive element driving circuit shown in FIG. 3, the problem is that the generated delay time becomes longer than the delay circuits 101 and 105. The NMOS transistor M3 is turned off when the potential at the output circuit high withstand voltage transistor connection point is lowered, but the operation speed is slowed down by the time constant due to the parasitic capacitance of the second resistor R2 and the drain node of the NMOS transistor M3. Further, if the second resistance R2 is reduced, the delay time is reduced. However, since the current consumption is increased, there is a limit to reducing the resistance.
The present invention has been made under such circumstances, and provides an inductive element driving circuit that overcomes the trade-off between low current consumption and high speed operation, and can prevent through current and improve driving efficiency.

  In order to solve the above problems, the inductive element driving circuit according to the present invention is characterized by using a voltage detection circuit in which a capacitor is inserted.

  That is, the inductive element driving circuit of the present invention has an input terminal for inputting a pulse width modulation (PWM) signal, a first PMOS transistor whose source is connected to the first power supply terminal, and a source connected to the ground terminal. A first NMOS transistor having a drain connected to the drain of the first PMOS transistor, a first gate voltage generating circuit connected to the input terminal and supplying a gate signal to the first PMOS transistor; A second gate voltage generation circuit connected to the input terminal and supplying a gate signal to the first NMOS transistor, and provided at a connection point between the drain of the first PMOS transistor and the drain of the first NMOS transistor An output terminal for outputting a signal for driving the inductive element; and detecting a change in potential of the output terminal to detect the first A voltage detection circuit configured to control on / off of the NMOS transistor, the voltage detection circuit including a source follower circuit including a second NMOS transistor and a first resistor, a capacitor, and the second A common-source amplifier circuit composed of a second PMOS transistor and a second resistor having a different breakdown voltage from the NMOS transistor, and one end of the capacitor based on a gate signal generated by the first gate voltage generation circuit. A switch for connecting and disconnecting the second power supply terminal, a drain of the second NMOS transistor of the source follower circuit is connected to the output terminal, a source is connected to one end of the first resistor, and the first resistor The other end of the resistor is grounded, the other end of the capacitor is connected to the source of the second NMOS transistor, and the source is the second The drain is connected to the second gate voltage generation circuit, one end of the second resistor is connected to the drain of the second PMOS transistor, the other end is grounded, and the first resistor is connected to the power supply terminal. The gate voltage generation circuit includes an OR circuit between the input terminal and the gate of the first PMOS transistor, and a level shift circuit that converts an output voltage of the OR circuit into a voltage of the first power supply terminal. A PWM signal is input to the first input terminal of the circuit from the input terminal, and the second input terminal of the OR circuit is connected to the gate of the first NMOS transistor via a first delay circuit, The output terminal of the OR circuit is connected to the gate of the first PMOS transistor, and the second gate voltage generation circuit includes the input terminal and the gate of the first NMOS transistor. An AND circuit in between, and a first input terminal of the AND circuit is connected to an output of the voltage detection circuit via a second delay circuit, and the second input terminal of the AND circuit has the input terminal The PWM signal is input, and the output terminal of the AND circuit is connected to the gate of the first NMOS transistor.

  According to the present invention, an inductive element driving circuit that can reduce power consumption, improve driving efficiency by high-speed operation, and prevent a through current can be obtained.

FIG. 3 is a power supply circuit diagram including the inductive element driving circuit according to the first embodiment. The timing chart explaining the flow of the signal which flows through the induction | guidance | derivation element drive circuit shown in FIG. The power supply circuit diagram containing the conventional inductive element drive circuit.

The inductive element drive circuit of the present invention clamps a high voltage with a second NMOS transistor M2 which is a high breakdown voltage element, and a pair of high breakdown voltages of the output circuit by a PMOS transistor M3 which is a low breakdown voltage element, a resistor R2 and a capacitor C1. Overcoming the trade-off between low current consumption and high speed operation by detecting the potential drop at the transistor connection point and controlling the NMOS high voltage transistor M1 to turn on after the PMOS high voltage transistor M0 of the output circuit is turned off. And, it is characterized by preventing a through current.
Preferred embodiments of the present invention will be described below with reference to the drawings.

A first embodiment will be described with reference to FIGS. 1 and 2.
FIG. 1 is a power supply circuit diagram including the inductive element driving circuit according to the first embodiment, and FIG. 2 is a timing chart for explaining the flow of signals flowing through the inductive element driving circuit shown in FIG.
As shown in FIG. 1, the inductive element driving circuit includes a PMOS high voltage transistor having an input terminal 11 for inputting a pulse width modulation (PWM) signal and a source connected to a first power supply terminal (15 V in this embodiment). M0, a first NMOS high voltage transistor M1 having a source connected to the ground terminal GND and a drain connected to the drain of the PMOS high voltage transistor M0, the drain of the PMOS high voltage transistor M0, and the first NMOS high voltage An output terminal (LX) 12 provided at a connection point of the drain of the transistor M1 and outputting a signal for driving the inductive element (inductor) L1, and a potential change at the connection point is detected to turn off the PMOS high voltage transistor M0. And a voltage detection circuit 9 configured to turn on the first NMOS high voltage transistor M1 later. That.

  The voltage detection circuit 9 includes a source follower circuit composed of a second NMOS high withstand voltage transistor M2 and a first resistor R1, a capacitor C1, a PMOS transistor M3 and a common source amplifier circuit composed of a second resistor R2. And a switch S1 that connects and disconnects one end of the capacitor C1 and the second power supply terminal (5 V in this embodiment), and the drain of the second NMOS high voltage transistor M2 of the source follower circuit is connected to the output terminal 12. The source is connected to one end of the first resistor R1, the other end of the first resistor R1 is grounded, the other end of the capacitor C1 is connected to the source of the second NMOS high voltage transistor M2, and the switch S1 Due to the contact and separation, one end of the capacitor C1 is connected to or disconnected from the second power supply terminal, and the gate of the PMOS transistor M3 of the common source amplifier circuit is The amount C1 is connected to one end, the source is connected to the second power supply terminal, the drain is connected to the second delay circuit 5 via the latch circuit 8, and the second resistor R2 has one end connected to the drain of the PMOS transistor M3. And the other end is grounded.

The gate voltage generation circuit of the PMOS high withstand voltage transistor M0 has an OR circuit 2 formed between the input terminal 11 and the gate of the PMOS high withstand voltage transistor M0. The PWM signal is input, the second input terminal is connected to the gate of the first NMOS high voltage transistor M1 via the first delay circuit 1, and the output terminal is connected to the level shift circuit (LS) 3 and the buffer circuit 4. To the gate of the PMOS high voltage transistor M0.
The gate voltage generation circuit of the first NMOS high voltage transistor M1 has an AND circuit 6 formed between the input terminal 11 and the gate of the first NMOS high voltage transistor M1, and the first input terminal of the AND circuit 6 Is connected to the second delay circuit 5, and the second input terminal of the AND circuit 6 receives a PWM signal from the input terminal 11, and the output terminal of the AND circuit 6 is connected to the first NMOS via the buffer circuit 7. It is connected to the gate of the high voltage transistor M1.
The voltage detection circuit 9 detects the voltage of the output terminal 12 whose potential has changed when the PMOS high breakdown voltage transistor M0 is turned off, and outputs a High signal from the voltage detection circuit 9, thereby the first NMOS high breakdown voltage transistor M1. Turn on. That is, by turning off the PMOS high voltage transistor M0 and then turning on the first NMOS high voltage transistor M1, the conduction periods of these transistors are prevented from overlapping.

As shown in FIG. 1, an input terminal of a NOT circuit (NOT circuit) 10 is connected between the OR circuit 2 and the level shift circuit 3, and an output terminal is connected to the switch S1. The level shift circuit 3 is provided because the voltage of the input PWM signal is different from the power supply voltage of the output circuit. The buffer circuits 4 and 7 are provided to drive the large gate capacitances of the high breakdown voltage transistors M0 and M1.
The basic operation of the inductive element driving circuit is based on the input PWM signal, and the PMOS high-voltage transistor M0 and the NMOS high-voltage transistor M1 connected in series between the power sources having different potentials are complementarily turned on and off to generate a predetermined pulse. The signal is output from the output terminal (LX) 12. This pulse signal drives the inductive element L1, and generates a stable output voltage by the capacitor C2 having one end connected to the inductive element L1 and the other end grounded.

In the present invention, the dead time is set so that the PMOS high voltage transistor M0 and the NMOS high voltage transistor M1 do not turn on simultaneously by feeding back the LX terminal voltage and the gate voltage (NGATE voltage) of the NMOS high voltage transistor M1 to provide a delay time. And prevent through current.
The delay circuit 1 is a circuit that determines the dead time by delaying the gate signal NGATE of the first NMOS high voltage transistor M1. The OR circuit 2 outputs a High level when 1 (high: hereinafter referred to as “High”) is input to one or both of the first and second input terminals, and 0 (low: hereinafter referred to as “ Low level is output when the input is “Low”. When the PWM signal becomes High, the OR circuit 2 immediately turns off the PMOS high voltage transistor M0 via the level shift circuit 3 and the buffer circuit 4.
Subsequently, in order for the PMOS high voltage transistor M0 to be turned on, both the PWM signal input to the OR circuit 2 and the output of the delay circuit 1 must be Low. Since the gate of the first NMOS high withstand voltage transistor M1 becomes Low and this Low signal passes through the delay circuit 1 and then the PMOS high withstand voltage transistor M0 is turned on, the through current of the output circuit high withstand voltage transistors M0 and M1 is reduced. Can be prevented.

On the other hand, in order to turn on the first NMOS high voltage transistor M1, it is necessary that the PWM signal and the output of the delay circuit 5 are at a high level. The high level PWM signal and the high level output of the delay circuit 5 are input to the AND circuit 6, and the AND circuit 6 outputs a high signal. The AND circuit outputs a High signal when the two inputs are High, and outputs a Low signal when either or both of the two inputs are Low.
The voltage detection circuit 9 detects that the LX terminal voltage VLX at the output terminal (LX) 12 has become a Low level, and outputs a High signal. That is, since the first NMOS high breakdown voltage transistor M1 is turned on after detecting that the PMOS high breakdown voltage transistor M0 is turned off, a through current can be prevented.

The voltage detection circuit 9 will be described in more detail.
When the PMOS high withstand voltage transistor M0 is on, the first NMOS high withstand voltage transistor M1 is off, and the PWM signal input from the input terminal 11 is at the low level, the switch S1 is closed and applied to the gate of the PMOS transistor M3. The VX terminal voltage is 5V (see FIG. 2). Further, since the PMOS high voltage transistor M0 is on, a high voltage (15V) is output from the output terminal (LX) 12. The gate voltage of the high-voltage second NMOS high-voltage transistor M2 is 5V, and the source voltage (VS terminal voltage) is 5V-VTHN (VTHN is the threshold value of the second NMOS high-voltage transistor M2 = approximately 4V). Become. The capacitor C1 connected to the source of the second NMOS high voltage transistor M2 is charged with VX−VS = VTHN (= approximately 1V). The PMOS transistor M3 is turned off, and the input voltage of the latch circuit 8 becomes low level.

Next, when the PWM signal input to the input terminal 11 becomes High level, the switch S1 is turned off, and the charge at the VX terminal is stored. The PMOS high voltage transistor M0 is turned off later than the switch S1 because of its large gate capacitance. When the PMOS high voltage transistor M0 is turned off, the LX terminal voltage of the output terminal 12 becomes −0.6 V due to the coil current (see FIG. 2). At this time, the source voltage (VS terminal voltage) of the second NMOS high withstand voltage transistor M2 becomes −0.6 V following the LX terminal voltage, and the electric charge of the capacitor C1 is preserved and the potential difference is maintained. The voltage drops to 0.4 V (see FIG. 2). As a result, the PMOS transistor M3 is turned on, the rising edge is input to the latch circuit 8, and a high level signal is output.
Since the on-resistance of the PMOS transistor M3 of the present invention is sufficiently lower than the second resistor R2 in the prior art, charges can be charged at high speed even if a parasitic capacitance exists in the drain of the PMOS transistor M3.
In the embodiment, a resistor is used for the voltage detection circuit, but a current source can be used instead of the resistor.

DESCRIPTION OF SYMBOLS 1, 5 ... Delay circuit 2 ... OR circuit 3 ... Level shift circuit 4, 7 ... Buffer circuit 6 ... AND circuit 8 ... Latch circuit 9 ... Voltage detection circuit 10. ..NOT circuit 11 ... Input terminal 12 ... Output terminal (LX)

Claims (1)

An input terminal for inputting a pulse width modulation (PWM) signal; a first PMOS transistor whose source is connected to the first power supply terminal; a source which is connected to the ground terminal; and a drain which is the drain of the first PMOS transistor A first NMOS transistor connected to the first NMOS transistor; a first gate voltage generating circuit connected to the input terminal for supplying a gate signal to the first PMOS transistor; and connected to the input terminal; A second gate voltage generation circuit for supplying a gate signal to the NMOS transistor, and a signal for driving the inductive element provided at a connection point between the drain of the first PMOS transistor and the drain of the first NMOS transistor are output. Control of ON / OFF of the first NMOS transistor by detecting potential change of the output terminal and the output terminal A voltage detection circuit configured so that the voltage detection circuit has a source follower circuit configured by a second NMOS transistor and a first resistor, a capacitor, and a voltage resistance of the second NMOS transistor. A common-source amplifier circuit composed of a second PMOS transistor and a second resistor, and one end of the capacitor and a second power supply terminal based on a gate signal generated by the first gate voltage generation circuit. The drain of the second NMOS transistor of the source follower circuit is connected to the output terminal, the source is connected to one end of the first resistor, and the other end of the first resistor is The other end of the capacitor is connected to the source of the second NMOS transistor, and the second PMOS transistor gate of the source-grounded amplifier circuit is connected. The first resistor is connected to one end of the capacitor, the source is connected to the second power supply terminal, the drain is connected to the second gate voltage generation circuit, and one end of the second resistor is connected to the second PMOS transistor. And the other end is grounded. The first gate voltage generation circuit supplies an OR circuit between the input terminal and the gate of the first PMOS transistor, and an output voltage of the OR circuit. A level shift circuit for converting the voltage into a voltage at a power supply terminal; a PWM signal is input from the input terminal to a first input terminal of the OR circuit; and a second delay terminal of the OR circuit is a first delay circuit The output terminal of the OR circuit is connected to the gate of the first PMOS transistor, and the second gate voltage generating circuit is connected to the gate of the first NMOS transistor An AND circuit is provided between an input terminal and the gate of the first NMOS transistor, and a first input terminal of the AND circuit is connected to an output of the voltage detection circuit via a second delay circuit, and the AND circuit The inductive element drive circuit according to claim 1, wherein a PWM signal is input to the second input terminal from the input terminal, and an output terminal of the AND circuit is connected to a gate of the first NMOS transistor.

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