WO2010058569A1 - Elément de mémoire non volatile et dispositif de mémoire non volatile - Google Patents

Elément de mémoire non volatile et dispositif de mémoire non volatile Download PDF

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Publication number
WO2010058569A1
WO2010058569A1 PCT/JP2009/006196 JP2009006196W WO2010058569A1 WO 2010058569 A1 WO2010058569 A1 WO 2010058569A1 JP 2009006196 W JP2009006196 W JP 2009006196W WO 2010058569 A1 WO2010058569 A1 WO 2010058569A1
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Prior art keywords
electrode
resistance
current
layer
nonvolatile memory
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PCT/JP2009/006196
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English (en)
Japanese (ja)
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三河巧
辻清孝
岡田崇志
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パナソニック株式会社
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Priority to JP2010512447A priority Critical patent/JP4531863B2/ja
Priority to US12/863,535 priority patent/US8227788B2/en
Publication of WO2010058569A1 publication Critical patent/WO2010058569A1/fr
Priority to US13/529,707 priority patent/US8399875B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode

Definitions

  • the present invention relates to a nonvolatile memory element and a nonvolatile memory device having a resistance change element in which a resistance value stably held by application of a voltage pulse changes.
  • the resistance variable element is an element that has a property that the resistance value reversibly changes by an electrical signal and that can store information corresponding to the resistance value in a nonvolatile manner.
  • the resistance change element directly receives an electrical stimulus, that is, through transfer of electrons.
  • the resistance value of the element is changed by changing the redox state of the variable resistance material.
  • a cross-point nonvolatile memory element As an example of a large-capacity nonvolatile memory equipped with this resistance variable element, a cross-point nonvolatile memory element has been proposed.
  • An element having a structure suitable for miniaturization, and an element having a configuration using a resistance change film as a memory portion and a non-linear element such as a varistor as a current limiting element is disclosed (for example, see Patent Document 1).
  • FIG. 19 is a diagram showing a nonvolatile memory device equipped with a conventional variable resistance element.
  • This figure shows a cross-sectional view of a memory cell 380 along the direction of the bit line 310 in a cross-point memory cell array composed of a bit line 310, a word line 320, and a memory cell 380 formed at each intersection thereof. is there.
  • a resistance change layer 330 that stores information due to a change in electrical resistance due to electrical stress is sandwiched between an upper electrode 340 and a lower electrode 350 to form a resistance change element 360.
  • a two-terminal nonlinear element 370 having a nonlinear current / voltage characteristic capable of flowing a current bidirectionally is formed on the resistance variable element 360.
  • a memory cell is formed by a series circuit of the resistance variable element 360 and the nonlinear element 370. 380 is formed.
  • the non-linear element 370 is a two-terminal element having a non-linear current-voltage characteristic in which the current change with respect to the voltage change is not constant, such as a diode.
  • the bit line 310 serving as the upper wiring is electrically connected to the nonlinear element 370
  • the word line 320 serving as the lower wiring is electrically connected to the lower electrode 350 of the resistance variable element 360. In this non-linear element 370, current flows in both directions when the memory cell 380 is rewritten.
  • a varistor (ZnO or YO) having a non-linear current-voltage characteristic symmetrical in both directions (both positive voltage side and negative voltage side) is used. SrTiO 3 etc.) are used.
  • a current density necessary for rewriting the resistance variable element 360 that is, a current of 30 kA / cm 2 or more can be passed, and a large capacity can be realized.
  • a resistance change operation (a high resistance state and a low resistance state by applying a voltage) (Reversible transition between the two) becomes unstable, and in some cases, the resistance variable element or the current limiting element is destroyed due to overcurrent.
  • An object of the present invention is to provide a variable resistance nonvolatile memory element and a nonvolatile memory device that can stabilize the resistance change operation and reduce the leakage current of a cross-point memory. To do.
  • a bipolar variable resistance element that reversibly transitions between a high resistance state and a low resistance state by applying a voltage of different polarity is used when changing from a low resistance state to a high resistance state (when the resistance is increased). : At the time of reset operation) The current and voltage are larger than the current and voltage at the time of changing from the high resistance state to the low resistance state (at the time of low resistance: set operation). That is, the bipolar variable resistance element has current-voltage characteristics that are asymmetric with respect to polarity.
  • a variable resistance element having such characteristics and a current limiting element symmetrical in both directions (when the absolute value of the applied voltage is small, the resistance is large, the absolute value of the applied voltage is increased, and the slope of the current-voltage curve ( ⁇ I Let us consider a case in which a device having a large / ⁇ V) is connected. At this time, if the current drive capability of the current limiting element is set high so that the current necessary for increasing the resistance can flow, the current limiting by the current limiting element becomes relatively insufficient when the resistance is reduced, and the resistance change Excess current flows in the mold element. In addition, the leakage current flowing through the non-selected cells increases, making it difficult to write and read data for the selected cells.
  • the nonvolatile memory element of the present invention is a resistance variable element that reversibly transitions between a low resistance state and a high resistance state by applying electrical signals having different polarities.
  • a current that flows when a voltage having an absolute value greater than 0 and an arbitrary value less than a predetermined voltage value and having a polarity of the first polarity is applied as the first current
  • a current flowing when a voltage having a second polarity different from the first polarity is applied is a second current
  • the first current is the first value.
  • a current limiting element larger than the current of 2 the resistance variable element is interposed between the first electrode, the second electrode, the first electrode and the second electrode, A variable resistance layer made of an oxygen-deficient transition metal oxide, The variable resistance element and the current limiting element are arranged so that the polarity of the voltage applied to the current limiting element becomes the first polarity when the type element transitions from the low resistance state to the high resistance state.
  • An interface that is connected in series and exhibits a resistance change phenomenon when an electrical signal is applied between the first electrode and the second electrode is an interface between the first electrode and the resistance change layer. And it is being fixed to one interface among the interfaces of the 2nd electrode and the resistance change layer.
  • a sufficiently large current required at the time of reset operation for increasing the resistance can be obtained sufficiently, and at the time of setting operation for reducing the resistance, the minimum necessary current can flow without much current flowing, and the resistance can be stably increased.
  • a variable resistance nonvolatile memory device that performs a changing operation can be realized.
  • the polarity of resistance change is always stable, it is possible to realize a variable resistance nonvolatile memory device that performs a resistance change operation more stably.
  • Another nonvolatile memory element of the present invention is a resistance change that reversibly transitions between a low resistance state and a high resistance state having a resistance value larger than that of the low resistance state by applying electrical signals having different polarities.
  • the first current is a current that flows when a type element and a first value whose absolute value is greater than 0 and less than a predetermined voltage value and whose polarity is the first polarity are applied.
  • the first current is A bidirectional current limiting element having an asymmetric characteristic that is greater than the second current, the resistance variable element comprising: a first electrode; a second electrode; and the first electrode. From an oxygen-deficient transition metal oxide interposed between the second electrode A variable resistance layer, and a direction of a current flowing through the variable resistance element when the variable resistance element transitions from a low resistance state to a high resistance state, and the first current is applied to the current limiting element.
  • variable resistance element and the current limiting element are connected in series so that the direction of current when flowing matches, and an electric signal is applied between the first electrode and the second electrode.
  • the interface where the resistance change phenomenon occurs is fixed to one of the interface between the first electrode and the resistance change layer and the interface between the second electrode and the resistance change layer. ing.
  • a sufficiently large current required at the time of reset operation for increasing the resistance can be obtained sufficiently, and at the time of setting operation for reducing the resistance, the minimum necessary current can flow without much current flowing, and the resistance can be stably increased.
  • a variable resistance nonvolatile memory device that performs a changing operation can be realized.
  • the variable resistance element includes a first electrode, a second electrode, and a variable resistance layer interposed between the first electrode and the second electrode, When a positive electrical signal is applied between the first electrode and the second electrode with reference to the first electrode, the resistance value between the first electrode and the second electrode increases.
  • the resistance change layer includes an oxygen-deficient transition metal oxide
  • the current limiting element includes a third electrode, a fourth electrode, the third electrode, and the first electrode.
  • a variable resistance nonvolatile memory device that performs a changing operation can be realized.
  • the variable resistance element includes a first electrode, a second electrode, and a variable resistance layer interposed between the first electrode and the second electrode, When a positive electrical signal is applied between the first electrode and the second electrode with reference to the first electrode, the resistance value between the first electrode and the second electrode increases. When a negative electrical signal is applied between the first electrode and the second electrode with reference to the first electrode, the resistance value between the first electrode and the second electrode.
  • the resistance change layer includes an oxygen-deficient transition metal oxide
  • the current limiting element includes a third electrode, the first electrode, the third electrode, and the third electrode. A semiconductor layer interposed between the first electrode and the third electrode, and the third electrode between the third electrode and the first electrode.
  • the variable resistance element includes a first electrode, a second electrode, and a variable resistance layer interposed between the first electrode and the second electrode.
  • the resistance change layer includes an oxygen-deficient transition metal oxide
  • the current limiting element includes the second electrode, the fourth electrode, and the second electrode.
  • a semiconductor layer interposed between the second electrode and the fourth electrode, and between the second electrode and the fourth electrode Serial polarity potential of the fourth electrode is positive and the second electrode as a reference may be configured such that the first polarity.
  • the resistance change element and the current limiting element share the electrode, thereby simplifying the manufacturing process and realizing a higher-density storage device.
  • the first electrode is made of a first material
  • the second electrode is made of a second material
  • the standard electrode potential of the first material is V1
  • the first electrode When the standard electrode potential of the material 2 is V2, and the standard electrode potential of the transition metal in the oxygen-deficient transition metal oxide is Vt, Vt ⁇ V2 and V1 ⁇ V2 may be satisfied.
  • variable resistance layer is in physical contact with the first electrode and has a first layer having a composition represented by MO x (M is a transition metal element), and the second layer A second layer in physical contact with the electrode and having a composition represented by MO y may satisfy x ⁇ y.
  • variable region of the variable resistance layer can be fixed to the interface with the second electrode having a higher oxygen content. This is because the mechanism of resistance change operation is dominated by oxygen oxidation / reduction in the vicinity of the electrode interface and preferentially operates at an interface rich in oxygen that can contribute to oxidation / reduction. Also in this configuration, the resistance changing type nonvolatile memory device that performs the resistance changing operation more stably can be realized because the polarity of the resistance changing is always stable.
  • the semiconductor layer is made of an n-type semiconductor, and the third electrode and the fourth electrode are made of different materials, and the electron affinity of the semiconductor layer is ⁇ s, When the work function of the electrode is ⁇ 1 and the work function of the fourth electrode is ⁇ 2, ⁇ s ⁇ 1 ⁇ 2 may be satisfied.
  • the height differs between the Schottky barrier between the semiconductor layer and the third electrode and the Schottky barrier between the semiconductor layer and the fourth electrode. Since the current driving capability of the diode element is determined by the current in the direction in which the reverse bias between the semiconductor layer and the metal interface is applied, the current driving capability in the direction in which the reverse bias is applied to the third electrode having a lower barrier is increased. In this case, when a current flows in the direction from the fourth electrode to the third electrode, the current flows more easily than in the reverse direction.
  • the first electrode of the resistance change element and the fourth electrode of the diode element are preferably connected.
  • the 2nd electrode of a resistance change element and the 3rd electrode of a diode element are connected.
  • a large current required for the reset operation for increasing the resistance can be obtained sufficiently, and for the set operation for reducing the resistance, a minimum current can be supplied without much current flowing.
  • the diode element can be formed using the same mask, which is advantageous in terms of reduction in process cost and miniaturization. .
  • the semiconductor layer is made of an n-type semiconductor, and the third electrode and the first electrode are made of different materials, and the electron affinity of the semiconductor layer is ⁇ s, When the work function of the electrode is ⁇ 1 and the work function of the first electrode is ⁇ 2, ⁇ s ⁇ 1 ⁇ 2 may be satisfied.
  • the semiconductor layer is made of an n-type semiconductor, and the second electrode and the fourth electrode are made of different materials, and the electron affinity of the semiconductor layer is ⁇ s, When the work function of the electrode is ⁇ 1 and the work function of the fourth electrode is ⁇ 2, ⁇ s ⁇ 1 ⁇ 2 may be satisfied.
  • the current drive capability in the direction in which the reverse bias is applied to the third electrode having a larger contact area is increased.
  • the first electrode of the resistance change element and the first of the diode element Preferably, four electrodes are connected, or the second electrode of the resistance change element and the third electrode of the diode element are connected.
  • variable resistance nonvolatile memory device that stably performs a resistance change operation.
  • there is no need to use different electrode materials for the upper electrode and the lower electrode of the current limiting element so there is no need to introduce a metal that can be a new contamination source into the semiconductor, which is advantageous in terms of the manufacturing method. It is.
  • the nonvolatile memory element when the area of the portion where the third electrode and the semiconductor layer are in contact is S1, and the area of the portion where the first electrode and the semiconductor layer are in contact is S2, S1 > S2 may be satisfied.
  • S1> S2 when the area of the portion where the second electrode and the semiconductor layer are in contact is S1, and the area of the portion where the fourth electrode and the semiconductor layer are in contact is S2, S1> S2 may be satisfied.
  • variable resistance nonvolatile memory device that performs a changing operation can be realized.
  • there is no need to use different electrode materials for the upper electrode and the lower electrode of the current limiting element so there is no need to introduce a metal that can be a new contamination source into the semiconductor, which is advantageous in terms of the manufacturing method. It is.
  • the transition metal oxide may be tantalum oxide or hafnium oxide.
  • a nonvolatile memory device in addition to high-speed operation, it has stable reversible characteristics and good resistance retention characteristics.
  • a nonvolatile memory device can be manufactured by a manufacturing process having high affinity with a normal Si semiconductor process.
  • the nonvolatile memory device of the present invention includes a substrate, a plurality of first wirings formed in parallel to each other on the substrate, and a main surface of the substrate above the plurality of first wirings.
  • a plurality of second wirings formed parallel to each other in a plane and three-dimensionally intersecting with the plurality of first wirings, and a solid of the plurality of first wirings and the plurality of second wirings
  • a cross-point type nonvolatile memory comprising a plurality of the nonvolatile memory elements provided to electrically connect the first wiring and the second wiring corresponding to each of the intersections It is a storage device. With this configuration, it is possible to provide a cross-point memory type nonvolatile memory device that can reduce the leakage current in addition to stabilizing the resistance change operation.
  • variable resistance nonvolatile memory element and the nonvolatile memory device of the present invention have an effect of stabilizing the resistance change operation in a nonvolatile memory element including a bipolar variable resistance element. Further, when such a nonvolatile memory element is applied to a cross-point memory cell array, there is an effect that leakage current of non-selected cells can be reduced.
  • FIG. 1 is a cross-sectional view illustrating an example of a schematic configuration of the nonvolatile memory element and the nonvolatile memory device according to the first embodiment of the present invention.
  • FIG. 2 is a top view illustrating an example of a schematic configuration of the nonvolatile memory element and the nonvolatile memory device according to the first embodiment of the present invention.
  • 3A and 3B are diagrams showing the characteristics of the resistance variable element.
  • FIG. 3A is a graph showing an example of the current-voltage characteristics of the resistance variable element 105, and FIG. It is the graph which showed an example of the change of resistance value when a target pulse is applied.
  • FIG. 4 is an explanatory diagram of a current limiting element having a symmetric current-voltage characteristic.
  • FIG. 4 (a) shows a current limiting element in which an n-type semiconductor is sandwiched between a lower electrode and an upper electrode made of the same metal.
  • FIG. 4B is a graph schematically showing current-voltage characteristics of the current limiting element of FIG. 4A.
  • FIG. 5 is an explanatory diagram of a current limiting element having asymmetric current-voltage characteristics.
  • FIG. 5A shows a current limiting element 112 (an n-type semiconductor formed of a lower electrode and an upper electrode made of different metals).
  • FIG. 5B is a graph schematically showing current-voltage characteristics of the current limiting element of FIG. 5A.
  • FIG. 6 is a diagram showing the voltage division relation and current at each interface in the current limiting element, and FIG.
  • FIG. 6A shows the voltage at each interface in the symmetrical current limiting element shown in FIG.
  • FIG. 6B is a diagram showing the voltage division relationship and current
  • FIG. 6B is a diagram showing the voltage division relationship and current at each interface in the asymmetric current limiting element shown in FIG.
  • FIG. 7 is a diagram for explaining a circuit of the nonvolatile memory device according to the first embodiment of the present invention.
  • FIG. 7A is a circuit diagram of the nonvolatile memory device according to the first embodiment of the present invention.
  • FIG. 7B is an equivalent circuit diagram showing currents flowing through the selected cell and the non-selected cell when the selected cell of FIG. 7A is used as a reference.
  • FIG. 8 is a table showing an example of selectable metal and semiconductor layers.
  • FIG. 8 is a table showing an example of selectable metal and semiconductor layers.
  • FIG. 9 is a process diagram showing a method for manufacturing the nonvolatile memory device 10 of the present embodiment, in which FIG. 9A shows a step of forming a first wiring on a substrate, and FIG. FIG. 9C shows a step of forming a first interlayer insulating layer, a first contact plug, and a second contact plug, FIG. 9C shows a step of forming a resistance variable element, and FIG. 9D ) Is a diagram showing a step of forming a second interlayer insulating layer, a third contact plug, and a fourth contact plug.
  • 10A and 10B are process diagrams illustrating a method for manufacturing the nonvolatile memory device 10 according to the present embodiment.
  • FIG. 9A shows a step of forming a first wiring on a substrate
  • FIG. 9C shows a step of forming a first interlayer insulating layer, a first contact plug, and a second contact plug
  • FIG. 9C shows a step of forming a resistance variable element
  • FIG. 10A illustrates a step of forming a current limiting element
  • FIG. 10B illustrates a third method
  • FIG. 10C shows a step of forming an interlayer insulating layer, a fifth contact plug, and a sixth contact plug
  • FIG. 10C shows a step of forming a second wiring and a lead wiring.
  • FIG. 11 is sectional drawing which shows an example of schematic structure of the non-volatile memory element and non-volatile memory device of 2nd Embodiment of this invention.
  • FIG. 12 is a cross-sectional view showing an example of a schematic configuration of the nonvolatile memory element and the nonvolatile memory device according to Embodiment 3 of the present invention.
  • FIG. 11 is sectional drawing which shows an example of schematic structure of the non-volatile memory element and non-volatile memory device of 2nd Embodiment of this invention
  • FIG. 12 is a cross-sectional view showing an example of a schematic configuration of the nonvolatile memory element and the non
  • FIG. 13 is a process diagram showing a method for manufacturing a main part of the nonvolatile memory device 30 of this embodiment.
  • FIG. 13A shows a conductive layer, a semiconductor layer, and a conductive layer on the second interlayer insulating layer.
  • FIG. 13B shows a step of forming a resist pattern on the conductive layer
  • FIG. 13C shows a step of forming the upper electrode of the current limiting element
  • FIG. 13D is a diagram showing a step of forming a resist pattern on a semiconductor layer using a desired mask
  • FIG. 13E is a diagram showing a step of forming a semiconductor layer and a lower electrode of a current limiting element. .
  • FIG. 14 is sectional drawing which shows an example of schematic structure of the non-volatile memory element and non-volatile memory device of 4th Embodiment of this invention.
  • FIG. 15 is a process diagram showing the method for manufacturing the nonvolatile memory device 40 of the present embodiment
  • FIG. 15A is a diagram showing the steps of forming the first wiring and the first conductive layer on the substrate.
  • FIG. 15B is a diagram showing a step of forming the first interlayer insulating layer, the through hole, and the first variable resistance layer
  • FIG. 15C is a step of filling the material of the second variable resistance layer.
  • FIG. 15D is a diagram showing a step of forming a first intermediate electrode
  • FIG. 15E is a diagram showing a step of forming a first contact plug.
  • FIG. 16 is a process diagram showing a method of manufacturing the nonvolatile memory device 40 of this embodiment.
  • FIG. 16A shows a first semiconductor layer, a second conductive layer, a second wiring, and a third wiring.
  • FIG. 16B shows a step of forming the conductive layer
  • FIG. 16B shows a step of forming the second interlayer insulating layer, the through hole, and the third resistance change layer
  • FIG. 16C shows the fourth step. It is a figure which shows the step which fills the material of the variable resistance layer of.
  • 17A and 17B are process diagrams showing a method for manufacturing the nonvolatile memory device 40 of the present embodiment, in which FIG.
  • FIG. 17A shows a step of forming a second intermediate electrode
  • FIG. FIG. 17C is a diagram showing a step of forming a second semiconductor layer, a fourth conductive layer, and a third wiring.
  • FIG. 18 is a process diagram showing a method of manufacturing the nonvolatile memory device 40 of this embodiment.
  • FIG. 18A shows a third interlayer insulating layer, a third contact plug 223, and a fourth contact plug.
  • FIG. 18B is a diagram showing the steps for forming the first lead-out wiring 225 and the second lead-out wiring 226.
  • FIG. 19 is a diagram showing a nonvolatile memory device equipped with a conventional variable resistance element.
  • FIG. 1 is a cross-sectional view illustrating an example of a schematic configuration of the nonvolatile memory element and the nonvolatile memory device according to the first embodiment of the present invention.
  • FIG. 2 is a top view illustrating an example of a schematic configuration of the nonvolatile memory element and the nonvolatile memory device according to the first embodiment of the present invention.
  • a cross-sectional view of the cross-section of the alternate long and short dash line indicated by 1A-1A ′ in FIG. 2 in the direction of the arrow corresponds to FIG.
  • the nonvolatile memory device 10 of this embodiment is roughly configured to be parallel to each other on the main surface of the substrate 100 and the substrate 100 and in a first direction (left and right direction in FIGS. 1 and 2).
  • a plurality of first wirings 101 formed so as to extend, and in parallel with each other in a plane parallel to the main surface of the substrate 100 above the plurality of first wirings 101 and in a second direction (paper surface in FIG. 1).
  • a plurality of second wirings 119 formed so as to extend in a direction perpendicular to the vertical direction (vertical direction in FIG.
  • a non-volatile memory element 11 provided to connect (electrically connect, hereinafter the same) the first wiring 101 and the second wiring 119 corresponding to each of the three-dimensional intersections with the wiring 119. I have.
  • the nonvolatile memory element 11 includes a variable resistance element 105, a current limiting element 112, and a third contact plug 110 that connects the variable resistance element 105 and the current limiting element 112.
  • the resistance change element 105 includes a lower electrode 106 (first electrode), an upper electrode 108 (second electrode), and a resistance change layer 107 interposed between the lower electrode 106 and the upper electrode 108. Yes.
  • the lower electrode 106 and the resistance change layer 107 are in physical contact, and the upper electrode 108 and the resistance change layer 107 are in physical contact.
  • the current limiting element 112 includes a lower electrode 113 (third electrode), an upper electrode 115 (fourth electrode), and a semiconductor layer 114 interposed between the lower electrode 113 and the upper electrode 115.
  • the lower electrode 113 and the semiconductor layer 114 are in physical contact, and the upper electrode 115 and the semiconductor layer 114 are in physical contact.
  • a first interlayer insulating layer 102 is formed on the substrate 100 so as to cover the first wiring 101.
  • the first wirings 101 are arranged at equal intervals on the first electrode wirings 101 as viewed from the stacking direction of the first wirings 101 (upward direction in FIG. 1; hereinafter referred to as the thickness direction).
  • a plurality of variable resistance elements 105 are formed.
  • the first wiring 101 and the lower electrode 106 of the resistance variable element 105 located thereabove are connected by a first contact plug 103 formed so as to penetrate the first interlayer insulating layer 102.
  • a second interlayer insulating layer 109 is formed on the first interlayer insulating layer 102 so as to cover the resistance variable element 105.
  • a plurality of current limiting elements 112 are formed on the second interlayer insulating layer 109 so as to overlap the resistance variable element 105 when viewed in the thickness direction.
  • the third contact plug 110 connects (shorts) the upper electrode 108 of the variable resistance element 105 and the lower electrode 113 of the current limiting element 112 without passing through either the variable resistance layer 107 or the semiconductor layer 114. .
  • a third interlayer insulating layer 116 is formed on the second interlayer insulating layer 109 so as to cover the current limiting element 112.
  • a second wiring 119 is formed on the third interlayer insulating layer 116 so as to be orthogonal to the first electrode wiring as viewed in the thickness direction and to overlap the resistance variable element 105 and the current limiting element 112. ing.
  • the second wiring 119 and the upper electrode 115 of the current limiting element 112 below the second wiring 119 are connected by a fifth contact plug 117 formed so as to penetrate the third interlayer insulating layer 116.
  • the lead is extended outside the region where the nonvolatile memory elements 11 are arranged in the thickness direction so as to extend in parallel with the second wiring 119, that is, in the second direction.
  • a wiring 120 is formed.
  • the second contact plug 104, the fourth contact plug 111, and the sixth contact plug 118 are connected to the first interlayer insulating layer 102, the first wiring 101 and the lead wiring 120, respectively. It is formed so as to penetrate the second interlayer insulating layer 109 and the third interlayer insulating layer 116. That is, the second contact plug 104, the fourth contact plug 111, and the sixth contact plug 118 are stacked in this order and connected to each other to form a stack contact, and the first wiring 101 and the lead wiring 120 is connected.
  • the first wiring 101, the second wiring 119, and the lead-out wiring 120 are made of, for example, aluminum.
  • the first interlayer insulating layer 102, the second interlayer insulating layer 109, and the third interlayer insulating layer 116 are made of, for example, silicon oxide.
  • the first contact plug 103, the second contact plug 104, the third contact plug 110, the fourth contact plug 111, the fifth contact plug 117, and the sixth contact plug 118 are made of, for example, tungsten. .
  • the nonvolatile memory element 11 is provided at each of the three-dimensional intersections of the first wiring 101 and the second wiring 119 that intersect with each other.
  • a nonvolatile memory device having a point-type memory cell array is realized.
  • the resistance change layer 107 includes an oxygen-deficient transition metal oxide (oxygen content [atomic ratio: occupies the total number of atoms as compared to the stoichiometric oxide]. Transition metal oxide) with a small proportion of oxygen atoms].
  • the resistance change layer 107 is a transition metal oxide made of tantalum oxygen-deficient oxide (TaO x : 0 ⁇ x ⁇ 2.5) or hafnium oxygen-deficient oxide (HfO x : 0 ⁇ x ⁇ 2). Including things. More preferably, the resistance change layer 107 is composed of an oxygen-deficient oxide of tantalum or an oxygen-deficient oxide of hafnium.
  • the standard electrode potential of the material (first material) constituting the lower electrode 106 is V1
  • the standard electrode potential of the material (second material) constituting the upper electrode 108 is V2.
  • the oxygen-deficient transition metal oxide included in the resistance change layer 107 assuming that the standard electrode potential of the transition metal itself (when the oxidation number of the transition metal is zero) is Vt, Vt ⁇ V2 and V1 ⁇ V2 Satisfy the relationship.
  • the material of the upper electrode 108 is less likely to be oxidized than the material of the resistance change layer 107.
  • the material of the upper electrode 108 is not oxidized and reduced, and the material of the resistance change layer 107 is oxidized and reduced.
  • the oxidation state of the resistance change layer 107 changes and a resistance change phenomenon appears.
  • the oxidation / reduction reaction at the electrode interface is preferentially developed on the upper electrode 108 side. That is, the interface where the resistance change phenomenon appears can be fixed to the upper electrode side.
  • a positive voltage (positive electrical signal) is applied to the upper electrode 108 side with respect to the lower electrode 106, and current flows from the upper electrode 108 to the lower electrode 106. .
  • electrons are taken from the variable resistance layer 107 to the electrode on the upper electrode side, whereby the material of the variable resistance layer 107 is oxidized and the resistance value increases.
  • a negative voltage negative electrical signal
  • current flows from the lower electrode 106 to the upper electrode 108.
  • electrons are applied from the electrode to the resistance change layer 107 on the upper electrode side, whereby the material of the resistance change layer 107 is reduced and the resistance value decreases.
  • tantalum nitride can be used for the lower electrode 106
  • platinum can be used for the upper electrode 108, for example.
  • V1 0.48V (standard electrode potential of tantalum nitride).
  • V2 1.18V (standard electrode potential of platinum).
  • Vt ⁇ 0.6 V (standard electrode potential of tantalum). Therefore, the relationship of Vt ⁇ V2 and V1 ⁇ V2 is satisfied.
  • Vt ⁇ 1.55 V (standard electrode potential of hafnium).
  • Vt ⁇ V2 and V1 ⁇ V2 is also satisfied.
  • the thickness of the resistance change layer can be set to 30 nm, for example.
  • FIG. 3A is a graph showing an example of the current-voltage characteristics of the resistance variable element 105
  • FIG. It is the graph which showed an example of the change of resistance value when a target pulse is applied.
  • the low resistance state is increased at point A. Change to resistance state (high resistance).
  • the voltage at point A is about +0.9 V, and the current is about +9 mA.
  • the point C Changes from a high resistance state to a low resistance state (lower resistance).
  • the voltage at point C is about -0.7 V, and the current is about -0.1 mA.
  • the high resistance state is a state in which the resistance value (resistance value between the lower electrode 106 and the upper electrode 108) is higher than that in the low resistance state.
  • the low resistance state refers to a state where the resistance value is lower than that of the high resistance state.
  • the resistance variable element 105 In order to increase the resistance of the resistance variable element 105, it is necessary to pass a current of about 9 mA so as to reach point A. On the other hand, in order to reduce the resistance, it is only necessary to reach point C, and only a current of about 0.1 mA needs to flow. That is, the resistance variable element 105 has a characteristic that the current required for increasing the resistance is larger than the current required for decreasing the resistance.
  • FIG. 3B shows an electrical pulse (electrical signal) having a voltage of +1.5 V and a pulse width of 100 nsec between the lower electrode 106 and the upper electrode 108 with respect to the lower electrode 106.
  • Measurement result of resistance value of resistance change element 105 resistance value between lower electrode 106 and upper electrode 1078 when an electric pulse having a voltage of ⁇ 1.2 V and a pulse width of 100 nsec is alternately applied. It is an example. As shown in the figure, when an electric pulse with a voltage of +1.5 V is applied, the resistance value becomes about 1200 to 1500 ⁇ (high resistance state). On the contrary, when an electric pulse with a voltage of -1.2 V is applied, the resistance value becomes about 150 ⁇ (low resistance state).
  • the absolute value of the voltage of the electric pulse applied when the resistance is increased is the absolute value of the voltage of the electric pulse applied when the resistance is decreased. It is larger than
  • the resistance variable element 105 has an asymmetric characteristic with respect to polarity.
  • the configuration of the current limiting element 112 in the above-described configuration includes a lower electrode 113 made of tungsten, a semiconductor layer 114 made of n-type semiconductor silicon, and an upper electrode 115 made of tantalum nitride.
  • the thickness of the semiconductor layer 114 can be 3 to 20 nm, for example.
  • Tungsten has a work function of 4.6 eV
  • silicon has an electron affinity of 3.78 eV
  • tantalum nitride has a work function of 4.76 eV.
  • the current limiting element 112 is an MSM diode using a Schottky barrier formed at the metal-semiconductor interface.
  • the current limiting element 112 has asymmetric current-voltage characteristics corresponding to the polarity of the voltage. That is, a voltage having an absolute value that is an arbitrary value that is greater than 0 and less than a predetermined voltage value and has a positive polarity (first polarity) on the upper electrode 115 with respect to the lower electrode 113.
  • the current that flows when a voltage is applied is the first current
  • the current that flows when a voltage having an absolute value of the first value and a negative polarity (second polarity different from the first polarity) is applied Is a second current
  • the current-voltage characteristic is such that the first current is larger than the second current. That is, the current limiting element 112 has a higher current driving capability when a voltage having the first polarity is applied than when a voltage having the second polarity is applied.
  • the predetermined voltage value is 1V
  • the predetermined voltage value is 1V
  • + aV is applied to the upper electrode with respect to the lower electrode.
  • the current that flows when the voltage is applied is larger than the current that flows when a voltage of ⁇ aV is applied to the upper electrode with reference to the lower electrode.
  • the current limiting element is an absolute value of an applied voltage in either the first polarity or the second polarity.
  • the larger the absolute value of the applied voltage the larger the absolute value of the applied voltage, and the larger the absolute value of the applied current, the greater the absolute value of the flowing current.
  • the element has a current-voltage characteristic (non-linear characteristic) in which the rate of change (slope: change amount of absolute value of current / change amount of absolute value of voltage) increases.
  • the predetermined voltage value can be specifically defined as follows.
  • the resistance variable element 105 and the current limiting element 112 are connected in series to form the nonvolatile memory element 11.
  • the nonvolatile memory element 11 is configured such that a voltage necessary for increasing or decreasing the resistance of the variable resistance element 105 is applied between the lower electrode 106 and the upper electrode 108 of the variable resistance element 105.
  • the voltage applied between the lower electrode 113 and the upper electrode 115 of the current limiting element 112 when a voltage is applied to both ends (the voltage applied to the current limiting element 112 when the resistance is increased or decreased)
  • the absolute value of the voltage having the larger absolute value can be set as the predetermined voltage value.
  • the current limiting element 112 can realize an appropriate current limit.
  • the predetermined voltage value include the variable resistance element described above (lower electrode: tantalum nitride, upper electrode: platinum, variable resistance layer: tantalum oxide, variable resistance layer thickness: 30 nm, as viewed from the thickness direction.
  • Shape 0.5 ⁇ m ⁇ 0.5 ⁇ m square
  • current limiting element lower electrode: tungsten, upper electrode: tantalum nitride, semiconductor layer: silicon, semiconductor layer thickness: 10 nm, shape viewed from the thickness direction: 0 .5 [mu] m x 0.5 [mu] m square), it can be set to 3.0 [V].
  • a current limiting element having a symmetric current-voltage characteristic corresponding to the polarity will be outlined.
  • Such a current limiting element can be obtained, for example, by configuring the lower electrode and the upper electrode with the same metal and sandwiching the n-type semiconductor between the two electrodes.
  • FIG. 4 is an explanatory diagram of a current limiting element having a symmetric current-voltage characteristic.
  • FIG. 4 (a) shows a current limiting element in which an n-type semiconductor is sandwiched between a lower electrode and an upper electrode made of the same metal.
  • FIG. 4B is a graph schematically showing current-voltage characteristics of the current limiting element of FIG. 4A.
  • the work function of the metal that is the electrode material is ⁇ 1
  • the work function of the n-type semiconductor is ⁇ s
  • the electron affinity of the n-type semiconductor is ⁇ s.
  • a Schottky barrier is formed at the interface between the metal (electrode) and the n-type semiconductor.
  • ⁇ B ⁇ 1 ⁇ s is satisfied. Since no current flows in the equilibrium state, the Fermi levels of the metal and n-type semiconductor match. Since the electron density at the center of the semiconductor layer sufficiently away from the interface with the metal does not change before contact, the energy band is bent downward.
  • the MSM diode exhibits a high resistance value due to the influence of the Schottky barrier generated at the interface that is reverse-biased when the absolute value of the voltage is below a certain level, but the absolute value of the voltage is at a certain level. If it exceeds, the resistance value will drop rapidly.
  • the current-voltage characteristics are symmetric with respect to polarity and non-linear with respect to voltage.
  • Being symmetric with respect to polarity means that when the absolute values of the applied voltages V are equal, the absolute values of the currents are equal.
  • the non-linearity with respect to the voltage means that a current does not flow so much in a region where the absolute value of the applied voltage is small, and a large current flows in a region where the absolute value of the applied voltage is large (curve I). That is, the slope ( ⁇ I / ⁇ V) increases as the absolute value of the applied voltage increases.
  • the current limiting element 112 having an asymmetric current-voltage characteristic corresponding to the polarity in this embodiment will be described.
  • the current limiting element 112 of the present embodiment is obtained by configuring the lower electrode and the upper electrode with different metals and sandwiching the n-type semiconductor between the two electrodes.
  • FIG. 5 is an explanatory diagram of a current limiting element having asymmetric current-voltage characteristics.
  • FIG. 5A shows a current limiting element 112 (an n-type semiconductor formed of a lower electrode and an upper electrode made of different metals).
  • FIG. 5B is a graph schematically showing current-voltage characteristics of the current limiting element of FIG. 5A.
  • the material of the lower electrode is metal 1, and the material of the upper electrode is metal 2.
  • the work function of metal 1 is ⁇ 1
  • the work function of metal 2 is ⁇ 2 (where ⁇ 2> ⁇ 1)
  • the work function of the n-type semiconductor is ⁇ s
  • the electron affinity of the n-type semiconductor is ⁇ s.
  • Schottky barriers having different heights are formed at the interface between the lower electrode and the n-type semiconductor and at the interface between the upper electrode and the n-type semiconductor, respectively.
  • the barrier on the upper electrode side is higher than the barrier on the lower electrode side. Therefore, when the upper electrode side is reverse biased (when a negative voltage is applied to the upper electrode with the lower electrode as a reference), when the upper electrode side is forward biased (a positive voltage is applied to the upper electrode with the lower electrode as a reference). Current) is less likely to flow (current drive capability is lower).
  • the current-voltage characteristics are asymmetric with respect to polarity and nonlinear with respect to voltage. It is the same as the curve I in FIG. 4B in that a current does not flow so much in a region where the absolute value of the applied voltage is small and a large current flows in a region where the absolute value of the applied voltage is large. However, if the absolute values of the voltages are equal, the current that flows when a positive voltage is applied to the upper electrode with respect to the lower electrode is greater than the current that flows when a negative voltage is applied to the upper electrode with respect to the lower electrode. It is getting bigger (curve II).
  • the negative part curve and the positive part curve Does not intersect at least in a range larger than 0 and smaller than a predetermined voltage value (for example, 1 V). Therefore, when an arbitrary value larger than 0 V and smaller than the predetermined voltage value is set to a and a voltage of + aV is applied to the upper electrode with the lower electrode as a reference, the current that flows when the lower electrode is used as a reference is -aV to the upper electrode. The relationship that it is always greater than the current that flows when a voltage is applied is satisfied.
  • the current flowing through the MSM diode element is limited by the reverse biased interface in the range where the absolute value of the applied voltage is below a certain level, so two Schottky diodes are connected in series in different directions. This can be explained by the connected model.
  • a mechanism in which the current-voltage characteristics are asymmetric in the current limiting element 112 will be described using the model.
  • FIG. 6 is a diagram showing the voltage division relation and current at each interface in the current limiting element
  • FIG. 6A shows the voltage at each interface in the symmetrical current limiting element shown in FIG.
  • FIG. 6B is a diagram showing the voltage division relationship and current
  • FIG. 6B is a diagram showing the voltage division relationship and current at each interface in the asymmetric current limiting element shown in FIG.
  • the negative voltage ⁇ V TOTAL is applied to the upper electrode with reference to the lower electrode.
  • the flowing current is ⁇ I 0
  • the voltage distributed to the upper electrode interface is ⁇ V R
  • the voltage distributed to the lower electrode interface is ⁇ V F. That is, in the symmetrical current limiting element, if the absolute values of the applied voltages are equal, the currents are equal in magnitude (see curve I in FIG. 5B).
  • FIG. 6B is a diagram showing the voltage division relationship and current at each interface in the asymmetric current limiting element shown in FIG.
  • the reverse bias current I 1R (> 0) flowing in the lower electrode interface is expressed by the following equation (5), where V 1R (> 0) is the voltage distributed to the lower electrode interface.
  • the forward bias direction current I 1F (> 0) flowing in the lower electrode interface is expressed by the following equation (7), where V 1F (> 0) is the voltage distributed to the lower electrode interface.
  • I U I L. That is, the case where a positive voltage is applied to the upper electrode 115 with respect to the lower electrode 113 (point C) is more than the case where a negative voltage is applied to the upper electrode 115 with respect to the lower electrode 113 (point B). A large current flows (see curve II in FIG. 5B). Thus, the asymmetrical current limiting element 112 is obtained by configuring the upper electrode 113 and the lower electrode 115 with different metals.
  • the specific characteristics of the current limiting element vary depending on the thickness of each layer and the size of the electrode surface.
  • the specific configuration of the current limiting element can be appropriately selected with reference to the above description so that desired characteristics can be obtained in relation to the resistance variable element and other components. Since such a specific design is easy for those skilled in the art, detailed description is omitted.
  • the resistance variable element 105 and the current limiting element 112 are connected in series, and the resistance variable element 105 transitions from the low resistance state to the high resistance state.
  • Polarity first polarity in which a large current flows through the current limiting element when the voltage applied to the current limiting element 112 is equal to the absolute value of the voltage applied to the current limiting element (when the resistance is increased) It is comprised so that.
  • a current flows from the upper electrode 108 to the lower electrode 106 of the variable resistance element 105.
  • the current flowing in such a direction means that a voltage having a polarity such that the upper electrode 115 becomes a positive potential with respect to the lower electrode 113 is applied to the corresponding current limiting element 112.
  • the polarity at which the upper electrode 115 becomes positive with respect to the lower electrode 113 is a polarity (first polarity) at which the current driving capability of the current limiting element 112 is increased.
  • the direction of the voltage for changing the resistance change layer 107 of the resistance change element 105 from the low resistance state to the high resistance state is the same as the direction in which the current driving capability of the current limiting element 112 is large, and the resistance change Of the variable resistance element 105 so that the direction of the voltage for changing the variable resistance layer 107 of the resistive element 105 from the high resistance state to the low resistance state is the same as the direction in which the current driving capability of the current limiting element is small.
  • the upper electrode 108 and the lower electrode 113 of the current limiting element 112 are connected without passing through either the resistance change layer 107 or the semiconductor layer 114.
  • variable resistance element 105 when the variable resistance element 105 is transitioned from the low resistance state to the high resistance state, and the first current flows through the current limiting element 112.
  • the variable resistance element 105 and the current limiting element 112 are connected in series so that the direction of the current at the time matches.
  • FIG. 7 is a diagram for explaining a circuit of the nonvolatile memory device according to the first embodiment of the present invention.
  • FIG. 7A is a circuit diagram of the nonvolatile memory device according to the first embodiment of the present invention.
  • FIG. 7B is an equivalent circuit diagram showing currents flowing through the selected cell and the non-selected cell when the selected cell of FIG. 7A is used as a reference.
  • 105 and the current limiting element 112 are formed to constitute a cross-point memory cell array. Since the current limiting element 112 has an asymmetric characteristic with respect to the polarity, the current driving capability is indicated by the magnitude of the symbols ⁇ and ⁇ of the diode element.
  • one upper electrode and the other lower electrode may be the same member.
  • the upper electrode of the resistance variable element and the lower electrode of the current limiting element may be the same member.
  • the upper electrode of the current limiting element and the lower electrode of the variable resistance element may be the same member.
  • EleSetPositionEleSetPosition when a current flows from the second wiring 119 to the first wiring 101 (when a current flows from the top to the bottom with respect to the substrate), the resistance variable element becomes highly resistive, The current drive capability of the limiting element is increased. However, when a current flows from the first wiring 101 to the second wiring 119 (when a current flows from the bottom to the top of the substrate), the resistance variable element increases in resistance, and the current of the current limiting element is increased. You may be comprised so that a driving capability may become large. In this case, for example, the materials of the upper electrode and the lower electrode may be switched in each of the resistance variable element and the current limiting element. Further, the arrangement (vertical relationship) of the resistance variable element and the current limiting element may be switched.
  • FIG. 8 is a table showing an example of selectable metal and semiconductor layers. Further, by adding nitrogen to n-type silicon, the current driving capability can be reduced ( ⁇ B can be increased), and a desired current driving capability can be designed. Moreover, the effect similar to the case where a different electrode is used can be acquired by giving the magnitude relationship of the nitrogen addition amount of an upper electrode interface, and the nitrogen addition amount of a lower electrode interface. Therefore, it is possible to form a current limiting element having asymmetric characteristics by making the amount of nitrogen added different between the upper electrode side and the lower electrode side.
  • the semiconductor layer of the current limiting element can be made of any semiconductor material such as silicon nitride other than silicon. In the actual nonvolatile memory device 10, it is preferable to use silicon nitride because of the electrical resistance and current capacity.
  • FIG. 9A shows a step of forming the first wiring on the substrate
  • FIG. 9B shows a step of forming the first interlayer insulating layer, the first contact plug, and the second contact plug
  • FIG. 9C shows a step of forming a resistance variable element
  • FIG. 9D shows the formation of a second interlayer insulating layer, a third contact plug, and a fourth contact plug. It is a figure which shows a step.
  • FIG. 10A is a diagram showing a step of forming a current limiting element
  • FIG. 10B is a diagram showing a step of forming a third interlayer insulating layer, a fifth contact plug, and a sixth contact plug.
  • FIG. 10C is a diagram showing steps for forming the second wiring and the lead-out wiring.
  • the first wiring 101 is formed on the substrate 100 on which a transistor, a lower layer wiring, and the like are formed using a desired mask. It is formed.
  • the substrate is coated so as to cover the first wiring 101.
  • a first interlayer insulating layer 102 is formed on the entire surface of 100.
  • a contact hole (opening) reaching the first wiring 101 through the first interlayer insulating layer 102 is formed.
  • a first contact plug 103 and a second contact plug 104 are formed by filling the contact hole with a filler mainly composed of tungsten.
  • a conductive layer made of is formed in this order. Patterning is performed with a desired mask so that the upper end surface of the first contact plug 103 is covered and the upper end surface of the second contact plug 104 is exposed, and the lower electrode 106 and the resistance change layer 107 of the resistance change element 105 are exposed.
  • the upper electrode 108 is formed.
  • the oxygen-deficient tantalum oxide can be formed by, for example, so-called reactive sputtering, in which a target made of tantalum is sputtered in an argon and oxygen gas atmosphere.
  • the first variable resistance element 105 is covered.
  • a second interlayer insulating layer 109 is formed on the entire surface of the interlayer insulating layer 102.
  • a contact hole (opening) that reaches the upper electrode 108 of the resistance variable element 105 through the second interlayer insulating layer 109 and a contact hole (through the second interlayer insulating layer 109 that reaches the second contact plug 104) Opening) is formed.
  • a third contact plug 110 is formed by filling the former contact hole with a filler mainly composed of tungsten.
  • a filler mainly composed of tungsten is embedded in the latter contact hole to form the fourth contact plug 111.
  • a conductive layer made of tungsten, a semiconductor layer made of silicon or silicon nitride, and tantalum nitride are formed on the second interlayer insulating layer 109.
  • the conductive layers to be formed are formed in this order. Patterning is performed with a desired mask so that the upper end surface of the third contact plug 110 is covered and the upper end surface of the fourth contact plug 111 is exposed, and the lower electrode 113, the semiconductor layer 114, and the upper portion of the current limiting element 112 are formed.
  • An electrode 115 is formed.
  • the second limit so as to cover the current limiting element 112 is performed.
  • a third interlayer insulating layer 116 is formed on the entire surface of the interlayer insulating layer.
  • a filler mainly composed of tungsten is embedded in the former contact hole to form a fifth contact plug 117.
  • a filler containing tungsten as a main component is buried in the latter contact hole to form a sixth contact plug 118.
  • the upper end surface of the fifth contact plug 117 is covered on the third interlayer insulating layer 116.
  • the lead wiring 120 is patterned with a desired mask so as to cover the second wiring 119 and the upper end surface of the sixth contact plug 118.
  • variable resistance nonvolatile memory device that stably performs a variable resistance operation.
  • FIG. 11 is sectional drawing which shows an example of schematic structure of the non-volatile memory element and non-volatile memory device of 2nd Embodiment of this invention.
  • the nonvolatile memory device 20 and the nonvolatile memory element 21 of the second embodiment are different from the nonvolatile memory device 10 and the nonvolatile memory element 11 of the first embodiment in that the resistance change layer of the resistance change element has a laminated structure. And different.
  • Other configurations are the same as those of the first embodiment. Therefore, in 2nd Embodiment, the same code
  • the resistance change layer includes two layers: a resistance change layer 107 a (first layer) and a resistance change layer 107 b (second layer). Become.
  • the resistance change layer 107a and the resistance change layer 107b are made of the same element. That is, it is an oxygen-deficient oxide of the same transition metal.
  • the oxygen content of the contact resistance variable layer 107a in contact with the lower electrode 106 (the transition metal is M, when the composition of the resistance variable layer 107a represented as MO x, value of x) is in contact with the upper electrode 108 resistance oxygen content of the change layer 107b (the transition metal is M, when the composition of the resistance variable layer 107b represented as MO y, the value of y) is lower than (x ⁇ y).
  • the mechanism of resistance change operation is dominated by the oxidation-reduction reaction of the transition metal near the electrode interface. Therefore, the resistance change phenomenon preferentially appears on the upper electrode side (interface between the upper electrode 108 and the resistance change layer 107b) rich in oxygen that can contribute to the oxidation-reduction reaction.
  • the thickness of the resistance change layer 107a and the resistance change layer 107b can be, for example, 30 to 50 nm.
  • the shape of the resistance change layer 107a and the resistance change layer 107b viewed from the thickness direction can be, for example, a square of 0.5 ⁇ m ⁇ 0.5 ⁇ m.
  • a resistance change type nonvolatile memory device and a nonvolatile memory element that perform a resistance change operation more stably can be realized by always stabilizing the interface where the resistance change phenomenon occurs.
  • the resistance change layers having different oxygen contents can be formed, for example, by the resistance change layer manufacturing method (reactive sputtering method) shown in the first embodiment. That is, if the oxygen flow rate during film formation is increased, the oxygen content of the stacked tantalum oxide is increased, and if the oxygen flow rate is decreased, the oxygen content is decreased.
  • FIG. 12 is a cross-sectional view showing an example of a schematic configuration of the nonvolatile memory element and the nonvolatile memory device according to Embodiment 3 of the present invention.
  • the nonvolatile memory device 30 and the nonvolatile memory element 31 of the third embodiment are different from each other in that the sizes (contact areas) of the lower electrode and the upper electrode of the current limiting element are different. 20 and the nonvolatile memory element 21.
  • Other configurations are the same as those of the second embodiment. Therefore, in 3rd Embodiment, the same code
  • the contact area between the lower electrode 113 and the semiconductor layer 114 is S1
  • the contact area between the upper electrode 115 ′ and the semiconductor layer 114 is S2.
  • a positive voltage is applied to the second wiring 119 with respect to the first wiring 101.
  • a large current necessary for increasing the resistance can be obtained.
  • a negative voltage is applied to the second wiring 119 with respect to the first wiring 101 (when the resistance change element 105 is reduced in resistance)
  • a minimum current necessary for reducing the resistance is passed.
  • the current limiting element 112 ′ can prevent a large current from flowing suddenly after the resistance is lowered. Accordingly, it is possible to realize a variable resistance nonvolatile memory element and a nonvolatile memory device that stably perform a resistance changing operation.
  • FIG. 13 is a process diagram showing a method for manufacturing the main part of the nonvolatile memory device 30 of this embodiment. Since the manufacturing method of other parts is the same as that of the first embodiment, the description thereof is omitted.
  • FIG. 13A shows a step of forming a conductive layer, a semiconductor layer, and a conductive layer in this order on the second interlayer insulating layer
  • FIG. 13B shows a step of forming a resist pattern on the conductive layer
  • FIG. 13C is a diagram showing a step of forming the upper electrode of the current limiting element
  • FIG. 13D is a diagram showing a step of forming a resist pattern on the semiconductor layer using a desired mask.
  • 13 (e) is a diagram showing a step of forming a semiconductor layer and a lower electrode of the current limiting element.
  • the third contact plug 110 and the fourth contact plug 111 are formed.
  • a conductive layer 113a made of tungsten, a semiconductor layer 114a made of silicon or silicon nitride, and a conductive layer 115a made of tantalum nitride are formed in this order on the entire surface of the formed second interlayer insulating layer 109. .
  • a resist pattern 121 is formed on the conductive layer 115a made of tantalum nitride using a desired mask.
  • the conductive layer 115a made of tantalum nitride is patterned using the resist pattern 121, so that the upper electrode of the current limiting element is formed. 115 'is formed and the remaining resist is removed.
  • silicon is used so that the upper electrode 115 ′ of the current limiting element 112 ′ is covered.
  • a resist pattern 122 is formed on the resulting semiconductor layer 114a using a desired mask.
  • the upper surface of the third contact plug 110 is covered with the resist pattern 122 and the fourth
  • the semiconductor layer 114a made of silicon or silicon nitride and the conductive layer 113a made of tungsten are patterned so that the upper end surface of the contact plug 111 is exposed, and the semiconductor layer 114 and the lower electrode 113 of the current limiting element 112 ′ are formed.
  • the nonvolatile memory device 40 and the nonvolatile memory element 41 of the fourth embodiment are different from the first to third embodiments in that the lower electrode of the resistance variable element is formed integrally with the wiring and the remainder is passed through. It is formed in the hole, the lower electrode of the current limiting element is formed in the through hole, the remainder is formed integrally with the wiring, and the memory cell is further divided into two layers.
  • the fourth embodiment is suitable for miniaturization and large capacity.
  • the nonvolatile memory device 40 of this embodiment is roughly configured to extend in parallel with each other on the main surface of the substrate 200 and the substrate 200 and in the first direction (left-right direction in FIG. 14).
  • a plurality of formed first wirings 201 and a plane parallel to the main surface of the substrate 200 above the plurality of first wirings 201 are parallel to each other and in a second direction (perpendicular to the paper surface in FIG. 14).
  • a plurality of second wirings 211 formed so as to extend three-dimensionally with the plurality of first wirings 201, and the main surface of the substrate 200 above the plurality of second wirings 211.
  • a plurality of third wirings 221 formed so as to extend parallel to each other in a parallel plane and in a third direction (left-right direction in FIG. 14) and to form a three-dimensional intersection with the plurality of second wirings 211; , First wiring 2
  • a first nonvolatile memory element 41 provided to connect the first wiring 201 and the second wiring 211 corresponding to each of the three-dimensional intersections of the first wiring 211 and the second wiring 211;
  • a second nonvolatile memory element 42 provided to connect the second wiring 211 and the third wiring 221 corresponding to each of the three-dimensional intersections of the wiring 211 and the third wiring 221 is provided.
  • the first wiring 201 and the third wiring 221 have the same shape when viewed from the stacking direction of the first wiring 201 (upward direction in FIG. 14; hereinafter, the thickness direction) and are mutually connected. They are overlapping.
  • the first nonvolatile memory element 41 includes a first variable resistance element 204 and a first current limiting element 208.
  • the upper electrode of the first variable resistance element 204 and the lower electrode of the first current limiting element 208 are the same member.
  • the first variable resistance element 204 includes a first conductive layer 202 constituting a lower electrode (second electrode), a first intermediate electrode 206 constituting an upper electrode (first electrode), and these two And a resistance change layer sandwiched between two electrodes.
  • the variable resistance layer includes two layers, a first variable resistance layer 205b (second layer) and a second variable resistance layer 205a (first layer).
  • the first resistance change layer 205b in contact with the first conductive layer 202 is made of an oxygen-deficient tantalum oxide having a high oxygen content.
  • the second variable resistance layer 205a in contact with the first intermediate electrode 206 is made of an oxygen-deficient tantalum oxide having a low oxygen content. Note that hafnium oxide may be used instead of tantalum oxide. Alternatively, other oxygen-deficient transition metal oxides may be used.
  • the definition of the oxygen content in the first variable resistance layer 205b and the second variable resistance layer 205a is the same as that in the second embodiment, and thus detailed description thereof is omitted.
  • the thicknesses of the first resistance change layer 205a and the second resistance change layer 205b can be set to, for example, 100 to 200 nm and 1 to 10 nm, respectively.
  • the diameters of the first variable resistance layer 205a and the second variable resistance layer 205b viewed from the thickness direction can be set to 50 to 300 nm ⁇ , for example.
  • the first current limiting element 208 includes a first intermediate electrode 206 constituting a lower electrode (first electrode), a second conductive layer 210 constituting an upper electrode (third electrode), and the two And a first semiconductor layer 209 sandwiched between electrodes.
  • the first intermediate electrode 206 plays two roles of an upper electrode of the first variable resistance element 204 and a lower electrode of the first current limiting element 208.
  • the second nonvolatile memory element 42 includes a second variable resistance element 214 and a second current limiting element 218.
  • the upper electrode of the second variable resistance element 224 and the lower electrode of the second current limiting element 228 are the same member.
  • the second resistance variable element 214 includes a third conductive layer 212 constituting a lower electrode (second electrode), a second intermediate electrode 216 constituting an upper electrode (first electrode), And a resistance change layer sandwiched between two electrodes.
  • the resistance change layer includes two layers, a third resistance change layer 215b (second layer) and a fourth resistance change layer 215a (first layer).
  • the third resistance change layer 215b in contact with the third conductive layer 212 is made of an oxygen-deficient tantalum oxide having a high oxygen content.
  • the fourth variable resistance layer 215a in contact with the second intermediate electrode 216 is made of an oxygen-deficient tantalum oxide having a low oxygen content. Note that hafnium oxide may be used instead of tantalum oxide. Alternatively, other oxygen-deficient transition metal oxides may be used.
  • the definition of the oxygen content in the third resistance change layer 215b and the fourth resistance change layer 215a is the same as that in the second embodiment, and a detailed description thereof will be omitted.
  • the thicknesses of the third resistance change layer 215a and the fourth resistance change layer 215b can be set to 100 to 200 nm and 1 to 10 nm, respectively, for example.
  • the second current limiting element 218 includes a second intermediate electrode 216 constituting a lower electrode (first electrode), a fourth conductive layer 220 constituting an upper electrode (third electrode), and the two And a second semiconductor layer 219 sandwiched between electrodes.
  • the second intermediate electrode 216 plays two roles of an upper electrode of the second variable resistance element 214 and a lower electrode of the second current limiting element 218.
  • the first wiring 201 and the first conductive layer 202 are stacked in this order so as to overlap each other in the same shape when viewed from the thickness direction.
  • a first interlayer insulating layer 203 is formed so as to cover the first wiring 201 and the first conductive layer 202.
  • a plurality of through-holes are formed on the first conductive layer 202 so as to penetrate the first interlayer insulating layer 203 and reach the first conductive layer 202 and are arranged at equal intervals when viewed from the thickness direction.
  • the first resistance change layer 205b, the second resistance change layer 205a, and the first intermediate electrode 206 are stacked in this order on the first conductive layer 202 exposed in the through hole. Yes.
  • the first semiconductor layer 209, the second conductive layer 210, the second wiring 211, and the third conductive layer are formed so as to cover the upper end surface of the first intermediate electrode 206.
  • the layers 212 are laminated in this order so as to overlap each other in the same shape when viewed from the thickness direction.
  • a second interlayer insulating layer 213 is formed so as to cover the first semiconductor layer 209, the second conductive layer 210, the second wiring 211, and the third conductive layer 212.
  • a plurality of through holes are formed on the third conductive layer 212 so as to penetrate the second interlayer insulating layer 213 and reach the third conductive layer 212 so as to be arranged at equal intervals in the thickness direction.
  • a third variable resistance layer 215b, a fourth variable resistance layer 215a, and a second intermediate electrode 216 are stacked in this order on the third conductive layer 212 formed and exposed in the through hole. .
  • the second interlayer insulating layer 213, the second semiconductor layer 219, the fourth conductive layer 220, and the third wiring 221 are arranged in the thickness direction so as to cover the upper end surface of the second intermediate electrode 216. Are stacked in this order so as to overlap each other in the same shape as viewed from the top.
  • a third interlayer insulating layer 222 is formed so as to cover the second semiconductor layer 219, the fourth conductive layer 220, and the third wiring 221.
  • a contact hole is formed at the end of the third wiring so as to penetrate the third interlayer insulating layer 222 and reach the third wiring, and on the third wiring exposed in the contact hole.
  • a fourth contact plug 224 is formed, and a first lead-out wiring 225 is formed so as to cover the upper end surface of the fourth contact plug 224 and extend in a fourth direction that three-dimensionally intersects with the third wiring.
  • the second lead wiring 226 is formed so as to extend in the fourth direction.
  • the first contact plug 207, the second contact plug 217, and the third contact plug 223 are connected to the first interlayer insulating layer 203, the first wiring 201, and the lead wiring 226, respectively. It is formed so as to penetrate the second interlayer insulating layer 213 and the third interlayer insulating layer 222. That is, the first contact plug 107, the second contact plug 217, and the third contact plug 223 are stacked in this order and connected to each other to form a stack contact, and the first wiring 201 and the lead wiring 226 is connected.
  • the first nonvolatile memory elements 41 are provided at the three-dimensional intersections of the first wiring 201 and the second wiring 211 that intersect each other.
  • the first conductive layer 202 and the third conductive layer 212 function as a lower electrode of the resistance variable element, and are made of, for example, platinum.
  • the first intermediate electrode 206 and the second intermediate electrode 216 function as an upper electrode of the resistance variable element and a lower electrode of the current limiting element, and are made of, for example, tantalum nitride.
  • the second conductive layer 210 and the fourth conductive layer 220 function as an upper electrode of the current limiting element, and are made of, for example, tungsten.
  • the first semiconductor layer 209 and the second semiconductor layer 219 are made of, for example, silicon or silicon nitride.
  • the first wiring 201, the second wiring 211, the third wiring 221, the first lead wiring 225, and the second lead wiring 226 are made of, for example, copper.
  • the first contact plug 207, the second contact plug 217, the third contact plug 223, and the fourth contact plug 224 are made of, for example, tungsten.
  • the first interlayer insulating layer 203, the second interlayer insulating layer 213, and the third interlayer insulating layer 222 are made of, for example, silicon oxide.
  • Vt ⁇ 0.6 V (standard electrode potential of tantalum).
  • Vt ⁇ 1.55 V (hafnium standard electrode potential). Therefore, in any case, the relationship of Vt ⁇ V2 and V1 ⁇ V2 is satisfied.
  • the first resistance change layer 205b in contact with the lower electrode has a higher oxygen content than the second resistance change layer 205a in contact with the upper electrode, and the third resistance change layer 215b in contact with the lower electrode is higher.
  • the oxygen content is higher than that of the fourth resistance change layer 215a in contact with the electrode. Therefore, for the reasons described in the first and second embodiments, the resistance change phenomenon is preferentially expressed at the interface between the lower electrode and the resistance change layer.
  • the resistance variable element and the current limiting element are connected in series, and the resistance variable element transitions from the low resistance state to the high resistance state.
  • the current limiting element is configured to have a polarity in which a large current flows when the absolute value of the voltage applied to the current limiting element is equal.
  • a current flows from the lower electrode to the upper electrode of the variable resistance element.
  • the current flowing in such a direction means that a voltage having a polarity such that the upper electrode has a negative potential with respect to the lower electrode is applied to the corresponding current limiting element.
  • the polarity at which the upper electrode has a negative potential with respect to the lower electrode is a polarity that increases the current driving capability of the current limiting element.
  • the direction of the voltage for changing the resistance change layer of the resistance variable element from the low resistance state to the high resistance state is the same as the direction in which the current driving capability of the current limiting element is large.
  • the upper electrode of the resistance variable element and the current limiting element are arranged so that the direction of the voltage for changing the resistance variable layer from the high resistance state to the low resistance state is the same as the direction in which the current driving capability of the current limiting element is small.
  • the lower electrode is made of the same member.
  • the upper electrode of the resistance variable element and the lower electrode of the current limiting element are formed of the same member, and the lower electrode of the resistance variable element
  • the semiconductor layer and the upper electrode of the current limiting element are formed so as to overlap the wiring in the same shape as the wiring as viewed from the thickness direction. For this reason, it is suitable for miniaturization and large capacity.
  • the lower electrode of the resistance variable element and the upper electrode of the current limiting element are the same member (second electrode).
  • the whole top and bottom may be swapped. That is, the resistance variable element 204 is increased in resistance when a positive voltage is applied to the second wiring 211 with the first wiring 201 as a reference, and the third wiring 221 with the second wiring 211 as a reference.
  • the nonvolatile memory device 40 and the nonvolatile memory elements 41 and 42 may be configured so that the resistance variable element 214 has a high resistance when a positive voltage is applied to the capacitor.
  • the direction of the current that flows when the resistance change element 204 and the resistance change element 214 are increased in resistance may be upside down.
  • [Production method] 15 to 18 are process diagrams showing a method for manufacturing the nonvolatile memory device 40 of this embodiment.
  • FIG. 15A is a diagram showing steps for forming the first wiring and the first conductive layer on the substrate
  • FIG. 15B is a diagram showing the first interlayer insulating layer, the through hole, the first resistance change layer, and the like.
  • FIG. 15C shows a step of filling the material of the second resistance change layer
  • FIG. 15D shows a step of forming the first intermediate electrode
  • FIG. 15E is a diagram showing a step of forming a first contact plug.
  • FIG. 16A is a diagram showing steps for forming the first semiconductor layer, the second conductive layer, the second wiring, and the third conductive layer
  • FIG. 16B is a diagram showing the second interlayer insulating layer
  • FIG. 16C is a diagram showing a step of forming a through hole and a third variable resistance layer
  • FIG. 16C is a diagram showing a step of filling the material of the fourth variable resistance layer.
  • FIG. 17A shows a step of forming the second intermediate electrode
  • FIG. 17B shows a step of forming the second contact plug
  • FIG. 17C shows the second semiconductor layer. It is a figure which shows the step which forms a 4th conductive layer and 3rd wiring.
  • FIG. 18A is a diagram showing steps for forming the third interlayer insulating layer, the third contact plug 223, and the fourth contact plug
  • FIG. 18B is a diagram showing the first lead wiring 225 and the second contact plug 223.
  • FIG. 11 is a diagram showing steps for forming a lead wiring 226.
  • the first wiring 201 is formed on the substrate 200 on which a transistor, a lower layer wiring, and the like are formed.
  • the material (copper) and the material of the first conductive layer 202 (platinum) are stacked in this order, patterning is performed using a desired mask, whereby the first wiring 201 and the first conductive layer 202 are formed.
  • FIG. 15B in the step of forming the first interlayer insulating layer, the through hole, and the first variable resistance layer, the first wiring 201 and the first conductive layer 202 are covered.
  • the first interlayer insulating layer 203 is formed on the entire surface of the substrate 200.
  • a through hole (opening) that penetrates through the first interlayer insulating layer 203 and reaches the first conductive layer 202 is formed.
  • an oxygen-deficient tantalum oxide having a high oxygen content is stacked by sputtering to form the first resistance change layer 205b. .
  • Unnecessary variable resistance layers stacked on the first interlayer insulating layer 203 are removed by CMP).
  • an oxygen-deficient tantalum oxide having a low oxygen content is formed in the through hole using a sputtering method. Filled. (An unnecessary variable resistance layer stacked on the first interlayer insulating layer 203 is also removed by the CMP method).
  • a first intermediate electrode 206 made of tantalum nitride is embedded and formed in a recess formed on the second variable resistance layer 205a by sputtering (laminated on the first interlayer insulating layer 203). Unnecessary tantalum nitride is removed by CMP).
  • a contact hole that penetrates through the first interlayer insulating layer 203 and reaches the first conductive layer 202 is formed.
  • the contact hole is filled with tungsten to form a first contact plug 207.
  • the first interlayer insulating layer 203 is formed.
  • the material of the first semiconductor layer 209 silicon or silicon nitride
  • the material of the second conductive layer 210 tungsten
  • the material of the second wiring 211 copper
  • the material of the third conductive layer 212 platinum
  • patterning is performed with a desired mask so that the upper end surface of the first intermediate electrode 206 is covered and the upper end surface of the first contact plug 207 is exposed.
  • the patterning is performed so that the second wiring 211 is orthogonal to the first wiring 201 when viewed from the thickness direction.
  • the first semiconductor layer 209, the second conductive layer 210, the second wiring 211, and the third conductive layer 212 are completed.
  • a second interlayer insulating layer 213 is formed on the entire surface of the first interlayer insulating layer 203 so as to cover the second wiring 211 and the third conductive layer 212.
  • a through hole (opening) that reaches the third conductive layer 212 through the second interlayer insulating layer 213 is formed.
  • an oxygen-deficient tantalum oxide having a high oxygen content is stacked by sputtering to form the third resistance change layer 215b.
  • an oxygen-deficient tantalum oxide having a low oxygen content is formed in the through hole by a sputtering method. Filled (the unnecessary variable resistance layer stacked on the second interlayer insulating layer 213 is also removed by the CMP method).
  • a part of the oxygen-deficient tantalum oxide having a low oxygen content is removed by an etching method, and the fourth resistance The change layer 215a is completed.
  • a second intermediate electrode 216 made of tantalum nitride is embedded in the recess formed on the fourth variable resistance layer 215a by sputtering (stacked on the second interlayer insulating layer 213). Unnecessary tantalum nitride is removed by CMP).
  • a contact hole that penetrates through the second interlayer insulating layer 213 and reaches the third conductive layer 212 is formed.
  • the contact hole is filled with tungsten to form a second contact plug 2 17.
  • the second semiconductor layer is formed on the second interlayer insulating layer 213.
  • the material 219 silicon or silicon nitride
  • the material of the fourth conductive layer 220 tungsten
  • the material of the third wiring 221 copper
  • patterning is performed with a desired mask so that the upper end surface of the second intermediate electrode 216 is covered and the upper end surface of the second contact plug 217 is exposed.
  • the patterning is performed so that the third wiring 221 is orthogonal to the second wiring 211 when viewed from the thickness direction.
  • a third interlayer insulating layer 222 is formed on the entire surface of the second interlayer insulating layer 213 so as to cover 220 and the third wiring 221.
  • a contact hole (opening) is formed so as to penetrate the third interlayer insulating layer 222 and reach the upper end surface of the second contact plug 217 and the third wiring 221.
  • Each contact hole is filled with tungsten to form a third contact plug 223 and a fourth contact plug 224 (unnecessary tungsten stacked on the third interlayer insulating layer 222 is removed by CMP). ).
  • the third contact plug 223 and the second lead plug 223 and the second lead wiring 226 are formed on the third interlayer insulating layer 222.
  • the lead wiring 225 and the lead wiring 226 are patterned with a desired mask so that the upper end surfaces of the four contact plugs 224 are covered.
  • nonvolatile memory element and nonvolatile memory device of the present invention are useful as a variable resistance nonvolatile memory element and nonvolatile memory device that can stabilize the resistance change operation and reduce the leakage current of the cross-point memory.
  • Nonvolatile Memory Device According to First Embodiment of the Present Invention 11 Nonvolatile Memory Device According to First Embodiment of the Present Invention 20 Nonvolatile Memory Device According to Second Embodiment of the Present Invention 21 Second Embodiment of the Present Invention Nonvolatile memory element 30 according to the third embodiment of the present invention 31 Nonvolatile memory element according to the third embodiment of the present invention 40 Nonvolatile memory apparatus according to the fourth embodiment of the present invention 41 Nonvolatile Memory Element According to Fourth Embodiment of Invention 42 Nonvolatile Memory Element According to Fourth Embodiment of Present Invention 50 Nonvolatile Memory Device 100 Mounted with Conventional Variable Resistance Element Substrate 101 First Wiring 102 First Interlayer insulating layer 103 First contact plug 104 Second contact plug 105 Resistance change element 106 Lower electrode 107 of resistance change element Resistance change layer 1 Low resistance layer of 7a oxygen content (first layer) 107b Variable resistance layer with high oxygen content (second layer) 108 Upper electrode 109 of variable resistance element

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Abstract

L’invention concerne un élément à résistance variable (105) qui passe de manière réversible entre un état de faible résistance et un état de haute résistance par application de signaux électriques de différentes polarités. Si un courant, circulant lorsqu'une tension d'une première polarité est appliquée (cette tension étant une première valeur qui est une valeur arbitraire pour laquelle la valeur absolue est supérieure à 0 et inférieure à une valeur de tension prédéterminée), est défini en tant que premier courant, et qu'un courant, circulant lorsqu'une tension d'une seconde polarité différente de la première polarité (la valeur absolue de cette tension étant la première valeur), est défini en tant que second courant, un élément de limitation de courant (112) permet au premier courant de devenir supérieur au second courant. Lorsque l'élément à résistance variable (105) passe d'un état de faible résistance à un état de haute résistance, l'élément à résistance variable (105) et l'élément de limitation de courant (112) sont connectés en série de telle sorte que la polarité de la tension appliquée à l'élément de limitation de courant (112) devient la première polarité.
PCT/JP2009/006196 2008-11-19 2009-11-18 Elément de mémoire non volatile et dispositif de mémoire non volatile WO2010058569A1 (fr)

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