WO2009119248A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2009119248A1 WO2009119248A1 PCT/JP2009/053715 JP2009053715W WO2009119248A1 WO 2009119248 A1 WO2009119248 A1 WO 2009119248A1 JP 2009053715 W JP2009053715 W JP 2009053715W WO 2009119248 A1 WO2009119248 A1 WO 2009119248A1
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Images
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1602—Diamond
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/47—Schottky barrier electrodes
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Definitions
- the present invention relates to a semiconductor device formed of a semiconductor material in which the energy level of a conductive impurity is deeper than the thermal excitation energy corresponding to the operating temperature.
- Non-Patent Document 1 a technique of forming a pn junction diode using a diamond semiconductor is known (see Non-Patent Document 1).
- the energy level of the conductive impurity is deeper than the thermal excitation energy corresponding to the operating temperature.
- the acceptor and donor with the shallowest energy level are B (boron) and P (phosphorus), respectively, but the energy levels of B and P are 0.37 eV and 0.6 eV, respectively, Is greater by one digit or more than the thermal excitation energy of 0.026 eV.
- the current density is about several A / cm 2 (8 V) at the maximum, which is compared with a pn junction diode or the like formed of silicon carbide. Then, it is a value that is two or more digits lower.
- the present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device capable of flowing a high-density current.
- the semiconductor device has a first semiconductor having the first conductivity type, a second conductivity type different from the first conductivity type, and an impurity concentration higher than the impurity concentration of the first semiconductor.
- the first semiconductor layer is joined to the first semiconductor layer to form a rectifying contact, and the second electrode is formed to be in ohmic contact with the second semiconductor layer.
- FIG. 4 is a cross-sectional process diagram for explaining the flow of the manufacturing method of the junction element shown in FIG. 3.
- FIG. 4 is a diagram showing current-voltage characteristics of the junction element shown in FIG. 3.
- FIG. 4 is a diagram showing forward current density-voltage characteristics of the junction element shown in FIG. 3. The light emission characteristic when a voltage is applied to the junction element shown in FIG. 3 in the forward direction is shown.
- FIG. 11 is a cross-sectional process diagram for explaining the flow of the manufacturing method of the junction element shown in FIG. 10.
- FIG. 13 is a cross-sectional process diagram for describing the flow of the manufacturing method of the bonding element shown in FIG. 12.
- the present invention is applicable to all semiconductor materials in which at least one of a donor level and an acceptor level such as boron (BN) is sufficiently deeper than thermal excitation energy corresponding to the operating temperature.
- a donor level and an acceptor level such as boron (BN)
- thermal excitation energy is used.
- the present invention can be applied when operating at a low temperature at which the temperature becomes sufficiently low.
- a semiconductor substrate on which an epitaxial layer or other film or electrode is formed is referred to as a “diamond substrate” or simply “substrate” unless otherwise specified.
- FIG. 1 is a schematic diagram showing the configuration of the junction element according to the first embodiment of the present invention.
- the junction element 1 includes a first conductivity type semiconductor layer 2, a second conductivity type semiconductor layer 3 bonded to the semiconductor layer 2, and a semiconductor layer.
- 2 includes an electrode layer 4 in rectifying contact (Schottky contact) and an electrode layer 5 in ohmic contact with the semiconductor layer 3.
- the semiconductor layer 2 is formed of an n-type diamond semiconductor.
- the semiconductor layer 3 is made of a p-type diamond semiconductor.
- the impurity concentration of the semiconductor layer 3 is set higher than the impurity concentration of the semiconductor layer 2. Note that the impurity concentration of the semiconductor layer 3 is desirably set to be one digit or more higher than the impurity concentration of the semiconductor layer 2.
- the energy level (in this embodiment, the donor level) of the conductive impurity of the semiconductor layer 2 is assumed to be deeper than the thermal excitation energy corresponding to the operating temperature of the junction element 1 (so-called deep level).
- the semiconductor layer 2 is an n-type semiconductor and the semiconductor layer 3 is a p-type semiconductor, the semiconductor layer 2 may be a p-type semiconductor and the semiconductor layer 3 may be an n-type semiconductor.
- the materials constituting the electrode layer 4 and the electrode layer 5 may be freely selected as appropriate, but according to the present invention, the electrode layer 4 and the electrode layer 5 can be formed of the same material. That is, in the case of a generally known pn junction type diode, both conductive layers are required to have a low resistance ohmic contact. However, for wide bandgap semiconductors such as diamond, an electrode material that exhibits low contact resistance in contact with one conductive type conductive layer exhibits strong rectification and low resistance when in contact with the other conductive type conductive layer. I can't.
- the junction element according to the present invention has a configuration in which one electrode is an ohmic contact and the other electrode is a Schottky contact.
- the material for forming the electrode layer 4 and the electrode layer 5 may be aluminum (Al), nickel (Ni), molybdenum (Mo), tungsten (W), tantalum (Ta), platinum (Pt), etc. in addition to the above-mentioned Ti. Also, an alloy composed of two or more elements containing these elements, carbides, nitrides, and silicides of these elements may be used. The point to satisfactorily form both electrodes is to optimize the film forming conditions by designing the material so that the contact resistance of the electrode layer 5 is minimized. The electrode thus obtained is automatically optimized with respect to the electrode layer 4, and the electrode layer 4 exhibits extremely excellent rectification.
- FIGS. 2A to 2D are energy band diagrams of the junction element 1 according to the first embodiment of the present invention, where black circles and white circles indicate electrons and holes involved in conduction, respectively.
- FIG. 2A shows an energy band diagram of the junction element 1 placed in a thermal equilibrium state at the time of zero bias.
- a depletion layer having a width WSB by Schottky contact is formed on the left side of the semiconductor layer 2 when in a thermal equilibrium state at zero bias, and the semiconductor layer 2 and the semiconductor layer 3 are formed on the right side of the semiconductor layer 2.
- a depletion layer having a width W PN1 + W PN2 is formed by a pn junction (bipolar junction) formed by bonding.
- W PN1 and W PN2 indicate the widths of the depletion layers extending from the junction point of the pn junction toward the semiconductor layer 2 and the semiconductor layer 3, respectively.
- a neutral region having a width W 1 is formed between both depletion layers of the semiconductor layer 2, and electrons exist in the conduction band and deep donor level of the neutral region.
- the acceptor level of the semiconductor layer 3 is illustrated as a shallow energy level, but when the energy level is deep, holes also exist in the acceptor level.
- Figure 2 (b) shows an energy band diagram of the junction element 1 when a forward voltage V F is applied.
- conduction electrons existing in the conduction band of the semiconductor layer 2 are swept out by the semiconductor layer 3 and recombine with holes to disappear.
- holes in the semiconductor layer 3 diffuse into the semiconductor layer 2. A part of the holes disappears by recombination with the bound conduction electrons in the deep donor level in the initial stage when a voltage is applied in the forward direction, but the majority does not disappear due to recombination with the conduction electrons. passes through, it is gently accelerated in the diffusion potential and composite electric field in the forward voltage V F of the electrode layer 4 to reach the electrode layer 4.
- electrons present in the electrode layer 4 are blocked by a Schottky barrier between the electrode layer 4 and the semiconductor layer 2 and cannot enter the semiconductor layer 2. That is, in a state where a voltage is applied in the forward direction, electrons cannot be injected into the semiconductor layer 2 and the entire region is depleted, and as a result, it acts as a good conductor for holes that are minority carriers. .
- the impurity concentration of the semiconductor layer 3 can be set higher than the impurity concentration of the semiconductor layer 2. Therefore, the resistance of the semiconductor layer 3 can be reduced, and the impurity concentration of the semiconductor layer 3 can be set to 10 19 to 10 20 / cm 3 .
- the junction element 1 according to the first embodiment of the present invention extremely low resistance can be achieved in the forward characteristics. In other words, the junction element 1 according to the first embodiment of the present invention can achieve a higher current density than a generally known pn junction type element (such as a pn junction diode).
- FIG. 2C shows an energy band diagram of the junction element 1 when the voltage is applied in the forward direction to return to the zero bias state again.
- the energy band of the junction element is almost the same as the energy band shown in FIG. 2A, but the difference is that the neutral region of the semiconductor layer 2 disappears and the semiconductor layer 2 is depleted. ing. This is because donor-bound conduction electrons annihilated by the process of applying a voltage in the forward direction are not easily supplied from the rectifying electrode layer 4, and generation of electron-hole pairs is also short in a short time because the gap in the intermediate region is deep. This is because it does not happen.
- the neutral region width W1 of the semiconductor layer 2 can be made zero in a zero-bias thermal equilibrium state.
- the width of the depletion layer formed by the rectifying contact of the electrode layer 4 on the semiconductor layer 2 is W SB
- the pn of the semiconductor layer 2 and the semiconductor layer 3 junction when the width of the depletion layer formed in the semiconductor layer 2 side and W PN1 it is desirable to adjust the thickness of the semiconductor layer 2 so as to satisfy L1 ⁇ W SB + W PN1.
- an energy band diagram as shown in FIG. 2C is obtained even in a thermal equilibrium state, and the initial effect can be eliminated.
- FIG. 2D shows an energy band diagram of the junction element 1 when the reverse voltage V is applied.
- the reverse voltage V being applied across the depleted semiconductor layer 2
- holes in the semiconductor layer 3 are blocked by a large energy barrier formed in the pn junction portion, I can't move.
- electrons are blocked by the Schottky barrier and do not exist in the semiconductor layer 2 and therefore cannot flow in the reverse direction (even if they exist, they are blocked by the energy barrier of the pn junction and move to the semiconductor layer 2 region). Can not).
- the junction element 1 according to the first embodiment of the present invention when a depletion layer is formed in the semiconductor layer 2, when a voltage is applied in the forward direction, Electrons present in the electrode layer 4 cannot move to the semiconductor layer 2. Therefore, the majority of the holes in the semiconductor layer 3 can reach the electrode layer 4 while diffusing into the semiconductor layer 2 without disappearing due to recombination with conduction electrons in the semiconductor layer 2. Therefore, according to the junction element 1 according to the first embodiment of the present invention, it is possible to act as a good conductor for holes without being affected by the resistance value, and a semiconductor formed of Si or SiC semiconductor. A current equivalent to or higher than that of the element can be passed.
- junction element 1 according to the first embodiment of the present invention is a semiconductor element that actually has a pn junction and performs a unipolar operation, it is extremely from a conduction state to a cutoff state, and from a cutoff state to a conduction state. It can move at high speed. Therefore, if the junction element 1 according to the first embodiment of the present invention is replaced with a conventional pn diode, switching loss can be greatly reduced.
- FIG. 3 is a schematic diagram showing the configuration of the junction element according to the second embodiment of the present invention.
- the bonding element 10 includes a substrate 6, a second conductivity type semiconductor layer 7 formed on the entire surface of the substrate 6, and an upper portion of the semiconductor layer 7.
- a second conductive type semiconductor layer 3 and a first conductive type semiconductor layer 2 sequentially stacked in a mesa shape, an electrode layer 4 in rectifying contact with the semiconductor layer 2, and an electrode layer 5 in ohmic contact with the semiconductor layer 7.
- the substrate 6 is formed of a single crystal diamond Ib (001) substrate manufactured by high temperature and high pressure synthesis.
- the semiconductor layer 7 is formed of a p + type diamond semiconductor.
- the semiconductor layer 3 is formed of a p-type diamond semiconductor and has an impurity concentration lower than that of the semiconductor layer 7.
- the semiconductor layer 2 is formed of an n-type diamond semiconductor and has an impurity concentration lower than that of the semiconductor layer 3.
- the substrate 6 may be of a type other than Ib, and may be a substrate of another plane orientation or a polycrystalline substrate.
- the semiconductor layer 7 is provided to make it easy to obtain ohmic contact. By integrating the semiconductor layer 3 with the semiconductor layer 7 and making the semiconductor layer 7 a second semiconductor layer according to the present invention, a higher current density can be obtained.
- An example of the impurity species, impurity concentration, and layer thickness of the semiconductor layer 2, the semiconductor layer 3, and the semiconductor layer 7 is as follows.
- FIG. 4 is a cross-sectional process diagram illustrating a flow of a method for manufacturing the bonding element 10 according to the second embodiment of the present invention.
- the junction element 10 When the junction element 10 is manufactured, first, as shown in FIG. 4A, high-temperature and high-pressure synthesis that is sufficiently washed with a mixed acid of nitric acid and sulfuric acid using a microwave plasma CVD (chemical vapor deposition) method.
- the semiconductor layer 7, the semiconductor layer 3, and the semiconductor layer 2 are sequentially homoepitaxially grown on the surface of the diamond Ib (001) substrate 6.
- methane (CH 4 ) and hydrogen (H 2 ) can be used as the diamond source gas
- diborane (B 2 H 6 ) can be used as the p-type impurity gas
- phosphine (PH 3 ) can be used as the n-type impurity gas.
- a filament CVD method widely known as a diamond thin film synthesis method may be used.
- a metal mask 8 is formed on the surface of the semiconductor layer 2 using photolithography / vacuum deposition / lift-off method, and inductively coupled plasma etching (ICP) is performed using the metal mask 8 as an etching mask.
- ICP inductively coupled plasma etching
- RIE reactive ion etching
- the substrate 6 is sufficiently washed with a mixed acid of nitric acid and sulfuric acid, and then photolithography / vacuum deposition / lift-off method or vacuum deposition / Using the photolithography / etching method, the electrode layer 4 and the electrode layer 5 having desired shapes are formed on the surfaces of the semiconductor layer 2 and the semiconductor layer 7, respectively, as shown in FIG. Finally, if necessary, a heat treatment is performed at 420 ° C. for 30 minutes in a vacuum or an inert gas atmosphere in order to enhance the adhesion between the semiconductor layer 2 and the semiconductor layer 7 and the electrode layer 4 and the electrode layer 5. The series of manufacturing steps is completed.
- the electrode layer 4 and the electrode layer 5 are formed of one material at a time, but may be formed in order so that the electrode layer 4 has ohmic characteristics and the electrode layer 5 has Schottky characteristics.
- FIG. 5 shows the IV characteristics (mesa diameter 70 ⁇ m) of the junction element 10 manufactured by the above-described manufacturing method.
- the vertical axis represents the logarithm of the absolute value of the current.
- FIG. 6 shows the result of measuring the forward characteristics of the same junction element 10 as in FIG. 5 with the measurement area widened, and the vertical axis represents current density and is plotted with a linear axis.
- the ON voltage V F from the approximate line extrapolating the ON voltage V F was 4.3 V.
- the ON resistivity R ON S of the pn diode was calculated from the slope of the straight line, the ON resistivity R ON S was 0.8 m ⁇ cm 2 . This value is very low even compared to the conventionally known on-resistance R ON S.
- the current density of the junction element 10 showed a value of 1000 times or more compared to the normal pn junction diode described in Non-Patent Document 1.
- the applied voltage was 2V lower than the bias voltage of the normal pn junction diode described in Non-Patent Document 1. Therefore, the junction element 10 according to the second embodiment of the present invention is quite different from the problem that the normal pn junction diode described in Non-Patent Document 1 has a high internal resistance and cannot realize a large current density. The solution is in the way.
- FIG. 7 shows the light emission characteristics when a forward voltage is applied to the same junction element 10 as in FIGS.
- a voltage is applied in the forward direction to a general pn junction diode, minority carriers are injected into opposite conductive regions, and light emission due to recombination of electrons and holes is observed.
- a diamond pn diode sharp light emission by excitons at a wavelength of 235 nm and broad light emission from a defect level are observed in a wavelength region of 300 nm to 700 nm.
- no light emission was observed even when a large current (current density 1800 A / cm 2 ) was injected. This indicates that the junction element 10 is actually a semiconductor element that has a pn junction but operates unipolarly.
- FIG. 8 is a schematic diagram showing the configuration of the junction element according to the third embodiment of the present invention.
- the bonding element 20 includes a substrate 6, a second conductivity type semiconductor layer 7 formed on the entire surface of the substrate 6, and an upper portion of the semiconductor layer 7.
- the semiconductor layer 2 of the 1st conductivity type formed in this, the electrode layer 4 which carries out a rectifying contact with the semiconductor layer 2, and the electrode layer 5 which carries out the ohmic contact with the semiconductor layer 7 are provided.
- the substrate 6 is formed of a single crystal diamond Ib (001) substrate manufactured by high temperature and high pressure synthesis.
- the semiconductor layer 7 is formed of a p + type semiconductor.
- the semiconductor layer 2 is formed of an n-type diamond semiconductor and has an impurity concentration lower than that of the semiconductor layer 7.
- the substrate 6 may be of a type other than Ib, and may be a substrate of another plane orientation or a polycrystalline substrate.
- An example of the impurity species, impurity concentration, and layer thickness of the semiconductor layer 2 and the semiconductor layer 7 is as follows.
- the Fermi level of the semiconductor layer 7 when the Fermi level of the semiconductor layer 7 is not degenerated from the valence band, a pn diode can be formed even by hopping conduction or impurity band conduction. Since diamond has a low dielectric constant of 5.7 (about half the dielectric constant of silicon), the acceptor level of boron is as deep as 360 meV. Therefore, the conduction characteristic when the boron concentration is 5 ⁇ 10 20 / cm 3 shows hopping conduction through the boron atom, but the Fermi level is not degenerated from the valence band yet.
- a pn junction can be formed with the semiconductor layer 2 even if the semiconductor layer 7 has a high boron concentration of 5 ⁇ 10 20 / cm 3 .
- suitable materials may be freely selected, but the same material can be used as in the above embodiment.
- An example of the same electrode material is titanium (Ti). Titanium shows a good ohmic contact with the semiconductor layer 7 and shows an ideal rectifying property with respect to the semiconductor layer 2.
- FIG. 9 shows the IV characteristics (mesa diameter 70 ⁇ m) of the junction element 20 manufactured by the above-described manufacturing method.
- the vertical axis represents the logarithm of the absolute value of the current.
- V ⁇ 4V, 12 digits or more
- the leakage current is suppressed to 10 ⁇ 13 A or less when the reverse bias is up to 6 V, and the current has already reached 10 ⁇ 2 A when the forward bias is 3 V, and the current of the junction element of the first embodiment (forward bias 3 V) Current of about 10 ⁇ 3 A, see FIG. 6).
- the on-resistance ratio R ON S of the junction element 20 was 0.1 m ⁇ cm 2 or less, and the current density J at a forward bias of 4 V reached 3200 A / cm 2 .
- all of the rectification ratio, the on-resistivity, and the current density exceed the performance of the junction element according to the first embodiment. .
- FIG. 10 is a schematic diagram showing the configuration of the junction element according to the fourth embodiment of the present invention.
- the junction element 30 includes a substrate 9, semiconductor layers 3 and 2 sequentially stacked in a mesa shape on the surface side of the substrate 9, and a semiconductor layer. 2 is provided with an electrode layer 4 in rectifying contact and an electrode layer 5 in ohmic contact with the back side of the substrate 9.
- the substrate 9 is formed of a boron highly doped (200 ppm) low resistance p + type single crystal diamond IIb (001) substrate manufactured by high temperature and high pressure synthesis.
- the semiconductor layer 3 is formed of a p-type diamond semiconductor and has an impurity concentration lower than that of the substrate 9.
- the semiconductor layer 2 is formed of an n-type diamond semiconductor and has an impurity concentration lower than that of the semiconductor layer 3.
- the substrate 9 may be of another type as long as it has a low resistance, or may be a substrate of another plane orientation or a low resistance polycrystalline substrate.
- a p + type epitaxial layer may be inserted between the substrate 9 and the semiconductor layer 3.
- the semiconductor layer 3 may be integrated with the substrate 9, and the substrate 9 itself may be the second semiconductor layer according to the present invention.
- FIG. 11 is a cross-sectional process diagram illustrating the flow of the method for manufacturing the junction element 30 according to the fourth embodiment of the present invention.
- a boron high-concentration dope low sufficiently washed with a mixed acid of nitric acid and sulfuric acid using a well-known microwave plasma CVD method or a filament CVD method.
- the semiconductor layer 3 and the semiconductor layer 2 are sequentially homoepitaxially grown on the surface of the resistance p + type single crystal diamond IIb (001) substrate 9.
- a metal mask 8 is formed on the surface of the semiconductor layer 2 using photolithography / vacuum deposition / lift-off method, and then inductively coupled plasma etching (ICP) is performed using the metal mask 8 as an etching mask.
- ICP inductively coupled plasma etching
- RIE reactive ion etching
- the metal mask 8 is peeled off with a mixed solution of sulfuric acid and hydrogen peroxide, and the substrate 9 is sufficiently cleaned with a mixed acid of nitric acid and sulfuric acid.
- FIG. 11 (d) after the electrode layer 4 having a desired shape is formed on the surface of the semiconductor layer 2 by using photolithography / vacuum deposition / lift-off method or vacuum deposition / photolithography / etching method, An electrode layer 5 is formed on the entire back surface of the substrate 9 by vacuum deposition.
- a heat treatment is performed in a vacuum or an inert gas atmosphere at 420 ° C. for 30 minutes, A series of manufacturing steps is completed.
- the electrode layer 4 and the electrode layer 5 are sequentially formed. However, the electrode layer 4 and the electrode layer 5 may be formed at the same time using the same material.
- the contact resistance of the electrode layer 5 and the resistance component of the semiconductor layer 7 are increased.
- the electrode layer 5 is disposed on the back side of the substrate 9, the surface of the substrate 6 can be used effectively. Further, since the current entered from the electrode layer 5 penetrates perpendicularly and uniformly into the substrate 9 and the pn junction, the contact resistance of the electrode layer 5 and the resistance component of the substrate 9 can be prevented from increasing.
- FIG. 12 is a schematic diagram showing the configuration of the junction element according to the fifth embodiment of the present invention.
- the junction element 40 includes a first conductivity type substrate 11, a first conductivity type semiconductor layer 12 formed on the entire surface of the substrate 11, and A semiconductor layer 13 of a second conductivity type different from the first conductivity type formed in a mesa shape on the semiconductor layer 12, an electrode layer 4 in rectifying contact with the semiconductor layer 13, and an electrode in ohmic contact with the semiconductor layer 11 Layer 5.
- the substrate 11 is formed of an N (nitrogen) highly doped low resistance n + type single crystal 4H—SiC substrate (resistivity 15 m ⁇ cm) formed by sublimation, and an 8 ° off (0001) Si surface is formed. Has on the surface.
- the semiconductor layer 12 is a nitrogen highly doped (N D > 10 18 cm ⁇ 3 ) n + type conductive layer, and its thickness is 0.5 ⁇ m.
- the substrate 11 may be other polymorphs, and the plane orientation and the off angle are not limited to the above. If the substrate 11 is of high quality, the semiconductor layer 12 may be omitted and the mesa-shaped semiconductor layer 13 may be formed directly on the substrate 11.
- a material for forming a large Schottky barrier with respect to the semiconductor layer 13 can be obtained.
- Such materials include titanium (Ti), nickel (Ni), molybdenum (Mo), tungsten (W), tantalum (Ta), etc., alloys composed of two or more elements containing these elements, carbides of these elements, Nitride and silicide can be exemplified.
- the point to satisfactorily form both electrodes is to optimize the film forming conditions by designing the material so that the contact resistance of the electrode layer 5 is minimized.
- the electrode thus obtained is automatically optimized with respect to the electrode layer 4, and the electrode layer 4 exhibits extremely excellent rectification.
- a material capable of realizing low resistance ohmic contact with the substrate 11 is selected.
- a Ni 2 Si film formed by heat-treating a Ni vapor deposition film is most suitable, but is not limited to this, and a vapor deposition film of cobalt (Co), Ta, Ti, Mo Alternatively, a heat treatment film thereof can be used.
- FIG. 13 is a cross-sectional process diagram illustrating the flow of the method for manufacturing the junction element 40 according to the fifth embodiment of the present invention.
- a well-known atmospheric pressure CVD method is used on the (0001) Si surface of the substrate 11 which has been sufficiently cleaned by a known RCA cleaning method.
- the substrate 11 is thermally oxidized (note that the thermal oxide film is thin and is not shown).
- a SiO 2 mask 14 having a film thickness of 1.5 ⁇ m is formed on the surface of the semiconductor layer 13 using SiO 2 atmospheric pressure CVD / photolithography / dry etching, and then inductively coupled plasma using the SiO 2 mask 14 as an etching mask.
- Etching (ICP) or reactive ion etching (RIE) is performed until the surface of the semiconductor layer 12 (or substrate 11) is exposed, thereby forming a mesa structure of the semiconductor layer 13 as shown in FIG. To do.
- the substrate 11 is lightly etched with a buffered hydrofluoric acid solution to remove the thermal oxide film on the back surface side of the substrate 11 to expose the bulk surface of the substrate 11, and then the entire back surface of the substrate 11 by electron beam evaporation.
- a Ni film is formed to a thickness of about 50 nm.
- the substrate 11 is rapidly heat-treated in a high-purity nitrogen atmosphere at 1000 ° C., thereby forming the electrode layer 5 on the back surface side of the substrate 11 as shown in FIG.
- the substrate 11 is immersed in a buffered hydrofluoric acid solution to completely remove the SiO 2 mask 14 and the thin thermal oxide film formed thereunder, thereby exposing the mesa-shaped substrate surface.
- an electrode layer 4 having a desired shape is formed on the surface of the semiconductor layer 13 using photolithography / vacuum deposition / lift-off method or vacuum deposition / photolithography / etching method. The series of manufacturing steps is completed.
- the present invention is not limited by the description and the drawings that constitute a part of the disclosure of the present invention according to this embodiment.
- the semiconductor layer 2 and the semiconductor layer 3 are made of the same semiconductor material.
- the junction element according to the present invention forms a pn junction using different kinds of semiconductor materials, although there are certain restrictions.
- the same effect can also be exhibited in the heterojunction pn diode. That is, when a semiconductor material having a narrow forbidden band is the semiconductor layer 2 among the two semiconductor materials forming the heterojunction, it is possible to achieve a large current density and a low on-resistance by applying the present invention. is there.
- the present invention is not effective for the reverse configuration. As described above, it is a matter of course that all other embodiments, examples, operation techniques, and the like made by those skilled in the art based on the present embodiment are included in the scope of the present invention.
- a semiconductor device capable of flowing a high-density current can be provided.
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Abstract
Description
M. Kubovic et al., Diamond & Related Materials, Vol. 16 (2007) pp.1033-1037
〔接合素子の構成〕
始めに、図1を参照して、本発明の第1の実施形態となる接合素子の構成について説明する。図1は、本発明の第1の実施形態となる接合素子の構成を示す模式図である。
次に、図2(a)~(d)を参照して、本発明の第1の実施形態となる接合素子1の動作原理について説明する。図2(a)~(d)は本発明の第1の実施形態となる接合素子1のエネルギーバンド図を示し、図中の黒丸及び白丸はそれぞれ伝導に関与する電子及び正孔を示す。
〔接合素子の構成〕
次に、図3を参照して、本発明の第2の実施形態となる接合素子の構成について説明する。図3は、本発明の第2の実施形態となる接合素子の構成を示す模式図である。
(b)半導体層3:B(ホウ素),3.5×1018/cm3,0.7μm
(c)半導体層7:B(ホウ素),4×1020/cm3,1.4μm
〔接合素子の製造方法〕
次に、図4を参照して、本発明の第2の実施形態となる接合素子10の製造方法について説明する。図4は、本発明の第2の実施形態となる接合素子10の製造方法の流れを示す断面工程図である。
図5は、上述の製造方法により製造された接合素子10のIV特性(メサ直径70μm)を示す。なお図中、縦軸は電流の絶対値の対数を示す。図に示す通り、印加電圧V=0~-4[V]の間は、電流値は、測定器の検出限界以下であり、測定することができなかった。このことから、極めて良好な整流特性が得られることが確認された。なお印加電圧V=±4Vでの整流比を計算すると、接合素子10の整流比は約12桁を達成している。この値は非特許文献1で記載された通常のpn接合ダイオードの整流比と比べると2桁以上高い値を示す。
〔接合素子の構成〕
第2の実施形態となる接合素子では、オーミックコンタクトを得やすくするために第2半導体層としての半導体層3の下に半導体層7を設けた。このため第2の実施形態となる接合素子では、主に半導体層3の抵抗成分によって順方向動作時の電流密度が規定された。そこで本実施形態では、半導体層3と半導体層7を一体化して半導体層7を第2半導体層とすることにより、第2半導体層の抵抗を下げ、より大きな電流密度を実現する。以下、図8を参照して、本発明の第3の実施形態となる接合素子の構成について説明する。図8は、本発明の第3の実施形態となる接合素子の構成を示す模式図である。
(b)半導体層7:B(ホウ素),5×1020/cm3,5μm
半導体層7としては、フェルミ準位が価電子帯と縮退していなければ、一般的なp型半導体の伝導特性を示すものだけでなく、ホッピング伝導や不純物バンド伝導を示すものを用いても良い。半導体層7のフェルミ準位が価電子帯と縮退した場合、半導体層7は金属的な伝導特性を示し、pnダイオードを形成することができない。これに対して、半導体層7のフェルミ準位が価電子帯と縮退していない場合には、ホッピング伝導や不純物バンド伝導であってもpnダイオードを形成することができる。ダイヤモンドは、誘電率が5.7と低い(シリコンの誘電率の約半分)ために、ホウ素のアクセプター準位は360meVと深い。従ってホウ素濃度が5×1020/cm3の時の伝導特性はホウ素原子を介したホッピング伝導を示すが、フェルミ準位はまだ価電子帯と縮退していない。このため、ダイヤモンドの場合、ホウ素濃度が5×1020/cm3と高濃度である半導体層7であっても半導体層2とpn接合を形成することができる。電極層4,5としてはそれぞれ適した材料を自由に選んで良いが、前記実施形態と同様に同じ材料を用いることもできる。同一電極材料の一例としては、チタン(Ti)を例示することができる。チタンは、半導体層7に対しては良好なオーミックコンタクトを示し、半導体層2に対しては理想的な整流性を示す。
本発明の第3の実施形態となる接合素子20の製造方法は、半導体層3を形成する工程を除いた以外は上記第2の実施形態となる接合素子10の製造方法と同じであるので、以下ではその説明を省略する。
図9は、上述の製造方法により製造された接合素子20のIV特性(メサ直径70μm)を示す。なお図中、縦軸は電流の絶対値の対数を示す。図に示す通り、極めて良好な整流特性(V=±4Vで12桁以上)が得られていることがわかる。また逆バイアスが6Vまででリーク電流は10-13A以下に抑えつつ、順バイアスの3Vで電流は既に10-2Aに達しており、第1の実施形態の接合素子の電流(順バイアス3Vで約10-3A,図6参照)よりも約1桁大きい電流を実現している。さらに本接合素子20のオン抵抗率RONSは0.1mΩcm2以下であり、順バイアス4Vでの電流密度Jは3200A/cm2に達した。このように本発明の第3の実施形態となる接合素子20によれば、整流比,オン抵抗率,及び電流密度のいずれも第1の実施形態となる接合素子の性能を上回る値を実現した。
〔接合素子の構成〕
次に、図10を参照して、本発明の第4の実施形態となる接合素子の構成について説明する。図10は、本発明の第4の実施形態となる接合素子の構成を示す模式図である。
次に、図11を参照して、本発明の第4の実施形態となる接合素子30の製造方法について説明する。図11は、本発明の第4の実施形態となる接合素子30の製造方法の流れを示す断面工程図である。
上記の製造方法により作製された接合素子30の電気特性を測定したところ、第1の実施形態の接合素子1と変わらぬ良好な整流特性が得られた。またその順方向特性を詳細に解析した所、オン抵抗率RONSは0.5mΩcm2、電流密度Jは4000A/cm2となり、第1の実施形態の接合素子1を凌ぐ性能が得られることが知見された。上述の第2の実施形態となる接合素子10は電極層5を基板6の表面側に配置した構成であるために、基板6表面を有効活用することができない。また電極層5から流入した電流が半導体層7を経由して基板面に平行に伝導する構成であるために、電極層5のコンタクト抵抗と半導体層7の抵抗成分が高くなる。これに対し本実施形態では、電極層5が基板9の裏面側に配置されているので、基板6表面を有効活用することができる。また電極層5から入った電流は基板9及びpn接合に垂直、且つ、一様に侵入するので電極層5のコンタクト抵抗や基板9の抵抗成分が高くなることを防止できる。
〔接合素子の構成〕
次に、図12を参照して、本発明の第5の実施形態となる接合素子の構成について説明する。図12は、本発明の第5の実施形態となる接合素子の構成を示す模式図である。
次に、図13を参照して、本発明の第5の実施形態となる接合素子40の製造方法について説明する。図13は、本発明の第5の実施形態となる接合素子40の製造方法の流れを示す断面工程図である。
上記の製造方法により作製された接合素子40の電気特性を測定した所、ダイヤモンド半導体装置と同様、通常のSiC-pnダイオードに比べて極めて低いオン抵抗と大電流密度が得られた。
Claims (12)
- 第1不純物濃度の不純物を有する、第1導電型の第1半導体層と、
前記第1半導体層に接合し、前記第1不純物濃度より高い第2不純物濃度の不純物を有する、前記第1導電型とは異なる第2導電型の第2半導体層と、
前記第1半導体層に整流性接触する第1電極と、
前記第2半導体層にオーミック接触する第2電極と
を備えることを特徴とする半導体装置。 - 基板と、
前記基板の表面全面に配設された、第2不純物濃度の不純物を有する、第2導電型の第2半導体層と、
前記第2半導体層の表面にメサ状に積層された、前記第2不純物濃度より低い第1不純物濃度の不純物を有する、前記第2導電型とは異なる第1導電型の第1半導体層と、
前記第1半導体層に整流性接触する第1電極と、
前記第2半導体層にオーミック接触する第2電極と
を備えることを特徴とする半導体装置。 - 基板と、
前記基板の表面全面に配設された、第3不純物濃度の不純物を有する、第2導電型の第3半導体層と、
前記第3半導体層の表面にメサ状に順次積層された、前記第3不純物濃度より低い第2不純物濃度の不純物を有する、第2導電型の第2半導体層、及び前記第2不純物濃度より低い第1不純物濃度の不純物を有する、第2導電型とは異なる第1導電型の第1半導体層と、
前記第1半導体層に整流性接触する第1電極と、
前記第3半導体層にオーミック接触する第2電極と
を備えることを特徴とする半導体装置。 - 第3不純物濃度の不純物を有する、第2導電型の基板と、
前記基板の表面側にメサ状に順次積層された、前記第3不純物濃度より低い第2不純物濃度の不純物を有する、第2導電型の第2半導体層、及び前記第2不純物濃度より低い第1不純物濃度の不純物を有する、第2導電型とは異なる第1導電型の第1半導体層と、
前記第1半導体層に整流性接触する第1電極と、
前記基板にオーミック接触する第2電極と、
を備えることを特徴とする半導体装置。 - 請求項1乃至請求項4のうち、いずれか1項に記載の半導体装置において、前記第1不純物濃度は前記第2不純物濃度より少なくとも一桁以上低いことを特徴とする半導体装置。
- 請求項1乃至請求項5のうち、いずれか1項に記載の半導体装置において、前記第1半導体層の伝導不純物のエネルギー準位が半導体装置の動作温度に対応する熱励起エネルギーよりも深い位置にあることを特徴とする半導体装置。
- 請求項1乃至請求項6のうち、いずれか1項に記載の半導体装置において、前記第1半導体層の厚みL1が、熱的平衡状態において、前記第1電極の整流性接触が第1半導体層に形成する空乏層の幅をWSB、第1半導体層と第2半導体層の双極性接合が第1半導体層側に形成する空乏層の幅をWPN1とするとき、L1≦WSB+WPN1を満足することを特徴とする半導体装置。
- 請求項1乃至請求項7のうち、いずれか1項に記載の半導体装置において、ダイヤモンド(C)、炭化珪素(SiC)、酸化亜鉛(ZnO)、チッ化アルミニウム(AlN)、及びチッ化ホウ素(BN)の中から選ばれた1つを主材料として構成されていることを特徴とする半導体装置。
- 請求項1乃至請求項7のうち、いずれか1項に記載の半導体装置において、常温以下の低温で動作することを意図して製造された炭化珪素(SiC)、チッ化ガリウム(GaN)、ガリウム砒素(GaAs)、シリコン(Si)、及びゲルマニウム(Ge)のいずれかを主材料として構成されていることを特徴とする半導体装置。
- 請求項1乃至請求項9のうち、いずれか1項に記載の半導体装置において、前記第1電極と前記第2電極が同一電極材料により形成されていることを特徴とする半導体装置。
- 請求項1乃至請求項10のうち、いずれか1項に記載の半導体装置において、前記第1電極及び/又は前記第2電極がチタン(Ti)、アルミニウム(Al)、ニッケル(Ni)、モリブデン(Mo)、タングステン(W)、タンタル(Ta)、白金(Pt)から選ばれた1つの元素、又はこれら元素のうちの1つを含む2元素以上からなる合金、又は、これら元素の炭化物、窒化物、及び珪化物から選ばれた1つにより構成されていることを特徴とする半導体装置。
- 請求項1乃至請求項11のうち、いずれか1項に記載の半導体装置において、前記第1半導体層の禁制帯幅が前記第2半導体層の禁制帯幅より小さいことを特徴とする半導体装置。
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CN200980110742.7A CN101981702B (zh) | 2008-03-26 | 2009-02-27 | 半导体装置 |
KR1020107023743A KR101250070B1 (ko) | 2008-03-26 | 2009-02-27 | 반도체 장치 |
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JP2010028052A (ja) * | 2008-07-24 | 2010-02-04 | National Institute Of Advanced Industrial & Technology | ダイヤモンド半導体素子 |
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CN102482360A (zh) | 2009-10-22 | 2012-05-30 | 旭化成化学株式会社 | 甲基丙烯酸类树脂、其成形体及甲基丙烯酸类树脂的制造方法 |
JP6203074B2 (ja) | 2014-02-17 | 2017-09-27 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP6257459B2 (ja) * | 2014-06-23 | 2018-01-10 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR101625381B1 (ko) | 2014-08-29 | 2016-06-02 | 삼성중공업 주식회사 | 해상 구조물 계류 장치 |
JP6444718B2 (ja) * | 2014-12-15 | 2018-12-26 | 株式会社東芝 | 半導体装置 |
JP6458525B2 (ja) | 2015-02-10 | 2019-01-30 | 富士電機株式会社 | 炭化珪素半導体装置の製造方法 |
US20160266496A1 (en) * | 2015-03-10 | 2016-09-15 | Uab Research Foundation | Fabrication and encapsulation of micro-circuits on diamond and uses thereof |
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CN105428233A (zh) * | 2015-11-20 | 2016-03-23 | 如皋市大昌电子有限公司 | 一种二极管的生产工艺 |
JP6703683B2 (ja) * | 2017-12-20 | 2020-06-03 | 国立研究開発法人産業技術総合研究所 | 単結晶ダイヤモンドおよびそれを用いた半導体素子 |
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EP2276068A1 (en) | 2011-01-19 |
CN101981702B (zh) | 2015-09-23 |
CN104867969A (zh) | 2015-08-26 |
US9136400B2 (en) | 2015-09-15 |
KR20100139067A (ko) | 2010-12-31 |
CN101981702A (zh) | 2011-02-23 |
EP2276068A4 (en) | 2013-10-16 |
KR101250070B1 (ko) | 2013-04-03 |
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JP2009260278A (ja) | 2009-11-05 |
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