WO2008126914A1 - 電極構造及び半導体装置 - Google Patents

電極構造及び半導体装置 Download PDF

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Publication number
WO2008126914A1
WO2008126914A1 PCT/JP2008/057127 JP2008057127W WO2008126914A1 WO 2008126914 A1 WO2008126914 A1 WO 2008126914A1 JP 2008057127 W JP2008057127 W JP 2008057127W WO 2008126914 A1 WO2008126914 A1 WO 2008126914A1
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WO
WIPO (PCT)
Prior art keywords
electrode
semiconductor device
plating layer
copper plating
layer
Prior art date
Application number
PCT/JP2008/057127
Other languages
English (en)
French (fr)
Inventor
Kikuo Okada
Kojiro Kameyama
Takahiro Oikawa
Original Assignee
Sanyo Electric Co., Ltd.
Sanyo Semiconductor Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd. filed Critical Sanyo Electric Co., Ltd.
Priority to US12/307,228 priority Critical patent/US8154129B2/en
Publication of WO2008126914A1 publication Critical patent/WO2008126914A1/ja

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Definitions

  • the present invention relates to an electrode structure and a semiconductor device, and to suppression of on-resistance.
  • a power MOS transistor is integrated on one semiconductor chip so that operation cells of the MOS transistor are connected in parallel, and a large current flows in the vertical direction of the semiconductor chip.
  • the on-resistance is up to 1 2 ⁇ ⁇ Reduced.
  • Figure 11 shows a conventional semiconductor device, where (a) is a plan view and (b) is its X
  • the semiconductor chip 101 is a vertical MOS transistor having a plurality of operation cells (not shown) on the front surface side, and a current flowing between the front surface and the back surface.
  • the source electrode 110 and the goto pad electrode 112 are formed on the surface of the semiconductor chip 1001.
  • the operation cell includes a gate electrode, a gate oxide film, and a source region.
  • the source electrode 110 covers all the operating cells and is connected to each source region.
  • Each gate electrode is electrically connected to the gate pad electrode 1 1 2.
  • the source electrode 1 1 0 and the gate pad electrode 1 1 2 are electrically connected to the leads 1 1 6 a and 1 1 6 b by wires 1 1 7 a and 1 1 7 b.
  • a collector electrode 1 13 is formed on the back surface of the semiconductor substrate 1.
  • the collector electrode 1 1 3 is fixed to the island 1 1 4 by a conductive paste 1 1 5 such as solder.
  • the source electrode 110 is formed so as to cover all the plurality of operation cells.
  • the wire 1 1 7 a is bonded only to a part of the source electrode 1 1 0, a difference occurs in the distance between the bonding portion 1 1 9 of the wire 1 1 7 a and each operation cell.
  • each operation cell operates non-uniformly based on the resistance of the source electrode 110, and there is a possibility of chip destruction due to current concentration.
  • the source electrode 1 1 0 and the lead 1 1 6 a are connected by a plurality of wires 1 1 7 a.
  • each wire 1 1 7 a is joined to the source electrode 1 10 over a wide range. For this reason, the difference in distance between the joint 1 1 9 of the wire 1 1 7 a and each operation cell is reduced, and the current density is made uniform.
  • the source electrode 1 1 0 and the lead 1 2 0 a are connected by a metal frame 1 2 0 b integrated with the lead 1 2 0 a without using a wire.
  • the metal frame 1 2 0 b is joined to the source electrode 1 10 over a wide range, each operation cell is hardly affected by the resistance in the in-plane direction of the source electrode 1 1 0.
  • the metal frame 1 2 0 b has a much lower resistance than the wire, a low on-resistance semiconductor device is realized.
  • the conductive paste 1 2 2 for fixing the source electrode 1 1 0 and the metal frame 1 2 0 b is It tends to be non-uniform, and this causes a difference in current density. Furthermore, it is difficult to align the source electrode 110 and the metal frame 120b. In addition, the cost increases corresponding to the area of the metal frame 120 b.
  • an electrode structure includes a pad electrode, a protective film formed so as to partially expose and cover the pad electrode, a copper plating layer formed on the pad electrode, A cap layer formed on the copper plating layer, wherein the copper plating layer and the cap layer are continuously formed by an electrolytic plating method, and the copper plating layer has a side surface. It is characterized by being covered with a passivation film.
  • the electrode structure according to the present invention includes a pad electrode, a protective film formed so as to partially expose and cover the pad electrode, and a copper plating layer formed on the pad electrode, A cap layer formed on the copper plating layer, wherein the copper plating layer is formed by an electrolytic plating method, and the cap layer is formed by an electroless plating method. It is characterized in that it is formed so as to cover the upper surface and the side surface.
  • the semiconductor device includes a plurality of operation cells on a surface of a semiconductor substrate, and a first electrode connected to all of the operation cells, and the semiconductor substrate according to the operation of the operation cells.
  • the first electrode is electrically connected to the first external connection terminal via a joint portion, and the first electrode is the operation device.
  • a copper plating layer for suppressing non-uniform operation based on the distance between the cell and the joint is provided.
  • the semiconductor device has an electrode structure having a thick copper plating layer formed by an electrolytic plating method. For this reason, the position and number of electrode joints can be freely designed.
  • FIG. 1 is a cross-sectional view showing the first electrode structure and its manufacturing process
  • FIG. 2 is a cross-sectional view showing the second electrode structure and its manufacturing process
  • FIG. 3 is a cross-sectional view of the first semiconductor chip.
  • FIG. 4 is a plan view and a sectional view of a second semiconductor chip
  • FIG. 5 is a plan view and a sectional view of a third semiconductor chip
  • FIG. 6 is a plan view and a sectional view of the second semiconductor chip.
  • FIG. 7 is a plan view and a sectional view of a first semiconductor device
  • FIG. 8 is a plan view and a sectional view of a second semiconductor device
  • FIG. Figure 9 shows the third semiconductor device FIG.
  • FIG. 10 is a plan view and a sectional view of a fourth semiconductor device
  • FIG. 11 is a plan view and a sectional view of a semiconductor device according to the prior art
  • FIG. FIG. 1 is a plan view and a sectional view of a semiconductor device according to the prior art
  • FIG. 13 is a plan view and a sectional view of a semiconductor device according to the prior art.
  • reference numeral 2 denotes a semiconductor substrate.
  • an element region such as a source region is formed on the main surface, but details thereof are omitted here.
  • 10 a indicates a pad layer, which is formed by depositing A 1 by, for example, sputtering so as to be electrically connected to the element region.
  • FIG. 1 shows a cross-sectional view of the first electrode structure 10 A and its manufacturing method.
  • a nitride film 10b is formed so that the pad layer 10a is exposed. Then, a titanium barrier layer 10 c and a copper seed layer 10 d are continuously formed on the nitride film 10 b by sputtering or vapor deposition so as to be electrically connected to the pad layer 10 a. To form.
  • the resist layer is opened so as to open on the node layer 10a.
  • the strike film 3 3 a is patterned.
  • a copper plating layer 10 e, a nickel plating layer 10 f and a gold plating layer 10 g are successively deposited by an electrolytic plating method.
  • the resist film 33a is removed, and the exposed portions of the titanium barrier layer 10c and the copper seed layer 10d are partially removed.
  • a passivation film 26a such as a solder resist is patterned so as to cover the side surface of the copper plating layer 10e, so that the first electrode structure 1 OA is completed.
  • the copper plating layer 10 e is formed by the electrolytic plating method. Therefore, the copper plating layer 10 e can be formed in a low cost and in a short time even if the thickness exceeds 10 / m.
  • a passivation film 26 6 a is formed on the side surface of the copper plating layer 10 e to prevent this oxidation.
  • FIG. 2 shows a cross-sectional view of the second electrode structure 10 B and its manufacturing method.
  • a nitride film 10b, a titanium barrier layer 10c, and a copper seed layer 100 are formed on the pad layer 10a. form d.
  • the resist film 33b is patterned so as to open on the pad layer 10a.
  • a copper plating layer 10 e is formed by an electrolytic plating method.
  • a nickel plating layer 10 f and a gold plating layer 10 g are formed by an electroless plating method so as to cover the entire copper plating layer 10 e. To do.
  • the nickel plating layer 10 f and the gold plating layer 10 g are formed so as to cover the side surface of the copper plating layer 10 e by the electroless plating method. Is done. Accordingly, it is not necessary to form the passivation film 26 a for preventing oxidation unlike the first electrode structure 10 A.
  • the source electrode 10 is formed by the first or second electrode structure.
  • a vertical MOS transistor will be described as an example of the semiconductor chip 1.
  • the present invention is not limited to this, and can be similarly applied to other devices such as IGBT (insulated gate bipolar transistor) as long as current flows in the vertical direction of the semiconductor chip.
  • IGBT insulated gate bipolar transistor
  • FIG. 3 shows the first semiconductor chip 1A, where (a) is a plan view and (b) is a cross-sectional view taken along the line XX.
  • the semiconductor chip 1A includes an N + type semiconductor substrate 2 and an N ⁇ type epitaxial layer 3 which are drain regions, a P type channel layer 4 formed on the main surface of the epitaxial layer 3, and a channel layer 4
  • An interlayer insulating film 11 that insulates between the gate electrode 7 and the source electrode 10, and a gate pad electrode 12 that is electrically connected to the gate electrode 7 through a connection wiring (not shown) are provided on the surface side.
  • the semiconductor chip 1A includes a drain electrode 13 on the entire back surface.
  • the source electrode 10 is formed by the first or second electrode structure, the resistance in the in-plane direction is small. For this reason, a difference in voltage applied to each source region 8 is unlikely to occur, and therefore there is little bias in the current distribution in the in-plane direction, and current concentration in a specific operating cell is suppressed. .
  • FIG. 4 shows the second semiconductor chip 1 B, (a) is a plan view, and (b) is a cross-sectional view taken along the line ⁇ - ⁇ .
  • the source electrode 10 and the gate pad electrode are formed on the surface side. Not only the pole 12 but also the drain electrode 29 is formed on the same surface.
  • a low-resistance drain current deriving means 30 is provided so as to reach at least the semiconductor substrate 2 from the drain electrode 29.
  • the drain current is led out to the lower part of the drain electrode 29 via the conductive layer 31a, and further led to the drain electrode 29 via the drain current deriving means 30.
  • the drain current deriving means 30 needs to have a resistance lower than that of the epitaxial layer 3, and for example, an N + -type ion implantation layer, a buried electrode made of metal or the like is preferable.
  • the drain current deriving means 30 b may be formed from the back surface of the semiconductor substrate 2 toward the drain electrode 29. Also in this case, the drain current is guided to the drain electrode 29 formed on the surface side.
  • the conductive layer 3 1 b and the drain current deriving means 30 b can be formed in the same process if the opening 3 2 b is formed in advance at the position where the drain current deriving means 30 b is formed. .
  • a plurality of openings 3 2c reaching the epitaxial layer 3 from the back surface of the semiconductor substrate 2 are formed, and the conductive layer 31c is opened. It may be formed so as to be embedded in the mouth 3 2 c. With this configuration, the drain current is led to the drain electrode 29 without passing through the high-resistance semiconductor substrate 2 through the portion formed in the opening 3 2 c of the conductive layer 3 1 c.
  • FIG. 7 shows the first semiconductor device 5 O A, (a) is a plan view, and (b) is a cross-sectional view taken along the line XX.
  • the island 14 is an external connection terminal that is electrically connected to the drain electrode 13 of the semiconductor chip 1A.
  • the island 14 is formed by punching copper. Then, on this island 14, the semiconductor chip 1 A is fixed by a conductive paste 15 such as a field or silver, and the island 14 and the drain electrode 13 are electrically connected.
  • the lead 16 a is an external connection that is electrically connected at the junction 19 applied with the conductive paste 18 such as solder by the source electrode 10 of the semiconductor chip 1 A and the wire 17 a.
  • the lead 16 b is an external connection terminal that is electrically connected to the gate pad electrode 12 of the semiconductor chip 1 by the via 17 b.
  • the source electrode 10 since the source electrode 10 has the first or second electrode structure, the electric resistance in the in-plane direction is small. Therefore, the operation cell formed immediately below the junction 19 and the operation cell formed away from the junction 19 operate so that the currents are approximately the same.
  • the thermal expansion coefficient of the copper plating layer 10 e and the semiconductor chip 1 A are greatly different. Therefore, if the copper plating layer 10 e is too thick, the source electrode 10 and the semiconductor chip 1 A are separated. There is a possibility that. Therefore, preferably, the junction portion 19 is connected to the source electrode 10. When formed at the center, the maximum distance between the junction 19 and the operating cell is reduced, so that the thickness of the copper plating layer 10 e can be minimized and peeling can be prevented.
  • the number of wires 17 a can be reduced, damage to the interlayer insulating film 11 during wire bonding is suppressed, and the gate electrode 7 and the source electrode 10 are short-circuited. Can be prevented.
  • FIG. 8 shows the second semiconductor device 50 B, in which (a) is a plan view and (b) is a sectional view taken along line XX.
  • the lead 20 a is formed integrally with the metal frame 20 b, and the metal frame 20 b is coated with a conductive paste 21 such as solder.
  • the joined portion 22 is electrically connected to the source electrode 10.
  • the source electrode 10 since the source electrode 10 has the first or second electrode structure, the electric resistance in the in-plane direction is small. For this reason, the metal frame 2 O b is formed with a small area so that the conductive paste 21 spreads uniformly between the source electrode 10 and the metal frame 20 b, thereby suppressing variations in on-resistance. .
  • the metal frame 20 b is formed in the central portion apart from the end of the source electrode 10. Therefore, the maximum distance between the junction 22 and the operation cell can be reduced, and further, it is possible to prevent the conductive paste 21 from extending to the gate pad electrode 12 and causing a short circuit.
  • One third semiconductor device 50 C is
  • FIG. 9 shows the third semiconductor device 50 C, where (a) is a plan view and (b) is its x—
  • FIG. 1 A first figure.
  • the source electrode 10, the gate pad electrode 12, and the gate electrode The external terminals of the rain electrode 13 are respectively composed of a source bump electrode 23a, a gate bump electrode 23b, and a drain bump electrode 23c. Then, the semiconductor chip 1 A is mounted face-down on the conductive pattern 2 5 of the mounting board 2 4, the bump electrodes 2 3 and the conductive pattern 2 5 are aligned, and solder reflow due to heat or under pressure Adhesion and connection using supersonic vibration.
  • a source bump electrode 2 3 a and a gate bump electrode 2 3 b that are electrically connected to each other are provided with a protective film 2 made of, for example, a solder resist. It is formed so as to be exposed from the 6 contact holes.
  • the drain electrode 13 is electrically led out to the front surface side of the semiconductor chip 1 A by a lead frame 27 extending from the back surface to the front surface of the semiconductor chip 1 A, and is connected via the drain bump electrode 23 c. Electrically connected to the conductive pattern 25 c.
  • the source electrode 10 since the source electrode 10 has the first or second electrode structure, the electric resistance in the in-plane direction is small. For this reason, the position and the number of the source bump electrodes 23 a can be freely designed so as to correspond to the conductive pattern 25 a of the mounting substrate 24.
  • 1 B indicates the second semiconductor chip 1 B, but details thereof are omitted.
  • 10 is composed of the first or second electrode structure, and details thereof are omitted.
  • First semiconductor device 5 OD-FIG. 10 shows the fourth semiconductor device 50 D, where (a) is a plan view and (b) is its x FIG.
  • the semiconductor chip 1 B has a source bump electrode 2 3 a formed on the source electrode 10, a gate bump electrode 2 3 b formed on the gate pad electrode 12, and a drain bump electrode 2 3 d formed on the drain electrode 29. Then, the conductive patterns 25a, 25b and 25d on the mounting board 24 are mounted face down.
  • the source electrode 10 since the source electrode 10 has the first or second electrode structure, the electric resistance in the in-plane direction is small. Therefore, the number and position of the source bump electrodes 23a can be freely designed according to the conductive pattern 25a.
  • gate electrode and the drain electrode have not been described in detail in the above embodiment, these may be formed to have the same structure in the same process as the source electrode.
  • the present invention is characterized in that the position and number of joints with the external connection terminal can be freely set because the resistance in the in-plane direction of the source electrode 10 is low.
  • the locations and number of joints shown are only examples.
  • the method for forming the drain electrode is not specifically described, it may be formed in the same step as the surface electrode forming step.
  • the copper plating layer 10 e does not have to be pure copper, and most of the constituent materials may be made of copper.
  • the openings 3 2 b to 3 2 completely penetrate the epitaxial layer 3 and the semiconductor substrate 2, and the drain electrodes 29 and When the conductive layers 3 1 b to 3 1 are formed so as to be connected, a lower resistance is realized.

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Abstract

例えばパワーＭＯＳトランジスタでは、主表面に形成された複数のソース領域に共通して接続されるようにソース電極が形成されている。このため、ソース電極の面内方向の抵抗に基づいて、電流密度に隔たりが生じてしまい、ソースとリードとを接続するワイヤの本数を増やす必要があった。本発明では、電極構造は、パッド電極１０ａ上に形成された電解めっき法による銅めっき層１０ｅと、無電解めっき法により形成され、銅めっき層１０ｅの上面及び側面を覆うように形成されたニッケルめっき層１０ｆ，金めっき層と、から構成される。

Description

明 細 書 電極構造及び半導体装置 技術分野
本発明は電極構造及び半導体装置に関し、 オン抵抗の抑制に関する。 背景技術
近年、 携帯端末などの普及により、 スイッチング素子は、 小型で、 且つ低オン 抵抗であることが求められている。 このため、 例えばパワー M O S トランジスタは、 1つの半導体チップには M O S トランジスタの動作セルが並列接続するように集積化 され、 半導体チップの縦方向に大電流が流れる。 例えば、 チャネルがトレンチの側面 に形成される トレンチ構造の縦型 M O S トランジスタでは、 動作セルが、 7 2 0 0万 個 Z平方インチという高密度で形成されると、 オン抵抗が 1 2 πι Ωまで低減される。
第 1 1図は従来技術に係る半導体装置を示し、 （ a ) は平面図、 （b ) はその X
- Xにおける断面図を示す。
半導体チップ 1 0 1は、 表面側に複数の動作セル （図示せず） を備えており、 表面と裏面との間で電流が流れる縦型 M O S トランジスタを示す。 具体的には、 半導 体チップ 1 0 1の表面上には、 ソース電極 1 1 0およびグートパッ ド電極 1 1 2が形 成される。 なお、 動作セルは、 ゲート電極、 ゲート酸化膜、 およびソース領域を備え る。 そして、 ソース電極 1 1 0は、 全ての動作セルを覆い、 各ソース領域と接続され る。 また、 各ゲート電極は、 ゲートパッ ド電極 1 1 2と電気的に接続される。 かかる 構成において、ソース電極 1 1 0およびゲートパッド電極 1 1 2は、ワイヤ 1 1 7 a、 1 1 7 bにより、 リード 1 1 6 a、 1 1 6 bと電気的に接続される。 一方、 半導体基 板 1の裏面には、 コレクタ電極 1 1 3が形成される。 そして、 コレクタ電極 1 1 3は、 半田等の導電ペースト 1 1 5によりアイランド 1 1 4に固着される。
関連した技術文献としては、 例えば日本特許公開公報 2 0 0 1 - 2 5 0 9 4 6 号が挙げられる。 発明の開示
前述したように、 ソース電極 1 1 0は、 複数の動作セルを全て覆うように形成 されている。 ところが、 ワイヤ 1 1 7 aは、 ソース電極 1 1 0の一部にのみ接合され ているため、 ワイヤ 1 1 7 aの接合部 1 1 9と各動作セルとの距離に差が生じる。 こ の結果、 ソース電極 1 1 0の持つ抵抗に基づいて各動作セルが不均一に動作してしま い、 電流集中によるチップ破壊が生じる可能性がある。
このため、 従来においても、 各動作セルの不均一動作を抑制するために、 多く の試みがなされてきた。
例えば、 第 1 2図に示すように、 ソース電極 1 1 0とリード 1 1 6 aとは、 複 数のワイヤ 1 1 7 aにより接続される。 このとき、 各ワイヤ 1 1 7 aは、 ソース電極 1 1 0と広範にわたって接合される。 このため、 ワイヤ 1 1 7 aの接合部 1 1 9と各 動作セルとの距離の差が減少し、 電流密度が均一化される。
半導体装置は、年々微細化が進展しており、ワイヤ 1 1 7 aの本数を増やすと、 微細化の妨げとなってしまう。 また、 ワイヤ 1 1 7 aをソース電極 1 1 0にボンディ ングする際には、 そのストレスでゲート電極とソース電極 1 1 0とを絶縁分離する層 間絶縁膜が短絡してしまわないように注意が必要であるが、 ワイヤ 1 1 7 aの本数を 増やすと、 それだけ不良が発生する可能性が高まってしまう。 また、 ワイヤ 1 1 7 a の本数に応じて、 コストがそれだけ上昇してしまう。
また、 第 1 3図に示すように、 ソース電極 1 1 0とリード 1 2 0 aとは、 ワイ ャが用いられず、 リード 1 2 0 aと一体化した金属フレーム 1 2 0 bにより接続され る。 このとき、 金属フレーム 1 2 0 bは、 ソース電極 1 1 0と広範にわたって接合さ れるため、 各動作セルは、 ソース電極 1 1 0の面内方向の抵抗の影響を殆ど受けなく なる。 さらには、 金属フレーム 1 2 0 bは、 ワイヤよりも大幅に抵抗が低いため、 低 オン抵抗の半導体装置が実現される。
しかしながら、 ソ一ス電極 1 1 0の面積に対応すべく金属フレーム 1 2 0 bの 面積を大きくすると、 ソース電極 1 1 0と金属フレーム 1 2 0 bとを固着する導電性 ペースト 1 2 2が不均一になりやすく、これに伴い、電流密度にも差が生じてしまう。 さらには、 ソース電極 1 1 0と金属フレーム 1 2 0 bとを貼り合わせるときの位置合 わせも難しくなる。 また、 金属フレーム 1 2 0 bの面積に応じて、 コストがそれだけ 上昇してしまう。
上記に鑑み、 本発明に係る電極構造は、 パッド電極と、 前記パッド電極を一部 露出して覆うように形成された保護膜と、 前記パッド電極上に形成された銅めつき層 と、 前記銅めつき層上に形成されたキャップ層と、 を備え、 前記銅めつき層及び前記 キャップ層は、 電解めつき法により連続して形成されており、 前記銅めつき層は、 側 面がパッシベーション膜で覆われていることを特徴とする。
または、 本発明に係る電極構造は、 パッド電極と、 前記パッド電極を一部露出 して覆うように形成された保護膜と、 前記パッド電極上に形成された銅めつき層と、 前記銅めつき層上に形成されたキャップ層と、 を備え、 前記銅めつき層は電解めつき 法により形成されており、 前記キャップ層は、 無電解めつき法により、 前記銅めつき 層の上面及び側面を覆うように形成されていることを特徴とする。
また、 本発明に係る半導体装置は、 半導体基板の表面に複数の動作セルと、 前 記動作セルと全て接続された第 1の電極とを有し、 前記動作セルの動作に応じて前記 半導体基板の縦方向に電流が流れる半導体装置であって、 前記第 1の電極は、 第 1の 外部接続端子と接合部を介して電気的に接続されており、 前記第 1の電極は、 前記動 作セルと前記接合部との距離に基づく不均一動作を抑制するための銅めつき層を備え ることを特徴とする。
本発明では、 半導体装置は、 電解めつき法により形成された厚い銅めつき層を 有した電極構造を有する。 このため、 電極の接合部の位置及び本数を自由に設計でき る。
また、 銅めつき層は、 側面部がパッシベーシヨン膜又はめつき膜で覆われるた め、 銅めつき層の厚さによらず、 側面部の酸化を防止できる。 図面の簡単な説明
第 1図は第 1の電極構造及びその製造工程を示す断面図であり、 第 2図は第 2 の電極構造及びその製造工程を示す断面図であり、 第 3図は第 1の半導体チップの平 面図及び断面図であり、 第 4図は第 2の半導体チップの平面図及び断面図であり、 第 5図は第 3の半導体チップの平面図及び断面図であり、 第 6図は第 4の半導体チップ の平面図及び断面図であり、 第 7図は第 1の半導体装置の平面図及び断面図であり、 第 8図は第 2の半導体装置の平面図及び断面図であり、 第 9図は第 3の半導体装置の 平面図及び断面図であり、 第 1 0図は第 4の半導体装置の平面図及び断面図であり、 第 1 1図は従来技術に係る半導体装置の平面図および断面図であり、 第 1 2図は従来 技術に係る半導体装置の平面図および断面図であり、 第 1 3図は従来技術に係る半導 体装置の平面図および断面図である。 発明を実施するための最良の形態
以下、 本発明の実施形態に係る半導体装置について、 図面を参照して詳細に説 明する。 以下は、 先ず電極構造について説明し、 次にその電極構造を有する半導体チ ップについて説明し、 最後にその半導体チップを有する半導体装置について説明する。
<電極構造〉
はじめに、 半導体装置の電極構造について具体的に説明する。 以下において、 2は半導体基板を示しており、 例えば M O S トランジスタの場合、 その主表面にソー ス領域等の素子領域が形成されるが、 ここではその詳細を省略する。 また、 1 0 aは パッド層を示しており、 素子領域と電気的に接続されるように、 例えばスパッタ法に より A 1が堆積されて形成されたものである。
一第 1の電極構造 1 0 A—
第 1図は、 第 1の電極構造 1 0 A及びその製造方法の断面図を示す。
まず、 第 1図 （a ) に示すように、 パッド層 1 0 aが露出するように、 窒化膜 1 0 bを形成する。 そして、 窒化膜 1 0 b上には、 パッド層 1 0 aと電気的に接続す るように、 チタンバリア層 1 0 c及び銅シード層 1 0 dを、 スパッタ法ゃ蒸着法によ り連続して形成する。
次に、 第 1図 （b ) に示すように、 ノ ッド層 1 0 a上を開口するように、 レジ スト膜 3 3 aをパターニングする。 そして、 銅めつき層 1 0 e , ニッケルめっき層 1 0 f 及び金めつき層 1 0 gを、 電解めつき法により連続して堆積する。
次に、 第 1図 （c ) に示すように、 レジス ト膜 3 3 aを除去し、 チタンバリア 層 1 0 c及び銅シード層 1 0 dの露出する部分を部分的に除去する。
次に、 第 1図 （d ) に示すように、 銅めつき層 1 0 eの側面を覆うように、 ソ ルダーレジスト等のパッシベーション膜 2 6 aをパターユングして、 第 1の電極構造 1 O Aが完成する。
以上、 第 1の電極構造 1 O Aにおいて、 銅めつき層 1 0 eは電解めつき法によ り形成されている。 このため、 銅めつき層 1 0 eは、 1 0 / mを超える厚さであって も、 低コス ト ·短時間で形成できる。
また、 銅めつき層 1 0 eは、 厚く形成されると、 その側面が酸化されやすくな る。 しかし、 第 1の電極構造 1 0 Aでは、 銅めつき層 1 0 eの側面にパッシベーショ ン膜 2 6 aを形成して、 この酸化を防止する。
一第 2の電極構造 1 0 B—
第 2図は、 第 2の電極構造 1 0 B及びその製造方法の断面図を示す。
まず、 第 2図 （a ) に示すように、 第 1の電極構造 1 O Aと同様に、 パッド層 1 0 a上に、窒化膜 1 0 b ,チタンバリア層 1 0 c及び銅シード層 1 0 dを形成する。
次に、 第 2図 （b ) に示すように、 パッド層 1 0 a上を開口するように、 レジ ス ト膜 3 3 bをパターニングする。 そして、 銅めつき層 1 0 eを電解めつき法により 形成する。
次に、 第 2図 （c ) に示すように、 レジス ト膜 3 3 bを除去し、 チタンバリア 層 1 0 c及び銅シード層 1 0 dの露出部分を部分的に除去する。 次に、 第 2図 （d) に示すように、 銅めつき層 1 0 eを全て覆うように、 ニッ ケルめっき層 1 0 f , 金めつき層 1 0 gを無電解めつき法により形成する。
以上、 第 2の電極構造 1 0 Bでは、 二ッケルめっき層 1 0 f 及び金めつき層 1 0 gは無電解めつき法により銅めつき層 1 0 eの側面も含んで覆うように形成される。 これにより、 第 1の電極構造 1 0 Aの如く酸化防止のためのパッシベーシヨン膜 2 6 aを形成する必要がない。
<第 1又は第 2の電極構造を有する半導体チップの構造〉
続いて、 前記第 1又は第 2の電極構造を有した半導体チップの構造について具 体的に説明する。 以下において、 ソース電極 1 0は、 前記第 1又は第 2の電極構造に より形成されている。
なお、 以下においては、 縦型 MO S トランジスタを半導体チップ 1の例として 説明する。 しかし、 本発明はこれに限定されず、 半導体チップの縦方向に電流が流れ るものであれば、 I GBT (絶縁ゲート型バイポーラトランジスタ） 等、 他のデバィ スにも同様に適用される。
一第 1の半導体チップ 1 A—
第 3図は第 1の半導体チップ 1 Aを示し、 （a) は平面図、 （b) はその X - X線 における断面図である。
まず、 半導体チップ 1 Aの構成について説明する。 半導体チップ 1 Aは、 ドレ イン領域となる N+型の半導体基板 2及び N—型のェピタキシャル層 3と、 ェピタキ シャル層 3の主表面に形成された P型のチャネル層 4と、 チャネル層 4に形成された ェピタキシャル層 3まで達するトレンチ 5と、 トレンチ 5にゲート絶縁膜 6を介して 埋め込まれたポリシリコンからなるゲート電極 7と、 トレンチ 5に隣接して設けられ た N +型のソース領域 8と、 隣接するソース領域 8間に形成された P +型のボディ領 域 9と、 各ソース領域 8を被覆するように形成されたソース電極 1 0と、 ゲート電極 7とソース電極 1 0との間を絶縁する層間絶縁膜 1 1と、 ゲート電極 7と不図示の連 結配線により電気的に接続されたゲートパッド電極 1 2と、を表面側に備える。また、 半導体チップ 1 Aは、 裏面の全面にドレイン電極 1 3を備える。
つづいて、 半導体チップ 1 Aの動作について説明する。 ゲートパッド電極 1 2 を介してゲート電極 7に電圧が印加されると、 各ゲート電極 7に隣接してチャネル層 4にチャネルが形成される。 このとき、 ソース電極 1 0と ドレイン電極 1 3との間に 電圧が印加されると、 電流が、 ドレイン電極 1 3から半導体基板 2及びェピタキシャ ル層 3を通り、 チャネル層 4に形成された各チャネルを介して各ソース領域 8を経て、 ソース電極 1 0へと流れる。 つまり、 ソース領域 8、 ゲート電極 7、 およびゲート酸 化膜 6からなる動作セルが 1チップに複数形成されており、 各動作セルが並列接続さ れている。
ここで、 第 1の半導体チップ 1 Aでは、 ソース電極 1 0は、 前記第 1又は第 2 の電極構造により形成されているため、 面内方向における抵抗が小さい。 このため、 各ソース領域 8に印加される電圧に差が生じにく く、 したがって、 面内方向における 電流分布に偏りが少なく、 特定の動作セルに電流集中が起こるといったことが抑制さ れている。
一第 2の半導体チップ 1 B—
第 4図は第 2の半導体チップ 1 Bを示し、 （a ) は平面図、 （b ) はその χ - χ線 における断面図である。
第 2の半導体チップ 1 Βでは、 表面側に ソース電極 1 0及びゲ一トパッド電 極 1 2のみならず、 ドレイン電極 2 9 も同一面に形成される。 そして、 ドレイン電極 2 9から、 少なくとも半導体基板 2まで到達するように、 低抵抗のドレイン電流導出 手段 3 0が設けられている。
かかる構成により、 ドレイン電流は、 導電層 3 1 aを介してドレイン電極 2 9 の下部まで導出され、 さらにドレイン電流導出手段 3 0を介して、 ドレイン電極 2 9 まで導出される。
ちなみに、 ドレイン電流導出手段 3 0は、 ェピタキシャル層 3よりも抵抗が低 くなる必要があり、 例えば N +型のイオン注入層， 金属等の埋め込み電極等がよい。
なお、 ドレイン電流を表面側に形成されたドレイン電極 2 9に導出するには、 以下のように他の様々な方法が適用可能である。
例えば、 第 5図に示す第 3の半導体チップ 1 Cのよ うに、 ドレイン電流導出手 段 3 0 bが、 半導体基板 2の裏面からドレイン電極 2 9に向かって形成されてもよい。 この場合においても、 ドレイン電流は、 表面側に形成されたドレイン電極 2 9まで導 出される。 本形態では、 ドレイン電流導出手段 3 0 bを形成する位置にあらかじめ開 口部 3 2 bを形成しておけば、 導電層 3 1 bと ドレイン電流導出手段 3 0 bとを同一 工程で形成できる。
また、 第 6図に示す第 4の半導体チップ 1 Dのよ うに、 半導体基板 2の裏面か らェピタキシャル層 3に到達する複数の開口部 3 2 cが形成され、 導電層 3 1 cが開 口部 3 2 cに埋め込まれるように形成されてもよい。 かかる構成により、 ドレイン電 流は、 導電層 3 1 cの開口部 3 2 c内に形成された部分を経由することにより、 高抵 抗の半導体基板 2を介さないでドレイン電極 2 9まで導出される。
ぐ第 1の半導体チップ 1 Aを有する半導体装置〉 つづいて、 前記第 1の半導体チップ 1 Aを有する半導体装置について具体的に 説明する。 以下においては、 1 Aは、 前記第 1の半導体チップ 1 Aを示すが、 その詳 細は省略する。 また、 1 0は、 前記第 1又は第 2の電極構造からなるが、 その詳細は 省略する。
一第 1の半導体装置 5 O A—
第 7図は、 第 1の半導体装置 5 O Aを示し、 （a ) は平面図、 （b ) はその X — Xにおける断面図である。
アイランド 1 4は、 半導体チップ 1 Aのドレイン電極 1 3と電気的に接続され る外部接続端子であり、 例えば銅が打ち抜かれて形成される。 そして、 このアイラン ド 1 4上に、 ^田や銀等の導電性ペース ト 1 5により半導体チップ 1 Aが固着され、 アイランド 1 4と ドレイン電極 1 3とが電気的に接続される。
一方、 リード 1 6 aは半導体チップ 1 Aのソース電極 1 0とワイヤ 1 7 aによ り、 半田等の導電性ペースト 1 8が塗布された接合部 1 9において電気的に接続され る外部接続端子であり、 リード 1 6 bは半導体チップ 1のゲートパッ ド電極 1 2とヮ ィャ 1 7 bにより電気的に接続される外部接続端子である。
ここで、 ソース電極 1 0は、 前記第 1又は第 2の電極構造からなるため、 面内 方向における電気抵抗が小さい。 したがって、 接合部 1 9の直下に形成された動作セ ルと、 接合部 1 9から離れて形成された動作セルとでは、 電流が同程度となるように 動作する。
なお、 銅めつき層 1 0 eと半導体チップ 1 Aとでは熱膨張係数が大きく異なる ため、 銅めつき層 1 0 eを厚く しすぎると、 ソース電極 1 0と半導体チップ 1 Aとが 剥離してしまう可能性がある。 そこで、 好ましくは、 接合部 1 9がソース電極 1 0の 中心に形成されると、 接合部 1 9と動作セルとの最大距離が小さくなるため、 銅めつ き層 1 0 eの厚さを最小限に抑え、 剥がれを防止できる。
以上、 第 1の半導体装置 5 O Aでは、 ワイヤ 1 7 aの本数を減らすことができ るため、 ワイヤボンディングにおける層間絶縁膜 1 1の損傷が抑制され、 ゲート電極 7とソース電極 1 0とのショートを防止できる。
一第 2の半導体装置 5 0 B - 第 8図は、 第 2の半導体装置 5 0 Bを示し、 （a ) は平面図、 （b ) はその x— Xにおける断面図である。
第 2の半導体装置 5 0 Bでは、 リード 2 0 aは、 金属フレーム 2 0 bと一体と なって形成されており、 この金属フレーム 2 0 bが、 半田等の導電性ペース ト 2 1が 塗布された接合部 2 2において、 ソース電極 1 0と電気的に接続されている。
ここで、 ソース電極 1 0は、 前記第 1又は第 2の電極構造からなるため、 面内 方向における電気抵抗が小さい。 このため、 金属フレーム 2 O bは、 導電性ペース ト 2 1がソース電極 1 0と金属フレーム 2 0 b との間に均一に広がる程度に小さい面積 で形成され、 オン抵抗のばらつきを抑制される。 そして、 好ましくは、 金属フレーム 2 0 bは、 ソース電極 1 0の端から離間して中心部分に形成される。 したがって、 接 合部 2 2と動作セルとの最大距離を小さくすることができ、 さらには、 導電性ペース ト 2 1がゲートパッド電極 1 2にまで延びてショートが発生することを防止できる。
一第 3の半導体装置 5 0 C一
第 9図は、 第 3の半導体装置 5 0 Cを示し、 （a ) は平面図、 （b ) はその x—
Xにおける断面図である。
第 3の半導体装置 5 0 Cでは、 ソース電極 1 0 , ゲートパッド電極 1 2及びド レイン電極 1 3の外部端子は、 それぞれソースバンプ電極 2 3 a , ゲートバンプ電極 2 3 b及びドレインバンプ電極 2 3 cから構成される。 そして、 実装基板 2 4の導電 パターン 2 5上に半導体チップ 1 Aをフェイスダウンで実装し、 各バンプ電極 2 3と 導電パターン 2 5の位置あわせを行い、 熱による半田リフローや、 加圧状態での超音 波振動を用いて接着，接続する。
具体的には、 ソース電極 1 0及びゲートパッド電極 1 2上には、 それぞれ電気 的に接続されたソースバンプ電極 2 3 a , ゲートバンプ電極 2 3 bが、 例えばソルダ 一レジストからなる保護膜 2 6のコンタク ト孔から露出するように形成される。 また、 ドレイン電極 1 3は、 半導体チップ 1 Aの裏面から表面まで延在した導出フレーム 2 7により、 半導体チップ 1 Aの表面側にまで電気的に導出され、 ドレインバンプ電極 2 3 cを介して、 導電パターン 2 5 cと電気的に接続される。
ここで、 ソース電極 1 0は、 前記第 1又は第 2の電極構造からなるため、 面内 方向における電気抵抗が小さい。 このため、 ソースバンプ電極 2 3 aは、 実装基板 2 4の導電パターン 2 5 aに対応するように、 位置および数を自由に設計することがで きる。
<第 2の半導体チップ 1 Bを有する半導体装置〉
つづいて、 前記第 2の半導体チップ 1 Bを有する半導体装置について具体的に 説明する。 以下においては、 1 Bは、 前記第 2の半導体チップ 1 Bを示すが、 その詳 細は省略する。 また、 1 0は、 前記第 1又は第 2の電極構造からなるが、 その詳細は 省略する。
一第 4の半導体装置 5 O D - 第 1 0図は、 第 4の半導体装置 5 0 Dを示し、 （a ) は平面図、 （b ) はその x 一 xにおける断面図である。
半導体チップ 1 Bは、 ソース電極 1 0上にソースバンプ電極 2 3 a , ゲートパ ッド電極 1 2上にゲートバンプ電極 2 3 b , ドレイン電極 2 9上にドレインバンプ電 極 2 3 dがそれぞれ形成され、 実装基板 2 4上の導電パターン 2 5 a , 2 5 b及び 2 5 dにそれぞれフェイスダウンされて実装される。
ここで、 ソース電極 1 0は、 前記第 1又は第 2の電極構造からなるため、 面内 方向における電気抵抗が小さい。このため、ソースバンプ電極 2 3 aの数及び位置は、 導電パターン 2 5 aに応じて自由に設計されうる。
なお、 今回開示された実施形態は、 すべての点で例示であって制限的なもので はないと考えられるべきである。 本発明の範囲は、 上記した実施形態の説明ではなく 特許請求の範囲によって示され、 さらに特許請求の範囲と均等の意味および範囲内で のすベての変更が含まれる。
例えば、 上記実施形態では、 ゲート電極、 ドレイン電極については詳述しなか つたが、 これらについても、 ソース電極と同じ工程で同構造となるように形成されて もよい。
また、 本発明は、 ソース電極 1 0の面内方向の抵抗が低いために、 外部接続端 子との接合部の位置および本数が自由に設定されるところにその特徴があり、 実施形 態で示された接合部の位置および本数は一例にすぎない。
また、 ドレイン電極の形成方法については具体的に説明していないが、 表面電 極の形成工程と同工程で形成してもよい。
また、 銅めつき層 1 0 eは、 純銅である必要はなく、 構成物質の大部分が銅か らなればよい。 また、 第 2〜第 4の半導体チップ 1 B, 1 C, 1 Dでは、 開口部 3 2 b〜 3 2 は、 ェピタキシャル層 3及び半導体基板 2を完全に貫通して、 ドレイン電極 2 9と導 電層 3 1 b〜 3 1 とを接続されるように形成されると、 より低抵抗化が実現される。

Claims

請 求 の 範 囲
ノ、。ッド電極と、
前記パッド電極を一部露出して覆うように形成された保護膜と、
前記パッド電極上に形成された銅めつき層と、
前記銅めつき層上に形成されたキャップ層と、 を備え、
前記銅めつき層及び前記キャップ層は、電解めつき法により連続して形成され ており、
前記銅めつき層は、側面がパッシベーション膜で覆われていることを特徴とす る電極構造。
パッド電極と、
前記パッド電極を一部露出して覆うように形成された保護膜と、
前記パッド電極上に形成された銅めつき層と、
前記銅めつき層上に形成されたキャップ層と、 を備え、
前記銅めつき層は電解めつき法により形成されており、
前記キャップ層は、無電解めつき法により、前記銅めつき層の上面及び側面を 覆うように形成されていることを特徴とする電極構造。
半導体基板の表面に複数の動作セルと、前記動作セルと全て接続された第 1の 電極とを有し、
前記動作セルの動作に応じて前記半導体基板の縦方向に電流が流れる半導体 装置であって、
前記第 1の電極は、第 1の外部接続端子と接合部を介して電気的に接続されて おり、 前記第 1の電極は、電解めつき法により形成された銅めつき層を備えることを 特徴とする半導体装置。
前記第 1の電極は、前記銅めつき層の酸化を防止するためのキャップ層を有し、 前記キヤップ層は、前記銅めつき層と連続して電解めつき法により形成されて いることを特徴とする請求の範囲第 3項に記載の半導体装置。
前記銅めつき層は、側面がパッシベーション膜により覆われていることを特徴 とする請求の範囲第 4項に記載の半導体装置。
前記第 1の電極は、前記銅めつき層の酸化を防止するためのキャップ'層を有し、 前記キヤップ層は、無電解めつき法により、前記銅めつき層の上面及び側面を 覆うように形成されていることを特徴とする請求の範囲第 3項に記載の半導体 装置。
前記第 1の電極は、前記第 1の外部接続端子と接続されたワイヤと、前記接合 部において導電性ペーストにより接合されていることを特徴とする請求の範囲 第 3項乃至請求の範囲第 6項のいずれかに記載の半導体装置。
前記第 1の電極は、前記第 1の外部接続端子と接続された金属フレームと、前 記接合部において導電性ペーストにより接合されており、
前記金属フレームは、前記第 1の電極よりも表面積が小さいことを特徴とする 請求の範囲第 3項乃至請求の範囲第 6項のいずれかに記載の半導体装置。
前記第 1の外部端子は、 第 1のバンプ電極により構成されており、
前記半導体基板は、実装基板の導電パターンにフェイスダウンして実装される ために形成されており、
前記第 1のバンプ電極は、前記導電パターンに対応して形成されていることを 特徴とする請求の範囲第 3項乃至請求の範囲第 6項のいずれかに記載の半導体 装置。
前記半導体基板は、 裏面に第 2の電極を有し、
前記第 2の電極は、 裏面側から前記表面側まで延在した導出フレームにより、 前記半導体基板の表面側に電気的に導出されていることを特徴とする請求の範 囲第 9項に記載の半導体装置。
前記半導体基板は、 前記動作セルが形成されていない領域に、 前記半導体基 板の縦方向に伸びた低抵抗領域を有し、
前記低抵抗領域を介して、前記半導体基板の裏面から電流が導出されることを 特徴とする請求の範囲第 9項に記載の半導体装置。
PCT/JP2008/057127 2007-04-06 2008-04-04 電極構造及び半導体装置 WO2008126914A1 (ja)

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Publication number Priority date Publication date Assignee Title
EP2494590A2 (en) * 2009-10-30 2012-09-05 Vishay-Siliconix Semiconductor device

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4794615B2 (ja) * 2008-11-27 2011-10-19 パナソニック株式会社 半導体装置
JP5581005B2 (ja) 2008-12-26 2014-08-27 株式会社東芝 半導体装置の製造方法
JP2011151056A (ja) * 2010-01-19 2011-08-04 Yaskawa Electric Corp 半導体装置及び半導体装置の製造方法
JP2010272893A (ja) * 2010-08-25 2010-12-02 Panasonic Corp 半導体装置及びその製造方法
JP2012160595A (ja) * 2011-02-01 2012-08-23 Toshiba Corp 半導体装置及びその製造方法
JP5663607B2 (ja) * 2011-02-10 2015-02-04 パナソニックＩｐマネジメント株式会社 半導体装置
JP5865630B2 (ja) * 2011-08-23 2016-02-17 京セラ株式会社 電極構造、半導体素子、半導体装置、サーマルヘッドおよびサーマルプリンタ
KR101282202B1 (ko) 2011-11-10 2013-07-04 엘비세미콘 주식회사 반도체 소자용 범프 구조물 및 그의 제조 방법
US9159652B2 (en) 2013-02-25 2015-10-13 Stmicroelectronics S.R.L. Electronic device comprising at least a chip enclosed in a package and a corresponding assembly process
JP2014187204A (ja) * 2013-03-22 2014-10-02 Toshiba Corp 半導体装置の製造方法および半導体装置
KR102114501B1 (ko) * 2014-03-11 2020-05-25 매그나칩 반도체 유한회사 반도체 소자
JP2015204393A (ja) * 2014-04-15 2015-11-16 サンケン電気株式会社 半導体装置
CN105934813B (zh) 2014-04-16 2019-03-22 三菱电机株式会社 半导体装置
TWI690083B (zh) * 2015-04-15 2020-04-01 杰力科技股份有限公司 功率金氧半導體場效電晶體及其製作方法
KR102382635B1 (ko) * 2016-06-09 2022-04-05 매그나칩 반도체 유한회사 전력 반도체의 웨이퍼 레벨 칩 스케일 패키지 및 제조 방법
JP6904416B2 (ja) * 2017-06-09 2021-07-14 富士電機株式会社 半導体装置および半導体装置の製造方法
KR102420586B1 (ko) 2017-07-24 2022-07-13 삼성전자주식회사 반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법
CN115868013A (zh) * 2020-07-27 2023-03-28 罗姆股份有限公司 半导体装置
CN116438662B (zh) * 2021-10-15 2023-09-29 新唐科技日本株式会社 半导体装置
WO2023062906A1 (ja) * 2021-10-15 2023-04-20 ヌヴォトンテクノロジージャパン株式会社 半導体装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003142651A (ja) * 2001-10-31 2003-05-16 Mitsubishi Electric Corp 電力用半導体装置
JP2004071886A (ja) * 2002-08-07 2004-03-04 Renesas Technology Corp 縦型パワー半導体装置およびその製造方法
JP2005101293A (ja) * 2003-09-25 2005-04-14 Renesas Technology Corp 半導体装置
JP2005166757A (ja) * 2003-11-28 2005-06-23 Advanced Lcd Technologies Development Center Co Ltd 配線構造体、配線構造体の形成方法、薄膜トランジスタ、薄膜トランジスタの形成方法、及び表示装置
JP2006121041A (ja) * 2004-09-24 2006-05-11 Toshiba Corp 半導体装置および半導体装置の製造方法
JP2006324320A (ja) * 2005-05-17 2006-11-30 Renesas Technology Corp 半導体装置
JP2007073611A (ja) * 2005-09-05 2007-03-22 Renesas Technology Corp 電子装置およびその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3461357A (en) * 1967-09-15 1969-08-12 Ibm Multilevel terminal metallurgy for semiconductor devices
US5011580A (en) * 1989-10-24 1991-04-30 Microelectronics And Computer Technology Corporation Method of reworking an electrical multilayer interconnect
JP2001250946A (ja) * 2000-03-03 2001-09-14 Sanyo Electric Co Ltd 絶縁ゲート型半導体装置
JP3765565B2 (ja) * 2001-05-01 2006-04-12 アルプス電気株式会社 電子回路基板
JP2003023239A (ja) * 2001-07-05 2003-01-24 Sumitomo Electric Ind Ltd 回路基板とその製造方法及び高出力モジュール
US6770971B2 (en) * 2002-06-14 2004-08-03 Casio Computer Co., Ltd. Semiconductor device and method of fabricating the same
JP2004055812A (ja) * 2002-07-19 2004-02-19 Renesas Technology Corp 半導体装置
US20040183202A1 (en) * 2003-01-31 2004-09-23 Nec Electronics Corporation Semiconductor device having copper damascene interconnection and fabricating method thereof
JP4696532B2 (ja) * 2004-05-20 2011-06-08 株式会社デンソー パワー複合集積型半導体装置およびその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003142651A (ja) * 2001-10-31 2003-05-16 Mitsubishi Electric Corp 電力用半導体装置
JP2004071886A (ja) * 2002-08-07 2004-03-04 Renesas Technology Corp 縦型パワー半導体装置およびその製造方法
JP2005101293A (ja) * 2003-09-25 2005-04-14 Renesas Technology Corp 半導体装置
JP2005166757A (ja) * 2003-11-28 2005-06-23 Advanced Lcd Technologies Development Center Co Ltd 配線構造体、配線構造体の形成方法、薄膜トランジスタ、薄膜トランジスタの形成方法、及び表示装置
JP2006121041A (ja) * 2004-09-24 2006-05-11 Toshiba Corp 半導体装置および半導体装置の製造方法
JP2006324320A (ja) * 2005-05-17 2006-11-30 Renesas Technology Corp 半導体装置
JP2007073611A (ja) * 2005-09-05 2007-03-22 Renesas Technology Corp 電子装置およびその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2494590A2 (en) * 2009-10-30 2012-09-05 Vishay-Siliconix Semiconductor device
EP2494590A4 (en) * 2009-10-30 2013-04-24 Vishay Siliconix SEMICONDUCTOR DEVICE
EP2802013A1 (en) * 2009-10-30 2014-11-12 Vishay-Siliconix Semiconductor device
US9306056B2 (en) 2009-10-30 2016-04-05 Vishay-Siliconix Semiconductor device with trench-like feed-throughs
US10032901B2 (en) 2009-10-30 2018-07-24 Vishay-Siliconix Semiconductor device with trench-like feed-throughs

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