TWI819195B - 場效電晶體及半導體裝置 - Google Patents

場效電晶體及半導體裝置 Download PDF

Info

Publication number
TWI819195B
TWI819195B TW109106275A TW109106275A TWI819195B TW I819195 B TWI819195 B TW I819195B TW 109106275 A TW109106275 A TW 109106275A TW 109106275 A TW109106275 A TW 109106275A TW I819195 B TWI819195 B TW I819195B
Authority
TW
Taiwan
Prior art keywords
gate
drain
pad
electrode
field effect
Prior art date
Application number
TW109106275A
Other languages
English (en)
Other versions
TW202038320A (zh
Inventor
秋山千帆子
Original Assignee
日商住友電工器件創新股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商住友電工器件創新股份有限公司 filed Critical 日商住友電工器件創新股份有限公司
Publication of TW202038320A publication Critical patent/TW202038320A/zh
Application granted granted Critical
Publication of TWI819195B publication Critical patent/TWI819195B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0277—Electrolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05559—Shape in side view non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29344—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H01L29/475—Schottky barrier electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10344—Aluminium gallium nitride [AlGaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

本發明揭示一種場效電晶體，其包括：一半導體區域，該半導體區域包括在一第一方向上並排地配置之一第一非主動區域、一主動區域及一第二非主動區域；在該主動區域上之一閘極電極、一源極電極及一汲極電極；在該第一非主動區域上之一閘極焊墊；在該半導體區域上並與該半導體區域接觸之一閘極防護部，該閘極防護部與該閘極焊墊隔開並位於該半導體區域之第一非主動區域側上之一邊緣與該閘極焊墊之間；在該第二非主動區域上之一汲極焊墊；在該半導體區域上並與該半導體區域接觸之一汲極防護部，該汲極防護部與該汲極焊墊隔開並位於該半導體區域之第二非主動區域側上之一邊緣與該汲極焊墊之間；以及電連接至該閘極防護部之一金屬膜。

Description

場效電晶體及半導體裝置
本發明係關於一種場效電晶體及一種半導體裝置。
日本未審查專利公開第2010-177550號描述一種與半導體裝置相關之技術。此文獻中所揭示之半導體裝置包括：半導體晶片；兩個電極焊墊，兩個電極焊墊配置於半導體晶片上；及導電防護環，導電防護環配置於兩個電極焊墊與半導體晶片上之周邊之間。藉由消除防護環之一部分，將防護環劃分為彼此絕緣之複數個單元區域。
根據一項實施例，提供一種場效電晶體及一種半導體裝置，其包括：一基板，該基板包括一主表面及一背表面；一半導體區域，該半導體區域在該主表面上，該半導體區域包括在一第一方向上並排地配置之一第一非主動區域、一主動區域及一第二非主動區域；一閘極電極、一源極電極及一汲極電極，該閘極電極、該源極電極及該汲極電極在該主動區域上；一閘極焊墊，該閘極焊墊在該第一非主動區域上並電連接至該閘極電極；一閘極防護部，該閘極防護部在該半導體區域上並與該半導體區域接觸，該閘極防護部與該閘極焊墊隔開並位於該閘極焊墊與該半導體區域之一對邊緣之第一非主動區域側上之一邊緣之間，該對邊緣在該第一方向上並排地配置；一汲極焊墊，該汲極焊墊在該第二非主動區域上並電連接至該汲極電極；一汲極防護部，該汲極防護部在該半導體區域上並與該半導體區域接觸，該汲極防護部與該汲極焊墊隔開並位於該汲極焊墊與該半導體區域之該對邊緣之第二非主動區域側上之一邊緣之間；及一金屬膜，該金屬膜在該背表面上並電連接至該閘極防護部。該汲極防護部相對於該金屬膜、該閘極電極、該源極電極及該汲極電極處於一非導電狀態。
[本發明要解決之問題]
場效電晶體包括形成基板之主表面的半導體區域，以及設置於半導體區域中之主動區域上的閘極電極、源極電極及汲極電極。導線自此等電極延伸，且導線之尖端連接至用於導線結合之焊墊。舉例而言，連接至閘極電極之閘極焊墊設置於相對於主動區域位於一側上之非主動區域上。連接至汲極電極之汲極焊墊設置於相對於主動區域位於另一側上之非主動區域上。金屬膜設置於基板之背表面上，且背金屬膜經由導電結合材料而導電地結合至金屬基底構件。在許多情況下，將基底構件界定為參考電位(接地電位)。
在具有以上組態之場效電晶體中出現以下問題。在一項使用實例中，將低於參考電位之負電壓施加至閘極電極。因此，在閘極焊墊與基底構件之間產生閘極焊墊側為負的電場。在潮濕環境中，歸因於此電場，很可能在基底構件與背金屬膜之間發生導電結合材料中所含有之金屬(例如Ag、Au、Cu)之離子遷移。離子遷移係離子化金屬在電場中於物質表面上移動的現象。金屬離子藉由被電場吸引而移動，由於某種原因而自離子化狀態返回至金屬，並積累以形成枝晶。若金屬之枝晶自導電結合材料生長且閘極焊墊及背金屬膜短路，則半導體裝置之操作可能有缺陷。因此，本發明之目標係減少歸因於導電結合材料中所含有之金屬之離子遷移而引起的背金屬膜與閘極焊墊之間的短路，並提供一種場效電晶體及一種半導體裝置，其可改良場效電晶體之抗濕性。 [本發明之實施例之效果]
根據本發明，有可能減少歸因於導電結合材料中所含有之金屬之離子遷移而引起的背金屬膜與閘極焊墊之間的短路，並提供場效電晶體及半導體裝置，其可改良場效電晶體之抗濕性。
[本發明之實施例之描述] 首先，將列出並描述本發明之實施例之詳情。本發明之一項實施例係一種場效電晶體，其包括：半導體區域，半導體區域設置於基板之主表面上，並包括在第一方向上並排地配置之第一非主動區域、主動區域及第二非主動區域；閘極電極、源極電極及汲極電極，閘極電極、源極電極及汲極電極設置於主動區域上；閘極焊墊，閘極焊墊設置於第一非主動區域上並電連接至閘極電極；閘極防護部，閘極防護部由金屬製成，設置於半導體區域上並與半導體區域接觸，以便與在閘極焊墊與半導體區域之一對邊緣之第一非主動區域側上之邊緣之間的閘極焊墊隔開，該對邊緣在第一方向上並排地配置；汲極焊墊，汲極焊墊設置於第二非主動區域上並電連接至汲極電極；及汲極防護部，汲極防護部由金屬製成，設置於半導體區域上並與半導體區域接觸，以便與在閘極焊墊與半導體區域之該對邊緣之第二非主動區域側上之邊緣之間的汲極焊墊隔開。閘極防護部電連接至設置於基板之背表面上之金屬膜，且汲極防護部相對於金屬膜、閘極電極、源極電極及汲極電極處於非導電狀態。
源極電極可經由穿透基板及半導體區域之導線電連接至金屬膜，且閘極防護部可電連接至源極電極。
場效電晶體進一步包括源極焊墊，該源極焊墊與閘極焊墊並排地配置於第一非主動區域上，並電連接至源極電極，且閘極防護部可自源極焊墊沿著第一非主動區域側上之邊緣延伸。
場效電晶體可進一步包括絕緣膜，該絕緣膜在汲極焊墊及閘極焊墊上具有開口，且閘極防護部及汲極防護部可被絕緣膜覆蓋。
本發明之另一實施例係一種半導體裝置，其包括：場效電晶體；基底構件，基底構件具有金屬表面並安裝場效電晶體；及導電結合材料，導電結合材料插入於場效電晶體之金屬膜與基底構件之表面之間，並含有Ag、Au及Cu中之至少一者。
容納場效電晶體之封裝可具有非氣密結構。
下文將參考圖式描述根據本發明之場效電晶體及半導體裝置之特定實例。本發明並不限於此等實例，而是由所附申請專利範圍指示，並意欲包括在與所附申請專利範圍等效之範疇及含義內的任何修改。在以下描述中，將在圖式之描述中由相同的參考符號表示相同的元件，且省略冗餘的描述。
(第一實施例) 圖1係示出根據第一實施例之場效電晶體(在下文中簡稱為電晶體) 1A之組態的平面圖。圖2係沿著圖1中之線II-II截取的截面圖。圖3係沿著圖1中之線III-III截取的截面圖。圖4係沿著圖1中之線IV-IV截取的截面圖。如圖1至圖4中所示，電晶體1A包括基板3、絕緣膜5至9、閘極電極21、源極電極22、汲極電極23、閘極焊墊31、源極焊墊32、汲極焊墊33及場板35 (參見圖4)、金屬通路44 (參見圖2)，及背金屬膜45。
基板3包括平坦主表面3a及位於主表面3a之相對側上之平坦背表面3b。基板3包括生長基板30及設置於生長基板30之主表面30a上之氮化物半導體層4。生長基板30係例如SiC基板並包括背表面30b。生長基板30之背表面30b與基板3之背表面3b重合。生長基板30用於氮化物半導體層4之磊晶生長。
氮化物半導體層4係本實施例中之半導體區域之實例，並係形成於生長基板30之主表面30a上之磊晶層。氮化物半導體層4形成基板3之主表面3a。當電晶體1A係高電子遷移率電晶體(HEMT)時，氮化物半導體層4包括例如與主表面30a接觸之AlN緩衝層、設置於AlN緩衝層上之GaN通道層、設置於GaN通道層上之AlGaN (或InAlN)障壁層，及設置於障壁層上之GaN頂蓋層。AlN緩衝層係無摻雜的，並具有在例如10 nm至20 nm之範圍內之厚度。GaN通道層係無摻雜的，並具有在例如0.4 μm至1.2 μm之範圍內之厚度。障壁層具有在例如10 nm至30 nm之範圍內之厚度。然而，在InAlN障壁層之情況下，其厚度被設定為小於20 nm。GaN頂蓋層係n型的，並具有例如5 nm之厚度。
如圖1中所示，氮化物半導體層4包括主動區域4a及設置於主動區域4a周圍之非主動區域4b。主動區域4a係作為電晶體操作之區域。非主動區域4b係藉由將諸如氬(Ar)之離子(質子)植入至氮化物半導體層4中而被電去啟動之區域。非主動區域4b被設置用於在彼此鄰近之電晶體1A之間的電隔離並用於限制電晶體1A之操作區域。非主動區域4b包括：第一非主動區域4ba，其相對於主動區域4a位於沿著主表面3a在方向D1 (第一方向)上之一側上；及第二非主動區域4bb，其相對於主動區域4a位於在方向D1上之另一側上。亦即，第一非主動區域4ba、主動區域4a及第二非主動區域4bb在方向D1上以此順序並排地配置。
絕緣膜5至9構成位於氮化物半導體層4上之絕緣層合結構。絕緣膜5至9設置於主動區域4a及非主動區域4b之實質上整個表面上方。絕緣膜5至9主要包括例如矽化合物，諸如SiN、SiO2 及SiON。在本實施例中，絕緣膜5至9彼此接觸，但另一層可設置於層之間的至少一部分中。
複數個源極電極22設置於氮化物半導體層4之主動區域4a上，並通過形成於絕緣膜5中之開口51 (參見圖4)與氮化物半導體層4之主動區域4a形成歐姆接觸。如圖1中所示，複數個源極電極22沿著與方向D1相交(例如正交)之方向D2 (第二方向)並排地配置，且每一源極電極22之平面形狀為縱向方向係方向D1的矩形形狀。源極電極22係藉由使包括例如Ti層、Al層及Ti層(或Ta層、Al層及Ta層)之層合結構合金化而形成，並主要含有Al。
複數個汲極電極23設置於氮化物半導體層4之主動區域4a上，並通過形成於絕緣膜5中之開口與氮化物半導體層4之主動區域4a形成歐姆接觸。如圖1中所示，汲極電極23與源極電極22沿著方向D2交替地配置，且每一汲極電極23之平面形狀為縱向方向係方向D1的矩形形狀。汲極電極23亦係藉由使包括例如Ti層、Al層及Ti層(或Ta層、Al層及Ta層)之層合結構合金化而形成，並主要含有Al。
閘極電極21包括設置於氮化物半導體層4之主動區域4a上之複數個部分(指狀部分)，及在第一非主動區域4ba上延伸之部分。每一閘極電極21之指狀部分沿著方向D1延伸，並位於源極電極22與汲極電極23之間。此等閘極電極21之指狀部分與氮化物半導體層4之主動區域4a進行肖特基接觸。閘極電極21與氮化物半導體層4之間在方向D2上之接觸寬度(閘極長度)為例如0.5 μm。閘極電極21具有包括Ni層及在Ni層上之Au層的層合結構。在一項實例中，Ni層與氮化物半導體層4接觸，且Au層與Ni層接觸。替代地，Pd層可插入於Ni層與Au層之間。
場板35係沿著閘極電極21設置之金屬膜。如圖4中所示，絕緣膜7插入於場板35與閘極電極21之間。場板35具有例如Ti層(或Ta層)及Au層之層合結構。
閘極焊墊31係設置於第一非主動區域4ba上之閘極電極21之一部分上的金屬膜，並藉由通過形成於絕緣膜7及8中之開口與閘極電極21接觸而電連接至閘極電極21。在本實施例中，複數個閘極焊墊31在方向D2上並排地配置。每一閘極焊墊31經由結合導線電連接至外部導線。因此，每一閘極焊墊31之表面自絕緣膜9之開口曝露。每一閘極焊墊31具有包括例如TiW層及在TiW層上之Au層的層合結構。
源極焊墊32係設置於包括氮化物半導體層4之主動區域4a及第一非主動區域4ba之部分上方的金屬膜。本實施例之源極焊墊32包括在方向D2上與閘極焊墊31交替地配置之部分，及在源極電極22上方延伸並覆蓋源極電極22之部分(指狀部分)。源極焊墊32藉由在指狀部分處與每一源極電極22接觸而電連接至每一源極電極22。源極焊墊32之與閘極焊墊31並排地配置之部分各自自絕緣膜9之開口曝露，並各自通過穿透基板3之金屬通路44 (參見圖2)電連接至背金屬膜45。本實施例之源極焊墊32包括與氮化物半導體層4接觸之下層32a (參見圖2)。當在基板3中形成用於形成金屬通路44之通孔3c時，下層32a用於停止蝕刻。舉例而言，下層32a具有與閘極電極21相同的層合結構。每一源極焊墊32之除了下層32a之外的其餘部分具有與閘極焊墊31相同的層合結構，例如包括TiW層及在TiW層上之Au層的層合結構。此層合結構與下層32a周圍之氮化物半導體層4接觸。
金屬通路44係設置於自背表面3b至主表面3a穿透基板3 (生長基板30及氮化物半導體層4)之通孔3c中之導線。金屬通路44自基板3之背表面3b到達源極焊墊32，並與源極焊墊32接觸。設置金屬通路44以經由源極焊墊32以低電阻電連接設置於背表面3b上之背金屬膜45及源極電極22。當電晶體1A安裝於被界定為接地電位(參考電位)之基底構件上時，該基底構件及背金屬膜45經由諸如燒結型Ag膏之導電結合材料彼此電連接。結果，將接地電位施加至源極電極22。
汲極焊墊33各自係設置於包括氮化物半導體層4之第二非主動區域4bb及主動區域4a之部分上方的金屬膜。汲極焊墊33具有與閘極焊墊31及源極焊墊32相同的層合結構，例如包括TiW層及在TiW層上之Au層的層合結構。汲極焊墊33包括分別在汲極電極23上方延伸並覆蓋汲極電極23之部分(指狀部分)，並藉由與每一汲極電極23接觸而電連接至每一汲極電極23。此外，汲極焊墊33中設置於第二非主動區域4bb上之部分具有例如縱向方向係方向D2的矩形形狀，並經由結合導線電連接至外部導線。因此，汲極焊墊33之該部分之表面自絕緣膜9之開口曝露。
本實施例之電晶體1A進一步包括設置於主表面3a上(氮化物半導體層4上)之閘極防護部11及汲極防護部12。閘極防護部11由金屬膜製成，填充形成於絕緣膜5至8中之開口，並與氮化物半導體層4之第一非主動區域4ba接觸。閘極防護部11設置於邊緣3aa與閘極焊墊31之間，邊緣3aa位於主表面3a之一對邊緣3aa及3ab (換言之，氮化物半導體層4之一對邊緣)之第一非主動區域4ba上，該對邊緣3aa及3ab在方向D1中並排地配置。閘極防護部11與邊緣3aa及閘極焊墊31兩者隔開。在所圖示之實例中，閘極防護部11主要沿著方向D2 (沿著主表面3a之邊緣3aa)延伸。此外，閘極防護部11包括沿著主表面之側邊緣3ac延伸之部分11a，及沿著主表面3a之側邊緣3ad延伸之部分11b。部分11a及11b在方向D2上並排地配置。此等部分11a及11b分別自邊緣3aa附近並在方向D1上沿著側邊緣3ac及3ad延伸。閘極防護部11具有此類平面形狀，並因此自三個側環繞包括複數個閘極焊墊31之焊墊群組。
閘極防護部11經由分別對應於在方向D2上並排地配置之複數個源極焊墊32而設置之導線13以低電阻電連接至源極焊墊32，並經由源極焊墊32電連接至源極電極22。在本實施例中，閘極防護部11自源極焊墊32沿著主表面3a之邊緣3aa延伸。閘極防護部11經由導線13、源極焊墊32及金屬通路44以低電阻電連接至背金屬膜45，並被界定為與源極電極22相同的電位(例如參考電位)。
參看圖3，在與閘極防護部11之延伸方向相交之方向上的閘極防護部11與主表面3a之間的接觸寬度W1例如在1 μm至10 μm之範圍內，並在一項實施例中為6 μm。閘極防護部11與主表面3a上之閘極電極21之間的距離L1例如在5 μm至20 μm之範圍內，並在一項實施例中為15 μm。閘極防護部11與基板3之端表面(邊緣3aa)之間的距離L2例如在5 μm至40 μm之範圍內，並在一項實施例中為25 μm。閘極防護部11相對於主表面3a之高度h1 (在本實施例中等於閘極防護部11之厚度)例如在2 μm至8 μm之範圍內，並在一項實例中為4 μm。
汲極防護部12由金屬膜製成，填充形成於絕緣膜5至8中之開口，並與氮化物半導體層4之第二非主動區域4bb接觸。汲極防護部12設置於第二非主動區域4bb側上之主表面3a之邊緣3ab與汲極焊墊33之間，以便與邊緣3ab及汲極焊墊33兩者隔開。在所圖示之實例中，汲極防護部12主要沿著方向D2 (沿著主表面3a之邊緣3ab)延伸。汲極防護部12包括沿著側邊緣3ac延伸之部分12a及沿著側邊緣3ad延伸之部分12b。此等部分12a及12b分別在方向D1中自邊緣3ab附近並沿著側邊緣3ac及3ad延伸。汲極防護部12具有此類平面形狀，並因此自三個側環繞包括複數個汲極焊墊33之焊墊群組。
汲極防護部12相對於背金屬膜45、閘極電極21、源極電極22及汲極電極23處於非導電狀態。亦即，汲極防護部12與背金屬膜45、閘極電極21、源極電極22及汲極電極23絕緣。本實施例之汲極防護部12經由氮化物半導體層4之第二非主動區域4bb以及絕緣膜(介電體) 5至9連接至電極21至23及背金屬膜45。在電晶體1A之操作期間，汲極防護部12之電位係根據在汲極焊墊33與汲極防護部12之間的電阻值與在背金屬膜45與汲極防護部12之間的電阻值之比率除汲極焊墊33與背金屬膜45之間的電位差的值。因為汲極焊墊33與汲極防護部12之間的距離短於背金屬膜45與汲極防護部12之間的距離，所以汲極防護部12之電位接近於汲極焊墊33之電位。
在與汲極防護部12之延伸方向相交之方向上的汲極防護部12與主表面3a之間的接觸寬度例如在1 μm至10 μm之範圍內，並在一項實施例中為6 μm。汲極防護部12與主表面3a上之汲極焊墊33之間的距離例如在5 μm至20 μm之範圍內，並在一項實施例中為15 μm。汲極防護部12與基板3之端表面(邊緣3ab)之間的距離例如在5 μm至40 μm之範圍內，並在一項實施例中為25 μm。汲極防護部12相對於主表面3a之高度(在本實施例中等於汲極防護部12之厚度)例如在2 μm至8 μm之範圍內，並在一項實例中為4 μm。
閘極防護部11及汲極防護部12係與閘極焊墊31、源極焊墊32及汲極焊墊33同時形成，並由與此等焊墊31至33相同的材料製成。亦即，本實施例之閘極防護部11及汲極防護部12具有與焊墊31至33相同的層合結構，例如包括TiW層及在TiW層上之Au層的層合結構。閘極防護部11及汲極防護部12被絕緣膜9覆蓋。
將描述用於製造具有上述結構的本實施例之電晶體1A的方法。圖5A至圖9C係示出根據本實施例之製造方法之典型步驟的橫截面圖。圖5A、圖6A、圖7A、圖8A及圖9A示出對應於圖1中之線II-II的橫截面。圖5B、圖6B、圖7B、圖8B及圖9B示出對應於線III-III的橫截面。圖5C、圖6C、圖7C、圖8C及圖9C示出對應於線IV-IV的橫截面。
首先，在生長基板30上形成氮化物半導體層4，且製造基板3。具體言之，首先，在生長基板30上磊晶地生長AlN緩衝層，在AlN緩衝層上磊晶地生長GaN通道層，在GaN通道層上磊晶地生長AlGaN (或InAlN)障壁層，且在AlGaN (或InAlN)障壁層上磊晶地生長GaN頂蓋層。然後，藉由將Ar+ 離子植入至氮化物半導體層4之除了主動區域4a之外的部分中來形成非主動區域4b。因此製造了圖1至圖4中所示之基板3。
接下來，如圖5A至圖5C中所示，在基板3之主表面3a上沈積絕緣膜5。舉例而言，當絕緣膜5由諸如SiN之矽化合物製成時，藉由電漿CVD方法或低壓CVD (LPCVD)方法沈積絕緣膜5。在LPCVD之情況下，成膜溫度為例如850℃，且成膜壓力為例如10 Pa或更小。用於形成膜之原料係例如NH3 及SiH2 Cl2 。絕緣膜5之厚度例如在60 nm至100 nm之範圍內，並在一項實施例中為60 nm。
隨後，如圖6C中所示，在絕緣膜5中形成對應於源極電極22之開口51。同時，在絕緣膜5中形成對應於汲極電極23之其他開口。具體言之，在絕緣膜5上形成具有對應於此等開口之開口圖案之抗蝕劑遮罩，且通過開口圖案蝕刻絕緣膜5以形成此等開口。此後，藉由使用起離方法在開口51中形成源極電極22，且在其他開口中形成汲極電極23。亦即，在留下抗蝕劑遮罩之情況下，使用物理氣相沈積方法或其類似者循序地沈積用於源極電極22及汲極電極23之每一金屬層(例如Ti/Al/Ti或Ta/Al/Ta)。每一Ti層(或Ta層)之厚度例如在10 nm至30 nm之範圍內(在一項實施例中為10 nm)，且Al層之厚度例如在200 nm至400 nm之範圍內(在一項實施例中為300 nm)。在與抗蝕劑遮罩一起移除沈積於抗蝕劑遮罩上之金屬材料之後，在500℃至600℃之範圍內(在一項實施例中為550℃)之溫度下執行熱處理(退火)以使源極電極22及汲極電極23合金化。將溫度維持於500℃至600℃之範圍內之時間為例如1分鐘。
隨後，如圖6A至圖6C中所示，沈積覆蓋絕緣膜5、源極電極22及汲極電極23之絕緣膜6。舉例而言，當絕緣膜6由諸如SiN之矽化合物製成時，藉由電漿CVD方法沈積絕緣膜6。成膜溫度為例如300℃，且成膜材料為例如NH3 及SiH4 。絕緣膜6之厚度為例如100 nm。藉由此步驟，將要形成閘極電極21之區域被雙絕緣膜5及6覆蓋。
隨後，形成源極焊墊32之下層32a以及閘極電極21。首先，在絕緣膜6上沈積用於電子束之抗蝕劑(EB抗蝕劑)，且藉由EB寫入在EB抗蝕劑中形成用於閘極電極21以及源極焊墊32之下層32a的開口圖案。接下來，藉由通過EB抗蝕劑之開口圖案連續地蝕刻絕緣膜6及絕緣膜5，如圖7B及圖7C中所示而形成穿透絕緣膜5及6之開口52及53以曝露氮化物半導體層4。此後，在開口52以及源極焊墊32之下層32a中形成閘極電極21，且同時，藉由使用起離方法在開口53中形成源極焊墊32之下層32a。亦即，在留下EB抗蝕劑之情況下，藉由使用物理氣相沈積方法或其類似者循序地沈積用於閘極電極21及下層32a之每一金屬層(例如Ni/Au或Ni/Pd/Au)。Ni層之厚度例如在70 nm至150 nm之範圍內(在一項實施例中為100 nm)，Pd層之厚度例如在50 nm至100 nm之範圍內(在一項實施例中為50 nm)，且Au層之厚度例如在300 nm至700 nm之範圍內(在一項實施例中為500 nm)。此後，將沈積於EB抗蝕劑上之金屬材料與EB抗蝕劑一起移除。
隨後，如圖8A至圖8C中所示，沈積絕緣膜7。最初，在主表面3a上之整個表面上形成絕緣膜7，且絕緣膜7覆蓋絕緣膜6、閘極電極21及下層32a。舉例而言，當絕緣膜7由諸如SiN之矽化合物製成時，藉由電漿CVD方法沈積絕緣膜7。成膜溫度為例如300℃，且成膜材料為例如NH3 及SiH4 。絕緣膜7之厚度為例如100 nm。
隨後，如圖8C中所示，在絕緣膜7上沿著主動區域4a上之閘極電極21形成場板35。在此步驟中，使用例如起離方法形成場板35。亦即，形成具有對應於場板35之平面形狀之開口圖案之抗蝕劑遮罩，且使用物理氣相沈積方法或其類似者循序地沈積用於場板35之每一金屬層(例如Ti (或Ni)/Au)。在一項實施例中，Ti層(或Ni層)之厚度為10 nm，且Au層之厚度為200 nm。此後，將沈積於抗蝕劑遮罩上之金屬材料與抗蝕劑遮罩一起移除。
隨後，沈積覆蓋絕緣膜7及場板35之絕緣膜8。最初，在整個主表面3a上形成絕緣膜8。舉例而言，當絕緣膜8由諸如SiN之矽化合物製成時，藉由電漿CVD方法沈積絕緣膜8。成膜溫度為例如300℃，且成膜材料為例如NH3 及SiH4 。絕緣膜8之厚度為例如200 nm至500 nm。
隨後，如圖8A中所示，藉由蝕刻移除下層32a上之絕緣膜7及8以形成開口，且曝露下層32a。此時，藉由連續地蝕刻下層32a周圍之絕緣膜5至8，曝露了下層32a周圍之氮化物半導體層4。同時，藉由蝕刻移除對應於源極焊墊32及汲極焊墊33之區域中之絕緣膜5至8以形成開口。彼等開口包括在源極電極22上之區域及在汲極電極23上之區域，如圖8C中所示，且在該等區域中曝露了源極電極22及汲極電極23。彼等開口包括對應於非主動區域4b上之源極焊墊32及汲極焊墊33之區域，且在該等區域中曝露了氮化物半導體層4。同時，如圖8B中所示，藉由蝕刻移除對應於閘極焊墊31之區域中之絕緣膜7及8以形成開口55，且曝露了閘極電極21。此外，在此步驟中，如圖8A及圖8B中所示，藉由蝕刻移除對應於閘極防護部11之區域中之絕緣膜5至8以形成開口54，且曝露了氮化物半導體層4。同時，藉由蝕刻移除對應於汲極防護部12之區域中之絕緣膜5至8以形成開口，且曝露了氮化物半導體層4。具體言之，在絕緣膜8上形成具有對應於上述開口之開口圖案之抗蝕劑遮罩，且藉由該開口圖案蝕刻絕緣膜5至8以形成此等開口。
如圖9A至圖9C中所示，在移除抗蝕劑遮罩之後，同時形成閘極防護部11、汲極防護部12、導線13、閘極焊墊31、源極焊墊32及汲極焊墊33。具體言之，藉由濺鍍方法在整個主表面3a上形成晶種金屬層(Ti/TiW/Ti/Au)。每一Ti層之厚度為例如10 nm，TiW層之厚度為例如100 nm，且Au層之厚度為例如100 nm。然後，在晶種金屬層上形成在將要形成閘極防護部11、汲極防護部12、導線13、閘極焊墊31、源極焊墊32及汲極焊墊33之區域中具有開口之抗蝕劑遮罩。此後，執行電解電鍍程序以在抗蝕劑遮罩之每一開口中形成Au層。此時，Au層之厚度為例如3 μm。在電鍍程序之後，移除抗蝕劑遮罩，且移除經曝露之晶種金屬層。
隨後，在主表面3a上之整個表面上沈積絕緣膜(鈍化膜) 9。舉例而言，當絕緣膜9由諸如SiN之矽化合物製成時，藉由電漿CVD方法沈積絕緣膜9。成膜溫度為例如300℃，且成膜材料為例如NH3 及SiH4 。絕緣膜9之厚度為例如200 nm至500 nm。此後，在非主動區域4b中之閘極焊墊31、源極焊墊32及汲極焊墊33上形成絕緣膜9之開口以分別曝露閘極焊墊31、源極焊墊32及汲極焊墊33。因此完成了主表面3a側上之程序。
隨後，藉由旋塗在主表面3a上形成保護性抗蝕劑，且該抗蝕劑覆蓋主表面3a上之所有組件。然後，將支撐基板附接至抗蝕劑。支撐基板係例如玻璃板。然後，拋光基板3之背表面3b以使基板3變薄。此時，舉例而言，使具有500 μm之厚度之生長基板30變薄至100 μm。
隨後，藉由例如濺鍍方法在基板3之背表面3b及側表面上形成晶種金屬膜(例如TiW/Au)。在與源極焊墊32之下層32a重疊之位置處形成抗蝕劑圖案之後，藉由執行Ni電鍍程序來形成Ni遮罩。此後，移除抗蝕劑圖案，且藉由蝕刻移除經曝露之晶種金屬膜。藉此，通過Ni遮罩之開口曝露了背表面3b之與下層32a重疊之區域。當晶種金屬膜由TiW/Au製成時，可藉由使用氟基氣體之反應性離子蝕刻(RIE)容易移除晶種金屬膜。
隨後，藉由通過Ni遮罩之開口蝕刻生長基板30及氮化物半導體層4在基板3中形成通孔3c (參見圖2)。通孔3c自基板3之背表面3b到達下層32a。藉此，將下層32a通過通孔3c曝露於背表面3b。然後，藉由例如濺鍍方法在基板3之背表面3b上及在通孔3c之內表面上(包括在經曝露之下層32a上)形成晶種金屬膜(例如TiW/Au)。藉由在晶種金屬膜上執行電鍍，在背表面3b上形成背金屬膜45，且在通孔3c中形成自背表面3b到達下層32a之金屬通路44。最後，將基板3之主表面3a側上之組件與支撐基板分離。在清潔包括所取出之基板3之基板產品之後，沿著切割道執行分割以將個別晶片彼此分離。經由以上步驟，完成了本實施例之電晶體1A。
將與習知問題一起描述由上述本實施例之電晶體1A獲得之效果。通常，背金屬膜45經由導電結合材料而導電地結合至金屬基底構件。在許多情況下，基底構件被設定為參考電位(接地電位)。在此情況下，當將低於參考電位之負電壓施加至閘極電極21時，在閘極焊墊31與基底構件之間產生閘極焊墊31側為負的電場。在潮濕環境中，歸因於此電場，很可能發生導電結合材料中所含有之金屬(例如Ag、Au、Cu)之離子遷移。離子遷移係離子化金屬在電場之間於物質表面上移動的現象。金屬離子藉由被電場吸引而移動，由於某種原因而自離子化狀態返回至金屬，並積累以形成枝晶。若金屬之枝晶自導電結合材料中生長且閘極焊墊31及背金屬膜45短路，則電晶體之操作可能有缺陷。
近年來，已積極地開發使用GaN、SiC、Ga2 O3 及其類似者作為主要半導體材料之寬間隙半導體裝置，並將其投入實際應用。因為寬間隙半導體裝置具有高耐壓，所以藉由增加電力供應電壓以增加遷移率、減小電極之間的寄生電容及其類似者來增強半導體之效能。由於此原因，在寬間隙半導體裝置中，上文所提及之電場變強，且容易發生離子遷移。
因此，本實施例之電晶體1A在主表面3a之邊緣3aa與閘極焊墊31之間包括閘極防護部11。閘極防護部11電連接至背金屬膜45，並被界定為與背金屬膜45相同的電位(例如參考電位)。結果，主要在閘極防護部11與閘極焊墊31之間產生電場，且在閘極防護部11與背金屬膜45之間產生之電場小。因此，因為用於在閘極防護部11與背金屬膜45之間移動金屬離子之力極弱，所以可抑制在基板3之側表面上生長枝晶，且可減少背金屬膜45與閘極焊墊31之間的短路。
本實施例之電晶體1A在主表面3a之邊緣3ab與汲極焊墊33之間包括汲極防護部12。因此，可與閘極防護部11一起抑制濕氣進入主動區域4a中，且可改良電晶體1A之抗濕性。此處，若將汲極防護部12以低電阻電連接至閘極防護部11，則會發生以下問題。通常，將正偏壓電壓施加至汲極電極23。在使用GaN作為主要半導體材料之電晶體之情況下，至汲極電極23之偏壓電壓係超過例如50 V之高電壓。當將汲極防護部12電連接至閘極防護部11時，汲極防護部12被界定為與背金屬膜45相同的電位(例如參考電位)。因為汲極防護部12被配置為靠近汲極焊墊33，所以汲極防護部12與汲極焊墊33之間的電場增加。汲極焊墊33之表面自絕緣膜9之開口曝露，且濕氣進入絕緣膜9與汲極焊墊33之間的邊界。電場使濕氣在汲極防護部12與汲極焊墊33之間的進入加速。因此，電晶體1A之抗濕性降低。
為了解決此問題，在本實施例中，汲極防護部12相對於背金屬膜45、閘極電極21、源極電極22及汲極電極23處於非導電狀態。在此情況下，與以低電阻將汲極防護部12電連接至閘極防護部11之情況相比，可減小汲極防護部12與汲極焊墊33之間的電場。因此，可抑制電晶體1A之抗濕性降低。
如在本實施例中一樣，源極焊墊32可與閘極焊墊31並排地配置於第一非主動區域4ba上，且閘極防護部11可自源極焊墊32沿著第一非主動區域4ba側上之邊緣3aa延伸。舉例而言，就此類組態而言，可將閘極防護部11電連接至源極電極22，且可將閘極防護部11配置於閘極焊墊31與邊緣3aa之間。
如在本實施例中一樣，可運用在汲極焊墊33及閘極焊墊31上具有開口之絕緣膜9覆蓋閘極防護部11及汲極防護部12。在此情況下，可進一步改良電晶體1A之抗濕性。
(修改) 圖10係根據上述實施例之修改之電晶體1B的部分橫截面圖，並示出對應於圖1中所示之線II-II的橫截面。在本修改中，與上述實施例不同，絕緣膜5至8未插入於連接閘極防護部11及源極焊墊32之導線13與氮化物半導體層4之間，且導線13及氮化物半導體層4彼此接觸。亦即，本修改之導線13直接形成於經曝露之氮化物半導體層4上。在此情況下，導線13各自用作閘極防護部11之一部分，且可使上述實施例之效果更顯著。
(第二實施例) 圖11係示出根據第二實施例之半導體裝置100之組態的平面圖。圖11示出半導體裝置100之蓋被移除的狀態。半導體裝置100包括第一實施例之電晶體1A、封裝101、輸入匹配電路106、輸出匹配電路108，及輸出電容器109。電晶體1A、輸入匹配電路106、輸出匹配電路108及輸出電容器109容納於封裝101中。封裝101具有不執行氣密密封的非氣密結構。
封裝101包括基底構件103、側壁104、兩個輸入引線150，及兩個輸出引線160。基底構件103係板狀構件，其包括由金屬製成之平坦主表面103a。基底構件103由例如以下各者製成：銅；銅與鉬之合金；銅與鎢之合金；或銅板、鉬板、鎢板、銅與鉬之合金板及銅與鎢之合金板的層合材料。基底構件103之基底材料之表面被電鍍有鎳鉻(鎳鉻合金)-金、鎳-金、鎳-鈀-金、銀或鎳，或鎳-鈀。金、銀及鈀係電鍍材料，且NiCr及Ni係晶種材料。與僅使用電鍍材料之情況相比，當包括電鍍材料及晶種材料時，可增強黏附性。基底構件103之厚度為例如0.5 mm至1.5 mm。基底構件103之平面形狀係例如矩形形狀。
側壁104係由作為介電體之陶瓷製成之實質上矩形框架狀構件。側壁104包括沿著基底構件103之主表面103a在方向D1上彼此面對的一對部分141及142，以及在與方向D1交叉之方向D2上彼此面對的一對部分143及144。部分141及142沿著方向D2彼此平行地延伸，且部分143及144沿著方向D1彼此平行地延伸。部分141至144中之每一者之垂直於延伸方向的橫截面為矩形或正方形。側壁104在主表面103a之法線方向上之高度為例如0.5 mm至1.0 mm。側壁104經由諸如銀釺焊之黏合材料與基底構件103之主表面103a耦接。
輸入引線150及輸出引線160係金屬板狀構件，並在一項實例中係銅、銅合金或鐵合金之金屬薄片。輸入引線150在方向D1上具有與側壁104之部分141之上表面耦接的一端。輸入引線150藉由側壁104之部分141與基底構件103之主表面103a絕緣。輸出引線160具有在方向D1上與側壁104之部分142之上表面耦接的一端。輸出引線160藉由側壁104之部分142與基底構件103之主表面103a絕緣。
電晶體1A、輸入匹配電路106、輸出匹配電路108及輸出電容器109安裝於由基底構件103之主表面3a上之側壁104環繞的區域中。輸入匹配電路106、電晶體1A、輸出匹配電路108及輸出電容器109係自側壁104之部分141以此順序設置。輸入匹配電路106及輸出匹配電路108係例如平行板型電容器，其各自在陶瓷基板之上表面及下表面上具有電極。
輸入匹配電路106、電晶體1A及輸出匹配電路108運用諸如燒結型導電膏之導電結合材料固定於基底構件103上。導電結合材料包括Ag、Au及Cu中之至少一者。在一項實施例中，藉由燒結一種燒結型銀膏獲得導電結合材料。用於固定電晶體1A之導電結合材料插入於電晶體1A之背金屬膜45與基底構件103之主表面103a之間，並將它們電連接及牢固地連接。分別地，輸入匹配電路106安裝於電晶體1A之輸入側上，且輸出匹配電路108安裝於電晶體1A之輸出側上。輸入匹配電路106與電晶體1A、電晶體1A與輸出匹配電路108、輸出匹配電路108與輸出電容器109及輸出電容器109與輸出引線160與對應導線(未圖示)電連接。
輸入匹配電路106在輸入引線150與電晶體1A之間執行阻抗匹配。輸入匹配電路106之一端經由結合導線電連接至輸入引線150。輸入匹配電路106之另一端經由結合導線電連接至電晶體1A之閘極焊墊31 (參見圖1)。
輸出匹配電路108在電晶體1A與外部電路之間執行阻抗匹配。輸出匹配電路108執行匹配，使得獲得所要的輸出、效率及頻率特性。輸出匹配電路108之一端經由結合導線電連接至電晶體1A之汲極焊墊33 (參見圖1)。輸出匹配電路108之另一端經由結合導線及輸出電容器109電連接至輸出引線160。
本實施例之半導體裝置100包括第一實施例之電晶體1A。因此，可抑制歸因於插入於電晶體1A與基底構件103之主表面103a之間的導電結合材料之離子遷移而引起的枝晶生長，且可減少基底構件103之主表面103a與閘極焊墊31之間的短路。可抑制濕氣進入主動區域4a，且可改良電晶體1A之抗濕性。當如在本實施例中一樣容納電晶體1A之封裝101具有非氣密結構時，電晶體1A之有用性變得更顯著。
根據本發明之場效電晶體及半導體裝置不限於上述實施例，且可對其進行各種其他修改。舉例而言，在上述實施例中，金屬通路44緊接地設置於非主動區域4b中之源極焊墊32下方，但可緊接地設置於主動區域4a中之源極電極22下方(或緊接地設置於形成於源極電極22中之開口下方)。在上述實施例中，閘極防護部11包括部分11a及11b，且汲極防護部12包括部分12a及12b，但在必要時可省略此等部分中之至少一者。在上述實施例中，閘極防護部11、汲極防護部12及源極焊墊32具有相同的組態並被同時形成。然而，它們可具有不同的組態並可以不同的時序被形成。相關申請 案 之交叉 參考
本申請案主張2019年2月28日申請之日本申請案第JP2019-035726號的優先權益，該日本申請案之全部內容以引用的方式併入本文中。
1A:場效電晶體 1B:電晶體 3:基板 3a:主表面 3aa:邊緣 3ab:邊緣 3ac:側邊緣 3ad:側邊緣 3b:背表面 3c:通孔 4:氮化物半導體層 4a:主動區域 4b:非主動區域 4ba:第一非主動區域 4bb:第二非主動區域 5:絕緣膜 6:絕緣膜 7:絕緣膜 8:絕緣膜 9:絕緣膜 11:閘極防護部 11a:部分 11b:部分 12:汲極防護部 12a:部分 12b:部分 13:導線 21:閘極電極 22:源極電極 23:汲極電極 30:生長基板 30a:主表面 30b:背表面 31:閘極焊墊 32:源極焊墊 32a:下層 33:汲極焊墊 35:場板 44:金屬通路 45:背金屬膜 51:開口 52:開口 53:開口 54:開口 55:開口 100:半導體裝置 101:封裝 103:基底構件 103a:主表面 104:側壁 106:輸入匹配電路 108:輸出匹配電路 109:輸出電容器 141:部分 142:部分 143:部分 144:部分 150:輸入引線 160:輸出引線 D1:方向 D2:方向 h1:高度 L1:距離 L2:距離 W1:接觸寬度 II-II:線 III-III:線 IV-IV:線
圖1係示出根據第一實施例之場效電晶體(在下文中簡稱為電晶體)之組態的平面圖；
圖2係沿著圖1中之線II-II截取的截面圖；
圖3係沿著圖1中之線III-III截取的截面圖；
圖4係沿著圖1中之線IV-IV截取的截面圖；
圖5A係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線II-II的橫截面；
圖5B係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線III-III的橫截面；
圖5C係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線IV-IV的橫截面；
圖6A係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線II-II的橫截面；
圖6B係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線III-III的橫截面；
圖6C係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線IV-IV的橫截面；
圖7A係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線II-II的橫截面；
圖7B係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線III-III的橫截面；
圖7C係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線IV-IV的橫截面；
圖8A係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線II-II的橫截面；
圖8B係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線III-III的橫截面；
圖8C係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線IV-IV的橫截面；
圖9A係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線II-II的橫截面；
圖9B係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線III-III的橫截面；
圖9C係示出根據第一實施例之製造方法之典型步驟的橫截面圖，並示出對應於圖1中之線IV-IV的橫截面；
圖10係根據修改之電晶體的部分橫截面圖，並示出對應於圖1中所示之線II-II的截面圖；及
圖11係示出根據第二實施例之半導體裝置之組態的平面圖。
1A:場效電晶體
3:基板
3a:主表面
3aa:邊緣
3ab:邊緣
3ac:側邊緣
3ad:側邊緣
4a:主動區域
4b:非主動區域
4ba:第一非主動區域
4bb:第二非主動區域
11:閘極防護部
11a:部分
11b:部分
12:汲極防護部
12a:部分
12b:部分
13:導線
21:閘極電極
22:源極電極
23:汲極電極
31:閘極焊墊
32:源極焊墊
33:汲極焊墊
44:金屬通路
D1:方向
D2:方向
II-II:線
III-III:線
IV-IV:線

Claims (14)

  1. 一種場效電晶體，其包含：一基板，該基板包括一主表面及一背表面；一半導體區域，該半導體區域在該主表面上，該半導體區域包括在一第一方向上並排地配置之一第一非主動區域、一主動區域及一第二非主動區域；一閘極電極、一源極電極及一汲極電極，該閘極電極、該源極電極及該汲極電極在該主動區域上；一閘極焊墊，該閘極焊墊在該第一非主動區域上並電連接至該閘極電極；一閘極防護部，該閘極防護部在該半導體區域上並與該半導體區域接觸，該閘極防護部與該閘極焊墊隔開並位於該閘極焊墊與該半導體區域之一對邊緣之第一非主動區域側上之一邊緣之間，該對邊緣在該第一方向上並排地配置；一汲極焊墊，該汲極焊墊在該第二非主動區域上並電連接至該汲極電極；一汲極防護部，該汲極防護部在該半導體區域上並與該半導體區域接觸，該汲極防護部與該汲極焊墊隔開並位於該汲極焊墊與該半導體區域之該對邊緣之第二非主動區域側上之一邊緣之間；及一金屬膜，該金屬膜在該背表面上並電連接至該閘極防護部，其中該汲極防護部相對於該金屬膜、該閘極電極、該源極電極及該汲極電極處於一非導電狀態。
  2. 如請求項1之場效電晶體，其進一步包含一導線，該導線穿透該基板及該半導體區域，其中該源極電極經由該導線電連接至該金屬膜，且其中該閘極防護部電連接至該源極電極。
  3. 如請求項1之場效電晶體，其進一步包含一源極焊墊，該源極焊墊電連接至該源極電極，該源極焊墊與該閘極焊墊並排地配置於該第一非主動區域上，且其中該閘極防護部自該源極焊墊沿著該第一非主動區域側上之該邊緣延伸。
  4. 如請求項1之場效電晶體，其進一步包含一絕緣膜，該絕緣膜在該汲極焊墊及該閘極焊墊上具有開口，其中該閘極防護部及該汲極防護部被該絕緣膜覆蓋。
  5. 如請求項1之場效電晶體，其中該閘極防護部由金屬製成。
  6. 如請求項1至5中任一項之場效電晶體，其中該汲極防護部由金屬製成。
  7. 一種半導體裝置，其包含： 如請求項1至6中任一項之場效電晶體；一基底構件，該基底構件具有一金屬表面並安裝該場效電晶體；及一導電結合材料，該導電結合材料插入於該場效電晶體之該金屬膜與該基底構件之一表面之間，該導電結合材料包括Ag、Au及Cu中之至少一者。
  8. 如請求項7之半導體裝置，其進一步包含一封裝，該場效電晶體非氣密地容納於該封裝中。
  9. 一種場效電晶體，其包含：一基板，該基板包括一主表面及一背表面；一半導體區域，該半導體區域在該主表面上，該半導體區域包括在一第一方向上並排地配置之一第一邊緣、一第一非主動區域、一主動區域、一第二非主動區域及一第二邊緣；一閘極電極、一源極電極及一汲極電極，該閘極電極、該源極電極及該汲極電極在該主動區域上；一閘極焊墊，該閘極焊墊在該第一非主動區域上並電連接至該閘極電極；一閘極防護部，該閘極防護部在該半導體區域上並與該半導體區域接觸，該閘極防護部與該閘極焊墊隔開並位於該第一邊緣與該閘極焊墊之間；一汲極焊墊，該汲極焊墊在該第二非主動區域上並電連接至該汲極電極； 一汲極防護部，該汲極防護部在該半導體區域上並與該半導體區域接觸，該汲極防護部與該汲極焊墊隔開並位於該第二邊緣與該汲極焊墊之間；及一金屬膜，該金屬膜在該背表面上並電連接至該閘極防護部，其中該汲極防護部與該金屬膜、該閘極電極、該源極電極及該汲極電極電絕緣。
  10. 如請求項9之場效電晶體，其進一步包含一導線，該導線嵌入於該基板及該半導體區域中，其中該源極電極經由該導線電連接至該金屬膜，且其中該閘極防護部電連接至該源極電極。
  11. 如請求項9之場效電晶體，其進一步包含一源極焊墊，該源極焊墊電連接至該源極電極，該源極焊墊與該閘極焊墊並排地配置於該第一非主動區域上，且其中該閘極防護部在一平面圖中沿著該第一邊緣自該源極焊墊延伸。
  12. 如請求項9之場效電晶體，其進一步包含一絕緣膜，該絕緣膜具有在該汲極焊墊上之一第一開口及在該閘極焊墊上之一第二開口，其中該閘極防護部及該汲極防護部被該絕緣膜覆蓋。
  13. 如請求項9之場效電晶體， 其中該閘極防護部由金屬製成。
  14. 如請求項9至13中任一項之場效電晶體，其中該汲極防護部由金屬製成。
TW109106275A 2019-02-28 2020-02-26 場效電晶體及半導體裝置 TWI819195B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-035726 2019-02-28
JP2019035726 2019-02-28

Publications (2)

Publication Number Publication Date
TW202038320A TW202038320A (zh) 2020-10-16
TWI819195B true TWI819195B (zh) 2023-10-21

Family

ID=72236422

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109106275A TWI819195B (zh) 2019-02-28 2020-02-26 場效電晶體及半導體裝置

Country Status (4)

Country Link
US (2) US11081452B2 (zh)
JP (1) JP7380310B2 (zh)
CN (1) CN111627997A (zh)
TW (1) TWI819195B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7380310B2 (ja) * 2019-02-28 2023-11-15 住友電工デバイス・イノベーション株式会社 電界効果トランジスタ及び半導体装置
WO2022143786A1 (zh) * 2020-12-31 2022-07-07 苏州能讯高能半导体有限公司 一种半导体器件及其制备方法
WO2023136121A1 (ja) * 2022-01-13 2023-07-20 住友電気工業株式会社 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050239259A1 (en) * 2004-04-26 2005-10-27 Ixys Corporation High voltage power device with low diffusion pipe resistance
US20170221878A1 (en) * 2014-07-31 2017-08-03 Sii Semiconductor Corporation Semiconductor device having esd element

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5535490B2 (ja) 2009-01-30 2014-07-02 住友電工デバイス・イノベーション株式会社 半導体装置
WO2015129131A1 (ja) 2014-02-25 2015-09-03 シャープ株式会社 半導体装置
JP6515714B2 (ja) 2015-07-14 2019-05-22 三菱電機株式会社 トランジスタ
JP7155482B2 (ja) * 2018-09-13 2022-10-19 住友電工デバイス・イノベーション株式会社 半導体装置
JP7380310B2 (ja) * 2019-02-28 2023-11-15 住友電工デバイス・イノベーション株式会社 電界効果トランジスタ及び半導体装置
DE102020120899A1 (de) * 2019-12-24 2021-06-24 Taiwan Semiconductor Manufacturing Co., Ltd. Abscheidungsprozess zum bilden von halbleitervorrichtungen und system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050239259A1 (en) * 2004-04-26 2005-10-27 Ixys Corporation High voltage power device with low diffusion pipe resistance
US20170221878A1 (en) * 2014-07-31 2017-08-03 Sii Semiconductor Corporation Semiconductor device having esd element

Also Published As

Publication number Publication date
US11081452B2 (en) 2021-08-03
JP7380310B2 (ja) 2023-11-15
US20200279818A1 (en) 2020-09-03
JP2020145423A (ja) 2020-09-10
US20210327827A1 (en) 2021-10-21
TW202038320A (zh) 2020-10-16
US11749622B2 (en) 2023-09-05
CN111627997A (zh) 2020-09-04

Similar Documents

Publication Publication Date Title
JP7066778B2 (ja) 高電子移動度トランジスタ（ｈｅｍｔ）
US11749622B2 (en) Field effect transistor and semiconductor device
JP5048230B2 (ja) 半導体装置およびその製造方法
JP5154000B2 (ja) 半導体装置
EP2741324B1 (en) III nitride transistor with source connected heat-spreading plate and method of making the same
US20220262710A1 (en) Semiconductor device and method of manufacturing the same
JP2018037497A (ja) 半導体装置
US9460995B2 (en) Semiconductor device and structure therefor
US11658093B2 (en) Semiconductor element with electrode having first section and second sections in contact with the first section, and semiconductor device
JP4837939B2 (ja) 半導体装置、及び半導体装置の製造方法
KR100620926B1 (ko) 집적형 쇼트키 배리어 다이오드 및 그 제조 방법
JP7332130B2 (ja) 半導体デバイスの製造方法、半導体装置の製造方法、半導体デバイス、及び半導体装置
US20230238333A1 (en) Chip-substrate composite semiconductor device
KR100616049B1 (ko) 쇼트키 배리어 다이오드 및 그 제조 방법
KR100612187B1 (ko) 쇼트키 배리어 다이오드의 제조 방법
KR20030019197A (ko) 쇼트키 배리어 다이오드 및 그 제조 방법
JP2023062209A (ja) 半導体デバイス及び半導体デバイスの製造方法
KR100620924B1 (ko) 쇼트키 배리어 다이오드 및 그 제조 방법
JP2020136459A (ja) 半導体装置の製造方法および半導体装置
JP2018010968A (ja) 半導体装置