JP7380310B2 - 電界効果トランジスタ及び半導体装置 - Google Patents
電界効果トランジスタ及び半導体装置 Download PDFInfo
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- JP7380310B2 JP7380310B2 JP2020028602A JP2020028602A JP7380310B2 JP 7380310 B2 JP7380310 B2 JP 7380310B2 JP 2020028602 A JP2020028602 A JP 2020028602A JP 2020028602 A JP2020028602 A JP 2020028602A JP 7380310 B2 JP7380310 B2 JP 7380310B2
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Description
最初に、本開示の実施形態を列記して説明する。一実施形態に係る電界効果トランジスタは、基板の主面上に設けられ、第1方向に並ぶ第1不活性領域、活性領域、及び第2不活性領域を有する半導体領域と、活性領域上に設けられたゲート電極、ソース電極及びドレイン電極と、第1不活性領域上に設けられ、ゲート電極と電気的に接続されたゲートパッドと、第1方向に並ぶ半導体領域の一対の端縁のうち第1不活性領域側の端縁とゲートパッドとの間において、ゲートパッドから離間して半導体領域上に設けられ、半導体領域に接する金属製のゲートガードと、第2不活性領域上に設けられ、ドレイン電極と電気的に接続されたドレインパッドと、半導体領域の一対の端縁のうち第2不活性領域側の端縁とドレインパッドとの間において、ドレインパッドから離間して半導体領域上に設けられ、半導体領域に接する金属製のドレインガードと、を備える。ゲートガードは、基板の裏面に設けられた金属膜と電気的に接続されている。ドレインガードは金属膜、ゲート電極、ソース電極及びドレイン電極に対して非導通状態にある。
本開示の電界効果トランジスタ及び半導体装置の具体例を、以下に図面を参照しつつ説明する。なお、本発明はこれらの例示に限定されるものではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味及び範囲内でのすべての変更が含まれることが意図される。以下の説明では、図面の説明において同一の要素には同一の符号を付し、重複する説明を省略する。
図1は、第1実施形態に係る電界効果トランジスタ(以下、単にトランジスタと称する)1Aの構成を示す平面図である。図2は、図1のII-II線に沿った断面図である。図3は、図1のIII-III線に沿った断面図である。図4は、図1のIV-IV線に沿った断面図である。図1~図4に示すように、トランジスタ1Aは、基板3、絶縁膜5~9、ゲート電極21、ソース電極22、ドレイン電極23、ゲートパッド31、ソースパッド32、ドレインパッド33、フィールドプレート35(図4を参照)、金属ビア44(図2を参照)、及び裏面金属膜45を備える。
図10は、上記実施形態の一変形例に係るトランジスタ1Bの部分断面図であって、図1に示したII-II線に対応する断面を示している。本変形例では、上記実施形態と異なり、ゲートガード11とソースパッド32とを接続する配線13と窒化物半導体層4との間に絶縁膜5~8が介在しておらず、配線13と窒化物半導体層4とが互いに接している。つまり、本変形例の配線13は、露出した窒化物半導体層4上に直接形成されている。この場合、配線13がゲートガード11の一部として機能し、上記実施形態の効果をより顕著とすることができる。
図11は、第2実施形態に係る半導体装置100の構成を示す平面図である。図11では、半導体装置100の蓋部を外した状態を示している。この半導体装置100は、第1実施形態のトランジスタ1A、パッケージ101、入力整合回路106、出力整合回路108、及び出力キャパシタ109を備える。トランジスタ1A、入力整合回路106、出力整合回路108、及び出力キャパシタ109は、パッケージ101に収容されている。パッケージ101は、ハーメチックシールが行われない非気密構造を有する。
3…基板
3a…主面
3aa,3ab…端縁
3ac,3ad…側縁
3b…裏面
3c…貫通孔
4…窒化物半導体層
4a…活性領域
4b…不活性領域
4ba…第1不活性領域
4bb…第2不活性領域
5~9…絶縁膜
11…ゲートガード
11a,11b…(ゲートガードの)部分
12…ドレインガード
12a,12b…(ドレインガードの)部分
13…配線
21…ゲート電極
22…ソース電極
23…ドレイン電極
30…成長基板
30a…主面
30b…裏面
31…ゲートパッド
32…ソースパッド
32a…下層
33…ドレインパッド
35…フィールドプレート
44…金属ビア
45…裏面金属膜
51~54…開口
100…半導体装置
101…パッケージ
103…ベース部材
103a…主面
104…側壁
106…入力整合回路
108…出力整合回路
109…出力キャパシタ
141~144…(側壁の)部分
150…入力リード
160…出力リード
D1,D2…方向
Claims (6)
- 基板の主面上に設けられ、第1方向に並ぶ第1不活性領域、活性領域、及び第2不活性領域を有する半導体領域と、
前記活性領域上に設けられたゲート電極、ソース電極及びドレイン電極と、
前記第1不活性領域上に設けられ、前記ゲート電極と電気的に接続されたゲートパッドと、
前記第1方向に並ぶ前記半導体領域の一対の端縁のうち前記第1不活性領域側の端縁と前記ゲートパッドとの間において、前記ゲートパッドから離間して前記半導体領域上に設けられ、前記半導体領域に接する金属製のゲートガードと、
前記第2不活性領域上に設けられ、前記ドレイン電極と電気的に接続されたドレインパッドと、
前記半導体領域の前記一対の端縁のうち前記第2不活性領域側の端縁と前記ドレインパッドとの間において、前記ドレインパッドから離間して前記半導体領域上に設けられ、前記半導体領域に接する金属製のドレインガードと、
を備え、
前記ゲートガードは、前記基板の裏面に設けられた金属膜と電気的に接続されており、
前記ドレインガードは前記金属膜、前記ゲート電極、前記ソース電極及び前記ドレイン電極に対して非導通状態にある、電界効果トランジスタ。 - 前記ソース電極は、前記基板及び前記半導体領域を貫通する配線を介して前記金属膜と電気的に接続されており、
前記ゲートガードは前記ソース電極と電気的に接続されている、請求項1に記載の電界効果トランジスタ。 - 前記第1不活性領域上において前記ゲートパッドと並んで設けられ、前記ソース電極と電気的に接続されたソースパッドを更に備え、
前記ゲートガードは前記ソースパッドから前記第1不活性領域側の前記端縁に沿って延出している、請求項1または請求項2に記載の電界効果トランジスタ。 - 前記ドレインパッド上及び前記ゲートパッド上に開口を有する絶縁膜を更に備え、
前記ゲートガード及び前記ドレインガードは前記絶縁膜によって覆われている、請求項1から請求項3のいずれか1項に記載の電界効果トランジスタ。 - 請求項1から請求項4のいずれか1項に記載された電界効果トランジスタと、
金属製の表面を有し、前記電界効果トランジスタを搭載するベース部材と、
前記電界効果トランジスタの前記金属膜と前記ベース部材の前記表面との間に介在し、Ag、Au及びCuのうち少なくとも1つを含む導電接合材と、
を備える、半導体装置。 - 前記電界効果トランジスタを収容するパッケージが非気密構造を有する、請求項5に記載の半導体装置。
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