JP6515714B2 - トランジスタ - Google Patents

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JP6515714B2
JP6515714B2 JP2015140308A JP2015140308A JP6515714B2 JP 6515714 B2 JP6515714 B2 JP 6515714B2 JP 2015140308 A JP2015140308 A JP 2015140308A JP 2015140308 A JP2015140308 A JP 2015140308A JP 6515714 B2 JP6515714 B2 JP 6515714B2
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pad
drain
transistor
semiconductor substrate
resistor
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JP2017022303A (ja
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伸介 渡辺
伸介 渡辺
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2015140308A priority Critical patent/JP6515714B2/ja
Priority to US15/016,764 priority patent/US9691762B2/en
Priority to DE102016212347.5A priority patent/DE102016212347B4/de
Priority to CN201610556805.3A priority patent/CN106356362B/zh
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Description

本発明は、高周波信号を増幅するトランジスタに関する。
電界効果トランジスタ（FET: Field Effect Transistor）は並列接続された複数のトランジスタセルを有する（例えば、特許文献１参照）。これにより、各トランジスタセルから出力された電力が合成され、トランジスタ全体で大きな出力電力が得られる。出力電力を外部へ供給したり、ドレインバイアス電圧をトランジスタに印加したりするためのワイヤやプローブはこのドレインパッドに接続される。
図３は、従来のトランジスタを示す平面図である。半導体基板１上に複数のゲート電極２、複数のソース電極３、複数のドレイン電極４、ゲートパッド５、ソースパッド６及びドレインパッド７が形成されている。ゲートパッド５は複数のゲート電極２に接続され、ソースパッド６は複数のソース電極３に接続され、ドレインパッド７は複数のドレイン電極４に接続されている。半導体基板１の裏面にグラウンド金属（不図示）が形成されている。半導体基板１内部のバイアホール９及びソースパッド６を介してソース電極３にグラウンド電位が印加される。
一般に、複数のトランジスタセルを合成したトランジスタの内部において、共振及び発振が起こりうることが知られている。例えば図３のトランジスタに対して電磁界解析を行うと、１７ＧＨｚで共振が起こることが予測される。この共振が起こるとき、ドレインパッド７の直下において電界の定在波が生じる。すなわちドレインパッド７から裏面のグラウンド金属へ向かう電界の強さが、ドレインパッド７の箇所ごとに異なった状態が発生する。もしトランジスタが１７ＧＨｚで十分な利得を有するならば、この周波数において発振が生じうる。
図４は、改良された従来のトランジスタを示す平面図である。上記のような共振及び発振を抑制するためにドレインパッド７内に抵抗１３が形成されている。トランジスタ内部で共振が生じドレインパッド７直下で電界の定在波が発生するとき、上下方向に流れる交流電流がドレインパッド７の表面に生じる。ドレインパッド７内の抵抗１３にも交流電流が流れ、１７ＧＨｚの電気エネルギーは熱エネルギーへと変わる。このため、１７ＧＨｚで損失が生じ、発振が抑制される。一方で、もし増幅したい信号の周波数が十分低く、各トランジスタセル８が均一に動作をするならば、ドレインパッド７直下の電界は位置によらず同じ強さとなる。このとき抵抗１３には電流が流れない。従って、所望の周波数では、性能の劣化は生じない。
特開平６−５６３６号公報
増幅させようとする信号の周波数が高くなると、各トランジスタセル８が不均一に動作することがある。このときドレインパッド７内に抵抗１３を形成していると、抵抗１３に交流電流が流れる。この結果、増幅させようとする信号でも損失が生じ、出力電力や電力付加効率の低下が生じる。このため、トランジスタの性能が劣化するという問題があった。また、高出力用トランジスタの場合、不均一動作が生じた時に抵抗１３に流れる交流電流は非常に大きいため、抵抗１３が損傷しうる。
本発明は、上述のような課題を解決するためになされたもので、その目的は性能の劣化や抵抗の損傷を生じることなく発振を抑制することができるトランジスタを得るものである。
本発明に係るトランジスタは、半導体基板と、前記半導体基板上に形成された複数のゲート電極、複数のソース電極及び複数のドレイン電極と、前記半導体基板上に形成され、前記複数のドレイン電極に接続されたドレインパッドと、前記半導体基板上に形成され、前記ドレインパッドと離間しつつ隣接して平行に配置された金属配線と、前記半導体基板上に形成され、前記金属配線の両端に接続されたグラウンドパッドとを備え、前記ドレインパッドの全体が前記金属配線と対向してキャパシタを構成することを特徴とする。
本発明では、ドレインパッドと離間しつつ平行に金属配線を配置し、金属配線の両端にグラウンドパッドを接続する。これにより、性能の劣化や抵抗の損傷を生じることなく発振を抑制することができる。
本発明の実施の形態１に係るトランジスタを示す平面図である。 本発明の実施の形態２に係るトランジスタを示す平面図である。 従来のトランジスタを示す平面図である。 改良された従来のトランジスタを示す平面図である。
本発明の実施の形態に係るトランジスタについて図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
図１は、本発明の実施の形態１に係るトランジスタを示す平面図である。このトランジスタは電界効果トランジスタ（FET: Field Effect Transistor）である。
半導体基板１上に複数のゲート電極２、複数のソース電極３、複数のドレイン電極４、ゲートパッド５、ソースパッド６及びドレインパッド７が形成されている。ゲートパッド５は複数のゲート電極２に接続され、ソースパッド６は複数のソース電極３に接続され、ドレインパッド７は複数のドレイン電極４に接続されている。電界効果トランジスタは複数のトランジスタセル８が並列接続されることで形成されている。各トランジスタセル８はゲート電極２、ドレイン電極４及びソース電極３を有する。
半導体基板１の裏面にグラウンド金属（不図示）が形成されている。ソース電極３は半導体基板１内部のバイアホール９及びソースパッド６を介して基板裏面のグラウンド金属に接続され、グラウンド電位が印加される。
金属配線１０が半導体基板１上に形成され、ドレインパッド７と離間しつつ隣接して平行に配置されている。ドレインパッド７の全体が金属配線１０と対向してキャパシタを構成する。なお、金属配線１０を構成する導体の材料は任意であり、ドレインパッド７と同種材料でもよい。ドレインパッド７と金属配線１０の間隔は１００マイクロメートル以下であることが望ましい。
グラウンドパッド１１が半導体基板１上に形成され、金属配線１０の両端に接続されている。グラウンドパッド１１は半導体基板１内部のバイアホール１２を介して基板裏面のグラウンド金属に接続され、グラウンド電位が印加される。抵抗１３が金属配線１０とグラウンドパッド１１との間に接続されている。ワイヤやプローブは従来と同様にドレインパッド７に接続される。
続いて、本実施の形態に係るトランジスタの動作を説明する。共振が生じている導体は適当な条件下において近傍に存在する別の導体と電気的に結合してその近傍の導体へ電気エネルギーを伝播しうる。特に両端開放となっているドレインパッド７は、両端短絡となっている金属配線１０と強く結合する。従って、ドレインパッド７直下で電界の定在波が生じた場合、ドレインパッド７に隣接した両端短絡の金属配線１０は電気エネルギーを受け取ることができる。金属配線１０に接続された抵抗１３は、受け取った電気エネルギーを熱エネルギーに変える。よって、金属配線１０、グラウンドパッド１１及び抵抗１３は共振周波数でのみ損失を起こし、トランジスタ内部の発振を抑制する。
一方で共振周波数以外の周波数、例えばトランジスタで増幅させる信号の周波数などでは、ドレインパッド７と金属配線１０の結合が起こらない。従って、金属配線１０や抵抗１３による損失が起こらないため、トランジスタの動作に影響を与えず、トランジスタの性能劣化が生じない。この際、ドレインパッド７と直接に接続されていない抵抗１３に電流が流れることもないため、抵抗１３の損傷も生じない。よって、本実施の形態は、性能の劣化や抵抗の損傷を生じることなく発振を抑制することができる。
ここで、共振周波数や発振周波数が未知であったり、予測した発振周波数が実際と異なっていたとしても、本実施の形態に係るトランジスタは適切に動作する。なぜならば上記のように発振周波数はドレインパッド７で電界定在波が生じる周波数であり、電界定在波が生じる周波数はドレインパッド７と金属配線１０が電気的に結合する周波数だからである。従って、金属配線１０、グラウンドパッド１１及び抵抗１３を形成することで、自動的に共振周波数や発振周波数に対してのみ損失を起こすようになる。
なお、本実施の形態では、グラウンドパッド１１へグラウンド電位を印加する方法としてバイアホール１２を用いているが、その他の方法も可能である。例えばワイヤやプローブを用いてグラウンド電位を印加してもよい。抵抗１３の種類は任意であり、イオン注入抵抗、薄膜抵抗又は細線抵抗等を使用できる。また、金属配線１０の抵抗成分が高く、金属配線１０のみで必要量の損失を起こせるならば、必ずしも抵抗１３を形成する必要はない。
実施の形態２．
図２は、本発明の実施の形態２に係るトランジスタを示す平面図である。外部からのノイズの影響を緩和する等の目的のために、複数のゲート電極２、複数のソース電極３及び複数のドレイン電極４を取り囲むガードリング１４が半導体基板１上に形成されている。ガードリング１４にはグラウンド電位が印加される。
金属配線１０はガードリング１４の一部を成している。このようにグラウンドパッド１１へ金属配線１０以外の金属配線を設置しても実施の形態１と同様の効果を得ることができる。また、金属配線１０及びガードリング１４は、グラウンド電位を印加した別の導体、例えばソースパッド６へ接続してもよい。
ただし、効果を得るには共振周波数でドレインパッド７とガードリング１４が電気的に結合する必要がある。ドレインパッド７で生じた電界定在波のエネルギーをガードリング１４へ伝えるためには、ドレインパッド７の端部に隣接してグラウンドパッド１１を形成する必要がある。ドレインパッド７の端部とグラウンドパッド１１の間隔は１００マイクロメートル以下であることが望ましい。
１ 半導体基板、２ ゲート電極、３ ソース電極、４ ドレイン電極、７ ドレインパッド、１０ 金属配線、１１ グラウンドパッド、１３ 抵抗、１４ ガードリング

Claims (8)

  1. 半導体基板と、
    前記半導体基板上に形成された複数のゲート電極、複数のソース電極及び複数のドレイン電極と、
    前記半導体基板上に形成され、前記複数のドレイン電極に接続されたドレインパッドと、
    前記半導体基板上に形成され、前記ドレインパッドと離間しつつ隣接して平行に配置された金属配線と、
    前記半導体基板上に形成され、前記金属配線の両端に接続されたグラウンドパッドとを備え、
    前記ドレインパッドの全体が前記金属配線と対向してキャパシタを構成することを特徴とするトランジスタ。
  2. 前記グラウンドパッドにはグラウンド電位が印加されていることを特徴とする請求項１に記載のトランジスタ。
  3. 前記グラウンドパッドに前記グラウンド電位を印加するワイヤ又は前記半導体基板内部のバイアホールを更に備えることを特徴とする請求項２に記載のトランジスタ。
  4. 前記ドレインパッドと前記金属配線の間隔は１００マイクロメートル以下であることを特徴とする請求項１〜３の何れか１項に記載のトランジスタ。
  5. 前記金属配線と前記グラウンドパッドとの間に接続された抵抗を更に備えることを特徴とする請求項１〜４の何れか１項に記載のトランジスタ。
  6. 前記抵抗はイオン注入抵抗、薄膜抵抗又は細線抵抗であることを特徴とする請求項５に記載のトランジスタ。
  7. 前記半導体基板上に形成され、前記複数のゲート電極、前記複数のソース電極及び前記複数のドレイン電極を取り囲むガードリングを更に備え、
    前記金属配線は前記ガードリングの一部を成していることを特徴とする請求項１〜６の何れか１項に記載のトランジスタ。
  8. 前記ドレインパッドの端部と前記グラウンドパッドの間隔は１００マイクロメートル以下であることを特徴とする請求項７に記載のトランジスタ。
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