CN106356362A - 晶体管 - Google Patents

晶体管 Download PDF

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CN106356362A
CN106356362A CN201610556805.3A CN201610556805A CN106356362A CN 106356362 A CN106356362 A CN 106356362A CN 201610556805 A CN201610556805 A CN 201610556805A CN 106356362 A CN106356362 A CN 106356362A
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pad
semiconductor substrate
metal wiring
drain
transistor
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CN106356362B (zh
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渡边伸介
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Mitsubishi Electric Corp
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Abstract

本发明得到一种晶体管，该晶体管能够抑制振荡，而不会发生性能的劣化、电阻的损伤。在半导体衬底(1)之上形成有多个栅极电极(2)、多个源极电极(3)及多个漏极电极(4)。漏极焊盘(7)形成于半导体衬底(1)之上，与多个漏极电极(4)连接。金属配线(10)形成于半导体衬底(1)之上，与漏极焊盘(7)分离并相邻，与漏极焊盘(7)平行地配置。接地焊盘(11)形成于半导体衬底(1)之上，与金属配线(10)的两端连接。

Description

晶体管
技术领域
本发明涉及对高频信号进行放大的晶体管。
背景技术
场效应晶体管(FET:Field Effect Transistor)具有并联连接的多个晶体管单元(例如参照专利文献1)。由此，能够对从各晶体管单元输出的功率进行合成，作为晶体管整体得到大的输出功率。用于将输出功率向外部供给、或者将漏极偏置电压施加于晶体管的导线、探针，与该漏极焊盘连接。
图3是表示现有的晶体管的俯视图。在半导体衬底1之上形成有多个栅极电极2、多个源极电极3、多个漏极电极4、栅极焊盘5、源极焊盘6以及漏极焊盘7。栅极焊盘5与多个栅极电极2连接，源极焊盘6与多个源极电极3连接，漏极焊盘7与多个漏极电极4连接。在半导体衬底1的背面形成有接地金属(未图示)。经由半导体衬底1内部的通路孔(via hole)9及源极焊盘6对源极电极3施加接地电位。
通常，已知在将多个晶体管单元进行了合成的晶体管的内部可能发生共振及振荡。例如，如果对图3的晶体管进行电磁场解析，则预测到在17GHz发生共振。在发生该共振时，在漏极焊盘7的正下方产生电场的驻波。即，产生如下状态：从漏极焊盘7朝向背面的接地金属的电场的强度在漏极焊盘7的各个部位不同。如果晶体管在17GHz具有充分的增益，则在该频率可能发生振荡。
图4是表示改良后的现有的晶体管的俯视图。为了抑制上述共振及振荡而在漏极焊盘7内形成有电阻13。在晶体管内部发生共振而在漏极焊盘7正下方产生电场的驻波时，在漏极焊盘7的表面产生沿上下方向流动的交流电流。交流电流还流过漏极焊盘7内的电阻13，17GHz的电能向热能转变。因此，在17GHz发生损耗，振荡得到抑制。另一方面，如果希望放大的信号的频率充分低，各晶体管单元8均匀地进行动作，则漏极焊盘7正下方的电场成为相同的强度，而不依赖于位置。此时电流不流过电阻13。因此，在所期望的频率，不发生性能的劣化。
专利文献1：日本特开平6－5636号公报
如果要放大的信号的频率变高，则各晶体管单元8有时不均匀地进行动作。此时，如果在漏极焊盘7内形成有电阻13，则交流电流流过电阻13。其结果，即使是要放大的信号，也会发生损耗，发生输出功率、功率附加效率的下降。因此，存在晶体管的性能劣化这一问题。另外，在高输出用晶体管的情况下，由于在发生不均匀动作时流过电阻13的交流电流非常大，因此可能损伤电阻13。
发明内容
本发明就是为了解决上述课题而提出的，其目的在于，得到一种晶体管，该晶体管能够抑制振荡，而不会发生性能的劣化、电阻的损伤。
本发明所涉及的晶体管的特征在于，具有：半导体衬底；多个栅极电极、多个源极电极及多个漏极电极，它们形成于所述半导体衬底之上；漏极焊盘，其形成于所述半导体衬底之上，与所述多个漏极电极连接；金属配线，其形成于所述半导体衬底之上，与所述漏极焊盘分离并相邻，与所述漏极焊盘平行地配置；以及接地焊盘，其形成于所述半导体衬底之上，与所述金属配线的两端连接。
发明的效果
在本发明中，与漏极焊盘分离并与漏极焊盘平行地配置金属配线，将接地焊盘与金属配线的两端连接。由此，能够抑制振荡，而不会发生性能的劣化、电阻的损伤。
附图说明
图1是表示本发明的实施方式1所涉及的晶体管的俯视图。
图2是表示本发明的实施方式2所涉及的晶体管的俯视图。
图3是表示现有的晶体管的俯视图。
图4是表示改良后的现有的晶体管的俯视图。
标号的说明
1半导体衬底，2栅极电极，3源极电极，4漏极电极，7漏极焊盘，10金属配线，11接地焊盘，13电阻，14保护环
具体实施方式
参照附图，对本发明的实施方式所涉及的晶体管进行说明。对相同或者相对应的结构要素标注同一标号，有时省略重复的说明。
实施方式1
图1是表示本发明的实施方式1所涉及的晶体管的俯视图。该晶体管是场效应晶体管(FET:Field Effect Transistor)。
在半导体衬底1之上形成有多个栅极电极2、多个源极电极3、多个漏极电极4、栅极焊盘5、源极焊盘6以及漏极焊盘7。栅极焊盘5与多个栅极电极2连接，源极焊盘6与多个源极电极3连接，漏极焊盘7与多个漏极电极4连接。场效应晶体管是通过使多个晶体管单元8并联连接而形成的。各晶体管单元8具有栅极电极2、漏极电极4以及源极电极3。
在半导体衬底1的背面形成有接地金属(未图示)。源极电极3经由半导体衬底1内部的通路孔9及源极焊盘6而与衬底背面的接地金属连接，被施加接地电位。
金属配线10形成于半导体衬底1之上，与漏极焊盘7分离并相邻，与漏极焊盘7平行地配置。漏极焊盘7整体与金属配线10相对而构成电容器。此外，构成金属配线10的导体的材料是任意的，也可以与漏极焊盘7是同种材料。期望漏极焊盘7和金属配线10之间的间隔小于或等于100微米。
接地焊盘11形成于半导体衬底1之上，与金属配线10的两端连接。接地焊盘11经由半导体衬底1内部的通路孔12而与衬底背面的接地金属连接，被施加接地电位。电阻13连接于金属配线10和接地焊盘11之间。导线、探针与现有技术相同地连接至漏极焊盘7。
下面，对本实施方式所涉及的晶体管的动作进行说明。发生共振的导体在适当的条件下可能与存在于附近的其他导体电耦合而向其附近的导体传播电能。特别地，两端开路的漏极焊盘7与两端短路的金属配线10强耦合。因此，如果在漏极焊盘7正下方产生电场的驻波，则与漏极焊盘7相邻的两端短路的金属配线10能够接受电能。与金属配线10连接的电阻13将所接受的电能转变为热能。由此，金属配线10、接地焊盘11以及电阻13仅在共振频率发生损耗，抑制晶体管内部的振荡。
另一方面，在除共振频率以外的频率、例如利用晶体管进行放大的信号的频率等，不发生漏极焊盘7和金属配线10的耦合。因此，由于不发生由金属配线10、电阻13造成的损耗，因此不会对晶体管的动作施加影响，不会发生晶体管的性能劣化。此时，由于电流也不会流过未与漏极焊盘7直接连接的电阻13，因此也不会发生电阻13的损伤。由此，本实施方式能够抑制振荡，而不会发生性能的劣化、电阻的损伤。
在这里，即使假设共振频率、振荡频率未知，所预测的振荡频率与实际不同，本实施方式所涉及的晶体管也适当地进行动作。其原因在于，如上所述，振荡频率是在漏极焊盘7处产生电场驻波的频率，产生电场驻波的频率是漏极焊盘7和金属配线10进行电耦合的频率。因此，通过形成金属配线10、接地焊盘11以及电阻13，从而自动地仅针对共振频率、振荡频率发生损耗。
此外，在本实施方式中，作为向接地焊盘11施加接地电位的方法而使用通路孔12，但其他方法也是可以的。例如也可以使用导线、探针而施加接地电位。电阻13的种类是任意的，能够使用离子注入电阻、薄膜电阻或者细丝电阻等。另外，如果金属配线10的电阻成分高、且仅利用金属配线10即能够发生所需要的量的损耗，则并非必须形成电阻13。
实施方式2
图2是表示本发明的实施方式2所涉及的晶体管的俯视图。出于缓和来自外部的噪声的影响等目的，包围多个栅极电极2、多个源极电极3以及多个漏极电极4的保护环14被形成于半导体衬底1之上。对保护环14施加接地电位。
金属配线10形成保护环14的一部分。即使以上述方式向接地焊盘11设置除金属配线10以外的金属配线，也能够得到与实施方式1相同的效果。另外，金属配线10及保护环14也可以向施加了接地电位的其他导体、例如源极焊盘6进行连接。
但是，为了得到效果，需要在共振频率使漏极焊盘7和保护环14电耦合。为了将在漏极焊盘7处产生的电场驻波的能量向保护环14传递，需要与漏极焊盘7的端部相邻地形成接地焊盘11。期望使漏极焊盘7的端部和接地焊盘11之间的间隔小于或等于100微米。

Claims (9)

1.一种晶体管，其特征在于，具有：
半导体衬底；
多个栅极电极、多个源极电极及多个漏极电极，它们形成于所述半导体衬底之上；
漏极焊盘，其形成于所述半导体衬底之上，与所述多个漏极电极连接；
金属配线，其形成于所述半导体衬底之上，与所述漏极焊盘分离并相邻，与所述漏极焊盘平行地配置；以及
接地焊盘，其形成于所述半导体衬底之上，与所述金属配线的两端连接。
2.根据权利要求1所述的晶体管，其特征在于，
所述漏极焊盘整体与所述金属配线相对而构成电容器。
3.根据权利要求1或2所述的晶体管，其特征在于，
对所述接地焊盘施加有接地电位。
4.根据权利要求3所述的晶体管，其特征在于，
还具有对所述接地焊盘施加所述接地电位的导线或者所述半导体衬底内部的通路孔。
5.根据权利要求1或2所述的晶体管，其特征在于，
所述漏极焊盘和所述金属配线之间的间隔小于或等于100微米。
6.根据权利要求1或2所述的晶体管，其特征在于，
还具有电阻，该电阻连接于所述金属配线和所述接地焊盘之间。
7.根据权利要求6所述的晶体管，其特征在于，
所述电阻是离子注入电阻、薄膜电阻或者细丝电阻。
8.根据权利要求1或2所述的晶体管，其特征在于，
还具有保护环，该保护环形成于所述半导体衬底之上，包围所述多个栅极电极、所述多个源极电极以及所述多个漏极电极，
所述金属配线形成所述保护环的一部分。
9.根据权利要求8所述的晶体管，其特征在于，
所述漏极焊盘的端部和所述接地焊盘之间的间隔小于或等于100微米。
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